A MOSFET device with integrated junction barrier Schottky

Abstract

The present invention discloses a MOSFET device with integrated junction barrier Schottky, which belongs to the field of semiconductor manufacturing and is used to solve the technical problem that the chip size of the integrated MOSFET device is increased and the manufacturing cost is increased by connecting a Schottky diode in parallel outside the MOSFET device. The device includes: an epitaxial layer, and a plurality of cells with the same shape and structure arranged on the surface of the epitaxial layer; each cell includes at least a well region, a source region and a highly doped P-type region; the well region is surrounded by a junction barrier Schottky region, and the junction barrier Schottky region includes multiple layers of annular highly doped P-type regions and several Schottky regions; a junction field effect transistor JFET region is formed between the well region and the adjacent annular highly doped P-type region; the ion doping concentration of the Schottky region and the JFET region is greater than or equal to the ion doping concentration of the epitaxial layer, and the width of the JFET region and the spacing between each layer of the annular highly doped P-type region are both within a preset range.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a MOSFET device with integrated junction barrier Schottky. Background Art

[0002] There are basal plane dislocations in silicon carbide crystals. Under certain conditions, basal plane dislocations can be converted into stacking faults. When the body diode in the silicon carbide power MOSFET device is turned on, under bipolar operation, the recombination of electrons and holes will cause the stacking faults to continue to expand, resulting in bipolar degradation. This phenomenon increases the on-state piezoresistance of the silicon carbide power MOSFET device, increases the leakage current in the blocking mode, and increases the on-state voltage drop of the body diode in the silicon carbide power MOSFET device, thereby reducing the reliability of the silicon carbide power MOSFET device.

[0003] In actual circuit applications, in order to avoid bipolar degradation, an external reverse-parallel Schottky diode is generally used to suppress the body diode in the power MOSFET device. However, this method will increase the chip size, and the unit price of the Schottky diode is high, so this product structure will increase the cost of the power MOSFET device. Summary of the invention

[0004] The embodiment of the present application provides a MOSFET device with an integrated junction barrier Schottky, which is used to solve the following technical problem: the method of connecting a Schottky diode in parallel to the outside of the MOSFET device leads to an increase in the chip size integrated with the MOSFET device and an increase in the manufacturing cost.

[0005] The present application embodiment adopts the following technical solutions:

[0006] The embodiment of the present application provides a MOSFET device of an integrated junction barrier Schottky, the MOSFET device comprising: an epitaxial layer, and a plurality of cells of the same shape and structure arranged on the surface of the epitaxial layer; the epitaxial layer is an N-type semiconductor; each of the cells comprises a well region, a source region and a highly doped P-type region, the well region is a P-type semiconductor, and the source region is an N-type semiconductor; the source region is located inside the well region, and the source region surrounds the highly doped P-type region; wherein the ion implantation depth of the source region is less than the ion implantation depth of the well region, and the highly doped P-type region contacts the well region; the well region forms a first PN junction with the epitaxial layer, and the well region forms a second PN junction; the well region is surrounded by a junction barrier Schottky region, the junction barrier Schottky region includes multiple layers of annular highly doped P-type regions, and Schottky regions formed between each layer of the annular highly doped P-type regions; the multiple layers of annular highly doped P-type regions have the same ion doping concentration as the highly doped P-type regions; the annular highly doped P-type region forms a third PN junction with the epitaxial layer; a junction field effect transistor JFET region is formed between the well region and the adjacent annular highly doped P-type region; the ion doping concentration of the Schottky region and the JFET region is greater than or equal to the ion doping concentration of the epitaxial layer, and the width of the JFET region and the spacing between each layer of the annular highly doped P-type regions are both within the same preset range.

[0007] In the embodiment of the present application, a Schottky diode is embedded in a MOSFET cell so that the Schottky diode and the MOSFET device share a structure, so that the MOSFET device does not need an external Schottky diode connected in parallel, thereby reducing the size of the integrated chip.

[0008] In a feasible embodiment, the MOSFET device also includes a first contact metal; the first contact metal covers the surface of the highly doped P-type region and forms an ohmic contact with the highly doped P-type region; a portion of the first contact metal is in contact with the source region to suppress the parasitic bipolar transistor effect inside the MOSFET device.

[0009] In a feasible embodiment, the MOSFET device also includes a second contact metal; the second contact metal covers the surface of the junction barrier Schottky region and forms a Schottky contact with several Schottky regions in the junction barrier Schottky region; a preset distance is maintained between the first contact metal and the second contact metal, so that the first contact metal and the second contact metal can be designed as ohmic contact and Schottky contact respectively through different processes.

[0010] The embodiment of the present application designs the two contact metals as separate structures, which makes it easier to perform different process treatments on the two contact metals without causing interference between the two, thereby reducing the difficulty of manufacturing MOSFET devices, improving the success rate of device processing, and reducing the number of devices that fail in processing.

[0011] In a feasible embodiment, the MOSFET device also includes an insulating gate oxide layer; the insulating gate oxide layer covers the source region, the well region and the JFET region of the cell; the width of the insulating gate oxide layer covering the JFET region is greater than or equal to 0.1 microns and is less than the width of the JFET region.

[0012] In a feasible implementation manner, the gate insulating oxide layer is covered with gate conductive polysilicon.

[0013] In a feasible implementation manner, the insulating gate oxide layer and the gate conductive polysilicon are wrapped with an insulating dielectric layer.

[0014] In a feasible embodiment, the insulating dielectric layer, the first contact metal and the second contact metal are covered with a source electrode; the source electrode is in contact with the first contact metal and the second contact metal; the insulating dielectric layer separates the insulating gate oxide layer and the gate conductive polysilicon from the source electrode.

[0015] In a feasible embodiment, the MOSFET device also includes: a silicon carbide substrate, the silicon carbide substrate is located on the surface of the epitaxial layer away from the cell side; the silicon carbide substrate is an N-type semiconductor; the ion doping concentration in the silicon carbide substrate is higher than the ion doping concentration in the epitaxial layer; the side of the silicon carbide substrate away from the epitaxial layer is covered with the drain electrode of the MOSFET device.

[0016] In a feasible implementation manner, the preset interval is [0.8 μm to 5 μm].

[0017] In a feasible implementation manner, the shape of the cell is a regular polygon or a circle.

[0018] An integrated junction barrier Schottky MOSFET device provided in an embodiment of the present application has a polygonal or circular cell design, which can achieve a higher channel width and total JFET region area, thereby making the MOSFET device have a lower specific on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0020] Figure 1 A cross-sectional view of an active region of a MOSFET device with an integrated junction barrier Schottky provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a regular hexagonal cell structure provided in an embodiment of the present application;

[0022] Figure 3 A partial cross-sectional view of a hexagonal cell structure provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of a circular cell structure provided in an embodiment of the present application;

[0024] Figure 5 A partial cross-sectional view of a circular cellular structure provided in an embodiment of the present application;

[0025] Figure 6 A schematic diagram of a regular quadrilateral cell structure provided in an embodiment of the present application;

[0026] Figure 7 A partial cross-sectional view of a regular quadrilateral cell structure provided in an embodiment of the present application;

[0027] Figure 8 A schematic diagram of another regular quadrilateral cell structure provided in an embodiment of the present application;

[0028] Fig. 9 A partial cross-sectional view of another regular quadrilateral cell structure provided in an embodiment of the present application;

[0029] Description of reference numerals:

[0030] 10. MOSFET device active area; 101. Silicon carbide substrate; 102. Epitaxial layer; 103. Well region; 104. Source region; 105. Highly doped P-type region; 106. Insulating gate oxide layer; 107. Gate conductive polysilicon; 108. Insulating dielectric layer; 109. First contact metal; 110. Second contact metal; 111. Source electrode; 112. Drain electrode; 113. JFET region; 114. Junction barrier Schottky region; 115. First PN junction; 116: Second PN junction; 117. Ring-shaped highly doped P-type region; 118. Third PN junction. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0032] An embodiment of the present application provides a MOSFET device with an integrated junction barrier Schottky diode, which embeds a junction barrier Schottky diode into each cell unit of the power MOSFET device so that the Schottky diode and the power MOSFET diode share the same structure, thereby reducing the size of the integrated chip and reducing costs.

[0033] Figure 1 A cross-sectional view of an active region of a MOSFET device with an integrated junction barrier Schottky provided in an embodiment of the present application, such as Figure 1 As shown, the MOSFET device 10 specifically includes: an epitaxial layer 102, and a plurality of cells with the same shape and structure arranged on the surface of the epitaxial layer, wherein the epitaxial layer is an N-type semiconductor.

[0034] After a lot of experiments, it is found that compared with strip cells, MOSFET devices with circular and polygonal cell designs can achieve higher channel width and total area of ​​junction field-effect transistor (JFET) region, and thus have lower specific on-resistance. Therefore, the cell shape in this application can be designed as a regular polygon or a circle.

[0035] Taking a regular hexagon as an example, Figure 2 A schematic diagram of a regular hexagonal cell structure provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, each cell includes a well region 103, a source region 104, and a highly doped P-type region 105. The well region 103 is a P-type semiconductor, and the source region 104 is an N-type semiconductor. The shapes of the well region 103, the source region 104, and the highly doped P-type region 105 are all regular hexagons, and the center points coincide.

[0036] like Figure 2 As shown, the source region 104 is inside the well region 103 , and the source region 104 surrounds the highly doped P-type region 105 . Figure 1 That is Figure 2 The cross-sectional view corresponding to the dotted line AA' in Figure 3 That is Figure 2 The cross-sectional view corresponding to the dotted line BB' in Figure 1 It can be seen from the figure that the ion implantation depth of the source region 104 in the cell is less than the ion implantation depth of the well region 103 , and the lower half of the highly doped P-type region 105 is in contact with the well region 103 .

[0037] Furthermore, a first PN junction 115 is formed at the boundary between the well region 103 and the epitaxial layer 102 , and a second PN junction 116 is formed at the boundary between the well region 103 and the source region 104 .

[0038] Furthermore, if Figure 2 As shown, the well region 103 is surrounded by a junction barrier Schottky region 114, which includes multiple layers of annular highly doped P-type regions 117 and Schottky regions formed between each layer of annular highly doped P-type regions 117. The annular highly doped P-type region 117 forms a third PN junction 118 with the epitaxial layer 102. The shape of the annular highly doped P-type region 117 is also a regular hexagon, and the center point is the same as the center point of other regions. A JFET region 113 is formed between the well region 103 and the adjacent annular highly doped P-type region.

[0039] In one embodiment, the outermost layer of the cell in the present application specifically includes 3 layers of annular highly doped P-type regions 117. Since the cells are closely arranged, two cells share the outermost annular highly doped P-type region 117. Therefore, there are 5 layers of annular highly doped P-type regions 117 between the well regions of every two cells, and 4 layers of Schottky regions are formed between the 5 layers of annular highly doped P-type regions. The ion doping concentration range of the well region 103 is: 5E15cm -3 ~5E18cm -3 The ion doping concentration range of the source region 104 is: 1E18cm -3 ~1E22cm -3 The ion doping concentration range of the highly doped P-type region 105 and the annular highly doped P-type region 117 is: 1E18 cm -3 ~1E22cm -3 .

[0040] Furthermore, the width n and ion implantation concentration of the JFET region 113 need to ensure that the MOSFET has a small on-state voltage drop, and in the blocking mode, the adjacent well intervals can play an effective electric field shielding effect to ensure the reliability of the device. Similarly, the ion implantation concentration and spacing s of each layer of the annular highly doped P-type region 117 in the junction barrier Schottky region 114 need to ensure that the junction barrier Schottky diode has sufficient current conduction capability, and in the blocking mode, the adjacent well intervals can play an effective electric field shielding effect to ensure the reliability of the device. Therefore, in the design of the present application, the ion doping concentration of the Schottky region formed between the annular highly doped P-type regions 117 in the junction barrier Schottky region 114 and the JFET region 113 is greater than or equal to the ion doping concentration of the epitaxial layer 102. The width n of the JFET region 113 and the spacing s between each layer of the annular highly doped P-type region 117 are both within a preset range. Experiments have shown that such a design can make the MOSFET device have a smaller on-state voltage drop, and in the blocking mode, the adjacent well regions can play an effective electric field shielding role.

[0041] In one embodiment, the preset interval is specifically [0.8 μm-5 μm]. The ion doping concentration range of the Schottky region formed between the JFET region 113 and the annular highly doped P-type region 117 in the junction barrier Schottky region 114 is: 1E15 cm -3 ~5E17cm -3 .

[0042] Furthermore, the MOSFET device 10 further includes a first contact metal 109 and a second contact metal 110. Figure 1 As shown, the first contact metal covers the surface of the highly doped P-type region 105, and forms an ohmic contact with the highly doped P-type region 105. In order to suppress the parasitic bipolar transistor effect inside the MOSFET device 10, a portion of the first contact metal 109 is in contact with the source region 104. The second contact metal covers the surface of the junction barrier Schottky region 114, and forms Schottky contacts with several Schottky regions in the junction barrier Schottky region 114.

[0043] If two pieces of contact metal are connected together, through appropriate contact metal design and high temperature annealing temperature, the two pieces of metal can form both ohmic contact and Schottky contact at the same time, which can simplify the process flow. However, the disadvantage is that it is not easy to form good ohmic contact and Schottky contact at the same time in actual device production, which may increase the failure rate and sacrifice the device yield. Figure 1As shown, a certain distance is maintained between the first contact metal 109 and the second contact metal 110 in the present application, so that the two contact metals can be designed as ohmic contacts and Schottky contacts respectively through different processes, thereby reducing the manufacturing difficulty and failure rate of MOSFET devices.

[0044] like Figure 1 As shown, the source region 104, the well region 103 and the JFET region 113 of the cell are covered with an insulating gate oxide layer 106, and the insulating gate oxide layer 106 starts from the source region 104 and ends at the JFET region 113. The width of the insulating gate oxide layer 106 covering the JFET region 113 is greater than or equal to 0.1 microns and less than the width of the JFET region 113.

[0045] For example, if the width of the JFET region 113 is 5 micrometers, the width of the insulating gate oxide layer 106 covering the JFET region 113 has a value range of [0.1 μm to 5 μm].

[0046] Furthermore, the gate insulating oxide layer 106 is covered with a gate conductive polysilicon 107. The insulating gate oxide layer 106 and the gate conductive polysilicon 107 are wrapped with an insulating dielectric layer 108, and the insulating dielectric layer 108 separates the insulating gate oxide layer 106 and the gate conductive polysilicon 107 from the adjacent first contact metal 109 and the second contact metal 110.

[0047] Furthermore, a source electrode 111 is covered on the insulating dielectric layer 108 , the first contact metal 109 and the second contact metal 110 , and the source electrode 111 is in contact with the first contact metal 109 and the second contact metal 110 of each cell, and the insulating dielectric layer 108 completely separates the insulating gate oxide layer 106 and the gate conductive polysilicon 107 from the source electrode 111 .

[0048] Furthermore, the side of the epitaxial layer 102 away from the cell side is covered with a silicon carbide substrate 101, which is an N-type semiconductor and has an ion doping concentration higher than that of the epitaxial layer 102. The side of the silicon carbide substrate 101 away from the epitaxial layer 102 is covered with a drain electrode 112 of the MOSFET device 10.

[0049] In one embodiment, the ion doping concentration of the silicon carbide substrate 101 is in the range of 1E18 cm -3 ~1E20cm -3 , the ion doping concentration range of the epitaxial layer 102 is: 1E14cm -3 ~5E16cm -3 .

[0050] As a feasible implementation mode, in addition to the regular hexagon, the cells in the present application can also be designed as circles, squares, regular octagons, etc. Figure 4 A schematic diagram of a circular cell structure provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the source region 104 and the highly doped P-type region 105 are both circular in shape, and the centers of the circles coincide. The cross-sectional view corresponding to the dotted line AA' is shown in FIG. Figure 1 As shown, the cross-sectional view corresponding to the dotted line BB' is as follows Figure 5 shown.

[0051] As another feasible implementation, there are many different arrangements for regular quadrilateral cells. Figure 6 A schematic diagram of a regular quadrilateral cell structure provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, each row of quadrilateral cells is staggered, and the cross-sectional view corresponding to the dotted line AA' is as follows Figure 1 As shown, the cross-sectional view corresponding to the dotted line BB' is as follows Figure 7 shown. Figure 8 Another schematic diagram of a regular quadrilateral cell structure provided in an embodiment of the present application is as follows: Figure 8 As shown, each row and column of cells are aligned, and the cross-sectional view corresponding to the dotted line AA' is shown in Figure 1 As shown, the cross-sectional view corresponding to the dotted line BB' is as follows Fig. 9 shown.

[0052] The embodiment of the present application provides an integrated junction barrier Schottky MOSFET device, which has a polygonal or circular cell design, can achieve a higher channel width and total JFET area, thereby making the MOSFET have a lower specific on-resistance. Embedding a Schottky diode into the MOSFET cell can make the MOSFET device no longer need an external Schottky diode in parallel, so as to reduce the size of the integrated chip.

[0053] The various embodiments in the present application are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0054] The above describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0055] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the embodiments of the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the claims of the present application.

Claims

1. A MOSFET device with integrated junction barrier Schottky, It is characterized in that The MOSFET device comprises: an epitaxial layer, and a plurality of cells with the same shape and structure arranged on the surface of the epitaxial layer; the epitaxial layer is an N-type semiconductor; Each of the cells comprises a well region, a source region and a highly doped P-type region, the well region is a P-type semiconductor, and the source region is an N-type semiconductor; The source region is located inside the well region, and the source region surrounds the highly doped P-type region; wherein the ion implantation depth of the source region is less than the ion implantation depth of the well region, and the highly doped P-type region is in contact with the well region; The well region and the epitaxial layer form a first PN junction, and the well region and the source region form a second PN junction; The well region is surrounded by a junction barrier Schottky region, the junction barrier Schottky region includes a multi-layer annular highly doped P-type region, and a Schottky region formed between each layer of the annular highly doped P-type region; the multi-layer annular highly doped P-type region has the same ion doping concentration as the highly doped P-type region; The annular highly doped P-type region and the epitaxial layer form a third PN junction; a junction field effect transistor JFET region is formed between the well region and the adjacent annular highly doped P-type region; The ion doping concentration of the Schottky region and the JFET region is greater than or equal to the ion doping concentration of the epitaxial layer, and the width of the JFET region and the spacing between each layer of the annular highly doped P-type region are both within the same preset range.

2. The MOSFET device of claim 1, It is characterized in that The MOSFET device also includes a first contact metal; The first contact metal covers the surface of the highly doped P-type region and forms an ohmic contact with the highly doped P-type region; A portion of the first contact metal contacts the source region to suppress a parasitic bipolar transistor effect inside the MOSFET device.

3. The MOSFET device of claim 2, It is characterized in that The MOSFET device also includes a second contact metal; The second contact metal covers the surface of the junction barrier Schottky region and forms Schottky contact with a plurality of Schottky regions in the junction barrier Schottky region; A preset distance is maintained between the first contact metal and the second contact metal, so that the first contact metal and the second contact metal can be designed as an ohmic contact and a Schottky contact respectively through different processes.

4. The MOSFET device of claim 3, It is characterized in that The MOSFET device also includes an insulating gate oxide layer; The insulating gate oxide layer covers the source region, the well region and the JFET region of the cell; The width of the insulating gate oxide layer covering the JFET region is greater than or equal to 0.1 micrometers and is smaller than the width of the JFET region.

5. The MOSFET device of claim 4, It is characterized in that The insulating gate oxide layer is covered with gate conductive polysilicon.

6. The MOSFET device of claim 5, It is characterized in that The insulating gate oxide layer and the gate conductive polysilicon are wrapped with an insulating dielectric layer.

7. The MOSFET device of claim 6, It is characterized in that The insulating dielectric layer, the first contact metal and the second contact metal are covered with a source electrode; The source electrode is in contact with the first contact metal and the second contact metal; The insulating dielectric layer separates the insulating gate oxide layer and the gate conductive polysilicon from the source electrode.

8. The MOSFET device of claim 1, It is characterized in that The MOSFET device further comprises: a silicon carbide substrate, the silicon carbide substrate being located on a surface of the epitaxial layer away from the cell; the silicon carbide substrate being an N-type semiconductor; The ion doping concentration in the silicon carbide substrate is higher than the ion doping concentration in the epitaxial layer; A side of the silicon carbide substrate facing away from the epitaxial layer is covered with a drain electrode of the MOSFET device.

9. The MOSFET device of claim 1, It is characterized in that The preset interval is [0.8 μm to 5 μm].

10. The MOSFET device of claim 1, It is characterized in that The shape of the cell is a regular polygon or a circle.

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