Cascade construction method and device of interrupt controller, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a cascade construction method and device of an interrupt controller, electronic equipment and a storage medium. In the method, cascade information of each interrupt controller is obtained as a cascade information set. The cascade information is generated according to a data structure corresponding to the interrupt controller. Whether the first interrupt controller deployed in the CPU is included in the interrupt controller set is detected. In the case of including the first interrupt controller, the specified interrupt controller in the chip set is cascaded with the first interrupt controller according to the cascade information set. In the case of not including the first interrupt controller, the specified interrupt controller is cascaded with the second interrupt controller in the CPU according to the cascade information set. In this way, the cascade construction can be realized, and to some extent, the constructed interrupt controller cascade can be more adapted to the actual hardware condition of the electronic equipment, thereby ensuring the cascade construction effect to some extent.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of interrupt control, and in particular to a cascade construction method and device of an interrupt controller, an electronic device, and a storage medium. BACKGROUND

[0002] At present, in order to facilitate the management of the interrupt source of an operating system, multiple interrupt controllers are often configured for an electronic device.

[0003] Correspondingly, in the case of configuring multiple interrupt controllers, it is often necessary to construct the cascade between the interrupt controllers. If the cascade construction becomes a technical problem to be solved. SUMMARY

[0004] The present application provides a cascade construction method and device of an interrupt controller, an electronic device, and a storage medium, to realize the cascade construction.

[0005] In a first aspect, the present application provides a cascade construction method of an interrupt controller, applied to an electronic device, wherein the electronic device is configured with a set of interrupt controllers, and the set of interrupt controllers includes interrupt controllers respectively deployed in a chipset and a central processing unit (CPU) of the electronic device, and the method comprises:

[0006] obtaining cascade information of each interrupt controller as a set of cascade information; the cascade information is generated according to a data structure corresponding to the interrupt controller;

[0007] detecting whether the set of interrupt controllers includes a first interrupt controller deployed in the CPU;

[0008] in the case of including the first interrupt controller, cascading a specified interrupt controller in the chipset with the first interrupt controller according to the set of cascade information;

[0009] in the case of not including the first interrupt controller, cascading the specified interrupt controller with a second interrupt controller in the CPU according to the set of cascade information.

[0010] In a second aspect, the present application provides a cascade construction device of an interrupt controller, applied to an electronic device, wherein the electronic device is configured with a set of interrupt controllers, and the set of interrupt controllers includes interrupt controllers respectively deployed in a chipset and a central processing unit (CPU) of the electronic device, and the device comprises:

[0011] an obtaining module, configured to obtain cascade information of each interrupt controller as a set of cascade information; the cascade information is generated according to a data structure corresponding to the interrupt controller;

[0012] detecting whether the first interrupt controller deployed in the CPU is included in the set of interrupt controllers;

[0013] a first cascading module, configured to, in the case that the first interrupt controller is included, cascade the specified interrupt controller in the chipset with the first interrupt controller according to the set of cascading information;

[0014] a second cascading module, configured to, in the case that the first interrupt controller is not included, cascade the specified interrupt controller with a second interrupt controller in the CPU according to the set of cascading information.

[0015] In a third aspect, the present application provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the processor implements the method when executing the program.

[0016] In a fourth aspect, the present application provides a readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method.

[0017] The cascading construction method of the interrupt controller provided by the embodiments of the present application acquires the cascading information of each interrupt controller as a set of cascading information; the cascading information is generated according to the data structure corresponding to the interrupt controller. It is detected whether the first interrupt controller deployed in the CPU is included in the set of interrupt controllers. In the case that the first interrupt controller is included, the specified interrupt controller in the chipset is cascaded with the first interrupt controller according to the set of cascading information. In the case that the first interrupt controller is not included, the specified interrupt controller is cascaded with the second interrupt controller in the CPU according to the set of cascading information. In the embodiments of the present application, the cascading between the interrupt controllers in the chipset and the CPU is constructed according to the actual hardware structure of the electronic device, that is, based on whether the first interrupt controller is deployed in the CPU of the electronic device, the cascading between the specified interrupt controller in the chipset and the interrupt controller in the CPU is constructed, and then the cascading construction can be realized, and to some extent, the constructed interrupt controller cascading can be more adapted to the actual hardware condition of the electronic device, so that the cascading construction effect can be ensured to some extent. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0019] Figure 1 is a step flow chart of a cascade construction method of an interrupt controller provided by an embodiment of the present application;

[0020] Figure 2 is a delivery schematic diagram provided by an embodiment of the present application;

[0021] Figure 3 is a cascade relationship schematic diagram of an interrupt controller provided by an embodiment of the present application;

[0022] Figure 4 is another cascade relationship schematic diagram of an interrupt controller provided by an embodiment of the present application;

[0023] Figure 5 is a structural block diagram of a cascade construction device of an interrupt controller of the present application;

[0024] Figure 6 is a structural block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0026] Figure 1 is a step flow chart of a cascade construction method of an interrupt controller provided by an embodiment of the present application, which can be applied to an electronic device, wherein the electronic device is configured with a set of interrupt controllers, and the set of interrupt controllers includes interrupt controllers respectively deployed in a chipset and a central processing unit (CPU) of the electronic device, as shown in Figure 1 , the method can include:

[0027] In step 101, cascade information of each interrupt controller is acquired as a set of cascade information, wherein the cascade information is generated according to a data structure corresponding to the interrupt controller.

[0028] In the embodiment of the present application, the interrupt controller can also be referred to as a programmable interrupt controller (PIC). The electronic device can be a mobile phone, a computer, or other computing device. The cascade information set in the embodiment of the present application can include cascade information of each interrupt controller. Further, in the embodiment of the present application, the cascade information can be generated directly according to the data structure corresponding to the interrupt controller to implement the obtaining operation. Alternatively, the cascade information can be generated in advance according to the data structure and stored in the electronic device in advance. Accordingly, the obtaining operation can be implemented by reading the cascade information of each interrupt controller generated in advance, thereby ensuring the obtaining efficiency.

[0029] In step 102, it is detected whether the first interrupt controller deployed in the CPU is included in the set of interrupt controllers.

[0030] In the embodiment of the present application, if the first interrupt controller is included in the set of interrupt controllers, it can be indicated that the first interrupt controller is deployed in the CPU currently used by the electronic device. If the first interrupt controller is not included in the set of interrupt controllers, it can be indicated that the first interrupt controller is not deployed in the CPU currently used by the electronic device. Since the hardware structure used by the electronic device can be different, for example, some electronic devices use an old version of CPU, and some electronic devices use a new version of CPU, therefore, the first interrupt controller can be deployed in the CPU of some electronic devices. The first interrupt controller is not deployed in the CPU of some electronic devices.

[0031] For example, it can be detected whether a specified register in the CPU is enabled. The specified register can be a pre-set function register, and the embodiment of the present application does not limit this. If the specified register is enabled, it can be determined that the first interrupt controller is deployed in the CPU. If the specified register is not enabled, it can be determined that the first interrupt controller is not deployed in the CPU.

[0032] In step 103, in the case where the first interrupt controller is included, the specified interrupt controller in the chipset is cascaded with the first interrupt controller according to the cascade information set.

[0033] In step 104, in the case where the first interrupt controller is not included, the specified interrupt controller is cascaded with the second interrupt controller in the CPU according to the cascade information set.

[0034] In the embodiment of the present application, the first interrupt controller and the second interrupt controller can be different types of interrupt controllers. The first interrupt controller can be set according to actual needs. For example, an interrupt controller with higher processing performance can be set as the first interrupt controller, or an interrupt controller with more available connection bits can be set as the first interrupt controller, and the embodiment of the present application does not limit this. The connection priority of the first interrupt controller can be higher than the connection priority of the second interrupt controller. That is, in the case where the first interrupt controller is deployed in the CPU, the cascade between the specified interrupt controller and the first interrupt controller is preferentially built.

[0035] To sum up, the cascade building method of the interrupt controller provided by the embodiment of the present application acquires the cascade information of each interrupt controller as a cascade information set; the cascade information is generated according to the data structure corresponding to the interrupt controller. It is detected whether the first interrupt controller deployed in the CPU is included in the interrupt controller set. In the case where the first interrupt controller is included, the specified interrupt controller in the chipset is cascaded with the first interrupt controller according to the cascade information set. In the case where the first interrupt controller is not included, the specified interrupt controller is cascaded with the second interrupt controller in the CPU according to the cascade information set. In the embodiment of the present application, according to the actual hardware structure of the electronic device, the cascade between the interrupt controller in the chipset and the CPU is built, that is, based on whether the first interrupt controller is deployed in the CPU of the electronic device, the cascade between the specified interrupt controller in the chipset and the interrupt controller in the CPU is built, and then the cascade building can be realized, and to some extent, the built interrupt controller cascade can be more adapted to the actual hardware situation of the electronic device, thereby ensuring the cascade building effect to some extent.

[0036] Optionally, in an implementation manner, the operation of acquiring the cascade information of each interrupt controller can specifically include: based on the basic input output system of the electronic device, setting specific values of data items defined in the data structure according to the data structure of the interrupt controller and related information of hardware in the electronic device, to generate the cascade information of each interrupt controller.

[0037] For example, in an application scenario, the electronic device can be a computer using the LoongArch architecture. The basic input output system (Basic Input Output System, BIOS) deployed in the electronic device can generate the cascade information of each interrupt controller in the startup link of the electronic device.

[0038] The data structure of the interrupt controller can be defined according to actual requirements, and can be defined in the BIOS or in a specified storage location of the electronic device for reading by the BIOS. Specifically, the data structure can be defined in a specified data table, such as a MADT table, and the embodiments of the present application do not limit this. For example, in an implementation scenario, the data structure of the interrupt controller can include a data structure of a processor core interrupt controller (CORE PIC), a data structure of a legacy input / output (Legacy Input / Output) interrupt controller (LIO PIC), a data structure of an extended IO interrupt controller (Extend Input / Output PIC, EIO PIC), a data structure of an HT interrupt controller (HyperTransport Programmable Interrupt Controller, HT PIC), a data structure of a bridge interrupt controller (Bridge I / O PIC, BIO PIC), a data structure of an MSI interrupt controller (Message Signaled Interrupt Programmable Interrupt Controller, MSI PIC), and a data structure of an LPC interrupt controller (Low Pin Count Programmable Interrupt Controller, LPC PIC). Further, the data structure of the interrupt controller can define data items required for generating cascade information of the interrupt controller to describe the cascade information. The data structures of different types of interrupt controllers can be different. Since the hardware conditions in different electronic devices can be different, for example, the models of the interrupt controllers used in different electronic devices can be different, and the available conditions of the CPUs can be different. Therefore, the related information of the hardware can be different. The related information of the hardware can be understood as the related information of the central processing unit (CPU) configured in the electronic device, the related information of the interrupt controller, and the like. In the embodiments of the present application, based on the related information of the hardware in the electronic device currently required to construct the cascade, the specific values of the data items defined in the data structure are adaptively set to generate the cascade information of each interrupt controller, which can realize flexible generation of the cascade information to a certain extent, so that the subsequent operation of constructing the interrupt controller cascade can be more flexible.

[0039] Further, in the embodiments of the present application, after the specific values of the data items defined in the data structure are set, the set data items in the data structure are converted into binary data to obtain the cascade information of the interrupt controller.

[0040] In the embodiment of the present application, based on the basic input and output system of the electronic device, according to the data structure of the interrupt controller and the related information of the hardware in the electronic device, the specific value of the data item defined in the data structure is set to generate the cascade information of each interrupt controller. Compared with the way of writing fixed cascade information in the kernel in advance and constructing fixed cascade relationship according to the fixed cascade information each time, in the embodiment of the present application, the adaptive cascade information can be generated flexibly based on the predefined data structure according to the actual situation of the hardware of the electronic device, so that the cascade can be constructed based on the cascade information generated each time, thereby the flexibility of constructing the cascade of the interrupt controller can be improved to a certain extent.

[0041] Meanwhile, when adjustment is needed, the kernel code needs to be modified correspondingly in the related technology to realize the modification of the fixed cascade information defined in the kernel. In the embodiment of the present application, only the data structure needs to be modified, and then the cascade information generated subsequently can be adjusted, thereby it can be ensured that the cascade information can be flexibly extended.

[0042] Optionally, the step of setting the specific value of the data item defined in the data structure according to the data structure of the interrupt controller and the related information of the hardware in the electronic device can specifically include:

[0043] In the case that the superior controller connection item is defined in the data structure, the specific value of the superior controller connection item is set according to the first connection bit information of the currently available connection bit of the superior interrupt controller to which the interrupt controller needs to be connected.

[0044] In the embodiments of the present application, the superior controller connection item can be used to describe how the interrupt controller is connected with the superior interrupt controller, for example, to describe which connection bit of the interrupt controller is connected with which connection bit of the superior interrupt controller. The connection bit of the interrupt controller can also be understood as a bit provided by the interrupt controller, and the superior controller can also be understood as an upstream controller. The superior interrupt controller required to be connected can be predefined in a data structure. Further, in actual application scenarios, the states of the connection bits in the superior interrupt controller required to be connected can be different, for example, some connection bits are occupied, or are malfunctioned and cannot be connected, which can all result in that the current connection cannot be used. Therefore, the related information of the hardware in the embodiments of the present application can include first connection bit information of the currently available connection bits of the superior interrupt controller required to be connected. Accordingly, by acquiring the connection bit information of the currently available connection bits of the superior interrupt controller, it can be ensured that the specific value set for the superior controller connection item is valid, so that the subsequent cascading operation can be smoothly performed. The connection bit information can be a connection bit number, the connection bit can be a pin, and the connection bit number can specifically be a pin number. It should be noted that one pin can represent one vector, and accordingly, the connection bit information can also be referred to as vector information, an interrupt vector, a vector, or a vector number, and the like.

[0045] For example, for the HT PIC, the superior interrupt controller can be the LIO PIC, the superior controller connection item can include a "Cascade Vector", and the nth byte of the "Cascade Vector" can represent the HT PIC interrupt vector of 32*n~31*(n+1) routed to the interrupt vector of the LIO PIC, that is, the "Cascade Vector" can be used to describe the connection of each 32 connection bits of the HT PIC to the common connection bits in the LIO PIC. For the LPC PIC, the superior interrupt controller can be the BIO PIC, and the superior controller connection item "Cascade Vector" defined in the data structure of the LPC PIC can be used to describe the BIO PIC vector number of the LPC PIC routed to the BIO PIC, that is, to describe which connection bit of the LPC PIC is connected to which connection bit of the BIO PIC. For the EIO PIC, the superior interrupt controller can be the CORE PIC, and the superior controller connection item "Cascade Vector" defined in the data structure of the EIO PIC can be used to describe the CORE PIC vector number of the EIO PIC routed to the CORE PIC, that is, to describe which connection bit of the EIO PIC is connected to which connection bit of the CORE PIC. Specifically, the specific value of the "Cascade Vector" can be set as the first connection bit information. It should be noted that when the vector number of the superior interrupt controller set in the "Cascade Vector" is not less than the interrupt controller of the current level, the connection bits in the interrupt controller of the current level can be connected to the connection bits of the superior interrupt controller one by one, otherwise, a many-to-one connection mode can be used.

[0046] In step S32, when the CPU connection item is defined in the data structure, the available state information and ID information of the CPU in the electronic device are acquired, and based on the available state information and ID information of the CPU, the specific value of the CPU connection item is set.

[0047] In actual application scenarios, some interrupt controllers need to be connected with other interrupt controllers, and some interrupt controllers can be directly connected with CPUs, that is, a CPU connection item can be defined in the data structure. In an implementation manner, the CPU connection item can be used to describe a processor core UID and a CPU core physical ID required to be connected by the interrupt controller. The processor core UID can be the same as a UID value in a preset differentiated system description table (DSDT) object. For example, for the data structure of the CORE PIC, the data structure of the CORE PIC can be defined with "ACPI ProcessorID" and "Physical Processor ID". Specifically, the CPU available state information and the ID information are used as related information of hardware in the electronic device, in this step, the currently available CPU can be determined according to the CPU available state information, and the specific value of the CPU connection item is set based on the physical ID and the UID of the CPU core of the currently available CPU, for example, the physical ID and the UID of a CPU core of an optional currently available CPU are selected, and the specific value of "Physical Processor ID" and the specific value of "ACPI ProcessorID" are filled respectively, so as to ensure that the set specific value is valid and ensure that the subsequent operation can be smoothly performed. One CPU core can correspond to one CORE PIC, and of course, multiple CPU cores can share one CORE PIC, and the embodiment of the present application does not limit this.

[0048] The data structure can also be defined with a flag item (Flags) of the CORE PIC. The "Flags" can specifically include a CPU available state flag item and a CORE PIC state flag item. The CPU available state flag item can be represented as "Enabled", and the CORE PIC state flag item can be represented as "Reserved". After the specific value of the CPU connection item of the CORE PIC is set based on the ID information of the available CPU, the specific value of "Enabled" can be set as 1, indicating that the CPU is available. When the CPU connected with the CORE PIC is unavailable, for example, when a fault occurs, and the available CPU is insufficient to cause the unavailable CPU connected with the CORE PIC, the specific value of "Enabled" can be set as 0, indicating that the CPU is unavailable. Further, after the specific value of the CPU connection item of the CORE PIC is set, the specific value of "Reserved" can be set as 0, otherwise no setting is performed, that is, the specific value of "Reserved" must be 0.

[0049] Further, in an implementation, for the BIO PIC, the CPU connection item can be a "Hardware ID", and the "Hardware ID" can be used to describe the node number of the CPU node connected in the chipset where the BIO PIC is located. Specifically, according to the CPU available state information, one CPU node can be selected from the currently available CPUs in the chipset where the BIO PIC is located, and the node number of the CPU node is set as the specific value of the "Hardware ID", so as to facilitate subsequent cascading of the BIO PIC with the upper controller in the CPU indicated by the specific value of the "Hardware ID".

[0050] In the embodiments of the present application, by defining the upper controller connection item or the CPU connection item in the data structure, and in the case where the data structure is defined with the upper controller connection item, the specific value of the upper controller connection item is set according to the first connection bit information of the currently available connection bit of the upper interrupt controller required to be connected by the interrupt controller. In the case where the data structure is defined with the CPU connection item, the CPU available state information and the ID information in the electronic device are obtained, and the specific values of the CPU connection item and the identification bit item are set based on the CPU available state information and the ID information. In this way, by setting the specific values of these items, it can be ensured to some extent that the interrupt controller cascade can be successfully constructed based on the generated cascade information subsequently.

[0051] Optionally, the operation of setting the specific value of the upper controller connection item according to the first connection bit information of the currently available connection bit of the upper interrupt controller required to be connected by the interrupt controller can specifically include:

[0052] Step S41, determining the second connection bit information of the interrupt controller corresponding to the same available connection bit in the upper interrupt controller, and setting the specific value of the upper controller connection item based on the first connection bit information and the second connection bit information.

[0053] In the embodiments of the present application, the upper controller connection item can be specifically used to describe which connection bits of the interrupt controller are connected with which connection bit in the upper interrupt controller. The connection bit indicated by the second connection bit information is the connection bit in the interrupt controller, and the connection bit indicated by the first connection bit information is the connection bit in the upper interrupt controller. In this implementation, the upper controller connection item can include a data item for describing the information of the second connection bit routed to the upper controller, and a data item for describing the information of the first connection bit connected in the upper controller.

[0054] For example, the interrupt controller can be an LIO PIC, and the required upper-level controller can be a CORE PIC. The upper-level controller connection item can include "Cascade vector" and "Cascade vector mapping". The "Cascade vector" describes the vector information routed from the LIO PIC to the CORE PIC, with each byte representing a CORE PIC vector number. The "Cascade vector mapping" describes the LIO PIC vector information routed to the CORE PIC. The CORE PIC vector is specified by the Cascade vector field. The LIO PIC vector set in the high 4 bytes of the "Cascade vector mapping" corresponds to the CORE PIC vector described in the high byte of the Cascade vector field, and the LIO PIC vector in the low 4 bytes corresponds to the CORE PIC vector described in the low byte of the Cascade vector field. In other words, the second connection bit defined in the high 4 bytes of the "Cascade vector mapping" is connected to the first connection bit defined in the high byte of the "Cascade vector," and the second connection bit defined in the low 4 bytes of the "Cascade vector mapping" is connected to the first connection bit defined in the low byte of the "Cascade vector." This implementation can route multiple connection bits to the same connection bit of the upper-level interrupt controller, thus saving resources to some extent.

[0055] Alternatively, in step S42, the first connection bit information is used to characterize the connection start position, and the number of connection bits contained in the interrupt controller is detected. Based on the first connection bit information and the number of connection bits, the specific value of the connection item of the upper-level controller is set.

[0056] In the embodiment of the present application, the superior controller connection item is specifically used to describe which connection bit of the superior interrupt controller starts to connect, and the number of connection bits required by the current interrupt controller. Accordingly, when cascading, the connection bits in the current interrupt controller can be connected with the connection bits of the superior interrupt controller one by one from the connection start position. For example, the current interrupt controller can be an MSI PIC, and the superior interrupt controller can be an HT PIC or an EIO PIC. The superior controller connection item can include "Start" and "Count", "Start" can be used to describe the start vector (i.e., the first connection bit information) of the MSI in the HT PIC or the EIO PIC, and "Count" can be used to describe the number of MSI vectors (i.e., the number of connection bits). In the implementation, a single connection bit can be mapped to a connection bit of the superior interrupt controller one by one, so that the burden of a single connection bit can be reduced in the case of sufficient resources. It should be noted that the specific values of the first connection bit information and the number of connection bits can be set based on the actual design of the hardware. That is, the specific values of "Start" and "Count" can be read, and the values of "Start" and "Count" can be set, and the embodiment of the present application does not limit this.

[0057] Optionally, in the case that the interrupt message target address item is also defined in the data structure, the embodiment of the present application can also perform the following steps:

[0058] In step S51, a preset address value is obtained to set the specific value of the interrupt message target address item.

[0059] Specifically, the interrupt message target address item can be "Message Address", which can be defined in the data structure of the MSI PIC. "Message Address" can be used to describe the target address of the MSI message, i.e., to describe the address to which the interrupt message sent by each external device managed by the MSI PIC is sent. The preset address value can be set based on the actual hardware design, and accordingly, the address value can be set as the specific value of "Message Address". In the embodiment of the present application, by defining the interrupt message target address item in the data structure and setting the interrupt message target address item as the target address of the interrupt message of the external device, it can be ensured that the interrupt message of the external device can be successfully transmitted, thereby ensuring normal response to the interrupt.

[0060] Optionally, in the case that the connected upper controller is connected with the CPU, the data structure can also be defined with a processor node item, and accordingly, the embodiment of the application can also perform: in step S51, setting the specific value of the processor node item according to the relevant information of the CPU connected with the upper controller. Wherein, the processor node item can specifically include the "Node" and "Node map" defined in the data structure of the EIOPIC. The "Node" is used to describe the processor node ID connected with the chipset, that is, to describe the ID of the CPU node to which the CPU core connected with the CORE PIC is connected. The "Node map" is used to describe the processor node group of the EIO interrupt routing, that is, to describe the ID of the processor node group to which the processor node to which the CPU core connected with the CORE PIC is connected belongs, and the 0-63 bits of the "Node map" can respectively represent 0-63 nodes. In the embodiment of the application, by defining the processor node item in the data structure, the finally generated cascading information can represent the CPU connected with the connected upper controller and the node group to which it belongs, and further provide more information for the cascading construction operation, thereby improving the cascading construction efficiency to a certain extent.

[0061] Optionally, in the case that there are at least two possible situations of the register base address and the register space size corresponding to the interrupt controller, the data structure can further define a base address item and a space size item. Accordingly, the embodiment of the present application can further perform: step S71, reading the model information of the interrupt controller configured in the electronic device, and setting the specific values of the base address item and the space size item according to the specific values of the base address and the space size corresponding to the model information. In the embodiment of the present application, the register base address and the register space size corresponding to some types of interrupt controllers (for example, CORE PIC, EIO PIC, MSI PIC) are general in the industry, that is, the register base address and the register space size corresponding to the interrupt controllers of this type are fixed, and there are no multiple situations. Accordingly, the data structure of these interrupt controllers can not define the base address item and the space size item. However, for LIO PIC, HT PIC, BIO PIC and LPC PIC, the specific models used are different, and the corresponding register base address and register space size are different. Therefore, the data structure of LIO PIC, HT PIC, BIO PIC and LPC PIC can all define a base address item (“Base Address”) and a space size item (“Size”). The “Base Address” can be used to describe the base address of the register, and the “Size” can be used to describe the size of the register space. Specifically, based on the read model information, the corresponding base address value and space size value can be found from the pre-set correspondence between the model information of the interrupt controller at the current level and the base address value and the space size value. The specific values of the base address item and the space size item are filled with the corresponding base address value and space size value found.

[0062] In the embodiment of the present application, in the case that there are at least two possible situations of the register base address and the register space size corresponding to the interrupt controller, the base address item and the space size item are defined in the data structure, and the model information of the interrupt controller actually configured in the electronic device is read, and the specific values of the base address item and the space size item are set according to the specific values of the base address and the space size corresponding to the model information, so that the base address and the space size adapted to the current hardware can be accurately set when the cascade is constructed subsequently, and thus the operation can be smoothly performed.

[0063] Optionally, in the case that the type item, the byte length item and the version item are also defined in the data structure, the embodiment of the present application can also perform: in step S81, reading the type information, the byte length information and the version number defined in the related information of the interrupt controller configured in the electronic device to set the specific values of the type item, the byte length item and the version item. Specifically, the data structure of CORE PIC, LIO PIC, EIO PIC, HT PIC, BIO PIC, MSI PIC and LPC PIC can all define the type item (“Type”), the byte length item (“Length”) and the version item (“Version”). Among them, “Type” can be used to describe the structure type, “Length” can be used to describe the structure byte length, and “Version” can be used to describe the version number. Specifically, the specific structure type, the structure byte length and the version number of the currently used interrupt controller can be determined from the specific information of the currently used interrupt controller in the electronic device to fill the type item, the byte length item and the version item respectively, thereby achieving the setting. In the embodiment of the present application, the type item, the byte length item and the version item are defined in the data structure, and the type information, the byte length information and the version number defined in the related information of the interrupt controller configured in the electronic device are read to set the specific values of the type item, the byte length item and the version item, so that the generated cascade information can be more rich, thereby improving the richness of the information.

[0064] Optionally, in the case that the interrupt source vector item is also defined in the data structure, the embodiment of the present application can also perform the following steps: S91, detecting the number of currently configured bridge chips in the electronic device, determining the GSI number of each interrupt source based on the number of bridge chips and the interrupt vectors of each interrupt source managed by the interrupt controller, to set the specific value of the interrupt source vector item. In the embodiment of the present application, the interrupt source vector item can be "GSI base", which can be defined in the data structure of the BIO PIC, and "GSI base" can be used to describe the GSI number of the start of the BIO PIC interrupt. For example, for the GSI number of each interrupt source, GSI number = GSI base + interrupt vector of the BIO PIC = 64 * number of currently configured bridge chips + the interrupt vector corresponding to the interrupt source in the BIO PIC. Wherein, the interrupt vector corresponding to each interrupt source in the BIO PIC can be pre-set. For example, assuming that the interrupt vector corresponding to the network card in the BIO PIC is 1, and the number of currently configured bridge chips is 1, then the GSI number of the network card can be 65. Accordingly, the interrupt vectors of each interrupt source managed by the BIO PIC can be filled as the specific value of the interrupt source vector item. In the embodiment of the present application, the interrupt source vector item is defined in the data structure, and the number of currently configured bridge chips in the electronic device is detected, the GSI number of each interrupt source is determined based on the number of bridge chips and the interrupt vectors of each interrupt source managed by the interrupt controller, to set the specific value of the interrupt source vector item, so that the generated cascade information can accurately represent the GSI number of each interrupt source, thereby ensuring the accuracy of the information.

[0065] It should be noted that the required byte size and byte offset of each data item can also be defined in the data structure. Accordingly, when the data structure of the interrupt controller is predefined, the data structure can be stored according to the byte size and byte offset. For example, in the data structure of the CORE PIC, the fields "Type", "Length", "Version", "ACPI Processor ID", "Physical Processor ID", "Flags" can be defined respectively, and the size of each field can be 1, 1, 1, 4, 4, 4 respectively, and the offset of each field can be 0, 1, 2, 3, 7, 11 respectively. The size and offset of the "Enabled" item in the "Flags" can be 1 and 0 respectively, and the size and offset of the "Reserved" item in the "Flags" can be 31 and 1 respectively. Further, in the data structure of the LIO PIC, the fields "Type", "Length", "Version", "Base Address", "Size", "Cascade vector", "Cascade vector mapping" can be defined respectively, and the size of each field can be 1, 1, 1, 8, 2, 2, 8 respectively, and the offset of each field can be 0, 1, 2, 3, 11, 13, 15 respectively. Further, in the data structure of the HT PIC, the fields "Type", "Length", "Version", "Base Address", "Size", "Cascade vector" can be defined respectively, and the size of each field can be 1, 1, 1, 8, 2, 8 respectively, and the offset of each field can be 0, 1, 2, 3, 11, 13 respectively. In the data structure of the EIO PIC, the fields "Type", "Length", "Version", "Cascade vector", "Node", "Node map" can be defined respectively, and the size of each field can be 1, 1, 1, 1, 1, 8 respectively, and the offset of each field can be 0, 1, 2, 3, 4, 5 respectively.

[0066] Further, the data structure of the MSI PIC can define domains of "Type", "Length", "Version", "Message Address", "Start", "Count" respectively, the size of each domain can be 1, 1, 1, 8, 4, 4 respectively, and the offset of each domain can be 0, 1, 2, 3, 11, 15 respectively. The data structure of the BIO PIC can define domains of "Type", "Length", "Version", "Base Address", "Size", "Hardware ID", "GSI base" respectively, the size of each domain can be 1, 1, 1, 8, 2, 2, 2 respectively, and the offset of each domain can be 0, 1, 2, 3, 11, 13, 15 respectively. The data structure of the LPC PIC can define domains of "Type", "Length", "Version", "Base Address", "Size", "Cascade vector" respectively, the size of each domain can be 1, 1, 1, 8, 2, 2 respectively, and the offset of each domain can be 0, 1, 2, 3, 11, 13 respectively.

[0067] The following describes an application scenario related to an embodiment of the present application. In a system having a plurality of interrupt controllers, related technologies directly use cascade information fixed in a kernel when acquiring the cascade information of the interrupt controllers. Thus, in the case of a change in hardware or the like requiring a change in information, the kernel needs to be modified, which limits flexible expansion of startup information and is not conducive to differentiated design of a computer system.

[0068] The cascade interrupt control system provided by the embodiment of the present application proposes a configurable data structure, defines the data structure of each interrupt controller, and describes operation information and cascade relationship of the interrupt controller. BIOS generates cascade information suitable for the specific situation of the current hardware based on the data structure, and delivers the cascade information to the operating system. Figure 2 is a delivery schematic diagram provided by the embodiment of the present application, as shown in Figure 2 After BIOS generates the cascade information based on the data structure of the interrupt controller, the cascade information is specifically delivered to the interrupt controller driver (PIC driver) of the operating system. The cascade information delivered by BIOS is parsed by the interrupt controller driver to construct the cascade relationship of the interrupt controllers. In this way, the problem of how to construct the cascade relationship of the interrupt controllers is solved, and the effect of dynamically constructing the cascade relationship of the interrupt controllers is achieved.

[0069] Optionally, the specified interrupt controller can include a third interrupt controller and a fourth interrupt controller. The step of cascading the specified interrupt controller in the chipset with the first interrupt controller according to the set of cascade information can specifically include:

[0070] In step 1031, the third interrupt controller is cascaded with the superior interrupt controller defined in the first cascade information according to the superior controller connection item in the first cascade information corresponding to the third interrupt controller in the set of cascade information.

[0071] In step 1032, the fourth interrupt controller is cascaded with the superior interrupt controller defined in the second cascade information according to the superior controller connection item in the second cascade information corresponding to the fourth interrupt controller in the set of cascade information; in the case of deploying the first interrupt controller in the CPU, the superior interrupt controller is the first interrupt controller.

[0072] In the set of cascade information, the interrupt controller cascade can be the cascade of a downstream interrupt controller to an upstream interrupt controller, and one interrupt managed by a downstream interrupt controller shares one or part of the interrupt source of an upstream interrupt controller, which can be referred to as the cascade of a downstream interrupt controller to an upstream interrupt controller. Specifically, the cascade information can be transmitted to the interrupt controller driver in the operating system of the electronic device to construct the interrupt controller cascade according to the cascade information. For example, the BIOS can send the generated cascade information of the interrupt controller to the interrupt controller driver of the operating system, and the interrupt controller driver constructs the interrupt controller cascade according to the cascade information. The operating system can be an operating system dependent on interrupt processing, and each interrupt controller can correspond to a respective interrupt controller driver. The interrupt controller driver can parse the cascade information of the interrupt controller, and accordingly construct the cascade relationship based on the parsed cascade information.

[0073] Specifically, the first cascade information corresponding to the third interrupt controller can be transmitted to the interrupt controller driver corresponding to the third interrupt controller, and the first cascade information is parsed by the interrupt controller driver to cascade the third interrupt controller with the first interrupt controller defined in the first cascade information according to the superior controller connection item in the first cascade information. The second cascade information corresponding to the fourth interrupt controller is transmitted to the interrupt controller driver corresponding to the fourth interrupt controller, and the second cascade information is parsed by the interrupt controller driver to cascade the fourth interrupt controller with the first interrupt controller defined in the second cascade information according to the superior controller connection item in the second cascade information. In this way, by cascading the third interrupt controller and the fourth interrupt controller in the chipset with the first interrupt controller in the CPU, the cascade between the interrupt controllers of the chipset and the CPU is realized, so that the interrupt information can be transmitted between the chipset and the CPU.

[0074] Further, in the case that the first interrupt controller is not included, the specified interrupt controller can be cascaded with the second interrupt controller in the CPU according to the cascade information set. Specifically, the first cascade information corresponding to the third interrupt controller can be transmitted to the interrupt controller driver corresponding to the third interrupt controller, and the first cascade information is parsed by the interrupt controller driver to cascade the third interrupt controller with the second interrupt controller defined in the first cascade information according to the superior controller connection item in the first cascade information. The second cascade information corresponding to the fourth interrupt controller can be transmitted to the interrupt controller driver corresponding to the fourth interrupt controller, and the second cascade information is parsed by the interrupt controller driver to cascade the fourth interrupt controller with the second interrupt controller defined in the second cascade information according to the superior controller connection item in the second cascade information. The first interrupt controller can be an EIO PIC, the second interrupt controller can be an HT PIC, the third interrupt controller can be a BIO PIC, and the BIO PIC can be used to manage the interrupt information of the specified device integrated in the chipset, such as the hard disk controller, the network card controller, etc. integrated in the chipset. The fourth interrupt controller can be an MSI PIC, and the MSI PIC can be responsible for processing the information sent by the device connected based on the peripheral component interconnect standard (PCI / PCIE).

[0075] It should be noted that for the BIO PIC, the specific value of the superior controller connection item in the cascade information of the BIO PIC can be pre-set, and the specific value of the superior controller connection item can be the pin number in the specified range of the superior interrupt controller. For example, the specified range can be 0-63 bits. The superior interrupt controller can be an HT PIC or an EIO PIC. Specifically, in the case that the EIO PIC is deployed in the CPU, the specific value of the superior controller connection item in the first cascade information of the BIO PIC can be the pin number in the specified range of the EIO PIC, and in the case that the EIO PIC is not deployed in the CPU, the specific value of the superior controller connection item in the first cascade information of the BIO PIC can be the pin number in the specified range of the HT PIC. That is, in the case that the EIO PIC is deployed, the superior controller connection item defined in the first cascade information and the second cascade information is the connection item in the EIO PIC. In the case that the EIO PIC is not deployed, the superior controller connection item defined in the first cascade information and the second cascade information is the connection item in the HT PIC.

[0076] Optionally, the embodiment of the present application can further perform the following operation: in step S111, cascading the interrupt controllers in the chip set according to the set of cascade information, and cascading the interrupt controllers in the CPU. For example, the CPU can further deploy a fifth interrupt controller and a sixth interrupt controller; the step of cascading the interrupt controllers in the CPU can specifically include:

[0077] In step S111a, cascading the second interrupt controller and the fifth interrupt controller according to the superior controller connection item in the third cascade information corresponding to the second interrupt controller in the set of cascade information.

[0078] In the embodiment of the present application, the fifth interrupt controller can be an LIO PIC. For example, the third cascade information corresponding to the second interrupt controller can be transmitted to the interrupt controller driver corresponding to the second interrupt controller, so as to realize the cascading of the HT PIC to the LIO PIC.

[0079] In step S111b, respectively cascading the fifth interrupt controller and the first interrupt controller and the sixth interrupt controller according to the superior controller connection item in the fourth cascade information corresponding to the fifth interrupt controller and the superior controller connection item in the fifth cascade information corresponding to the first interrupt controller in the set of cascade information.

[0080] In the embodiment of the present application, the sixth interrupt controller can be a CORE PIC. For example, the fourth cascade information corresponding to the fifth interrupt controller can be transmitted to the interrupt controller driver corresponding to the fifth interrupt controller, and the fifth cascade information corresponding to the first interrupt controller can be transmitted to the interrupt controller driver corresponding to the first interrupt controller, so as to realize the cascading of the LIO PIC and the EIO PIC to the CORE PIC.

[0081] In step S111c, connecting the sixth interrupt controller and the corresponding CPU core in the electronic device according to the CPU connection item in the sixth cascade information corresponding to the sixth interrupt controller in the set of cascade information.

[0082] For example, the sixth cascade information corresponding to the sixth interrupt controller can be transmitted to the interrupt controller driver corresponding to the sixth interrupt controller, so as to realize the connection of the CORE PIC and the CPU core indicated by the CPU connection item. In this way, by cascading the interrupt controllers in the CPU, the cascade between the interrupt controllers in the CPU can be realized, so that the interrupt controllers in the CPU can transmit interrupt information.

[0083] In the embodiment of the present application, the EIO PIC is directly connected with the CORE PIC connected with the CPU core. Therefore, in the case that the EIO PIC is deployed in the CPU, the EIO PIC is connected preferentially, and the transmission efficiency of the interrupt information of the BIO PIC and the MSI PIC can be ensured to a certain extent.

[0084] Optionally, the chip set further comprises a seventh interrupt controller. Accordingly, the operation of cascading the interrupt controllers in the chip set according to the cascade information set can specifically include: cascading the seventh interrupt controller and the third interrupt controller according to the upper controller connection item in the seventh cascade information corresponding to the seventh interrupt controller in the cascade information set. The seventh interrupt controller can be an LPC PIC, and the LPC PIC can be responsible for processing the interrupt information of specified devices, such as a PS / 2 mouse, a keyboard and a universal asynchronous receiver-transmitter (UART). The seventh cascade information corresponding to the seventh interrupt controller can be delivered to the interrupt controller driver corresponding to the seventh interrupt controller, so as to realize the cascading of the LPC PIC to the BIO PIC. In this way, by cascading the seventh interrupt controller and the third interrupt controller in the chip set, the cascade between the interrupt controllers in the chip set can be realized, so that the interrupt controllers in the chip set can transmit interrupt information.

[0085] Figure 3 is a schematic diagram of the cascade relationship of interrupt controllers provided by the embodiment of the present application, as shown in Figure 3 The HT PIC in the CPU can be cascaded to the LIO PIC, and the LIO PIC can be cascaded to the CORE PIC. The LPC PIC in the chip set (i.e. Figure 3 The LPC PIC in the chip set (i.e.

[0086] Further, taking the case that the LPC PIC, the BIO PIC, the MSI PIC, the HT PIC, the LIO PIC, the EIO PIC and the CORE PIC are deployed in the electronic device as an example, Figure 4 is another schematic diagram of the cascade relationship of interrupt controllers provided by the embodiment of the present application, as shown in Figure 4 The HT PIC in the CPU can be cascaded to the LIO PIC, and the LIO PIC can be cascaded to the CORE PIC, and the EIO PIC can be cascaded to the CORE PIC. The LPC PIC in the chip set can be cascaded to the BIO PIC. In the case that the EIO PIC is deployed in the CPU, the BIO PIC and the MSI PIC in the chip set are cascaded to the EIO PIC. It should be noted that,Figure 4 The solid line with the middle arrow represents a real established cascade, Figure 4 The dashed line with the middle arrow only represents one connection mode in the case that EIO PIC does not exist: BIO PIC and MSI PIC can be cascaded with HT PIC. Further, in the case that EIO PIC is deployed in the CPU, HT PIC can continue to be retained so as to manage other external interrupts based on HT PIC. Meanwhile, by retaining the original functions of HT PIC and LIO PIC, to some extent, it can be ensured that the operating system adapted for the old CPU can run well on the new CPU. Among them, the new CPU adds EIO PIC relative to the old CPU.

[0087] Figure 5 is a structural block diagram of a cascade construction device of an interrupt controller provided by an embodiment of the present application. The device can be applied to an electronic device, and the electronic device is configured with a set of interrupt controllers, which includes interrupt controllers respectively deployed in a chipset and a central processing unit (CPU) of the electronic device, as shown in the figure, the device 20 can include: Figure 5

[0088] An acquisition module 201 is configured to acquire cascade information of each interrupt controller as a set of cascade information, and the cascade information is generated according to a data structure corresponding to the interrupt controller;

[0089] A detection module 202 is configured to detect whether the set of interrupt controllers includes a first interrupt controller deployed in the CPU;

[0090] A first cascade module 203 is configured to, in the case that the first interrupt controller is included, cascade a specified interrupt controller in the chipset with the first interrupt controller according to the set of cascade information;

[0091] A second cascade module 204 is configured to, in the case that the first interrupt controller is not included, cascade the specified interrupt controller with a second interrupt controller in the CPU according to the set of cascade information.

[0092] ​The cascade construction apparatus of the interrupt controller provided in the embodiment of the present application acquires cascade information of each interrupt controller as a cascade information set; the cascade information is generated according to a data structure corresponding to the interrupt controller. It is detected whether the first interrupt controller deployed in the CPU is included in the interrupt controller set. In the case where the first interrupt controller is included, the specified interrupt controller in the chipset is cascaded with the first interrupt controller according to the cascade information set. In the case where the first interrupt controller is not included, the specified interrupt controller is cascaded with the second interrupt controller in the CPU according to the cascade information set. In the embodiment of the present application, the cascade between the interrupt controller in the chipset and the interrupt controller in the CPU is constructed according to the actual hardware structure of the electronic device, that is, based on whether the first interrupt controller is deployed in the CPU of the electronic device, the cascade between the specified interrupt controller in the chipset and the interrupt controller in the CPU is constructed, and then the cascade construction can be realized, and to some extent, the constructed interrupt controller cascade can be more adapted to the actual hardware condition of the electronic device, so that the cascade construction effect can be ensured to some extent.

[0093] Optionally, the acquisition module 201 is specifically configured to:

[0094] The setting sub-module is configured to set specific values of data items defined in the data structure of the interrupt controller based on the basic input and output system of the electronic device and the related information of the hardware in the electronic device, so as to generate the cascade information of each interrupt controller.

[0095] Alternatively, the reading sub-module is configured to read the cascade information of each interrupt controller generated in advance.

[0096] Optionally, the setting sub-module is specifically configured to:

[0097] In the case where the superior controller connection item is defined in the data structure, the specific value of the superior controller connection item is set according to the first connection bit information of the current available connection bit of the superior interrupt controller required to be connected by the interrupt controller.

[0098] In the case where the CPU connection item is defined in the data structure, the available state information and ID information of the CPU in the electronic device are acquired, and the specific value of the CPU connection item is set based on the available state information and ID information of the CPU.

[0099] Optionally, the setting sub-module is further specifically configured to:

[0100] The second connection bit information corresponding to the same available connection bit in the superior interrupt controller in the interrupt controller is determined, and the specific value of the superior controller connection item is set based on the first connection bit information and the second connection bit information.

[0101] Or, the first connection position information is used to represent a connection start position, and the number of connection bits contained in the interrupt controller is detected, and based on the first connection position information and the number of connection bits, the specific value of the upper controller connection item is set.

[0102] Optionally, in the case that there are at least two possible cases of the register base address and the register space size corresponding to the interrupt controller, the data structure further defines a base address item and a space size item; the setting submodule is further used to:

[0103] Read the model information of the interrupt controller configured in the electronic device, and set the specific values of the base address item and the space size item according to the base address specific value and the space size specific value corresponding to the model information.

[0104] Optionally, in the case that the data structure further defines a type item, a byte length item and a version item, the setting submodule is further used to:

[0105] Read the type information, the byte length information and the version number defined in the related information of the interrupt controller configured in the electronic device, to set the specific values of the type item, the byte length item and the version item.

[0106] Optionally, in the case that the data structure further defines an interrupt source vector item, the setting submodule is further used to:

[0107] Detect the number of bridges currently configured in the electronic device, and determine the GSI number of each interrupt source based on the number of bridges and the interrupt vectors of each interrupt source managed by the interrupt controller, to set the specific value of the interrupt source vector item.

[0108] Optionally, the apparatus 20 further comprises:

[0109] A third cascading module is configured to cascade the interrupt controllers in the chip set according to the cascading information set, and cascade the interrupt controllers in the CPU.

[0110] Optionally, the specified interrupt controller comprises a third interrupt controller and a fourth interrupt controller; the first cascading module 203 is specifically used to:

[0111] Cascade the third interrupt controller with the upper interrupt controller defined in the first cascading information according to the upper controller connection item in the first cascading information corresponding to the third interrupt controller in the cascading information set;

[0112] According to a superior controller connection item in second cascade information corresponding to the fourth interrupt controller in the cascade information set, the fourth interrupt controller is cascaded with a superior interrupt controller defined in the second cascade information.

[0113] Wherein, in the case that a first interrupt controller is deployed in the CPU, the superior interrupt controller is the first interrupt controller.

[0114] Optionally, a fifth interrupt controller and a sixth interrupt controller are also deployed in the CPU; the third cascade module is specifically used for:

[0115] According to a superior controller connection item in third cascade information corresponding to the second interrupt controller in the cascade information set, the second interrupt controller is cascaded with the fifth interrupt controller.

[0116] According to a superior controller connection item in fourth cascade information corresponding to the fifth interrupt controller in the cascade information set and a superior controller connection item in fifth cascade information corresponding to the first interrupt controller, the fifth interrupt controller and the first interrupt controller are respectively cascaded with the sixth interrupt controller.

[0117] According to a CPU connection item in sixth cascade information corresponding to the sixth interrupt controller in the cascade information set, the sixth interrupt controller is connected with a corresponding CPU core in the electronic device.

[0118] Optionally, the chip set further includes a seventh interrupt controller; the third cascade module is further specifically used for:

[0119] According to a superior controller connection item in seventh cascade information corresponding to the seventh interrupt controller in the cascade information set, the seventh interrupt controller is cascaded with the third interrupt controller.

[0120] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts refer to the part of the method embodiment.

[0121] Figure 6 is a structural block diagram of an electronic device according to an exemplary embodiment. For example, the electronic device 400 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0122] Referring to Figure 6The electronic device 400 can include one or more of the following components: a processing component 402, a memory 404, a power supply component 406, a multimedia component 408, an audio component 410, an input / output (I / O) interface 412, a sensor component 414, and a communication component 416.

[0123] The processing component 402 typically controls overall operations of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 402 can include one or more processors 420 to execute instructions to complete all or part of steps of the above methods. In addition, the processing component 402 can include one or more modules to facilitate

[0124] The memory 404 is configured to store various types of data to support operations of the electronic device 400. Examples of these data include instructions for any application or method operating on the electronic device 400, contact data, phonebook data, messages, pictures, videos, and so on. The memory 404 can be realized by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic or optical disk.

[0125] The power supply component 406 supplies electrical power for the various components of the electronic device 400. The power supply component 406 can include a power supply management system, one or more power supplies, and other components associated with generating, managing and distributing electrical power for the electronic device 400.

[0126] The multimedia component 408 includes a screen to provide an output interface between the electronic device 400 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, or a gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or a sliding action, but also detect duration and intensity of the touching or sliding action. In some embodiments, the multimedia component 408 includes a front camera and / or a rear camera. When the electronic device 400 is in an operating mode, such as a camera mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zooming capability.

[0127] The audio component 410 is configured to output and / or input an audio signal. For example, the audio component 410 includes a microphone (MIC) to receive an external audio signal when the electronic device 400 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 404 or transmitted via the communication component 416. In some embodiments, the audio component 410 also includes a speaker to output an audio signal.

[0128] The I / O interface 412 provides an interface for the processing component 402 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0129] The sensor component 414 includes one or more sensors to provide various state assessments for the electronic device 400. For example, the sensor component 414 can detect an open / closed state of the electronic device 400, relative positioning of components, such as a display and a keypad of the electronic device 400, a change in position of the electronic device 400 or a component of the electronic device 400, presence or absence of user contact with the electronic device 400, an orientation or acceleration / deceleration of the electronic device 400, and a temperature change of the electronic device 400. The sensor component 414 can include a proximity sensor to detect presence of an object within a proximity of the electronic device 400 without any physical contact. The sensor component 414 can also include a light sensor, such as a CMOS or CCD image sensor, to use in an imaging application. In some embodiments, the sensor component 414 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0130] The communication component 416 is configured to facilitate wired or wireless communication between the electronic device 400 and other devices. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, 2G, or 3G, or a combination thereof. In an exemplary embodiment, the communication component 416 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 416 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technology.

[0131] In an exemplary embodiment, the electronic device 400 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic elements, for performing the above-described methods.

[0132] Preferably, the embodiments of the present application further provide an electronic device, including a processor, a memory, a computer program stored in the memory and executable in the processor, which, when executed by the processor, implements each process of the above-mentioned embodiments of the cascade construction method of the interrupt controller and achieves the same technical effects. To avoid repetition, details are not described herein.

[0133] The embodiments of the present application further provide a computer readable storage medium, which stores a computer program. The computer program, when executed by a processor, implements each process of the above-mentioned embodiments of the cascade construction method of the interrupt controller and achieves the same technical effects. To avoid repetition, details are not described herein. The computer readable storage medium includes, for example, Read-Only Memory (ROM), Random Access Memory (RAM), magnetic disk or optical disk, etc.

[0134] It should be noted that, in this document, the terms "comprising" and "including" or any other variant thereof are intended to cover a non-exclusive inclusion, such that processes, methods, articles, or devices that comprise a list of elements not only include those elements, but also include other elements not expressly listed or inherent to such processes, methods, articles, or devices. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or device including the element.

[0135] Those skilled in the art can clearly understand the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, also can be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application essentially or say the part of contribution to the prior art can be embodied in the form of software product, the computer software product is stored in a storage medium (such as ROM / RAM, magnetic disc, optical disc), including a number of instructions to make a terminal (may be a mobile phone, computer, server, air conditioner, or network equipment, etc.) executes the method described in various embodiments of the present application.

[0136] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-mentioned specific embodiments, the above-mentioned specific embodiments are only illustrative, but not restrictive, those skilled in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims, all of which belong to the protection of the present application.

Claims

1. A method of building a cascade of interrupt controllers, characterized in that, The method is applied to an electronic device, wherein a set of interrupt controllers are configured in the electronic device, and the set of interrupt controllers comprises interrupt controllers respectively deployed in a chipset and a central processing unit (CPU) of the electronic device, and the method comprises the following steps: obtaining cascade information of each interrupt controller as a set of cascade information; detecting whether a first interrupt controller deployed in the CPU is included in the set of interrupt controllers; in the case where the first interrupt controller is included, cascading a specified interrupt controller in the chipset with the first interrupt controller according to the set of cascade information; in the case where the first interrupt controller is not included, cascading the specified interrupt controller with a second interrupt controller in the CPU according to the set of cascade information; so that the constructed interrupt controller cascade is more suitable for the actual hardware condition of the electronic device.

2. The method of claim 1, wherein, The obtaining of the cascade information of each interrupt controller comprises the following steps: based on a basic input / output system (BIOS) of the electronic device, setting specific values of data items defined in a data structure of the interrupt controller according to the data structure and related information of hardware in the electronic device, to generate the cascade information of each interrupt controller; or, reading pre-generated cascade information of each interrupt controller.

3. The method of claim 2, wherein, The setting of the specific values of the data items defined in the data structure according to the data structure and related information of hardware in the electronic device comprises the following steps: in the case where a superior controller connection item is defined in the data structure, setting a specific value of the superior controller connection item according to first connection bit information of a currently available connection bit of a superior interrupt controller required to be connected by the interrupt controller; in the case where a CPU connection item is defined in the data structure, obtaining CPU available state information and ID information in the electronic device, and setting a specific value of the CPU connection item based on the CPU available state information and the ID information.

4. The method of claim 3, wherein, The setting of the specific value of the superior controller connection item according to the first connection bit information of the currently available connection bit of the superior interrupt controller required to be connected by the interrupt controller comprises the following steps: determining second connection bit information of the same available connection bit in the interrupt controller corresponding to the superior interrupt controller, and setting the specific value of the superior controller connection item based on the first connection bit information and the second connection bit information; or, taking the first connection bit information as a connection starting position, and detecting a number of connection bits contained in the interrupt controller, and setting the specific value of the superior controller connection item based on the first connection bit information and the number of connection bits.

5. The method of claim 3, wherein, in the case where at least two possible conditions exist for a register base address and a register space size corresponding to the interrupt controller, a base address item and a space size item are further defined in the data structure; and the method further comprises the following steps: Read the model information of the interrupt controller configured in the electronic device, and set the specific values of the base address item and the space size item according to the base address specific value and the space size specific value corresponding to the model information.

6. The method of claim 3, wherein, In the case where the data structure further defines a type item, a byte length item, and a version item, the method further comprises: Read the type information, the byte length information, and the version number defined in the related information of the interrupt controller configured in the electronic device, to set the specific values of the type item, the byte length item, and the version item.

7. The method of claim 3, wherein, In the case where the data structure further defines an interrupt source vector item, the method further comprises: Detect the number of bridges currently configured in the electronic device, determine the GSI number of each interrupt source based on the number of bridges and the interrupt vectors of each interrupt source managed by the interrupt controller, and set the specific values of the interrupt source vector item.

8. The method according to any one of claims 1 to 7, characterized in that, The method further comprises: Cascade the interrupt controllers in the chip set according to the cascade information set, and cascade the interrupt controllers in the CPU.

9. The method of claim 8, wherein, The specified interrupt controllers include a third interrupt controller and a fourth interrupt controller; and the cascading of the specified interrupt controllers in the chip set with the first interrupt controller according to the cascade information set comprises: Cascading the third interrupt controller with a superior interrupt controller defined in first cascade information corresponding to the third interrupt controller according to a superior controller connection item in the first cascade information in the cascade information set; Cascading the fourth interrupt controller with a superior interrupt controller defined in second cascade information corresponding to the fourth interrupt controller according to a superior controller connection item in the second cascade information in the cascade information set; In the case where a first interrupt controller is deployed in the CPU, the superior interrupt controller is the first interrupt controller.

10. The method of claim 9, wherein, The CPU further deploys a fifth interrupt controller and a sixth interrupt controller; and the cascading of the interrupt controllers in the CPU comprises: Cascading the second interrupt controller with the fifth interrupt controller according to a superior controller connection item in third cascade information corresponding to the second interrupt controller in the cascade information set; Cascading the fifth interrupt controller and the first interrupt controller with the sixth interrupt controller respectively according to a superior controller connection item in fourth cascade information corresponding to the fifth interrupt controller and a superior controller connection item in fifth cascade information corresponding to the first interrupt controller in the cascade information set; Cascading the sixth interrupt controller with a corresponding CPU core in the electronic device according to a CPU connection item in sixth cascade information corresponding to the sixth interrupt controller in the cascade information set.

11. The method of claim 9, wherein, The chip set further includes a seventh interrupt controller; and the cascading of the interrupt controllers in the chip set according to the cascade information set comprises: Cascading the seventh interrupt controller with the third interrupt controller according to a superior controller connection item in seventh cascade information corresponding to the seventh interrupt controller in the cascade information set.

12. A cascading building apparatus of an interrupt controller, characterized by, The application is applied to an electronic device, wherein a set of interrupt controllers are configured in the electronic device, the set of interrupt controllers include interrupt controllers respectively deployed in a chipset and a central processing unit (CPU) of the electronic device, and the device includes: An acquisition module is configured to acquire cascade information of each interrupt controller as a set of cascade information, wherein the cascade information is generated according to a data structure corresponding to the interrupt controller; A detection module is configured to detect whether the set of interrupt controllers includes a first interrupt controller deployed in the CPU; A first cascade module is configured to, in the case that the first interrupt controller is included, cascade a specified interrupt controller in the chipset with the first interrupt controller according to the set of cascade information; A second cascade module is configured to, in the case that the first interrupt controller is not included, cascade the specified interrupt controller with a second interrupt controller in the CPU according to the set of cascade information; The interrupt controller cascade is constructed to be more adaptive to the actual hardware condition of the electronic device.

13. An electronic device, comprising: The application includes: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to one or more of claims 1-11 when executing the program.

14. A readable storage medium, characterized by, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device can execute the method according to one or more of claims 1-11.

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