A microprocessor architecture and a microprocessor fault detection method

Abstract

This invention proposes a microprocessor architecture, including: a master core, a slave core, a bus, and a comparator. The master core and the comparator are communicatively connected to the bus, and the slave core is communicatively connected to the comparator. When the microprocessor is in lockstep mode, the comparator blocks the slave core's access requests to the bus. Both the master core and the slave core execute the master core's tasks. The comparator compares the master core's execution data with the slave core's execution data to detect faults in the execution status of the master core's tasks. The invention also provides a microprocessor fault detection method, including: setting the microprocessor's operating mode according to task requirements, including lockstep mode and non-lockstep mode; if the microprocessor is in lockstep mode, both the master core and the slave core execute the master core's tasks, and faults in the execution status of the master core's tasks are detected by comparing the master core's execution data with the slave core's execution data.

Description

Technical Field

[0001] This invention belongs to the field of microprocessor technology, and specifically relates to a microprocessor that uses light lockstep technology to improve reliability. Background Technology

[0002] Microprocessors are widely used in various fields, with critical sectors such as automotive, medical, and aerospace placing higher reliability demands on their design. As semiconductor technology advances, transistor sizes continue to shrink, making devices more sensitive to radiation, electromagnetic interference, and voltage fluctuations. This leads to frequent transient failures, potentially causing circuit failures and ultimately resulting in significant loss of life and property. Therefore, highly reliable designs are needed to detect faults during microprocessor operation, and fault recovery techniques are employed to ensure the correct and reliable operation of the microprocessor. Lockstepping technology detects faults by comparing the outputs of two or more identical functional modules, possessing strong fault detection capabilities and representing a promising design technique for improving microprocessor reliability.

[0003] Based on the source of the data compared during lockstep, locksteps can be categorized into pipelined state-level locksteps, instruction-level locksteps, core-level locksteps, and board-level locksteps. Pipeline state-level locksteps compare data at each stage of the core pipeline, while instruction-level locksteps compare the execution result of each instruction. Pipeline state-level and instruction-level locksteps offer faster fault detection speeds, but they involve comparing a large number of signals and require significant modifications to the processor, thus limiting their widespread adoption. Board-level locksteps compare the output of the on-chip system, requiring fewer hardware modifications and are easier to implement, but they cannot guarantee the time interval between fault occurrence and fault detection, making fault recovery difficult.

[0004] Core-level lockstepping typically includes dual-core lockstepping and multi-core lockstepping. In multi-core lockstepping, multiple cores execute the same instructions. A multiplexer votes on the outputs of the multiple processor cores, selecting the majority of the same output as the system output. When a minority of cores fail, the multiplexer disables these cores without affecting normal system operation. Core-level lockstepping, by comparing communication information between the core and the bus, requires less hardware support compared to pipelined state-level lockstepping and instruction-level lockstepping. Compared to board-level lockstepping, it has stronger fault detection capabilities and is therefore widely used in automotive electronics.

[0005] Pipeline state-level lockstepping requires adding comparators to each pipeline stage, which degrades processor core performance, necessitates significant core modifications, is difficult to implement, and incurs large area and power consumption overhead due to the numerous signals compared. Instruction-level lockstepping compares the execution results of each instruction, requiring extensive processor modifications and is also difficult to implement. Furthermore, since core faults do not necessarily cause errors, both methods result in a high false positive rate. The need to handle false positives further increases operational overhead. For board-level lockstepping, the time between fault occurrence and fault detection cannot be guaranteed, potentially allowing for significant intervals, thus compromising the ability of checkpoint rollback techniques to correctly recover from faults.

[0006] In core-level lockstepping, multi-core lockstepping offers strong fault detection and recovery capabilities, but requires multiple redundant processor cores to run the program simultaneously, resulting in significant overhead in terms of area and power consumption. In contrast, dual-core lockstepping uses two processor cores to run the program simultaneously, achieving fault detection by comparing the outputs of the processor cores. It offers similar fault detection capabilities and can perform fault recovery through relevant hardware and software technologies. Therefore, the less expensive dual-core lockstepping is more widely used.

[0007] In safety-critical real-time embedded systems such as automobiles and aircraft, the system architecture becomes increasingly complex as the number of applications increases. To improve performance, reduce costs, and ensure reliability, tasks of different critical levels are run simultaneously within a single system, a process known as a hybrid critical system. In a typical kernel-level lockstep, the slave kernel can only run in lockstep mode. For non-critical tasks, running them in lockstep mode would waste resources. Summary of the Invention

[0008] To address the aforementioned problems, this invention proposes a light lockstep microprocessor architecture, comprising: a master core, a slave core, a bus, and a comparator. The master core and the comparator are communicatively connected to the bus, and the slave core is communicatively connected to the comparator. When the microprocessor is in lockstep mode, the comparator blocks the slave core's access requests to the bus. Both the master core and the slave core run master core tasks. The comparator compares the master core's execution data with the slave core's execution data to detect the execution status of the master core's tasks. When the microprocessor is in non-lockstep mode, the comparator allows the slave core to directly access the bus. The master core executes master core tasks, and the slave core executes slave core tasks.

[0009] In the microprocessor architecture described in this invention, the master core's operating data includes a master core bus request, and the slave core's operating data includes a slave core bus request. The master core sends the master core bus request and receives a bus response via the bus. The slave core sends the slave core bus request to the comparator, which blocks and saves the slave core bus request. The comparator obtains the master core bus request from the bus and compares it with the slave core bus request. If the master core bus request and the slave core bus request are the same, the execution state of the master core task is considered normal, and the comparator obtains the bus response from the bus and sends it to the slave core. If the master core bus request and the slave core bus request are different, the execution state of the master core task is considered abnormal, and an interrupt is initiated for the master core task.

[0010] The microprocessor architecture of the present invention includes master core running data including master core register data and slave core running data including slave core register data. The microprocessor further includes: a master core compressor disposed on the connection path between the master core and the bus; and a slave core compressor disposed on the connection path between the slave core and the comparator. In each detection cycle, the master core compressor compresses the master core register data generated by the master core in the current detection cycle and sends it to the comparator; the slave core compressor compresses the slave core register data generated by the slave core in the current detection cycle and sends it to the comparator. The comparator compares whether the compressed master core register data and the compressed slave core register data are the same. If they are the same, the execution state of the master core task is considered normal; if they are different, the execution state of the master core task is considered abnormal, and an interrupt is initiated for the master core task.

[0011] In the microprocessor architecture described in this invention, when the microprocessor enters lockstep mode, the master core starts the master core compressor, the comparator controls the slave core to empty the processor of the slave core and start the slave core compressor, and the master core and the slave core start running the master core task.

[0012] This invention also proposes a microprocessor lockstepping method, comprising: a mode setting step, setting the microprocessor's operating mode according to task requirements, the operating mode including lockstep mode and non-lockstep mode; a first operating step, if the microprocessor is in lockstep mode, both the master core and slave core of the microprocessor execute the master core task, and the master core's operating data is compared with the slave core's operating data by the microprocessor's comparator to detect the execution status of the master core task; a second operating step, if the microprocessor is in non-lockstep mode, allowing the slave core to directly access the bus, and the master core executes the master core task, and the slave core executes the slave core task.

[0013] The microprocessor lockstep method of the present invention includes a master core running data including a master core bus request and a slave core running data including a slave core bus request. The first running step includes: a task running step in which the master core obtains a bus response according to the master core bus request; the slave core sends the slave core bus request to the comparator, and the comparator caches the slave core bus request; a first comparison step in which the master core bus request is compared with the slave core bus request; if they are the same, the execution state of the master core task is considered normal, and the comparator sends the bus response to the slave core; if they are different, the execution state of the master core task is considered abnormal, and the master core task is interrupted.

[0014] The microprocessor lockstep method of the present invention includes master core running data including master core register data and slave core running data including slave core register data. The first running mode step further includes: a second comparison step, wherein in each detection cycle, the master core register data generated by the master core in the current detection cycle is compressed, and the slave core register data generated by the slave core in the current detection cycle is compressed; the compressed master core register data is compared with the compressed slave core register data; if they are the same, the execution state of the master core task is considered normal; if they are different, the execution state of the master core task is considered abnormal.

[0015] The microprocessor lockstep method of the present invention includes a lockstep mode switching step, wherein the mode setting step includes a master core compressor, controlling the slave core to empty the processor of the slave core and start the slave core compressor, so that the master core and the slave core run the master core task synchronously.

[0016] This invention uses light lockstep technology to automatically detect faults that occur during the operation of a microprocessor, thereby improving the reliability of the microprocessor. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the microprocessor light lockstep architecture of the present invention.

[0018] Figure 2 This is a schematic diagram of the comparator structure of the present invention.

[0019] Figure 3 This is a flowchart of the configuration process for entering lockstep mode from the kernel in this invention.

[0020] Figure 4 This is a flowchart of the configuration of the present invention entering non-lockstep mode from the kernel.

[0021] Figure 5 This is a schematic diagram of the bus data flow of the present invention.

[0022] Figure 6 This is a flowchart of the bus request process of the present invention.

[0023] Figure 7 This is a schematic diagram of the compressor structure of the present invention.

[0024] Figure 8 This is a flowchart of the register comparison process of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0026] Based on the importance of tasks and the harm they would cause to the system if they failed, tasks can be classified into criticality levels. For example, in an automotive system, the failure of a high-criticality task could lead to a fatal accident, while the failure of a low-criticality task might not affect the safety of the vehicle or its occupants. In a mixed-criticality system, tasks of different criticality levels run simultaneously. When a fault is detected during the execution of a low-criticality task, restarting the system to resolve the issue would affect the execution of the high-criticality task, which is not feasible. Therefore, checkpoint rollback technology is needed to recover from faults. Checkpoint rollback technology saves the state of the processor and program to storage at regular intervals. When an error is detected, it recovers by rolling back to the previous state.

[0027] The setting of checkpoints is related to system performance. If the interval between checkpoints is too large, rolling back to the checkpoint when a fault is detected will require repeatedly running a long program segment, which will impact processor performance. Furthermore, setting checkpoints requires processor participation, and frequent checkpoint setting will also affect processor performance. Therefore, to reduce the performance impact of checkpoint rollback technology, a relatively large checkpoint interval can be set, and the new technology proposed below can be used to accelerate fault detection.

[0028] A fault may propagate directly to the bus and be exposed. If it is not exposed, the fault may be overwritten or propagated to a register and stored. A fault in a register may take many cycles to be exposed to the bus. To speed up the exposure of faults stored in registers, fault detection can be performed by periodically comparing the master core register data with the slave core register data, thereby shortening the time interval between fault occurrence and fault detection, and reducing the time spent on repeated program segments due to rollback. In this invention, the time interval between fault occurrence and fault detection is reduced by periodically compressing the master core register data and the slave core register data before transmitting them to a comparator for comparison.

[0029] If the register transfer frequency is too high, it will lead to excessive bus usage, affecting processor bus access and reducing processor performance; if the register transfer frequency is too low, it will result in a long time to detect faults, reducing fault detection speed. Therefore, a trade-off needs to be struck between fault detection speed and system performance. To reduce bus usage and speed up fault detection, this invention divides all registers into N groups, compresses each group of registers, and transfers the compressed content each time. Comparing the same number of registers requires only 1 / N bus usage times, thereby reducing the impact on processor performance. This method can speed up fault detection with minimal performance overhead.

[0030] To adapt to hybrid critical systems, this invention implements a lightweight lockstep method and a microprocessor architecture employing this method. This method configures the slave core to run in lockstep or non-lockstep mode via a bus to achieve rational resource allocation. Furthermore, to accelerate fault detection, a fault detection method is proposed that compresses the state of the processor registers before transmitting it to the bus for comparison.

[0031] To rationally allocate resources in hybrid critical systems and improve system performance while ensuring system reliability, efficient resource utilization can be ensured by switching slave cores to lockstep or non-lockstep modes. For example, non-critical tasks can run in non-lockstep mode, while critical tasks can run in lockstep mode. The lightweight lockstep method proposed in this invention connects the master and slave cores via a bus, allowing configuration of the slave core's operating mode. The slave core can run in a lockstep mode for fault detection or a non-lockstep mode for normal functionality. In lockstep mode, the slave core obtains memory access information from the master core, enabling both cores to run the same program. Simultaneously, a comparator blocks bus requests from the slave core and captures bus requests from the master core, comparing the requested address and data to detect potential faults. In non-lockstep mode, the slave and master cores operate independently, running their respective programs to improve system performance.

[0032] This invention configures the slave core's operating mode by treating the comparator as a peripheral. The master core controls the slave core's operating mode and synchronizes the operating modes of the two cores by reading and writing the comparator's status register through memory access instructions. Because the comparator is treated as a peripheral, this method allows for online configuration and synchronization of the slave core's operating mode via software. Since the comparator only connects to the slave core, this method is easily expandable in multi-core processors. Furthermore, this invention addresses lightweight locksteps by proposing a method to compress the register state before transmitting it to the bus for comparison, thus accelerating fault detection. Bus occupancy leads to processor performance degradation. As processor core functionalities become increasingly demanding, the number of registers also increases. Frequent bus occupancy significantly impacts processor performance; therefore, compressing the register state effectively reduces bus occupancy and minimizes performance impact.

[0033] Specifically, the microprocessor architecture of this invention mainly consists of a main core, a backup slave core, a comparator, and a compressor, such as... Figure 1 As shown. The master core, running a normal program (master core task), can configure and synchronize the comparator's operating mode online via memory access instructions. This allows the slave core to run in either a lockstep mode for fault detection or a non-lockstep mode for normal functionality. In lockstep mode, the slave core connects to the bus via the comparator. The comparator receives memory access information from the master core as input to the slave core, ensuring both run the same program. Simultaneously, the comparator blocks bus requests from the slave core and captures bus requests from the master core, obtaining the master core's memory access address and data to detect potential faults. To shorten the time from fault occurrence to fault detection, the master core compressor compresses the contents of the master core registers and transmits them to the comparator via the bus. The slave core compressor also compresses the contents of its registers and transmits them to the comparator. The comparator compares the register data of the master and slave cores, reducing the time overhead of data transmission and comparison. In non-lockstep mode, the comparator directly connects the slave core to the bus. In this mode, the slave and master cores operate independently, running their respective programs, thus improving system performance. This invention allows for flexible configuration of the slave core's operating mode, and by compressing the processor state and transmitting it to the bus for comparison, it achieves faster fault detection with a smaller bus footprint.

[0034] The comparator is used to control the operating mode of the slave core, and in lockstep mode, it compares the outputs and register states of the master and slave cores. Its structure is as follows: Figure 2As shown, the comparator consists of a bus slave node, a mode register, a ready register, a compression register, a buffer, and the comparator itself. The comparator is used to acquire bus requests from the master core to configure and synchronize the slave core's operating mode, or to compare it with the slave core's bus requests. The master core reads and writes to the mode register and ready register via bus requests to configure the slave core's operating mode and synchronize the operation of the master and slave cores in lockstep mode. In lockstep mode, the slave node acquires the slave core's bus request, stores it in a buffer, and after the bus slave node captures the master core's bus request, it compares the master core's bus request with the slave core's bus request using the comparator to detect faults. The compression register stores the slave core's processor state, waiting for the master core to transmit the processor state to the comparator via the bus for comparison.

[0035] The following examples illustrate the configuration and synchronization of the slave kernel running mode according to this invention.

[0036] To configure the slave core's operating mode and synchronize the master and slave cores, the master core needs to read and write the mode register and ready register in the comparator via the bus. The master core writes the status to the mode register via the bus, triggering an interrupt in the slave core. The slave core saves the previous program state through the interrupt handler, drains the processor, writes the ready status to the ready processor, and begins running a new program. The master core retrieves the status of the ready register via the bus; if it finds the program ready, it begins running the new program in lockstep mode.

[0037] The process of switching the kernel from non-lockstep mode to lockstep mode is as follows: Figure 3 As shown, 1) The master core sends a write status request to the comparator's status processor via the bus, writing the lock-step state. Afterward, the master core continuously sends bus requests to read the status of the ready processor. 2) The comparator accepts the write request, writes the status to its status register, and generates an interrupt to the slave core. 3) The slave core saves its current task state through the interrupt handler and drains the processor. 4) After draining the processor, the slave core writes a ready signal to the comparator's ready register via a bus write request. 5) The slave core modifies its status register to start the slave core compressor and begin running the new task. 6) The master core receives the slave core's ready signal, modifies its status register to start the master core compressor and begin running the new task.

[0038] The process of switching the kernel from lockstep mode to non-lockstep mode is as follows: Figure 4As shown, 1) The master and slave cores save the program state. 2) The master and slave cores stop the compressor. 3) The master core requests to write the non-locked-step state to the comparator status register via the bus. 4) Both the master and slave cores send bus requests to read the ready register. 5) The comparator accepts the request, writes the non-locked-step state, connects the slave core directly to the bus, and then sets the ready register to non-ready. 6) The master and slave cores read the ready register as non-ready and begin independent operation.

[0039] The following examples illustrate the behavior of the system in both non-lockstep and lockstep modes.

[0040] In non-lockstep mode, the master and slave cores operate independently. The comparator directly connects the slave core to the bus, allowing it to access the bus and run its own program. In lockstep mode, the master core runs the normal program, while the slave core repeats the master core's execution for fault detection. In lockstep mode, only the master core can access the bus to read and write to devices. The comparator captures the master core's read and write operations and compares them with those of the slave core. If they differ, an interrupt is generated, and the interrupt handler addresses the fault. The comparator listens for and captures bus input to the master core and sends the input to the slave core. For bus read and write requests from the slave core, the comparator compares the data to detect faults. The data stream is as follows: Figure 5 As shown. At the same time, the master core compresses the register state and transmits it to the comparator via the bus for comparison with the register state of the slave core, thereby speeding up fault detection.

[0041] In lockstep mode, a bus operation process is as follows: Figure 6 As shown: 1) The slave core's bus request is blocked by the comparator and stored in a buffer, waiting to be compared. 2) The master core requests bus access and sends a bus request. 3) The bus access request is simultaneously transmitted to the external device and the comparator. The comparator retrieves the slave core's bus request from the buffer and compares it with the master core's bus request. If they do not match, an interrupt is triggered for fault recovery; otherwise, operation continues. 4) The external device accepts the bus request, sends a bus response, and simultaneously sends it to the master core and the comparator. 5) The comparator sends the bus response to the slave core as its input.

[0042] The compressor includes a master core compressor and a slave core compressor, used to compress the processor's registers and transmit the compressed data to the bus for comparison. Its structure is as follows: Figure 7As shown, the compressor consists of a multiplexer, a controller, and compression logic. The compressor obtains the number of instructions submitted by the corresponding core. For every certain number of instructions submitted, the core compares the contents of a portion of its registers. The compressor accepts the contents of all registers, including integer registers, floating-point registers, and status and control registers such as CSRs. It divides the registers into N groups. For every M instructions submitted, it compresses the data in each group of registers sequentially. The slave core compressor compresses the data stored in the slave core's registers and transmits it to the comparator, storing it in the comparator's compression register. The master core compressor compresses the data stored in its registers and transmits it via the bus to the comparator for comparison with the compressed data from the slave core. Alternatively, the slave and master core register data can be compressed within a preset time period and then compared by the comparator; or a detection period can be specified by the master core, slave core, or comparator for comparing the compressed data. This detection period can be fixed or non-fixed, and the invention is not limited to this.

[0043] In lockstep mode, the process of compressing and transferring registers is as follows: Figure 8 As shown. 1) For every N instructions submitted by the slave core, the compressor compresses a set of register data and transfers the data to the comparator's compression register, storing the data for comparison with the master core. 2) When the master core submits the same number of instructions, it compresses the data in the same registers and transfers the data to the bus via a bus write operation. 3) The comparator captures the bus request, compares the data with the data in the compression register to detect faults. If they are different, an interrupt is triggered for fault recovery; if they are the same, operation continues.

[0044] Finally, in order to increase fault coverage, when grouping registers, registers with low fault correlation should be grouped together as much as possible to reduce the situation where faults occur simultaneously in different registers and are overwritten after compression.

[0045] In summary, this invention proposes a method for connecting a comparator as a peripheral device between the slave core and the bus to facilitate online configuration of the slave core's operating mode. Furthermore, it detects faults by compressing and transmitting register states to the bus for comparison, thereby accelerating fault detection with reduced bus usage.

[0046] This invention proposes a lightweight lockstep method that allows configuration of whether the slave core operates in lockstep mode. Lightweight lockstep further involves compressing the contents of multiple registers to be compared before transmitting them to the slave core via the bus for comparison, thereby accelerating fault detection. The proposed microprocessor architecture places the comparator between the slave core and the bus. By reading and writing the status register and ready register in the comparator, the slave core can be controlled to operate in either lockstep or non-lockstep mode. Critical tasks run in lockstep mode, while non-critical tasks run in non-lockstep mode, facilitating efficient resource allocation. The operating mode can be controlled via memory access instructions, reducing modifications to the proprietary core and facilitating expansion. To reduce the time interval between fault occurrence and fault detection, the proposed method compresses the contents of registers and sends them to the bus periodically, accelerating fault detection. To reduce the bus occupancy of the transmission registers, the contents of multiple registers are compressed, and the compressed results are transmitted and compared.

[0047] The above embodiments are only used to illustrate the present invention and are not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the present invention, and the patent protection scope of the present invention should be defined by the claims.

Claims

1. A microprocessor architecture, characterized in that, include: The system includes a master core, a slave core, a bus, a comparator, a master core compressor, and a slave core compressor. The master core and the comparator are respectively connected to the bus, and the slave core is connected to the comparator. The master core compressor is located on the connection path between the master core and the bus, and the slave core compressor is located on the connection path between the slave core and the comparator. When the microprocessor is in lockstep mode, the comparator blocks the slave core's access request to the bus. Both the master core and the slave core are running master core tasks. The comparator compares the master core's master core running data with the slave core's slave core running data to detect the execution status of the master core task. The master core's execution data includes master core bus requests and master core register data, while the slave core's execution data includes slave core bus requests and slave core register data. The master core sends the master core bus request and receives bus responses via the bus. The slave core sends the slave core bus request to the comparator, which blocks and buffers the slave core bus request. The comparator retrieves the master core bus request from the core bus and compares it with the slave core bus request. If they are the same, the execution status of the master core task is considered normal, and the comparator retrieves the bus response from the bus and sends it to the slave core. If they are different, the execution status is considered normal. If the execution status of the main core task is abnormal, an interrupt is initiated for the main core task. In each detection cycle, the main core compressor compresses the main core register data generated by the main core in the current detection cycle and sends it to the comparator. The slave core compressor compresses the slave core register data generated by the slave core in the current detection cycle and sends it to the comparator. The comparator compares whether the compressed main core register data and the compressed slave core register data are the same. If they are the same, the execution status of the main core task is considered normal. If they are different, the execution status of the main core task is considered abnormal, and an interrupt is initiated for the main core task.

2. The microprocessor architecture as described in claim 1, characterized in that, When the microprocessor enters lockstep mode, the master core starts the master core compressor, the comparator controls the slave core to empty the slave core processor and start the slave core compressor, and the master core and the slave core begin to run the master core task.

3. The microprocessor architecture as described in claim 1, characterized in that... When the microprocessor is in non-lockstep mode, the comparator enables the slave core to directly access the bus, the master core executes master core tasks, and the slave core executes slave core tasks.

4. A microprocessor fault detection method, used for fault detection of a microprocessor having the microprocessor architecture as described in any one of claims 1-3, characterized in that, include: The mode setting steps involve setting the operating mode of the microprocessor according to the task requirements. This operating mode includes lockstep mode and non-lockstep mode. In the first running step, if the microprocessor is in lockstep mode, both the main core and the slave core of the microprocessor execute the main core task. The main core running data of the main core is compared with the slave core running data of the slave core through the comparator of the microprocessor to detect the execution status of the main core task.

5. The microprocessor fault detection method as described in claim 4, characterized in that, The master core running data includes master core bus requests, and the slave core running data includes slave core bus requests; The first operating step includes: The task execution steps are as follows: the master core obtains the bus response according to the master core bus request; the slave core sends the slave core bus request to the comparator, and the comparator caches the slave core bus request; The first comparison step involves comparing the master core bus request with the slave core bus request. If they are the same, the execution status of the master core task is considered normal, and the comparator sends the bus response to the slave core. If they are different, the execution status of the master core task is considered abnormal, and an interrupt is initiated for the master core task.

6. The microprocessor fault detection method as described in claim 5, characterized in that, The master core's running data includes master core register data, and the slave core's running data includes slave core register data; This first operational step also includes: The second comparison step involves compressing the master core register data generated by the master core in the current detection cycle and compressing the slave core register data generated by the slave core in the current detection cycle in each detection cycle. The compressed master core register data is then compared with the compressed slave core register data. If they are the same, the execution status of the master core task is considered normal; if they are different, the execution status of the master core task is considered abnormal.

7. The microprocessor fault detection method as described in claim 6, characterized in that, The steps to set up this mode include: The lockstep mode switching steps involve starting the master core compressor, controlling the slave core to drain its processor, and starting the slave core compressor, so that the master core and the slave core can run the master core task synchronously.

8. The microprocessor fault detection method as described in claim 4, characterized in that, Also includes: In the second running step, if the microprocessor is in non-lockstep mode, the slave core directly accesses the bus, and the master core executes the master core task, while the slave core executes the slave core task.

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