Capacitor, method of manufacturing the same, and dram

Abstract

This invention relates to a capacitor, its manufacturing method, and DRAM, belonging to the field of semiconductor technology. It solves the problems of technical limitations in increasing the depth of existing contact holes and the increased size of memory cells due to widening. The method includes providing a semiconductor substrate; sequentially forming an etch stop layer and multiple stacked structure layers on the semiconductor substrate, each stacked structure layer including a molding layer and a support layer above the molding layer; etching the etch stop layer and the multiple stacked structure layers to form multiple trenches; forming a top protective layer on a top support layer and a portion of the top molding layer in the top stacked structure layer; etching back each support layer and a portion of the etch stop layer below the top stacked structure layer in the multiple trenches to recess the unprotected support layers, forming multiple diffusion trenches; and depositing a lower electrode layer in the multiple diffusion trenches. Recessing the unprotected support layers to form diffusion trenches increases the relative surface area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a capacitor, a method for manufacturing the same, and DRAM. Background Technology

[0002] Memory is a device or component in a digital system used to store large amounts of information, and it is an important part of computers and digital devices. Memory can be divided into two main categories: Random Access Memory (RAM) and Read-Only Memory (ROM). RAM includes DRAM, PRAM, MRAM, etc., and capacitors are one of the key components in the manufacture of these RAMs. Each memory cell in a DRAM device consists of 1T1C (i.e., one transistor and one capacitor).

[0003] DRAM capacitors are manufactured using a process called Storage Node (SN). (See reference...) Figure 1 In the ONO (oxide-nitride-oxide) structure of the support component in a cylindrical capacitor, ONON layers are repeatedly deposited, and then an etching process is used to form capacitor holes and the layered patterns between the capacitor holes. The layered patterns, from bottom to top, include an etching stop layer 102, an oxide layer 104, a nitride layer 106, an oxide layer 108, and a nitride layer 110. (Reference) Figure 2 After etching the nitride and oxide layers to form contact holes, a titanium nitride (TiN) 202 layer is deposited as the lower electrode. Next, a dielectric film and the upper electrode are deposited to complete the capacitor. The capacitance is the ratio of the area of ​​the upper / lower electrodes to the dielectric constant. To increase this value, the contact hole needs to be deeper or wider, or a film with a high dielectric constant needs to be used. However, there are technical limitations to increasing the contact hole depth and the dielectric constant of the dielectric film, and increasing the contact hole width will increase the size of the memory cell. Summary of the Invention

[0004] In view of the above analysis, the present invention aims to provide a capacitor and a method for manufacturing the same, as well as a DRAM, to solve the problems that existing methods of increasing the depth of contact holes and improving the dielectric constant of dielectric films have technical limitations, and that the width of contact holes increases the size of memory cells.

[0005] On one hand, embodiments of the present invention provide a method for manufacturing a capacitor, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes a plurality of storage nodes disposed in an insulating material layer and spaced apart by the insulating material layer; sequentially forming an etch stop layer and a plurality of stacked structure layers over the semiconductor substrate, each stacked structure layer including a molding layer and a support layer above the molding layer; etching the etch stop layer and the plurality of stacked structure layers to form a plurality of trenches; forming a top protective layer over a top support layer and a portion of the top molding layer in a top stacked structure layer; etching back each support layer below the top stacked structure layer and a portion of the etch stop layer in the plurality of trenches to recess the unprotected support layers, forming a plurality of enlarged trenches; and depositing a lower electrode layer in the plurality of enlarged trenches.

[0006] The beneficial effects of the above technical solution are as follows: with the top protective layer protecting the top support layer, a portion of each support layer below the top stacked structure layer is etched back, causing the unprotected support layers to be recessed, which can increase the relative area between the lower electrode layer and the upper electrode layer, thereby increasing the capacitance value.

[0007] A further improvement to the above method involves etching the etch stop layer and the plurality of stacked structure layers to form a plurality of trenches, comprising: etching the plurality of stacked structure layers using an etching process to form a plurality of stacked structure layer patterns having a plurality of first openings; and using the plurality of stacked structure layer patterns as a mask to etch the etch stop layer below the plurality of first openings to form a plurality of second openings passing through the etch stop layer, thereby exposing the top surface of the middle portion of the memory node, wherein the plurality of trenches pass through the plurality of stacked structure layers and the etch stop layer.

[0008] A further improvement to the above method involves forming a top protective layer over the top support layer and a portion of the top molding layer in the top stacked structure layer. This includes forming the top protective layer on the top surface and sidewalls of the top support layer and the sidewalls of the portion of the top molding layer in the top stacked structure layer by a deposition process, while leaving the remaining sidewalls of the plurality of stacked structure layers unformed. The thickness of the top protective layer at the top surface of the top support layer is greater than the thickness of the top protective layer at the sidewalls of the top support layer.

[0009] Based on a further improvement of the above method, the deposition gas forming the top protective layer includes CH2F2 or CH3F.

[0010] Based on a further improvement of the above method, the molding layer comprises an oxide; and the support layer and the etch stop layer comprise silicon nitride; wherein the thickness of the molding layer and the support layer is in the range of 10 nm to 100 nm.

[0011] A further improvement to the above method involves etching back a portion of each support layer and the etch stop layer below the top stacked structure layer in the plurality of trenches to recess the unprotected support layers. This includes etching back a portion of each support layer and the etch stop layer below the top stacked structure layer in the plurality of trenches that is not covered by the top protective layer with phosphoric acid until the entire top surface of the memory node is exposed, thereby recessing the unprotected support layers and the etch stop layer while keeping the molding layers unetched to form a plurality of enlarged trenches that are larger than the plurality of trenches. The amount of etching back is in the range of 2 nm to 10 nm.

[0012] Further improvements to the above method include depositing a lower electrode layer in the plurality of enlarged trenches by: removing the top protective layer on the top surface and sidewalls of the top support layer and on the sidewalls of a portion of the top molding layer by an etching process; and depositing the lower electrode layer on the exposed surfaces of each support layer, each molding layer and the etching stop layer in the plurality of enlarged trenches by a deposition process.

[0013] Based on a further improvement of the above method, after depositing the lower electrode layer, the method further includes: removing the remaining portion of the stacked structure layer, and forming a capacitor dielectric layer and an upper electrode layer on the inner and outer walls of the lower electrode layer.

[0014] Based on further improvements to the above method, the plurality of stacked structure layers includes more than four stacked structure layers.

[0015] On the other hand, embodiments of the present invention provide a capacitor, comprising: a semiconductor substrate; a lower electrode formed on the semiconductor substrate, wherein the lower electrode is a plurality of trench walls; a first dielectric layer located on the inner wall of the lower electrode; a first upper electrode located on the inner wall of the first dielectric layer, wherein the lower electrode, the first dielectric layer, and the first upper electrode constitute a first capacitor; a second dielectric layer located on the outer wall of an adjacent lower electrode; and a second upper electrode located on the inner wall of the second dielectric layer, wherein the lower electrode, the second dielectric layer, and the second upper electrode constitute a second capacitor; wherein the lower portion of the lower electrode includes one or more concave-convex structures, the first dielectric layer is conformal to the inner wall of the lower electrode, and the second dielectric layer is conformal to the outer wall of the lower electrode.

[0016] Based on further improvements to the above-mentioned device, the concave-convex structure includes at least three or more protrusions.

[0017] In another aspect, embodiments of the present invention provide a DRAM, comprising: a semiconductor substrate; a buried channel transistor located on the semiconductor substrate; a bit line structure electrically connected to an active region of the buried channel transistor; a memory node contact electrically connected to another active region of the buried channel transistor; and a capacitor according to the above description, the capacitor being electrically connected to the memory node contact.

[0018] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0019] 1. With the top protective layer protecting the top support layer, a portion of each support layer below the top stacked structure layer is etched back, causing the unprotected support layers to be recessed, which can increase the relative surface area between the lower electrode layer and the upper electrode layer, thereby increasing the capacitance value.

[0020] 2. The top protective layer protects the top support layer, preventing it from being etched during the etching process, thus maintaining the depth of the capacitor vias.

[0021] 3. By etching back the stop layer, the subsequent lower electrode layer can make contact with the entire top surface of the storage node, thereby improving the electrical characteristics of the capacitor.

[0022] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0023] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0024] Figure 1 This is a schematic diagram of the cross-section formed during the manufacturing process of an existing capacitor.

[0025] Figure 2 This is a schematic diagram of a cross-section formed during the manufacturing process of an existing capacitor, showing the formation of the lower electrode layer.

[0026] Figure 3 This is a cross-sectional schematic diagram of a capacitor according to an embodiment of the present invention.

[0027] Figure 4 This is a cross-sectional schematic diagram of an intermediate stage in the manufacturing process of a capacitor according to an embodiment of the present invention.

[0028] Figure 5 This is a cross-sectional schematic diagram of an intermediate stage in the manufacturing process of a capacitor according to an embodiment of the present invention.

[0029] Figure 6 This is a cross-sectional schematic diagram of an intermediate stage in the manufacturing process of a capacitor according to an embodiment of the present invention.

[0030] Figure 7 This is a cross-sectional schematic diagram of an intermediate stage in the manufacturing process of a capacitor according to an embodiment of the present invention. Detailed Implementation

[0031] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0032] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0033] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0034] refer to Figure 3A specific embodiment of the present invention discloses a capacitor. The capacitor is located on a semiconductor substrate, which may include a bottom semiconductor material layer and an upper insulating material layer 304. A plurality of memory nodes 302 (also referred to as contact pads) are disposed in the insulating material layer 304 and spaced apart from each other by the insulating material layer 304. A lower electrode 344 is formed on the semiconductor substrate, wherein the lower electrode is in the form of a plurality of trench walls. A first dielectric layer 346 is located on the inner wall of the lower electrode 344 and a first upper electrode 348 is located on the inner wall of the first dielectric layer 346, wherein the lower electrode 344, the first dielectric layer 346 and the first upper electrode 348 constitute the first capacitor. The second dielectric layer 350 is located on the outer wall of the adjacent lower electrode 344, and the second upper electrode 352 is located on the inner wall of the second dielectric layer 350. The lower electrode 344, the second dielectric layer 350, and the second upper electrode 352 constitute a second capacitor. The lower part of the lower electrode 344 includes one or more concave-convex structures. The first dielectric layer 346 is conformal to the inner wall of the lower electrode 344, and the second dielectric layer 350 is conformal to the outer wall of the lower electrode 344. In an optional embodiment, the concave-convex structure includes at least three or more protrusions.

[0035] Another specific embodiment of the present invention discloses a DRAM. The DRAM includes: a semiconductor substrate, a buried channel transistor located on the semiconductor substrate, a bit line structure electrically connected to one active region of the buried channel transistor, a memory node contact electrically connected to another active region of the buried channel transistor, and a capacitor described above electrically connected to the memory node contact.

[0036] Another specific embodiment of the present invention discloses a method for manufacturing a capacitor. Hereinafter, reference will be made to... Figures 4 to 7 The manufacturing method of capacitors is described in detail.

[0037] refer to Figure 4 A semiconductor substrate 300 is provided. The semiconductor substrate 300 includes a bottom semiconductor material layer and an upper insulating material layer 304. A plurality of memory nodes 302 are disposed in the insulating material layer 304 and spaced apart from each other by the insulating material layer 304. The material of the plurality of memory nodes 302 is tungsten (W), and the material of the insulating material layer 304 is silicon dioxide (SiO2). For simplified view, only... Figure 4 The image shows the bottom semiconductor material layer, in Figures 5 to 7 The semiconductor material layer at the bottom is not shown.

[0038] refer to Figure 4An etch stop layer 306 and multiple stacked structure layers are sequentially formed over a semiconductor substrate. Each stacked structure layer includes a molding layer and a support layer above the molding layer. For example, the multiple stacked structure layers include four or more stacked structure layers. In a specific embodiment, the top stacked structure layer includes a top molding layer 320 and a top support layer 322 above the top molding layer 320. The bottom stacked structure layer includes a bottom molding layer 308 and a bottom support layer 310 above the bottom molding layer 308. The first intermediate stacked structure layer includes a molding layer 316 and a support layer 318 above the molding layer 316. The second intermediate stacked structure layer includes a molding layer 312 and a support layer 314 above the molding layer 312. The molding layers 308, 312, 316, and 320 comprise oxide. The support layers 310, 314, 318, and 322 and the etch stop layer 306 comprise silicon nitride, wherein the thickness of the molding layer and the support layer is in the range of 10 nm to 100 nm. By adjusting the thickness of the molding layer and the support layer, the relative surface area between the lower electrode layer and the upper electrode layer can be adjusted, thereby regulating the capacitance value of the subsequently generated capacitor. The thickness of the top molding layer 320 is greater than the thickness of the molding layers 308, 312, and 316 below it, and the thickness of the top support layer 322 is greater than the thickness of the support layers 310, 314, and 318 below it. The number of stacked structural layers can be set or adjusted according to the actual required capacitor value.

[0039] Continue to refer to Figure 4 The etching process involves etching an etch stop layer 306 and multiple stacked structural layers to form multiple trenches 326, each trench corresponding to a multiple memory node. Specifically, etching the etch stop layer 306 and multiple stacked structural layers to form the trenches 326 includes: etching the multiple stacked structural layers using an etching process to form multiple stacked structural layer patterns with multiple first openings 324; and using the multiple stacked structural layer patterns as a mask, etching the etch stop layer below the multiple first openings 324 to form multiple second openings 328 through the etch stop layer, thereby exposing the top surface of the middle portion of the corresponding memory node 302. The trenches 326 pass through the multiple stacked structural layers and the etch stop layer 306. The bottom width of the trench is smaller than the top width of the trench. Each trench 326 includes a first opening 324 through the multiple stacked structural layers and a second opening 328 through the etch stop layer. The trenches 326 pass through four stacked structural layers and the etch stop layer 306 from top to bottom. Specifically, the trench 326 passes through the top support layer 322, the top molding layer 320, the support layer 318, the molding layer 316, the support layer 314, the molding layer 312, the bottom support layer 310, the bottom molding layer 308, and the etch stop layer 306 from top to bottom.

[0040] refer to Figure 5A top protective layer 340 is formed on the top support layer 322 and a portion of the top molding layer 320 in the top stacked structural layers. Specifically, forming the top protective layer 340 over the top support layer and a portion of the top molding layer in the top stacked structural layers includes: forming the top protective layer 340 on the top surface and sidewalls of the top support layer 322 and on the sidewalls of a portion of the top molding layer 320 in the top stacked structural layers by a deposition process in a process chamber, while leaving the remaining sidewalls of the multiple stacked structural layers without forming a top protective layer, wherein the thickness of the top protective layer at the top surface of the top support layer 322 is greater than the thickness of the protective layer at the sidewalls of the top support layer 322. Figure 5 As shown, the thickness of the top protective layer 340 gradually decreases from top to bottom. The material of the top protective layer 340 can be a polymer-like material (CF2). n For example, the deposited gas of the top protective layer 340 may include CH2F2 or CH3F.

[0041] Compared with existing technologies, the top support layer is protected by a top protective layer, so as to keep the upper width and depth of the capacitor hole unchanged. That is, the upper width and depth of the capacitor hole remain unchanged, while the lower part of the capacitor hole is enlarged, which increases the lower electrode area without increasing the thickness of the molded part and improves the capacitor value.

[0042] refer to Figure 6 The process involves etching back a portion of the support layers 310, 314, and 318 below the top stacked structure layer in the multiple trenches 326 and the etch stop layer 306, causing the unprotected support layers 310, 314, and 318 to recess, forming multiple enlarged trenches. Specifically, this includes etching back a portion of the support layers 310, 314, and 318 below the top stacked structure layer in the multiple trenches that are not covered by the top protective layer and the etch stop layer 306, using phosphoric acid, until the entire top surface of the memory node 302 is exposed and the etching stops, causing the support layers 310, 314, and 318 and the etch stop layer 306 that are not protected by the top protective layer 340 to recess, while keeping the molding layers 308, 312, 316, and 320 unetched, to form multiple enlarged trenches 342 that are larger than the multiple trenches 326. The support layers 310, 314, and 318, which are not protected by the top protective layer 340, and the etch stop layer 306 are recessed, causing the unetched molding layers 308, 312, 316, and 320 to protrude from the multiple trenches 326, for example, forming steps in the molding layers. For example, the amount of etchback on the unprotected support layers ranges from 2 nm to 10 nm. By adjusting the amount of etchback, the relative surface area between the lower and upper electrode layers can be adjusted, thereby regulating the capacitance value of the subsequently generated capacitor.

[0043] Compared to existing technologies, by protecting the top support layer with a top protective layer to prevent it from being etched during the etch-back process, the surface area at the bottom of the capacitor aperture can be increased by more than 5% while maintaining the same depth. Furthermore, by using an etch-back stop layer, the subsequently formed lower electrode layer can make contact with the entire top surface of the memory node, thereby improving the electrical characteristics of the capacitor.

[0044] refer to Figure 7 A lower electrode layer 344 is deposited in multiple trenches 326. Depositing the lower electrode layer 344 in the multiple trenches 326 includes: removing a top protective layer 340 from the top surface and sidewalls of the top support layer 322 and from the sidewalls of a portion of the top molding layer 320 using an etching process. Then, the lower electrode layer 344 is deposited on the exposed surfaces of each support layer, each molding layer, and the etch stop layer in the multiple enlarged trenches 342 using a deposition process. Next, refer to… Figure 3 The remaining portion of the stacked structure layers is removed, and a dielectric layer and an upper electrode layer are formed on the inner and outer walls of the lower electrode layer 344. Specifically, the remaining portion of the stacked structure layers is removed to form a dielectric layer 346 and a dielectric layer 350 on the inner and outer walls of the lower electrode layer 344, respectively. Then, an upper electrode layer 348 is formed on the outer wall of the dielectric layer 346, and an upper electrode layer 352 is formed on the outer wall of the dielectric layer 350. For example, the material of the lower electrode layer and the upper electrode layer is TiN. A first capacitor is formed by the lower electrode layer 344, the upper electrode layer 348, and the dielectric layer 346 between the lower electrode layer 344 and the upper electrode layer 348. A second capacitor is formed by the lower electrode layer 344, the upper electrode layer 352, and the dielectric layer 350 between the lower electrode layer 344 and the upper electrode layer 352. The uneven structure includes at least three or more protrusions.

[0045] Compared with the prior art, in the case of the top protective layer protecting the top support layer, a portion of each support layer below the top stacked structure layer is etched back, so that the unprotected support layers are recessed, thereby increasing the relative surface area of ​​the lower electrode layer and the upper electrode layer by more than 5%, and thus providing a capacitance value of more than 5%.

[0046] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0047] 1. With the top protective layer protecting the top support layer, a portion of each support layer below the top stacked structure layer is etched back, causing the unprotected support layers to be recessed, which can increase the relative surface area between the lower electrode layer and the upper electrode layer, thereby increasing the capacitance value.

[0048] 2. The top protective layer protects the top support layer, preventing it from being etched during the etching process, thus maintaining the depth of the capacitor vias.

[0049] 3. By etching back the stop layer, the subsequent lower electrode layer can make contact with the entire top surface of the storage node, thereby improving the electrical characteristics of the capacitor.

[0050] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0051] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a capacitor, characterized in that, include: A semiconductor substrate is provided, wherein the semiconductor substrate includes a plurality of memory nodes disposed in and spaced apart by the insulating material layer; An etch stop layer and a plurality of stacked structure layers are sequentially formed on the semiconductor substrate, each stacked structure layer including a molding layer and a support layer above the molding layer; The etching stop layer and the plurality of stacked structure layers are etched to form a plurality of trenches; A top protective layer is formed on the top support layer and part of the top molding layer in the top stacked structure layer, wherein the thickness of the top protective layer gradually decreases from top to bottom; Etching back a portion of each support layer and the etch stop layer below the top stacked structure layer in the plurality of trenches to recess the unprotected support layers, forming a plurality of enlarged trenches, comprises: etching back a portion of each support layer and the etch stop layer below the top stacked structure layer in the plurality of trenches that is not covered by the top protective layer with phosphoric acid until the entire top surface of the memory node is exposed, thereby recessing the unprotected support layers and the etch stop layer while leaving the molding layers unetched, to form a plurality of enlarged trenches larger than the plurality of trenches, wherein the recessed etch stop layers are aligned vertically with the memory node; and A lower electrode layer is deposited in the plurality of enlarged trenches.

2. The method for manufacturing a capacitor according to claim 1, characterized in that, Etching the etch stop layer and the plurality of stacked structure layers to form a plurality of trenches includes: The plurality of stacked structural layers are etched using an etching process to form a pattern of multiple stacked structural layers with multiple first openings; and Using the multiple stacked structure layer patterns as a mask, the etch stop layer below the multiple first openings is etched to form multiple second openings through the etch stop layer, thereby exposing the top surface of the middle portion of the memory node, wherein the multiple trenches pass through the multiple stacked structure layers and the etch stop layer.

3. The method for manufacturing a capacitor according to claim 1, characterized in that, A top protective layer is formed above the top support layer and part of the top molding layer in the top stacked structural layer, including: A top protective layer is formed on the top surface and sidewalls of the top support layer and on the sidewalls of a portion of the top molded layer in the top stacked structural layers by a deposition process, while no top protective layer is formed on the sidewalls of the remaining portions of the multiple stacked structural layers; wherein the thickness of the top protective layer at the top surface of the top support layer is greater than the thickness of the top protective layer at the sidewalls of the top support layer.

4. The method for manufacturing a capacitor according to claim 3, characterized in that, The deposited gases that form the top protective layer include CH2F2 or CH3F.

5. The method for manufacturing a capacitor according to claim 3, characterized in that, The molding layer comprises an oxide; and The support layer and the etch stop layer comprise silicon nitride; wherein the thickness of the molding layer and the support layer is in the range of 10 nm to 100 nm.

6. The method for manufacturing a capacitor according to claim 3, characterized in that, in, The amount of back etching is in the range of 2 nm to 10 nm.

7. The method for manufacturing a capacitor according to claim 3, characterized in that, Depositing the lower electrode layer in the plurality of enlarged trenches includes: The top protective layer on the top surface and sidewalls of the top support layer, as well as on part of the sidewalls of the top molding layer, is removed by an etching process; and The lower electrode layer is deposited on the exposed surfaces of the support layers, molding layers, and etch stop layers in the plurality of enlarged trenches using a deposition process.

8. The method for manufacturing a capacitor according to claim 1, characterized in that, After depositing the lower electrode layer, the method further includes: Remove the remaining portion of the stacked structure layer, and form a capacitor dielectric layer and an upper electrode layer on the inner and outer walls of the lower electrode layer.

9. A method for manufacturing a capacitor according to any one of claims 1 to 8, characterized in that, The plurality of stacked structure layers includes more than four stacked structure layers.

10. A capacitor manufactured using the method of manufacturing a capacitor according to any one of claims 1 to 9, characterized in that, include: Semiconductor substrate; A lower electrode is formed on a semiconductor substrate, wherein the lower electrode is in the form of multiple trench walls; The first dielectric layer is located on the inner wall of the lower electrode; The first upper electrode is located on the inner wall of the first dielectric layer, wherein the lower electrode, the first dielectric layer and the first upper electrode constitute a first capacitor; A second dielectric layer is located on the outer wall of the adjacent lower electrode; and The second upper electrode is located on the inner wall of the second dielectric layer, and the lower electrode, the second dielectric layer and the second upper electrode constitute the second capacitor; The lower part of the lower electrode includes one or more concave-convex structures, the first dielectric layer is conformal to the inner wall of the lower electrode, and the second dielectric layer is conformal to the outer wall of the lower electrode.

11. The capacitor according to claim 10, characterized in that, The concave-convex structure includes at least three or more protrusions.

12. A DRAM, characterized in that, include: Semiconductor substrate; Buried channel transistors are located on the semiconductor substrate; The bit line structure is electrically connected to an active region of the buried channel transistor; The storage node contact is electrically connected to another active region of the buried trench transistor; as well as The capacitor of claim 10 is electrically connected to the storage node contact.

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