High-density substrate structure and method of processing the same

Abstract

The application relates to a high-density substrate structure and a processing method thereof, wherein a through-silicon via chip is arranged in a hollow area of a carrier plate, a second wiring layer of a new substrate is arranged on a metal column bump of the through-silicon via chip and a corresponding metal column bump of the carrier plate, a second metal bump of the new substrate is arranged on the second wiring layer of the new substrate, a third wiring layer of the new substrate is arranged on the second metal bump of the new substrate, a first wiring layer of the new substrate is arranged on a lower end of the metal column of the through-silicon via chip and the corresponding metal column bump of the carrier plate, a first metal bump of the new substrate is arranged on the first wiring layer of the new substrate, a fourth wiring layer of the new substrate is arranged on the first metal bump of the new substrate, and a solder mask layer is arranged on the third wiring layer of the new substrate and the fourth wiring layer of the new substrate. The application improves the wiring density per unit area of the high-density substrate, reduces the volume and thickness, and reduces the dielectric loss under high frequency.

Description

Technical Field

[0001] This invention relates to the field of substrate processing technology, specifically to a high-density substrate structure and its processing method. Background Technology

[0002] With the continuous advancement of integrated circuit technology, more and more electronic products are developing towards miniaturization, thinning, and intelligence. As the main packaging component of electronic chips, high-density substrates have seen significant progress in processing technology research due to their high integration density, complex and diverse customized requirements for multi-layer interconnection.

[0003] Embedded substrates, as an advanced technical solution in the packaging field, allow IC chips, resistors, or capacitors to be embedded within the substrate. The volume of the packaging substrate is the same as the volume of the substrate with the embedded chip, so one of the technical advantages of embedded substrates is that their thickness can be reasonably controlled. At the same time, the high-density leads of the embedded chip can be directly interconnected with the substrate in the vertical direction, significantly improving product yield and workability.

[0004] Core materials are widely used as the main substrate material for high-density substrates due to their advantages in double-sided interconnection, excellent stability, and good mechanical strength. However, due to the limitations of traditional substrate processing technology, and the fact that the large through-hole diameter of core materials cannot meet the processing needs of small-diameter products, when there is a need for higher density wiring, it is often necessary to increase the number of substrate layers and increase the substrate volume to increase the number of leads. This not only greatly increases the process difficulty, but also leads to a decrease in product yield due to the cumbersome processing flow. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-density substrate structure and its processing method that can increase the wiring density per unit area, reduce volume and thickness, and reduce dielectric loss at high frequencies.

[0006] According to the technical solution provided by the present invention, the high-density substrate structure includes a carrier plate and a through-silicon via (TSV) chip; a carrier plate metal pillar is provided in the carrier plate, and a carrier plate metal pillar bump is provided at both the upper and lower ends of the carrier plate metal pillar; interconnected vertical TSV chip metal pillars are provided in the TSV chip, and a TSV chip metal pillar bump is provided at the upper end of the TSV chip metal pillar.

[0007] A hollow area is provided in the middle of the carrier board, and the through silicon via chip is provided in the hollow area. A second coating film is provided between the carrier board and the through silicon via chip. A first coating film is provided between adjacent carrier board metal pillar protrusions on the front side of the carrier board and between adjacent carrier board metal pillar protrusions on the back side of the carrier board.

[0008] A second wiring layer of a new substrate is provided on the metal pillar bump of the through-silicon via chip and the corresponding metal pillar bump of the carrier board. A second metal bump of the new substrate is provided on the second wiring layer of the new substrate. A fourth covering film is provided between adjacent second metal bumps of the new substrate. A third wiring layer of the new substrate is provided on the second metal bump of the new substrate.

[0009] A new substrate first wiring layer is provided on the lower end of the through-silicon via chip metal pillar and on the corresponding carrier metal pillar bump. A new substrate first metal bump is provided on the new substrate first wiring layer. A third covering film is provided between adjacent new substrate first metal bumps. A new substrate fourth wiring layer is provided on the new substrate first metal bump.

[0010] Solder resist layers are provided on both the third wiring layer and the fourth wiring layer of the new substrate.

[0011] Preferably, the distance between the through-silicon via chip and the edge of the substrate is greater than 50 μm.

[0012] Preferably, the first, second, third, and fourth coating films are made of ABF, CBF, or molding compound.

[0013] Preferably, the thickness of the carrier plate is 100-500 μm.

[0014] The above-mentioned high-density substrate processing method includes the following steps:

[0015] S1. Provide a carrier plate, in which pre-fabricated carrier plate metal pillars are provided, and pre-fabricated carrier plate metal pillar protrusions are provided at the upper and lower ends of the carrier plate metal pillars for later use.

[0016] S2. Provide a through-silicon via (TSV) chip. The TSV chip has pre-set interconnected vertical TSV chip metal pillars inside. TSV chip metal pillar bumps have been pre-fabricated at the upper end of the TSV chip metal pillars for later use.

[0017] S3. After pressing the first coating film onto the front and back of the carrier plate, grind the back until the metal pillar protrusions of the carrier plate are exposed.

[0018] S4. Mill out a cutout area in the middle of the carrier board, attach the cutout carrier board to the carrier with the heat-release film, and then mount the through-silicon via chip into the cutout area with the front side of the through-silicon via chip facing up.

[0019] S5. Wrap the carrier and the through-silicon via chip with a second coating film, and remove the thermal stripping film and carrier to form a new substrate;

[0020] S6. Wiring and metal bumps are grown on the back side of the new substrate to form the first wiring layer and the first metal bump of the new substrate, and then covered with a third coating film to protect the first wiring layer and the first metal bump of the new substrate.

[0021] S7. Thin the front side of the new substrate until the metal pillar bumps of the carrier plate and the metal pillar bumps of the through-silicon via chip are exposed, and redewire and grow metal bumps on the surface of the metal pillar bumps of the carrier plate and the metal pillar bumps of the through-silicon via chip to form the second wiring layer and the second metal bump of the new substrate.

[0022] S8. The front side of the new substrate is covered with a fourth coating film, then thinned to expose the second metal bump of the new substrate, and rewiring is performed on the surface of the second metal bump of the new substrate to form the third wiring layer of the new substrate.

[0023] S9. Thin the back side of the new substrate to expose the first metal bump of the new substrate, and rewire the surface of the first metal bump of the new substrate to form the fourth wiring layer of the new substrate.

[0024] S10. Solder resist is formed on the surfaces of the third wiring layer and the fourth wiring layer of the new substrate to form a solder resist layer, thereby completing the processing of the high-density substrate.

[0025] Preferably, in step S4, one or more through-silicon via (TSV) chips are mounted into the cutout area.

[0026] Preferably, after the through-silicon via (TSV) chip is mounted onto the cutout area of ​​the carrier board, in step S4, the height of the metal pillar bumps of the TSV chip is greater than the height of the carrier board.

[0027] The advantages of this invention are as follows:

[0028] This invention embeds a through-silicon via (TSV) chip into a carrier substrate and performs double-sided multilayer wiring. This effectively combines the high-density interconnect points of the TSV chip with the advantages of the carrier substrate, not only efficiently increasing the wiring density per unit area and providing more leads on the package surface, but also significantly reducing the volume and thickness of the high-density substrate after packaging. This greatly reduces the failure risk associated with traditional layer-addition processes, significantly reduces the lead-out distance of the circuits, and reduces dielectric loss at high frequencies in high-density substrate products. It also provides better electrical signal transmission capabilities and higher transmission quality stability, enabling it to meet more complex functional requirements with a small size and low layer count. Attached Figure Description

[0029] Figure 1 This is a cross-sectional schematic diagram of the carrier plate provided in step S1 of Embodiment 1.

[0030] Figure 2This is a cross-sectional schematic diagram of the through-silicon via (TSV) chip provided in step S2 of Example 1.

[0031] Figure 3 This is a cross-sectional schematic diagram of the carrier plate after processing in step S3 of Example 1.

[0032] Figure 4 This is a cross-sectional view of the through-silicon via (TSV) chip after it has been mounted onto the carrier board in step S4 of Example 1.

[0033] Figure 5 This is a cross-sectional schematic diagram of the new substrate obtained after the processing in step S5 of Example 1.

[0034] Figure 6 This is a cross-sectional schematic diagram of the new substrate after the processing in step S6 of Example 1.

[0035] Figure 7 This is a cross-sectional schematic diagram of the new substrate after the processing in step S7 of Example 1.

[0036] Figure 8 This is a cross-sectional schematic diagram of the new substrate after the processing in step S8 of Example 1.

[0037] Figure 9 This is a cross-sectional schematic diagram of the new substrate after the processing in step S9 of Example 1.

[0038] Figure 10 This is a cross-sectional schematic diagram of the high-density substrate obtained after the processing in step S10 of Example 1. Detailed Implementation

[0039] The following detailed description of specific embodiments will make it easier to understand the structural logic and advantages of the present invention.

[0040] It should be noted that the appearance, proportions, and dimensions of the illustrated components in this invention are merely for the purpose of describing the content of this invention and for those skilled in the art to view and read, and are not intended to limit the specific conditions under which this invention can be implemented. Any adjustments to the size and proportions of electronic components, as well as the addition of layers to three-dimensional structures and circuit adjustments, should be covered within the technical scope of this invention, without affecting the understanding of the description of this invention. Example

[0041] A high-density substrate structure includes a carrier plate 101 and a through-silicon via (TSV) chip 201; a carrier plate metal pillar 102 is provided in the carrier plate 101, and a carrier plate metal pillar bump 103 is provided at both the upper and lower ends of the carrier plate metal pillar 102; interconnected vertically arranged TSV chip metal pillars 202 are provided in the TSV chip 201, and a TSV chip metal pillar bump 203 is provided at the upper end of the TSV chip metal pillar 202;

[0042] A hollow area is provided in the middle of the carrier plate 101, and the silicon via chip 201 is provided in the hollow area. A second coating film 304 is provided between the carrier plate 101 and the silicon via chip 201. A first coating film 301 is provided between adjacent carrier plate metal pillar protrusions 103 on the front side of the carrier plate 101 and between adjacent carrier plate metal pillar protrusions 103 on the back side of the carrier plate 101.

[0043] A new substrate second wiring layer 309 is provided on the through-silicon via chip metal pillar bump 203 and the corresponding carrier metal pillar bump 103 (i.e., the carrier metal pillar bump 103 located at the upper end of the carrier metal pillar 102). A new substrate second metal bump 308 is provided on the new substrate second wiring layer 309. A fourth covering film 310 is provided between adjacent new substrate second metal bumps 308. A new substrate third wiring layer 311 is provided on the new substrate second metal bump 308.

[0044] A new substrate first wiring layer 305 is provided on the lower end of the through-silicon via chip metal pillar 202 and the corresponding carrier metal pillar bump 103 (i.e., the carrier metal pillar bump 103 located at the lower end of the carrier metal pillar 102). A new substrate first metal bump 306 is provided on the new substrate first wiring layer 305. A third covering film 307 is provided between adjacent new substrate first metal bumps 306. A new substrate fourth wiring layer 312 is provided on the new substrate first metal bump 306.

[0045] Solder resist layers 313 are provided on both the third wiring layer 311 and the fourth wiring layer 312 of the new substrate.

[0046] The distance between the through-silicon via chip 201 and the edge of the carrier 101 is greater than 50 μm.

[0047] The first coating film 301, the second coating film 304, the third coating film 307 and the fourth coating film 310 are made of ABF, CBF or molding compound.

[0048] The thickness of the carrier plate 101 is 100-500 μm.

[0049] A method for processing a high-density substrate, the method comprising the following steps:

[0050] S1. Provide a carrier plate 101, in which a carrier plate metal pillar 102 has been prefabricated, and at the upper and lower ends of the carrier plate metal pillar 102, a carrier plate metal pillar protrusion 103 has been prefabricated, for later use.

[0051] S2. Provide a through-silicon via (TSV) chip 201. The TSV chip 201 has pre-formed interconnected vertical TSV chip metal pillars 202 inside. TSV chip metal pillar bumps 203 have been pre-fabricated at the upper end of the TSV chip metal pillars 202 for later use.

[0052] S3. After pressing the first covering film 301 onto the front and back sides of the carrier plate 101, grind the back side until the metal pillar protrusion 103 of the carrier plate is exposed.

[0053] S4. A cutout area is milled in the middle of the carrier plate 101. The cutout carrier plate 101 is then attached to the carrier 303 with the heat-release film 302. One or more through-silicon via (TSV) chips 201 are then mounted into the cutout area. The height of the metal pillar bumps 203 of the TSV chips is greater than the height of the carrier plate 101. The front side of the TSV chips 201 faces upward.

[0054] S5. The carrier plate 101 and the through-silicon via chip 201 are covered with the second covering film 304, and the thermal stripping film 302 and the carrier 303 are removed to form a new substrate.

[0055] S6. Wiring and metal bumps are grown on the back side of the new substrate to form the first wiring layer 305 and the first metal bump 306 of the new substrate, and then covered with a third covering film 307 to protect the first wiring layer 305 and the first metal bump 306 of the new substrate.

[0056] S7. Thin the front side of the new substrate until the carrier metal pillar bump 103 and the through silicon via chip metal pillar bump 203 are exposed, and redewire and grow metal bumps on the surface of the carrier metal pillar bump 103 and the through silicon via chip metal pillar bump 203 to form the second wiring layer 309 and the second metal bump 308 of the new substrate.

[0057] S8. The front side of the new substrate is covered with a fourth covering film 310, and then thinned to expose the second metal bump 308 of the new substrate. Rewiring is performed on the surface of the second metal bump 308 of the new substrate to form the third wiring layer 311 of the new substrate.

[0058] S9. Thin the back side of the new substrate to expose the first metal bump 306 of the new substrate, and rewire the surface of the first metal bump 306 of the new substrate to form the fourth wiring layer 312 of the new substrate.

[0059] S10. Solder resist is formed on the surfaces of the third wiring layer 311 and the fourth wiring layer 312 of the new substrate to form a solder resist layer 313, thereby completing the processing of the high-density substrate.

[0060] In this invention, the carrier board 101 can perform interconnection between upper and lower layers and conduction of circuits.

[0061] In this invention, when wiring is performed on a single side of a carrier board 101 that has been fitted with a through-silicon via chip 201, multi-layer stacked wiring can be performed.

[0062] In this invention, the through-silicon via chip 201 can be interconnected with the carrier board 101 on the upper and lower layers or on the left and right sides through wiring.

[0063] In this invention, when performing double-layer wiring, the wiring on one side is covered with a covering film before the wiring on the other side is performed.

[0064] The above description is only a preferred embodiment of the present invention. Any modifications and alterations made to the present invention by those skilled in the art without departing from the technical scope and content of the present invention shall fall within the protection scope defined in the claims.

Claims

1. A method for processing a high-density substrate, characterized in that: The method includes the following steps: S1. Provide a carrier plate (101), in which a carrier plate metal pillar (102) has been prefabricated, and at the upper and lower ends of the carrier plate metal pillar (102) are prefabricated carrier plate metal pillar protrusions (103) for later use; S2. Provide a through-silicon via (TSV) chip (201). Interconnected vertical TSV chip metal pillars (202) have been pre-formed inside the TSV chip (201). TSV chip metal pillar bumps (203) have been pre-fabricated at the upper end of the TSV chip metal pillars (202) for later use. S3. After pressing the first covering film (301) on the front and back of the carrier plate (101), grind the back until the metal pillar protrusion (103) of the carrier plate is exposed. S4. A cutout area is milled in the middle of the carrier board (101). The cutout carrier board (101) is attached to the carrier (303) with the heat-release film (302). Then, the through-silicon via chip (201) is mounted into the cutout area with the front side of the through-silicon via chip (201) facing up. S5. The carrier plate (101) and the through-silicon via chip (201) are covered with the second covering film (304), and the thermal stripping film (302) and the carrier (303) are removed to form a new substrate; S6. Wiring and metal bumps are grown on the back side of the new substrate to form a first wiring layer (305) and a first metal bump (306) of the new substrate, and then covered with a third covering film (307) to protect the first wiring layer (305) and the first metal bump (306) of the new substrate. S7. Thin the front side of the new substrate until the carrier metal pillar bump (103) and the through-silicon via chip metal pillar bump (203) are exposed, and redewire and grow metal bumps on the surface of the carrier metal pillar bump (103) and the through-silicon via chip metal pillar bump (203) to form the second wiring layer (309) and the second metal bump (308) of the new substrate. S8. The front side of the new substrate is covered with a fourth covering film (310), and then thinned to expose the second metal bump (308) of the new substrate. Rewiring is performed on the surface of the second metal bump (308) of the new substrate to form the third wiring layer (311) of the new substrate. S9. Thin the back side of the new substrate to expose the first metal bump (306) of the new substrate, and rewire the surface of the first metal bump (306) of the new substrate to form the fourth wiring layer (312) of the new substrate. S10. Solder resist molding is performed on the surfaces of the third wiring layer (311) and the fourth wiring layer (312) of the new substrate to form a solder resist layer (313), thereby completing the processing of the high-density substrate.

2. The processing method of the high-density substrate according to claim 1, characterized in that: In step S4, one or more through-silicon via (201) chips are mounted into the cutout area.

3. The processing method of the high-density substrate according to claim 1, characterized in that: In step S4, after the through-silicon via chip (201) is mounted onto the cutout area of ​​the carrier board (101), the height of the through-silicon via chip metal pillar bump (203) is greater than the height of the carrier board (101).

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