Integrated chip and method of manufacturing an integrated chip

Abstract

Various embodiments of the present invention are directed to an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate located above a handle substrate and an insulating layer disposed between the device substrate and the handle substrate. A gate electrode is located on the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulating layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and includes a first isolation segment laterally disposed between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode is directly located on the first isolation segment and electrically coupled to the contact region. Embodiments of the present application also relate to methods of fabricating an integrated chip.

Description

Integrated chips and methods for manufacturing integrated chips Technical Field

[0001] Embodiments of this application relate to integrated chips and methods for manufacturing integrated chips. Background Technology

[0002] Modern integrated circuits comprise millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Integrated circuits (ICs) can use many different types of transistor devices, depending on the application. In recent years, the growing market for cellular and RF (radio frequency) devices has led to a significant increase in the use of high-voltage transistor devices. For example, high-voltage transistor devices are commonly used in power amplifiers in RF transmission / reception chains due to their ability to handle high breakdown voltages (e.g., greater than about 50V) and high frequencies. Summary of the Invention

[0003] Some embodiments of this application provide an integrated chip, including: a semiconductor substrate, including a device substrate located on a processing substrate and an insulating layer disposed between the device substrate and the processing substrate; a gate electrode located on the device substrate between a drain region and a source region; a conductive via extending through the device substrate and the insulating layer to contact the processing substrate; a first isolation structure disposed within the device substrate and including a first isolation segment laterally disposed between the gate electrode and the conductive via; a contact region disposed within the device substrate between the first isolation segment and the conductive via; and a conductive gate electrode directly located on the first isolation segment, wherein the conductive gate electrode is electrically coupled to the contact region.

[0004] Some embodiments of this application provide an integrated chip, comprising: a device substrate and a processing substrate, the device substrate being located above an insulating layer and the processing substrate being located below the insulating layer; a first well region, a second well region, and a third well region disposed within the device substrate, wherein the second well region is laterally spaced between the first well region and the third well region; a high-voltage transistor disposed on the device substrate, including a gate electrode, a source region, and a drain region, wherein the gate electrode is disposed between the source region and the drain region, and wherein the gate electrode is directly located on a first interface between the first well region and the second well region; a conductive via disposed within the device substrate and electrically coupled to the processing substrate, wherein the conductive via is adjacent to the third well region; and a conductive termination structure disposed on the device substrate between the conductive via and the high-voltage transistor, wherein the conductive termination structure includes a contact region disposed within the third well region and a conductive gate electrode located on a second interface between the second well region and the third well region, wherein the conductive gate electrode is electrically coupled to the third well region via the contact region.

[0005] Further embodiments of this application provide a method for manufacturing an integrated chip, the method comprising: forming a first isolation structure in a device substrate, wherein the device substrate is located above an insulating layer and a processing substrate is located below the insulating layer; forming a conductive via extending through the device substrate to the processing substrate; doping the device substrate to form a first well region, a second well region, and a third well region within the device substrate, wherein the second well region is laterally spaced between the first well region and the third well region; forming a gate electrode above the device substrate such that the gate electrode is located above a first interface between the first well region and the second well region; forming a conductive gate electrode above the first isolation structure; and doping the device substrate to form a source region, a drain region, and a contact region within the device substrate, wherein the gate electrode is disposed between the source region and the drain region, and wherein the contact region is disposed within the third well region between the conductive via and the conductive gate electrode. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1A shows a cross-sectional view of some embodiments of an integrated chip including a conductive termination structure configured to be laterally adjacent to a high-voltage transistor.

[0008] Figure 1B shows a top view of some embodiments of the integrated chip of Figure 1A.

[0009] Figure 1C shows a top view of some alternative embodiments of the integrated chip of Figure 1A.

[0010] Figure 2 shows a cross-sectional view of some alternative embodiments of an integrated chip including a conductive termination structure configured to be laterally adjacent to a high-voltage transistor.

[0011] Figure 3A shows cross-sectional views of several different embodiments of an integrated chip including a conductive termination structure configured to be laterally adjacent to a high-voltage transistor.

[0012] Figure 3B shows a top view of some embodiments of the integrated chip of Figure 3A.

[0013] Figure 3C shows a cross-sectional view of some alternative embodiments of an integrated chip including a conductive termination structure configured to be laterally adjacent to a high-voltage transistor.

[0014] Figures 4A and 4B show various embodiments of graphs corresponding to the operation of an integrated chip including a conductive terminal structure configured to be laterally adjacent to a high-voltage transistor.

[0015] Figures 5A to 5B to 11A to 11B show various views of some embodiments of a method for forming an integrated chip including a conductive terminal structure configured to be laterally adjacent to a high-voltage transistor.

[0016] Figure 12 shows a flowchart illustrating some embodiments of a method for forming an integrated chip including a conductive termination structure configured to be laterally adjacent to a high-voltage transistor. Detailed Implementation

[0017] This invention provides numerous different embodiments or instances for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0019] Integrated chips typically include transistors designed to operate at many different voltages. High-voltage transistors are designed to operate at high breakdown voltages (e.g., greater than about 20 volts (V), greater than about 80 V, or another suitable value). High-voltage transistors can be implemented on silicon-on-insulator (SOI) substrates to improve performance, such as latch-up-free operation, high package density, and less leakage current. For example, the SOI substrate may include a processing substrate, a device substrate, and an insulating layer disposed between the device substrate and the processing substrate. The high-voltage transistor may include a gate structure disposed along the device substrate between a source region and a drain region. A first well region, including a first doping type (e.g., p-type), is disposed within the device substrate below the gate structure and adjacent to the drain region. A second well region, including a second doping type (e.g., n-type), is disposed within the device substrate and extends from the first well region to the source region. Furthermore, conductive vias extend through the device substrate and the insulating layer to contact the processing substrate, and the conductive vias are configured to bias the processing substrate. During operation, a bias voltage can be applied to the gate structure to generate an electric field that causes a channel region to extend beneath the gate structure and through the first well region. When the bias voltage is relatively high (e.g., greater than about 60-70V), a high electric field is generated in the device substrate. To mitigate the adverse effects of the high electric field, the substrate can be electrically coupled to ground via conductive vias. This mitigates the negative effects of the high electric field and increases the breakdown voltage of the high-voltage transistor.

[0020] Conductive vias can be formed in many different ways. For example, a conductive via can be formed laterally adjacent to the drain region and the first well region, such that an isolation structure separates the first well region from the conductive via. In such a configuration, when a high negative bias (e.g., about -60V or higher) is applied to the drain region, a high electric field will exist in the device substrate at the drain region and the first well region. However, because the drain region is close to the conductive via, the high electric field and / or voltage difference between the conductive via and the drain region may damage the isolation structure and / or the device substrate, leading to high-voltage transistor breakdown. Alternatively, a conductive via can be formed laterally adjacent to the source region and the second well region, such that an isolation structure separates the second well region from the conductive via. In such a configuration, when a high positive bias (e.g., about +60V or higher) is applied to the gate structure and / or the source region, a high electric field will exist in the device substrate at the drain region and the second well region. However, because the source region is close to the via, the high electric field and / or voltage difference between the via and the source region can damage the isolation structure and / or the device substrate, leading to breakdown of the high-voltage transistor. Therefore, the breakdown voltage of the high-voltage transistor can be mitigated based on the arrangement of the via relative to the source and / or drain regions of the high-voltage transistor.

[0021] Therefore, the present invention relates to an integrated chip including a conductive termination structure configured to increase the breakdown voltage capability of a high-voltage transistor. The integrated chip includes a device substrate above an insulating layer and a processing substrate below the insulating layer. A first well region, a second well region, and a third well region are disposed in the device substrate. A second well region is disposed between the first well region and the third well region. A high-voltage transistor is disposed on the device substrate and includes a gate electrode spaced between a drain region and a source region. The gate electrode is located on a first interface between the first well region and the second well region. Furthermore, a conductive via is disposed within the device substrate and electrically coupled to the processing substrate. A conductive termination structure is disposed on the processing substrate between the conductive via and the drain region. The conductive termination structure includes a contact region disposed within the third well region and a conductive gate electrode located on a second interface between the second well region and the third well region. The conductive gate electrode is electrically coupled to the third well region via the contact region. During operation of the high-voltage transistor device, an electric field generated by the gate electrode can accumulate at the drain region and / or the second well region. The conductive termination structure is configured to act on the electric field generated by the gate electrode and reduce the electric field strength along the surface of the device substrate (e.g., reduce the electric field strength accumulated at the drain and / or second well regions). This mitigates the damage of the accumulated electric field to the device substrate and other structures disposed within the device substrate, thereby increasing the breakdown voltage capability of the high-voltage transistor.

[0022] Figure 1A shows a cross-sectional view of some embodiments of an integrated chip 100 including a conductive terminal structure 121 configured to be laterally adjacent to a high-voltage transistor 122.

[0023] Integrated chip 100 includes a high-voltage transistor 122 disposed on a semiconductor substrate 102. In various embodiments, the semiconductor substrate 102 is configured as a silicon-on-insulator (SOI) substrate and includes a processing substrate 104, a device substrate 108, and an insulating layer 106 disposed between the processing substrate 104 and the device substrate 108. A first well region 116, a second well region 118, and a third well region 120 are disposed within the device substrate 108. The second well region 118 is laterally disposed between the first well region 116 and the third well region 120. In various embodiments, the second well region 118 includes a first doping type (e.g., p-type), and the first well region 116 and the third well region 120 each include a second doping type opposite to the first doping type (e.g., n-type). In various embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. A first isolation structure 110 extends from the top surface of the device substrate 108 to a point below the top surface of the device substrate 108. The first isolation structure 110 includes a first isolation segment 110a and a second isolation segment 110b. Furthermore, the second isolation structure 112 extends from the top surface of the device substrate 108 to the insulating layer 106. In various embodiments, the first isolation structure 110 and the second isolation structure 112 are configured to electrically isolate devices disposed on and / or within the semiconductor substrate 102 from each other.

[0024] A high-voltage transistor 122 is disposed on a processing substrate 104, such that the high-voltage transistor 122 is separated from the processing substrate 104 by an insulating layer 106. In various embodiments, the high-voltage transistor 122 includes a source region 126, a drain region 132, a gate electrode 130, and a gate dielectric layer 128 disposed between the semiconductor substrate 102 and the gate electrode 130. The gate electrode 130 is located on the device substrate 108 and is laterally disposed between the source region 126 and the drain region 132. The source region 126 is disposed within a first well region 116 and is laterally adjacent to the body contact region 124. Furthermore, the drain region 132 is disposed within a second well region 118 and is laterally separated from the source region 126 by a second isolation segment 110b. In various embodiments, the gate electrode 130 is located directly on a portion of the second isolation segment 110b and directly on a first interface 113 between the first well region 116 and the second well region 118. In some embodiments, source region 126 and drain region 132 each include a first doping type (e.g., p-type), and body contact region 124 includes a second doping type (e.g., n-type). In such embodiments, high-voltage transistor 122 is configured as a p-channel metal-oxide-semiconductor (PMOS) transistor, a p-channel laterally diffused metal-oxide-semiconductor (p-LDMOS) transistor, or another suitable device. In further embodiments, high-voltage transistor 122 may be configured as an n-channel MOS (NMOS) transistor, an n-channel LDMOS (n-LDMOS) transistor, or another suitable device. Furthermore, conductive vias 114 (which may be represented as a continuous ring around the high-voltage transistor, as shown in FIG. 1B, or as one or more conductive pillars commonly surrounding the high-voltage transistor, as shown in FIG. 1C) are disposed within semiconductor substrate 102 and extend continuously from the top surface of device substrate 108 through insulating layer 106 to the top surface of processing substrate 104. Conductive vias 114 are separated from device substrate 108 by a second isolation structure 112 and configured to bias processing substrate 104. For example, the conductive via 114 is configured to electrically couple the processing substrate 104 to ground (e.g., 0V), a ground node, a ground terminal, etc. By coupling the processing substrate 104 to ground via the conductive via 114, the stability and breakdown voltage of the high-voltage transistor 122 can be improved. In a further embodiment, the conductive via 114 may be referred to as a guard ring.

[0025] An interconnect structure is located on a device substrate 108 and includes a dielectric structure 140, a plurality of conductive contacts 142, and a plurality of wires 144. The conductive contacts 142 and wires 144 are disposed within the dielectric structure 140 and configured to provide electrical connections to a device (e.g., a high-voltage transistor 122) disposed on a semiconductor substrate 102. In various embodiments, a conductive termination structure 121 is laterally disposed between the high-voltage transistor 122 and a conductive via 114. In some embodiments, the conductive termination structure 121 includes a third well region 120, a contact region 136 disposed within the third well region 120, a conductive gate electrode 134, and a peripheral gate dielectric layer 133. The third well region 120 and the contact region 136 each include a second doping type (e.g., n-type), which is opposite to a first doping type (e.g., p-type) of the second well region 118, such that a PN junction diode structure of the conductive termination structure 121 exists between the second well region 118 and the third well region 120. The PN junction diode structure of the conductive termination structure 121 is configured, for example, to direct current to the contact region 136. In a further embodiment, contact region 136 is electrically coupled to conductive gate electrode 134 via wire 144 and conductive contact 142. Peripheral gate dielectric layer 133 separates conductive gate electrode 134 from device substrate 108. Furthermore, peripheral gate dielectric layer 133 and conductive gate electrode 134 are directly located on the first isolation segment 110a of the first isolation structure 110. Conductive gate electrode 134 is directly located on the second interface 115 between the second well region 118 and the third well region 120.

[0026] In some embodiments, when receiving a bias voltage, the gate electrode 130 of the high-voltage transistor 122 is configured to generate an electric field that controls the movement of charge carriers (e.g., electrons or electron holes) within a channel region 127 laterally disposed between the source region 126 and the drain region 132. For example, during operation, a gate-source voltage may be selectively applied to the gate electrode 130 relative to the source region 126 to form a conductive channel in the channel region 127. Furthermore, when the gate-source voltage is applied to form the conductive channel, a drain-to-source voltage is applied to move charge carriers between the source region 126 and the drain region 132. In various embodiments, the channel region 127 may extend laterally from the source region 126 to an adjacent second well region 118 (e.g., referred to in some embodiments as a drift region and / or “drain extension region”).

[0027] In various embodiments, during operation of the integrated chip 100, the conductive termination structure 121 is configured to act on an electric field generated by the gate electrode 130. This partially enhances the breakdown voltage capability of the high-voltage transistor 122, thereby improving the performance of the integrated chip 100. In some embodiments, during operation of the high-voltage transistor 122, a high negative voltage (e.g., about -60V or higher) may be applied to the drain region 132 and a high electric field will be present in the device substrate 108 at the drain region 132 and the second well region 118. The conductive gate electrode 134 and the contact region 136 are configured to attenuate the electric field and / or potential at the drain region 132 and / or the second well region 118. For example, charge carriers may travel from the second well region 118 to the contact region 136 (e.g., through the PN junction diode structure of the conductive termination structure 121) and may accumulate in the conductive gate electrode 134. This can partially reduce the electric field strength along the surface of the device substrate 108, thereby improving the breakdown voltage capability of the high-voltage transistor 122.

[0028] Furthermore, the first sidewall 134s1 of the conductive gate electrode 134 is laterally offset from the outer sidewall of the first isolation segment 110a by a first lateral distance L1. In various embodiments, the first lateral distance L1 is in the range of about 0 micrometers (µm) to 0.2 µm or another suitable value. In some embodiments, if the first lateral distance L1 is relatively small (e.g., less than about 0 µm), the conductive gate electrode 134 and the peripheral gate dielectric layer 133 may be located directly over at least a portion of the contact region 136 and / or the third well region 120. This may partially cause charge carriers to tunnel through the peripheral gate dielectric layer 133 into the conductive gate electrode 134, thereby damaging the peripheral gate dielectric layer 133 and / or reducing the performance of the high-voltage transistor 122. In a further embodiment, if the first lateral distance L1 is relatively large (e.g., greater than about 0.2 µm), the overall size of the conductive gate electrode 134 is significantly reduced, thereby mitigating the ability of the conductive gate electrode 134 to reduce the electric field strength along the surface of the device substrate 108. This may reduce the breakdown capability of the high-voltage transistor 122.

[0029] Figure 1B shows a top view of some embodiments of the integrated chip 100 taken along line A-A' of Figure 1A.

[0030] In some embodiments, as shown in the top view of FIG1B, the source region 126, gate electrode 130, second well region 118, drain region 132, conductive gate electrode 134, third well region 120, contact region 136, first isolation structure 110, second isolation structure 112, and conductive via 114 are concentric annular regions / structures. It should be understood that although the aforementioned regions / structures appear as rectangular annular rings when viewed from above in FIG1B, they can also be, for example, square annular rings, triangular annular rings, circular annular rings, elliptical annular rings, or some other closed-path shape. Therefore, in some embodiments, the conductive gate electrode 134 continuously and laterally surrounds the gate electrode 130. In further embodiments, the source region 126, gate electrode 130, second well region 118, drain region 132, conductive gate electrode 134, third well region 120, contact region 136, first isolation structure 110, second isolation structure 112, and conductive via 114 are concentric with each other and / or each concentric with respect to the center of the body contact region 124. In various embodiments, the third well region 120 may be referred to as the peripheral terminal well region and / or the contact region 136 may be referred to as the peripheral terminal contact region.

[0031] In some embodiments, the first well region 116 may extend continuously from the center of the body contact region 124 to the first interface 113. Therefore, when viewed from above, the dashed rectangle representing the first interface 113 may correspond, for example, to the outer periphery of the first well region 116 and may also correspond to the inner periphery of the second well region 118. In a further embodiment, the second well region 118 extends continuously from the first interface 113 to the second interface 115. Therefore, when viewed from above, the dashed rectangle representing the second interface 115 may correspond, for example, to the outer periphery of the second well region 118 and may also correspond to the inner periphery of the third well region 120.

[0032] Figure 1C illustrates some alternative embodiments of the top view of Figure 1B, wherein the conductive via 114 includes a plurality of conductive pillars commonly surrounding the gate electrode 130 and the conductive gate electrode 134. Figure 1C illustrates some embodiments of the top view of the integrated chip 100 taken along line A-A' of Figure 1A. In a further embodiment, a second isolation structure 112 continuously surrounds each of the plurality of conductive pillars. Each of the plurality of conductive pillars may, for example, contact a processing substrate (104 in Figure 1A) and / or be electrically coupled to ground (e.g., 0V), a ground node, a ground terminal, etc.

[0033] Figure 2 shows a cross-sectional view of some alternative embodiments of an integrated chip 200 including a conductive termination structure 121 configured to be laterally adjacent to a high-voltage transistor 122. The integrated chip 200 may include some aspects of the integrated chip 100 of Figures 1A to 1C (and vice versa); and therefore, the features and / or reference numerals explained above with respect to Figures 1A to 1C also apply to the integrated chip 200 in Figure 2.

[0034] Integrated chip 200 includes a high-voltage transistor 122 disposed on a semiconductor substrate 102. The high-voltage transistor 122 can be used in a variety of applications, such as, for example, radio frequency (RF) components, high-voltage applications such as gate drivers (Insulated Gate Bipolar Transistors (IGBTs) / Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)), smart power / high-voltage devices, pressure sensors, actuators, accelerometers, gyroscopes, or some other suitable applications. In various embodiments, the semiconductor substrate 102 may be configured as an SOI substrate and includes a processing substrate 104, a device substrate 108, and an insulating layer 106 disposed between the processing substrate 104 and the device substrate 108. In some embodiments, the insulating layer 106 may be, for example, or include silicon oxide, silicon-rich oxide (SRO), some other oxides, some other dielectrics, or any combination of the foregoing materials. In some embodiments, the processing substrate 104 and the device substrate 108 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), silicon, single-crystal silicon, doped silicon, or another suitable semiconductor material. The processing substrate 104 may, for example, include a substrate having a density of about 10... 14 Up to 10 16 atoms / cm 3 The first doping type (e.g., p-type) has a doping concentration within the range of [value missing] or another suitable value. In various embodiments, the processing substrate 104 and the device substrate 108 may each have a resistance in the range of about 1 to 100 ohm-cm (Ω*cm) or another suitable value. In some embodiments, if the resistance of the processing substrate 104 is relatively low (e.g., less than about 1 Ω*cm), the breakdown voltage of the high-voltage transistor 122 may be reduced. In a further embodiment, if the resistance of the processing substrate 104 is relatively high (e.g., greater than about 100 Ω*cm), the breakdown voltage of the high-voltage transistor 122 may be increased.

[0035] A first isolation structure 110 is disposed within a device substrate 108 and extends continuously from the top surface of the device substrate 108 to a point below the top surface of the device substrate 108. The first isolation structure 110 may be configured, for example, as a shallow trench isolation (STI) structure or another suitable isolation structure. The first isolation structure 110 includes a first isolation segment 110a and a second isolation segment 110b laterally separated from each other by a non-zero distance. Furthermore, a second isolation structure 112 extends continuously from the top surface of the device substrate 108 to an insulating layer 106. The second isolation structure 112 may be configured, for example, as a deep trench isolation (DTI) structure or another suitable isolation structure. In some embodiments, the first isolation structure 110 and the second isolation structure 112 may, for example, be or include silicon nitride, silicon carbide, silicon dioxide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination of the foregoing materials.

[0036] The high-voltage transistor 122 includes a source region 126, a drain region 132, a gate electrode 130, and a gate dielectric layer 128. The source region 126 and drain region 132 are disposed within a device substrate 108 and laterally separated from each other by a second isolation segment 110b of a first isolation structure 110. In various embodiments, the drain region 132 is adjacent to the first isolation segment 110a and the second isolation segment 110b of the first isolation structure 110. Furthermore, the gate electrode 130 is disposed above the device substrate 108 and laterally spaced between the source region 126 and the drain region 132. The gate dielectric layer 128 is disposed between the gate electrode 130 and the device substrate 108. In various embodiments, the high-voltage transistor 122 is configured as a p-channel metal-oxide-semiconductor (PMOS) transistor, a p-channel laterally diffused metal-oxide-semiconductor (p-LDMOS) transistor, or another suitable device. In such embodiments, the source region 126 and drain region 132 include a first doping type (e.g., p-type) and may have a doping density of approximately 10-10. 14 Up to 10 16 atoms / cm 3 The doping concentration may be within the range of or another suitable value. In a further embodiment, the gate electrode 130 may be, for example, polysilicon and / or a metal gate material, such as tungsten, titanium, tantalum, aluminum, another suitable conductive material, or any combination of the foregoing materials. In a further embodiment, the gate dielectric layer 128 may be, for example, silicon dioxide, a high-k dielectric material, etc. As used herein, a high-k dielectric material is a dielectric material having a dielectric constant greater than 3.9.

[0037] A lightly doped region 202 is disposed within the device substrate 108 and adjacent to a first side of the source region 126. A body contact region 124 is disposed within the device substrate 108 and adjacent to a second side of the source region 126, wherein the first side of the source region 126 is opposite to the second side of the source region 126. In various embodiments, the lightly doped region 202 includes a doping depth of approximately 10-1. 12 Up to 10 14 atoms / cm 3 A first doping type (e.g., p-type) with a doping concentration within the range of or another suitable value. In a further embodiment, the body contact region 124 includes a doping concentration having a doping concentration of approximately 10... 14 Up to 10 16 atoms / cm 3 The second doping type (e.g., n-type) has a doping concentration within the range of p-type or another suitable value. In various embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa.

[0038] The conductive via 114 extends continuously from the top surface of the semiconductor substrate 102 to the top surface of the processing substrate 104, thereby coupling the conductive via 114 to the processing substrate 104. In various embodiments, a second isolation structure 112 laterally surrounds the conductive via 114, thereby electrically isolating the conductive via 114 from devices disposed on / within the semiconductor substrate 102. In some embodiments, the conductive via 114 may be configured as, or referred to as, a substrate via (TSV). In further embodiments, the conductive via 114 may electrically couple the processing substrate 104 to a reference node, a reference terminal, a ground node, a ground terminal, etc. In various embodiments, the reference terminal and / or reference node may be biased with 0V or another suitable value. In further embodiments, the conductive via 114 may be, for example, or include aluminum, copper, tungsten, another suitable conductive material, or any combination of the foregoing materials.

[0039] A first well region 116, a second well region 118, and a third well region 120 are disposed within a device substrate 108. The second well region 118 is laterally disposed between the first well region 116 and the third well region 120. In various embodiments, the second well region 118 includes a first doping type (e.g., p-type), and the first well region 116 and the third well region 120 each include a second doping type (e.g., n-type). In various embodiments, the first well region 116, the second well region 118, and the third well region 120 each have approximately 10... 11 Up to 10 13 atoms / cm 3The doping concentration is within the range or another suitable value. A drain region 132 is disposed within and adjacent to the second well region 118. In various embodiments, the second well region 118 is configured as a drift region (or "drain extension region") and has a relatively low doping concentration, which provides higher resistance at high operating voltages. Furthermore, at least a portion of the gate electrode 130 of the high-voltage transistor 122 is located directly above at least a portion of the second well region 118. Additionally, a lightly doped region 202, a source region 126, and a body contact region 124 are disposed within the first well region 116.

[0040] An interconnect structure is located on device substrate 108 and includes a dielectric structure 140, a plurality of conductive contacts 142, and a plurality of wires 144. The conductive contacts 142 and wires 144 are disposed within the dielectric structure 140 and configured to provide electrical connections to devices (e.g., high-voltage transistor 122) disposed on and / or within semiconductor substrate 102. For example, source region 126 and body contact region 124 may be electrically coupled to each other via two or more conductive contacts 142 and at least one wire 144. The dielectric structure 140 may include one or more dielectric layers. In various embodiments, the one or more dielectric layers may be, for example, or include oxides, silicon dioxide, low-k dielectric materials, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the foregoing. As used herein, a low-k dielectric material is a dielectric material having a dielectric constant of less than 3.9. In a further embodiment, the conductive contact 142 and the wire 144 may be, for example, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, ruthenium, tungsten, another conductive material, or any combination of the foregoing materials.

[0041] The conductive termination structure 121 is configured to be laterally adjacent to the drain region 132 of the high-voltage transistor 122. In various embodiments, the conductive termination structure 121 includes a third well region 120, at least a portion of the second well region 118, a contact region 136 disposed within the third well region 120, and a termination gate structure including a conductive gate electrode 134 and a peripheral gate dielectric layer 133. The peripheral gate dielectric layer 133 is disposed between the conductive gate electrode 134 and the device substrate 108. In some embodiments, the conductive gate electrode 134 and the peripheral gate dielectric layer 133 are directly located on the first isolation segment 110a of the first isolation structure 110, such that the entire bottom surface of the peripheral gate dielectric layer 133 is in direct contact with the top surface of the first isolation segment 110a. In other words, in such an embodiment, at least a portion of the top surface of the first isolation segment 110a directly contacts the entire bottom surface of the peripheral gate dielectric layer 133. Furthermore, the conductive gate electrode 134 is laterally disposed between the contact region 136 and the drain region 132. In a further embodiment, the conductive gate electrode 134 is located directly over at least a portion of the third well region 120 and directly over at least a portion of the second well region 118. In an even further embodiment, the conductive gate electrode 134 is laterally offset from the contact region 136 by a non-zero distance in the direction toward the high-voltage transistor 122.

[0042] In various embodiments, when the conductive termination structure 121 is laterally adjacent to the drain region 132 (and / or the drift region of the high-voltage transistor 122), the third well region 120 and the contact region 136 each include a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type) of the second well region 118 (i.e., the drift region). Therefore, a PN junction diode structure of the conductive termination structure 121 exists between the second well region 118 and the third well region 120. In various embodiments, during operation of the integrated chip 200, the PN junction diode structure of the conductive termination structure 121 facilitates the transfer of charge carriers from the second well region 118 to the contact region 136 and / or the conductive gate electrode 134. This reduces the electric field strength along the surface of the device substrate 108, thereby improving the breakdown voltage capability of the high-voltage transistor 122. In various embodiments, the contact region 136 is electrically coupled to the conductive gate electrode 134 via two or more conductive contacts 142 and at least one wire 144. This facilitates the transfer of charge carriers from contact region 136 to conductive gate electrode 134, allowing conductive gate electrode 134 to store and / or accumulate charge carriers when high-voltage transistor 122 operates at high voltage. Therefore, damage to semiconductor substrate 102 and / or high-voltage transistor 122 can be mitigated at high operating voltages, thereby increasing the breakdown voltage capability of high-voltage transistor 122.

[0043] The conductive gate electrode 134 may be, for example, polysilicon and / or a metal gate material, such as tungsten, titanium, tantalum, aluminum, another suitable conductive material, or any combination of the foregoing materials. The peripheral gate dielectric layer 133 may be, for example, silicon dioxide, a high-k dielectric material, etc. In a further embodiment, the conductive gate electrode 134 comprises the same conductive material as the gate electrode 130 (e.g., polysilicon). In a further embodiment, the peripheral gate dielectric layer 133 comprises the same dielectric material as the gate dielectric layer 128 (e.g., a high-k dielectric material). In various embodiments, the contact region 136 has a depth of approximately 10... 14 Up to 10 16 atoms / cm 3 The doping concentration is within the range of or another suitable value.

[0044] The conductive gate electrode 134 includes a first sidewall 134s1 and a second sidewall 134s2 opposite to the first sidewall 134s1. In various embodiments, the outer opposing sidewalls of the peripheral gate dielectric layer 133 are aligned with the first sidewall 134s1 and the second sidewall 134s2 of the conductive gate electrode 134. In some embodiments, the first sidewall 134s1 is aligned with the outer sidewall of the first isolation segment 110a (e.g., a first lateral distance (L1 in FIG. 1A) is zero). The second sidewall 134s2 of the conductive gate electrode 134 is laterally offset from the outer sidewall of the first isolation segment 110a by a second lateral distance L2. In some embodiments, the second lateral distance L2 is in the range of about 0.3 μm to 7 μm or another suitable value. In embodiments, if the second lateral distance L2 is relatively small (e.g., less than about 0.3 μm), the overall size of the conductive gate electrode 134 is reduced, thereby mitigating the ability of the conductive gate electrode 134 to reduce the electric field strength along the surface of the device substrate 108. This may reduce the breakdown capability of the high-voltage transistor 122. In another embodiment, if the second lateral distance L2 is relatively large (e.g., greater than about 7 μm), the conductive gate electrode 134 may be relatively close to the drain region 132 and / or may be located on at least a portion of the drain region 132. This may cause charge carriers to tunnel from the drain region 132 through the peripheral gate dielectric layer 133 into the conductive gate electrode 134, thereby damaging the peripheral gate dielectric layer 133 and / or reducing the performance of the high-voltage transistor 122. In a further embodiment, the second lateral distance L2 may correspond to the width of the conductive gate electrode 134.

[0045] Furthermore, the sidewall 130s1 of the gate electrode 130 is laterally offset from the outer sidewall of the second isolation section 110b by a third lateral distance L3. In some embodiments, the third lateral distance L3 is in the range of about 0.3 μm to 7 μm or another suitable value. In embodiments, if the third lateral distance L3 is relatively small (e.g., less than about 0.3 μm), the overall size of the gate electrode 130 may be quite small, thereby reducing the performance of the high-voltage transistor 122. In yet another embodiment, if the third lateral distance L3 is relatively large (e.g., greater than about 7 μm), the gate electrode 130 may be relatively close to the drain region 132. This may adversely affect the flow of charge carriers from the source region 126 to the drain region 132, thereby reducing the performance of the high-voltage transistor 122 (e.g., reducing the breakdown voltage capability of the high-voltage transistor 122).

[0046] Figure 3A shows a cross-sectional view of some embodiments of an integrated chip 300 including a conductive termination structure 121 configured to be laterally adjacent to a high-voltage transistor 122. The integrated chip 300 of Figure 3A may correspond to some embodiments of the integrated chip 100 of Figures 1A to 1C, wherein the high-voltage transistor 122 is configured as an NMOS transistor.

[0047] In various embodiments, a conductive termination structure 121 is laterally disposed between a conductive via 114 and a source region 126 of a high-voltage transistor 122. The processing substrate 104 includes a first doping type (e.g., p-type). As shown in FIG3A, the high-voltage transistor 122 is configured as an NMOS transistor, an n-channel LDMOS (n-LDMOS) transistor, or another suitable device. In such an embodiment, a body contact region 124 includes a first doping type (e.g., p-type) and a drain region 132, and a source region 126 and a lightly doped region 202 each include a second doping type (e.g., n-type) opposite to the first doping type. In various embodiments, the first doping type is p-type and the second doping type is n-type. Furthermore, a first well region 116 is laterally disposed between a second well region 118 and a third well region 120. In some embodiments, the first well region 116 includes a first doping type (e.g., p-type), and the second well region 118 and the third well region 120 each include a second doping type (e.g., n-type). In various embodiments, the second well region 118 is configured as a drift region (or "drain extension region"), such that the third well region 120 of the conductive termination structure 121 is laterally separated from the drift region by the first well region 116.

[0048] In various embodiments, when the conductive termination structure 121 is laterally adjacent to the source region 126 and / or the body contact region 124, the third well region 120 and the contact region 136 each include a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type) of the first well region 116. Therefore, a PN junction diode structure of the conductive termination structure 121 exists between the first well region 116 and the third well region 120. In various embodiments, during operation of the integrated chip 300, the PN junction diode structure of the conductive termination structure 121 facilitates the transfer of charge carriers from the first well region 116 to the contact region 136 and / or the conductive gate electrode 134. This reduces the electric field strength along the surface of the device substrate 108, thereby improving the breakdown voltage capability of the high-voltage transistor 122. In a further embodiment, the second well region 118 (i.e., the drift region) and the third well region 120 of the conductive termination structure 121 include the same doping type (e.g., n-type).

[0049] In various embodiments, the drain region 132, the source region 126, and the contact region 136 include a second doping type (e.g., n-type) and may have a doping density of about 10. 14 Up to 10 16 atoms / cm 3 The doping concentration is within the range of or another suitable value. In a further embodiment, the second well region 118 and the third well region 120 include a second doping type (e.g., n-type) and may have a doping concentration of about 10. 11 Up to 10 13 atoms / cm 3 The doping concentration is within the range of or another suitable value. In some embodiments, the first well region 116 includes a first doping type (e.g., p-type) and may have a doping concentration of about 10. 11 Up to 10 13 atoms / cm 3 The doping concentration is within the range of or another suitable value.

[0050] Figure 3B shows a top view of some embodiments of the integrated chip 300 taken along line B-B' of Figure 3A. For clarity and ease of illustration, the first isolation structure 110 and the second isolation structure 112 are omitted from the top view of Figure 3B.

[0051] In some embodiments, as shown in the top view of FIG3B, the gate electrode 130, source region 126, body contact region 124, first well region 116, conductive gate electrode 134, third well region 120, contact region 136, and conductive via 114 are concentric annular regions / structures. It should be understood that although the aforementioned regions / structures appear as rectangular annular rings when viewed from above in FIG3B, they can also be, for example, square annular rings, triangular annular rings, circular annular rings, elliptical annular rings, or some other closed-path shape. In a further embodiment, the gate electrode 130, source region 126, body contact region 124, first well region 116, conductive gate electrode 134, third well region 120, contact region 136, and conductive via 114 are concentric with each other and / or each is concentric with respect to the center of the drain region 132.

[0052] Figure 3C shows a cross-sectional view of some alternative embodiments of the integrated chip 300 of Figures 3A and 3B, wherein the first sidewall 134s1 of the conductive gate electrode 134 is aligned with the outer sidewall of the first isolation segment 110a of the first isolation structure 110.

[0053] Figure 4A shows a graph 400a illustrating some embodiments of the integrated chip of Figures 1A to 1C, 2, or 3A to 3B. Graph 400a provides an example of the operating conditions applied to the integrated chip. However, it should be understood that other operating conditions are also possible, and thus graph 400a is merely an example. The x-axis of graph 400a corresponds to a first voltage V1, and the y-axis of graph 400a corresponds to a second voltage V2.

[0054] As shown in Figure 4A, in various embodiments, the first voltage V1 may correspond to a bias applied to the source region (126 in Figure 1A) and the gate electrode (130 in Figure 1A), and the second voltage V2 may correspond to the voltage at the conductive gate electrode (134 in Figure 1A) and / or the contact region (136 in Figure 1A). Voltage curve 410 reflects the operating characteristics of the high-voltage transistor (122 in Figure 1A) and the conductive termination structure (121 in Figure 1A). In such an embodiment, during operation of the integrated chip (100 in Figure 1A), the first voltage V1 is applied to the source region (126 in Figure 1A) and the gate electrode (130 in Figure 1A), the processing substrate (104 in Figure 1A) is electrically coupled to ground (e.g., 0V) via a conductive via (114 in Figure 1A), and the drain region (132 in Figure 1A) is electrically coupled to ground (e.g., 0V). In a further embodiment, under such operating conditions, the value of the second voltage V2 at the conductive gate electrode (134 in FIG. 1A) can be represented by the equation: V2 = X * V1, where X is a positive number in the range of about 0.01 to 0.02, about 0.014, or another suitable value. Therefore, as shown in voltage curve 410, the magnitude of the second voltage V2 at the conductive gate electrode (134 in FIG. 1A) increases with the increase of the magnitude of the first voltage V1. This is partly because charge carriers can pass through the PN junction diode structure of the conductive termination structure (121 in FIG. 1A) to the conductive gate electrode (134 in FIG. 1A). Therefore, as the first voltage V1 applied to the source region (126 in FIG. 1A) and / or the gate electrode (130 in FIG. 1A) increases, the conductive termination structure (121 in FIG. 1A) promotes a decrease in the electric field strength along the surface of the device substrate (108 in FIG. 1A).

[0055] In various embodiments, the first voltage V1 can be increased from a first voltage value 402 to a second voltage value 404, wherein the first voltage value 402 is approximately +5V, +10V, or another suitable value, and the second voltage value 404 is approximately +100V, +105V, +110V, or another suitable value. In a further embodiment, the second voltage V2 can be increased from a third voltage value 406 to a fourth voltage value 408, wherein the third voltage value 406 is approximately +0.05V, +0.07V, or another suitable value, and the fourth voltage value 408 is approximately +1.55V, +1.5V, or another suitable value.

[0056] Figure 4B shows a graph 400b illustrating some embodiments of the integrated chip of Figures 1A to 1C, 2, or 3A to 3B. Graph 400b provides an example of the operating conditions applied to the integrated chip. However, it should be understood that other operating conditions are also possible, and thus graph 400b is merely an example. The x-axis of graph 400a corresponds to a first voltage V1, and the y-axis of graph 400a corresponds to a second voltage V2.

[0057] As shown in Figure 4B, in some embodiments, the first voltage V1 may correspond to a bias applied to the drain region (132 in Figure 1A), and the second voltage V2 may correspond to the voltage at the conductive gate electrode (134 in Figure 1A) and / or the contact region (136 in Figure 1A). Voltage curve 412 reflects the operating characteristics of the high-voltage transistor (122 in Figure 1A) and the conductive termination structure (121 in Figure 1A). In such an embodiment, during operation of the integrated chip (100 in Figure 1A), the first voltage V1 is applied to the drain region (132 in Figure 1A), and the processed substrate (104 in Figure 1A), the source region (126 in Figure 1A), and the gate electrode (130 in Figure 1A) are each electrically coupled to ground (e.g., 0V). Under such operating conditions, the value of the second voltage V2 at the conductive gate electrode (134 in FIG1A) can be represented, for example, by the equation: V2 = Y * V1, where Y is a positive number in the range of about 0.20 to 0.40, about 0.314, or another suitable value.

[0058] In various embodiments, the first voltage V1 can be increased from a first voltage value 402 to a second voltage value 404, wherein the first voltage value 402 is about -0.01V, -0.05V, or another suitable value, and the second voltage value 404 is about -100V, -105V, -110V, or another suitable value. In a further embodiment, the second voltage V2 can be increased from a third voltage value 406 to a fourth voltage value 408, wherein the third voltage value 406 is about -0.05V, -0.05V, or another suitable value, and the fourth voltage value 408 is about -30V, -35V, or another suitable value.

[0059] Figures 5A to 5B to 11A to 11B illustrate various views of embodiments of a method according to the present invention for forming an integrated chip including a conductive termination structure configured laterally adjacent to a high-voltage transistor. Figures with the suffix "A" show cross-sectional views of the integrated chip during various forming processes. Figures with the suffix "B" show top views taken along line A-A' of the figures with the suffix "A". While the various views shown in Figures 5A to 5B to 11A to 11B are described with reference to the method, it should be understood that the structures shown in Figures 5A to 5B to 11A to 11B are not limited to this method but can exist independently of it. While Figures 5A to 5B to 11A to 11B describe a series of steps, it should be understood that these steps are not limiting, as the order of the steps can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some steps shown and / or described may be omitted, in whole or in part.

[0060] As shown in cross-sectional view 500a and top view 500b of Figures 5A and 5B, a semiconductor substrate 102 is provided. In some embodiments, the semiconductor substrate 102 is configured as an SOI substrate and includes a processing substrate 104, a device substrate 108, and an insulating layer 106 disposed between the processing substrate 104 and the device substrate 108. A process for forming the semiconductor substrate 102 may include: depositing the insulating layer 106 over the processing substrate 104 (e.g., by thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.); and bonding the device substrate 108 to the insulating layer 106. The processing substrate 104 may include a first doping type (e.g., p-type). In various embodiments, the processing substrate 104 and the device substrate 108 may each have a resistance in the range of about 1 to 100 ohm-cm (Ω*cm) or another suitable value. In a further embodiment, the thickness of the device substrate 108 is greater than the thickness of the processing substrate 104.

[0061] As shown in cross-sectional view 600a and top view 600b of Figures 6A to 6B, a first isolation structure 110 and a second isolation structure 112 are formed within a device substrate 108. In some embodiments, the process for forming the first isolation structure 110 may include: forming a masking layer (not shown) over a top surface of the device substrate 108; selectively etching the device substrate 108 according to the masking layer to form an opening extending into the top surface of the device substrate 108; filling the opening with a dielectric material (e.g., by CVD, PVD, ALD, thermal oxidation, etc.); and performing a removal process to remove the masking layer. In some embodiments, after filling the opening with the dielectric material, a planarization process (e.g., chemical mechanical planarization (CMP)) may be performed on the dielectric material. In various embodiments, the second isolation structure 112 may be formed by a process substantially similar to the process described above for forming the first isolation structure. In a further embodiment, the first isolation structure 110 is formed such that the first isolation structure 110 includes a first isolation segment 110a laterally offset from the second isolation segment 110b by a non-zero distance. In a further embodiment, the first width w1 of the first isolation segment 110a is greater than the second width w2 of the second isolation segment 110b. In a further embodiment, the first width w1 and the second width w2 are each in the range of about 1 μm to 10 μm or another suitable value. In some embodiments, as seen in FIG6B, the first isolation structure 110 and the second isolation structure 112 are formed such that the first isolation structure 110 and the second isolation structure 112 are and / or include one or more annular structures.

[0062] As shown in cross-sectional view 700a and top view 700b of Figures 7A to 7B, a conductive via 114 is formed within a device substrate 108. In some embodiments, the process for forming the conductive via 114 includes: selectively etching a second isolation structure 112 and an insulating layer 106 to form a trench extending from the top surface of the device substrate 108 to the processing substrate 104; depositing (e.g., by CVD, PVD, sputtering, electroplating, electroless plating, etc.) a conductive material (e.g., titanium, copper, aluminum, tungsten, tantalum, etc.) within the trench; and performing a planarization process (e.g., CMP process) on the conductive material. In various embodiments, the planarization process is performed such that the top surface of the conductive via 114 is coplanar with the top surfaces of the first isolation structure 110, the second isolation structure 112, and / or the top surface of the device substrate 108. In a further embodiment, the second isolation structure 112 laterally surrounds the conductive via 114, thereby separating the conductive via 114 from the device substrate 108. In some embodiments, as seen in FIG7B, the conductive via 114 is formed such that the conductive via 114 is an annular structure.

[0063] As shown in cross-sectional view 800a and top view 800b of Figures 8A and 8B, one or more ion implantation processes are performed on device substrate 108 to form one or more doped regions within device substrate 108. In various embodiments, one or more ion implantation processes may be performed to form a first well region 116, a second well region 118, and a third well region 120. In some embodiments, the second well region 118 includes a first doping type (e.g., p-type), and the first well region 116 and the third well region 120 each include a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type). In a further embodiment, each of the one or more ion implantation processes may include: forming a masking layer (not shown) over the top surface of device substrate 108; selectively implanting dopant into device substrate 108 according to the masking layer; and performing a removal process to remove the masking layer. In a further embodiment, a first ion implantation process may be performed to form the first well region 116 and the third well region 120, and a different second ion implantation process may be performed to form the second well region 118. The p-type dopant of the first doping type can be, for example, or include boron, boron difluoride (e.g., BF2), indium, some other suitable p-type dopant, or any combination of the foregoing materials. Furthermore, the n-type dopant of the second doping type can be, for example, or include phosphorus, arsenic, antimony, some other suitable n-type dopant, or any combination of the foregoing materials. In various embodiments, the second well region 118 can be configured as a drift region. In some embodiments, as seen in FIG8B, the second well region 118 and the third well region 120 are formed such that the second well region 118 and the third well region 120 are toroidal regions.

[0064] As shown in cross-sectional view 900a and top view 900b of Figures 9A to 9B, a gate structure 902 and a terminal gate structure 904 are formed over the top surface of a device substrate 108. The gate structure 902 includes a gate dielectric layer 128 and a gate electrode 130 located on the gate dielectric layer 128, and the terminal gate structure 904 includes a peripheral gate dielectric layer 133 and a conductive gate electrode 134 located on the peripheral gate dielectric layer 133. In some embodiments, the process for forming the gate structure 902 and the terminal gate structure 904 includes: depositing (e.g., by CVD, PVD, ALD, thermal oxidation, etc.) a gate dielectric structure over the top surface of the device substrate 108; depositing (e.g., by CVD, PVD, sputtering, electroplating, chemical plating, etc.) a gate electrode layer over the gate dielectric material; and patterning the gate dielectric structure and the gate electrode layer through a masking layer (not shown) to define the gate electrode 130, the gate dielectric layer 128, the conductive gate electrode 134, and the peripheral gate dielectric layer 133. Therefore, in some embodiments, the gate structure 902 may be formed simultaneously with the terminating gate structure 904. The gate dielectric structure may be, for example, silicon dioxide, a high-k dielectric material, etc. The gate electrode layer may be, for example, polysilicon and / or a metal gate material, such as tungsten, titanium, tantalum, aluminum, another suitable conductive material, or any combination of the foregoing materials. In some embodiments, as seen in FIG9B, the gate structure 902 and the terminating gate structure 904 are formed such that the gate structure 902 and the terminating gate structure 904 are ring structures.

[0065] In a further embodiment, the terminal gate structure 904 is configured such that the first sidewall 134s1 of the conductive gate electrode 134 is laterally offset from the outer sidewall of the first isolation segment 110a by a first lateral distance L1, and the second sidewall 134s2 of the conductive gate electrode 134 is laterally offset from the outer sidewall of the first isolation segment 110a by a second lateral distance L2. In some embodiments, the first lateral distance L1 is in the range of about 0 μm to 0.2 μm or another suitable value, and the second lateral distance L2 is in the range of about 0.3 μm to 7 μm or another suitable value. In various embodiments, the first lateral distance L1 is equal to 0, thereby aligning the outer sidewall of the first isolation segment 110a with the first sidewall 134s1 of the conductive gate electrode 134 (e.g., as shown and / or described in FIG. 2). In a further embodiment, the gate structure 902 is configured such that the sidewall 130s1 of the gate electrode 130 is laterally offset from the outer sidewall of the second isolation segment 110b by a third lateral distance L3. In some embodiments, the third lateral distance L3 is in the range of about 0.3 μm to 7 μm or another suitable value.

[0066] As shown in cross-sectional views 1000a and top views 1000b of Figures 10A and 10B, one or more ion implantation processes are performed on a device substrate 108 to define doped regions within the device substrate 108 and to define a high-voltage transistor 122 and a conductive termination structure 121 on the device substrate 108. In some embodiments, one or more ion implantation processes are performed to form a bulk contact region 124, a source region 126, and a lightly doped region 202 within a first well region 116, a drain region 132 within a second well region 118, and a contact region 136 within a third well region 120. In some embodiments, the source region 126, the lightly doped region 202, and the drain region 132 include a first doping type (e.g., p-type), and the contact region 136 and the bulk contact region 124 include a second doping type (e.g., n-type). In a further embodiment, each of the one or more ion implantation processes may include: forming a masking layer (not shown) over a top surface of the device substrate 108; selectively implanting a dopant into the device substrate 108; and performing a removal process to remove the masking layer. In a further embodiment, a first ion implantation process may be implemented to form a lightly doped region 202, a second ion implantation process may be implemented to form a drain region 132 and a source region 126, and a third ion implantation process may be implemented to form a contact region 136 and a bulk contact region 124. In some embodiments, as seen in FIG10B, one or more ion implantation processes are implemented such that the source region 126, the drain region 132, and / or the contact region 136 are annular regions.

[0067] The high-voltage transistor 122 includes a gate electrode 130, a gate dielectric layer 128, a source region 126, and a drain region 132. In various embodiments, the process for forming the high-voltage transistor 122 includes at least a portion of the process steps shown and / or described in Figures 7A to 11B. The conductive termination structure 121 includes a conductive gate electrode 134, a peripheral gate dielectric layer 133, and a contact region 136. In some embodiments, the process for forming the conductive termination structure 121 includes at least a portion of the process steps shown and / or described in Figures 7A to 11B. In a further embodiment, the high-voltage transistor 122 may be formed simultaneously with the conductive termination structure 121.

[0068] As shown in the cross-sectional view 1100a and top view 1100b of Figures 11A and 11B, an interconnect structure 1102 is formed over a device substrate 108. The interconnect structure 1102 includes a dielectric structure 140, a plurality of conductive contacts 142, and a plurality of wires 144. In various embodiments, the dielectric structure 140 can be formed by a CVD process, a PVD process, an ALD process, or another suitable deposition or growth process. In further embodiments, the plurality of conductive contacts 142 and the plurality of wires 144 can be formed by one or more patterning processes, one or more deposition processes, and / or other suitable fabrication processes. For clarity and ease of illustration, the dielectric structure 140 and the plurality of conductive contacts 142 are omitted from the top view of Figure 11B.

[0069] Figure 12 illustrates a method 1200 according to the present invention for forming an integrated chip including a conductive termination structure configured to be laterally adjacent to a high-voltage transistor. While method 1200 is shown and / or described as a series of steps or events, it should be understood that the method is not limited to the shown order or steps. Therefore, in some embodiments, steps may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown steps or events may be subdivided into multiple steps or events that may be performed at different times or simultaneously with other steps or sub-steps. In some embodiments, some shown steps or events may be omitted, and other steps or events not shown may be included.

[0070] In step 1202, an isolation structure is formed within the device substrate, wherein the device substrate is located above the insulating layer and the processing substrate is located below the insulating layer. Figures 6A and 6B show various views corresponding to some embodiments of step 1202.

[0071] In step 1204, a conductive via is formed extending through the device substrate to the processing substrate. Figures 7A and 7B show various views corresponding to some embodiments of step 1204.

[0072] In step 1206, a doping process is performed on the device substrate to form a first well region, a second well region, and a third well region, wherein the second well region is located between the first well region and the third well region. Figures 8A and 8B show various views corresponding to some embodiments of step 1206.

[0073] In step 1208, a gate electrode is formed over the device substrate such that the gate electrode is located on the first interface between the first well region and the second well region. Figures 9A and 9B show various views corresponding to some embodiments of step 1208.

[0074] In step 1210, a conductive gate electrode is formed above the isolation structure. Figures 9A and 9B show various views corresponding to some embodiments of step 1210.

[0075] In step 1212, a doping process is performed on the device substrate to form a source region, a drain region, and a contact region within the device substrate. A gate electrode is disposed between the source and drain regions, and the contact region is disposed within a third well region between the conductive via and the conductive gate electrode. Figures 10A and 10B show various views corresponding to some embodiments of step 1212.

[0076] Therefore, in some embodiments, this application relates to a high-voltage transistor device disposed on a device substrate, wherein the device substrate is separated from an underlying processing substrate by an insulating layer. Conductive vias extend through the device substrate to the processing substrate, and conductive termination structures are disposed on the device substrate laterally located between the high-voltage transistor device and the conductive vias.

[0077] In some embodiments, this application provides an integrated chip, comprising: a semiconductor substrate, including a device substrate located on a processing substrate and an insulating layer disposed between the device substrate and the processing substrate; a gate electrode located on the device substrate between a drain region and a source region; a conductive via extending through the device substrate and the insulating layer to contact the processing substrate; a first isolation structure disposed within the device substrate and including a first isolation segment laterally disposed between the gate electrode and the conductive via; a contact region disposed within the device substrate between the first isolation segment and the conductive via; and a conductive gate electrode directly located on the first isolation segment, wherein the conductive gate electrode is electrically coupled to the contact region. In embodiments, the integrated chip further comprises: a first well region disposed within the device substrate; a second well region disposed within the device substrate and adjacent to the first well region at a first interface, wherein the second well region includes a first doping type, and the first well region includes a second doping type opposite to the first doping type, and wherein the gate electrode is directly located on the first interface; and a third well region disposed within the device substrate and adjacent to the second well region at a second interface, wherein the third well region includes a second doping type, and wherein the conductive gate electrode is directly located on the second interface. In one embodiment, a drain region is disposed within a second well region, a source region is disposed within a first well region, and a contact region is disposed within a third well region, such that a conductive gate electrode is electrically coupled to the third well region via the contact region. In another embodiment, the source and drain regions include a first doping type, and the contact region includes a second doping type; the first doping type is p-type, and the second doping type is n-type. In another embodiment, a first isolation segment extends continuously from the sidewall of the contact region to the sidewall of the drain region, wherein the conductive gate electrodes are laterally spaced between the outer opposite sidewalls of the first isolation segment. In another embodiment, the conductive gate electrode is annular and laterally surrounds the drain region and the gate electrode. In another embodiment, the contact region is annular, such that the contact region surrounds the conductive gate electrode. In yet another embodiment, the integrated chip further includes a second isolation structure disposed within a device substrate and laterally surrounding a conductive via, wherein the second isolation structure extends continuously from the top surface of the device substrate to the top surface of an insulating layer. In one embodiment, the integrated chip further includes an interconnect structure located on the device substrate, wherein the interconnect structure includes a plurality of conductive contacts and a plurality of wires disposed within a dielectric structure, wherein a conductive gate electrode is coupled to a contact region via the conductive contacts and wires.

[0078] In some embodiments, this application provides an integrated chip, comprising: a device substrate located above an insulating layer and a processing substrate located below the insulating layer; a first well region, a second well region, and a third well region disposed within the device substrate, wherein the second well region is laterally spaced between the first well region and the third well region; a high-voltage transistor disposed on the device substrate, including a gate electrode, a source region, and a drain region, wherein the gate electrode is disposed between the source region and the drain region, and wherein the gate electrode is directly located on a first interface between the first well region and the second well region; a conductive via disposed within the device substrate and electrically coupled to the processing substrate, wherein the conductive via is adjacent to the third well region; and a conductive termination structure disposed on the device substrate between the conductive via and the high-voltage transistor, wherein the conductive termination structure includes a contact region disposed within the third well region and a conductive gate electrode located on a second interface between the second well region and the third well region, wherein the conductive gate electrode is electrically coupled to the third well region via the contact region. In one embodiment, the integrated chip further includes: a first isolation structure disposed within a device substrate, wherein the first isolation structure includes a first isolation segment laterally offset from a second isolation segment, wherein the first isolation segment separates a conductive gate electrode from the device substrate, and wherein the gate electrode is directly located on at least a portion of the second isolation segment. In another embodiment, the integrated chip further includes: a peripheral gate dielectric layer disposed between the conductive gate electrode and the first isolation segment, wherein the top surface of the first isolation segment directly contacts the entire bottom surface of the peripheral gate dielectric layer. In another embodiment, a contact region is adjacent to an outer wall of the first isolation segment, wherein the opposite outer wall of the conductive gate electrode is laterally offset from the outer wall of the first isolation segment in a direction toward the high-voltage transistor. In another embodiment, the gate electrode and the conductive gate electrode are annular and concentric with each other. In another embodiment, the conductive via is annular and laterally wraps around the outer periphery of the conductive termination structure. In another embodiment, the contact region and the third well region include the same doping type.

[0079] In some embodiments, this application provides a method for manufacturing an integrated chip, comprising: forming a first isolation structure in a device substrate, wherein the device substrate is located above an insulating layer and a processing substrate is located below the insulating layer; forming a conductive via extending through the device substrate to the processing substrate; doping the device substrate to form a first well region, a second well region, and a third well region within the device substrate, wherein the second well region is laterally spaced between the first well region and the third well region; forming a gate electrode above the device substrate such that the gate electrode is located above a first interface between the first well region and the second well region; forming a conductive gate electrode above the first isolation structure; and doping the device substrate to form a source region, a drain region, and a contact region within the device substrate, wherein the gate electrode is disposed between the source region and the drain region, and wherein the contact region is disposed within the third well region between the conductive via and the conductive gate electrode. In embodiments, the method further comprises: forming an interconnect structure above the device substrate including a plurality of conductive contacts and a plurality of wires disposed within a dielectric structure, wherein the conductive gate electrode is electrically coupled to the contact region via the interconnect structure. In one embodiment, the contact region is adjacent to the outer wall of the first isolation structure, wherein the conductive gate electrode is laterally offset from the outer wall of the first isolation structure by a non-zero distance. In another embodiment, the method further includes forming a second isolation structure in a device substrate, wherein the second isolation structure extends from the top surface of the device substrate to an insulating layer, and wherein the second isolation structure laterally surrounds a conductive via.

[0080] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An integrated chip, comprising: A semiconductor substrate, comprising a device substrate located on a processing substrate and an insulating layer disposed between the device substrate and the processing substrate; The gate electrode is located on the device substrate between the drain region and the source region; A conductive via extends through the device substrate and the insulating layer to contact the processing substrate; A first isolation structure is disposed within the device substrate and includes a first isolation segment laterally disposed between the gate electrode and the conductive via. The contact area is disposed within the device substrate between the first isolation section and the conductive via; And the conductive gate electrode is located directly on the first isolation section; A first well region is disposed within the device substrate; The second well region is disposed within the device substrate and adjacent to the first well region at the first interface. A third well region is disposed within the device substrate and adjacent to the second well region at a second interface. The gate electrode is directly located on the first interface between the first and second well regions. The conductive gate electrode is located on the second interface between the second and third well regions. The drain region is disposed within the second well region. The source region is disposed within the first well region. The contact region is disposed within the third well region, such that the conductive gate electrode is electrically coupled to the third well region via the contact region. A PN junction diode structure exists between the second and third well regions, facilitating the transfer of charge carriers from the second well region to the contact region and / or the conductive gate electrode.

2. The integrated chip according to claim 1, wherein, The second well region includes a first doping type, and the first well region includes a second doping type opposite to the first doping type, wherein the gate electrode is directly located on the first interface; and wherein the third well region includes the second doping type, wherein the conductive gate electrode is directly located on the second interface.

3. The integrated chip according to claim 1, wherein, The contact area is adjacent to the outer wall of the first isolation structure, wherein the conductive gate electrode is laterally offset from the outer wall of the first isolation structure by a non-zero distance.

4. The integrated chip according to claim 3, wherein, The source region and the drain region include a first doping type, and the contact region includes a second doping type, wherein the first doping type is p-type and the second doping type is n-type.

5. The integrated chip according to claim 1, wherein, The first isolation segment extends continuously from the sidewall of the contact region to the sidewall of the drain region, wherein the conductive gate electrodes are laterally spaced between the outer opposite sidewalls of the first isolation segment.

6. The integrated chip according to claim 1, wherein, The conductive gate electrode is annular and laterally surrounds the drain region and the gate electrode.

7. The integrated chip according to claim 6, wherein, The contact area is annular, thereby surrounding the conductive gate electrode.

8. The integrated chip according to claim 1, further comprising: A second isolation structure is disposed within the device substrate and laterally surrounds the conductive via, wherein the second isolation structure extends continuously from the top surface of the device substrate to the top surface of the insulating layer.

9. The integrated chip according to claim 1, further comprising: An interconnect structure is located on the device substrate, wherein the interconnect structure includes a plurality of conductive contacts and a plurality of wires disposed within a dielectric structure, wherein the conductive gate electrode is coupled to the contact region via the conductive contacts and the wires.

10. An integrated chip, comprising: A device substrate and a processing substrate, wherein the device substrate is located on an insulating layer and the processing substrate is located below the insulating layer; A first well region, a second well region, and a third well region are disposed within the device substrate, wherein the second well region is laterally spaced between the first well region and the third well region; a high-voltage transistor is disposed on the device substrate, including a gate electrode, a source region, and a drain region, wherein the gate electrode is disposed between the source region and the drain region, and wherein the gate electrode is directly located on the first interface between the first well region and the second well region; a conductive via is disposed within the device substrate and electrically coupled to the processing substrate, wherein the conductive via is adjacent to the third well region; and a conductive termination structure is provided. On the device substrate between the conductive via and the high-voltage transistor, the conductive termination structure includes a contact region disposed within the third well region and a conductive gate electrode located on a second interface between the second well region and the third well region, wherein the conductive gate electrode is electrically coupled to the third well region via the contact region, wherein a PN junction diode structure of the conductive termination structure exists between the second well region and the third well region, wherein the PN junction diode structure of the conductive termination structure facilitates the transfer of charge carriers from the second well region to the contact region and / or the conductive gate electrode.

11. The integrated chip according to claim 10, further comprising: A first isolation structure is disposed within the device substrate, wherein the first isolation structure includes a first isolation segment laterally offset from a second isolation segment, wherein the first isolation segment separates the conductive gate electrode from the device substrate, and wherein the gate electrode is located directly on at least a portion of the second isolation segment.

12. The integrated chip according to claim 11, further comprising: A peripheral gate dielectric layer is disposed between the conductive gate electrode and the first isolation segment, wherein the top surface of the first isolation segment directly contacts the entire bottom surface of the peripheral gate dielectric layer.

13. The integrated chip according to claim 11, wherein, The contact area is adjacent to the outer wall of the first isolation section, wherein the opposite outer wall of the conductive gate electrode is laterally offset from the outer wall of the first isolation section in the direction toward the high voltage transistor.

14. The integrated chip according to claim 11, wherein, The gate electrode and the conductive gate electrode are ring-shaped and concentric with each other.

15. The integrated chip according to claim 11, wherein, The conductive via is annular and laterally wraps around the outer periphery of the conductive terminal structure.

16. The integrated chip according to claim 10, wherein, The contact region and the third well region include the same doping type.

17. A method for manufacturing an integrated chip, the method comprising: A first isolation structure is formed in a device substrate, wherein the device substrate is located above an insulating layer and a processing substrate is located below the insulating layer; a conductive via is formed extending through the device substrate to the processing substrate; the device substrate is doped to form a first well region, a second well region, and a third well region within the device substrate, wherein the second well region is laterally spaced between the first well region and the third well region; a gate electrode is formed above the device substrate such that the gate electrode is located on a first interface between the first well region and the second well region; a conductive gate electrode is formed above the first isolation structure; and the device substrate is doped to form a source region, a drain region, and a contact region within the device substrate. A domain, wherein the gate electrode is disposed between the source region and the drain region, and wherein the contact region is disposed within the third well region between the conductive via and the conductive gate electrode, the conductive gate electrode being electrically coupled to the third well region via the contact region, wherein the conductive gate electrode is located on a second interface between the second well region and the third well region, the drain region being disposed within the second well region, the source region being disposed within the first well region, wherein a PN junction diode structure exists between the second well region and the third well region, wherein the PN junction diode structure facilitates the transfer of charge carriers from the second well region to the contact region and / or the conductive gate electrode.

18. The method of claim 17, further comprising: An interconnection structure comprising multiple conductive contacts and multiple wires disposed within a dielectric structure is formed above the device substrate.

19. The method of claim 17, wherein, The contact area is adjacent to the outer wall of the first isolation structure, wherein the conductive gate electrode is laterally offset from the outer wall of the first isolation structure by a non-zero distance.

20. The method of claim 17, further comprising: A second isolation structure is formed in the device substrate, wherein the second isolation structure extends from the top surface of the device substrate to the insulating layer, and wherein the second isolation structure laterally surrounds the conductive via.

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