A method for fabricating SOT-MRAM magnetic tunnel junctions

Abstract

This invention discloses a method for fabricating a SOT-MRAM magnetic tunnel junction, comprising the following steps: providing a substrate, and sequentially stacking an SOT layer, a free layer, a tunnel junction barrier layer, a reference layer, a pinning layer, a capping layer, and a hard mask layer on the substrate; photolithography to pattern the hard mask layer; etching layer by layer at an incident angle close to the normal direction until the reference layer is completely etched; cleaning etching at a larger incident angle to remove redeposited material on the sidewalls until the tunnel junction barrier layer is completely etched; performing sidewall passivation treatment; repeating steps S4 and S5 until the free layer on the upper surface of the SOT layer is completely etched, finally forming an SOT-MRAM magnetic tunnel junction structure. This invention reduces or avoids short circuits and damage caused by metal redeposited material in the MTJ through etching on the SOT layer and sidewall cleaning; the added sidewall passivation process further eliminates short circuit problems caused by sidewall conductive material, improving yield and reliability.

Description

Technical Field

[0001] This invention relates to the field of magnetic memory technology, and in particular to a method for fabricating a SOT-MRAM memory cell based on spin orbital moment. Background Technology

[0002] Magnetoresistive Random Access Memory (MRAM) boasts advantages such as low power consumption, high speed, and radiation protection, making it a highly promising emerging storage technology. The basic storage unit of MRAM is a magnetic tunnel junction (MTJ). The core unit of a MTJ typically comprises three layers: a free layer, a reference layer, and a tunnel junction barrier layer. These layers are extremely thin, typically on the order of angstroms. The free layer and reference layer are generally composed of magnetic materials, while the tunneling layer is typically composed of oxides. MRAM stores information using the magnetic moments of the free and reference layers. When the squares of the magnetic moments of the free and reference layers are the same, the tunneling resistance of the MTJ is low; when the squares of the magnetic moments of the free and reference layers are antiparallel, the tunneling resistance is high. The MRAM read circuit determines the data state ("0" or "1") by reading the magnitude of the tunneling resistance. The square of the magnetic moment of the free layer can be changed by an applied current, thus the data state of the storage cell can be rewritten to "0" or "1" by a write current.

[0003] The core of a traditional STT-MRAM (Spin-Torque Magnetic Random Access Memory) cell is a magnetic tunnel junction (MTJ) stack, consisting of a pinned layer, a pinned layer above the pinned layer, a tunnel layer above the pinned layer, and a free layer above the tunnel layer. Write current must flow through the tunnel layer, causing damage and leading to reliability issues in STT-MRAM cells. Therefore, SOT-MRAM (Spin-Orbit Magnetic Random Access Memory) was developed. Because write current does not flow through the tunnel layer, SOT-MRAM has higher reliability than STT-MRAM.

[0004] MTJ etching typically employs either RIE (Reactive Ion Etching) or IBE (Ion Beam Etching). To avoid RIE chemical corrosion damaging its electromagnetic properties, MTJ etching generally prefers the IBE method. However, due to the metal top electrode covering it and the fact that the material forming the MTJ also contains metal elements, IBE etching is accompanied by sidewall metal deposition and plasma bombardment, which can lead to severe short circuits and magnetic damage.

[0005] Therefore, there are two major challenges in MTJ etching: short circuits and damage. Tunnel junctions are composed of metallic materials, and some metals produce etching products that are not volatile gases but solid residues. These residues easily adhere to the sidewalls of the tunnel junction, causing short circuits. This is the primary challenge in tunnel junction etching. Secondly, there is damage. The etching materials used during the etching process, whether chlorine- or fluorine-based gases in reactive ion etching or inert gas plasmas in ion beam etching, can damage the surface material of the device, thereby reducing device performance. Halogen gases in reactive ion etching continuously penetrate into the device, causing damage to the MTJ's magnetism. Ion beam etching disrupts the crystal lattice structure of the cell surface, forming a damage layer that also causes magnetic damage. In particular, the etching of MTJ tunnel junctions in SOT-MRAM should avoid damaging the SOT layer as much as possible.

[0006] Chemical etching in RIE or plasma bombardment in IBE can damage the surface magnetic layer of the MTJ sidewall. The resistance, TMR (tunneling magnetoresistance), and thermal stability of the damaged magnetic layer are degraded compared to normal MTJ. At the same time, halogen elements or oxygen and nitrogen ions present in the damaged magnetic layer can affect the performance or lifespan of the finished device through diffusion during subsequent high-temperature processing or use. Summary of the Invention

[0007] In view of the defects or improvement needs of the above-mentioned technologies, the present invention provides a method for preparing SOT-MRAM magnetic tunnel junctions, which solves the problem of short circuits and damage to MTJ tunnel junctions caused by the etching process of SOT-MRAM tunnel junctions in the prior art, and improves product yield and reliability.

[0008] To achieve the above and other related objectives, the present invention provides a method for preparing a SOT-MRAM magnetic tunnel junction, comprising the following steps:

[0009] Step S1: Provide a substrate, and sequentially stack an SOT layer, a free layer, a tunnel junction barrier layer, a reference layer, a pinned layer, a capping layer, and a hard mask layer on the substrate;

[0010] Step S2: Perform photolithography on the hard mask layer, and pattern the hard mask layer by etching and resist removal;

[0011] Step S3: Etch the part to be etched layer by layer at an incident angle close to the normal direction until the reference layer is completely etched and the tunnel junction barrier layer is slightly etched, at which point the etching ends and the etching is stopped.

[0012] Step S4: Clean and etch the above-mentioned etched part at an incident angle larger than that described in step S3 to reduce and remove redeposit on the sidewall. The endpoint of the etching and cleaning is that the tunnel junction barrier layer is completely etched and the free layer is partially etched.

[0013] Step S5: Apply bias power and introduce process gas to passivate the sidewalls etched in step S4.

[0014] Step S6: Repeat steps S4 and S5 on the etched part after passivation treatment until the free layer on the upper surface of the SOT layer is completely etched to perform sidewall passivation and form an SOT-MRAM magnetic tunnel junction structure.

[0015] As a further preferred embodiment, the hard mask layer material is a composite material formed from one or more of tantalum, aluminum, copper, tungsten, tantalum nitride, titanium nitride, silicon oxide, and silicon nitride.

[0016] As a further preferred embodiment, the thickness of the hard mask layer is 50nm to 100nm, and the thickness of the photoresist used for photolithography on the hard mask layer is 90nm to 700nm.

[0017] As a further preferred option, the etching gas introduced in steps S3 and S4 is a mixture of one or more of He, Ne, Ar, Kr, and Xe.

[0018] As a further preferred embodiment, the incident angle approaching the normal in step S3 is 0° to 30° with the normal, and the incident power is 300W to 600W.

[0019] As a further preferred embodiment, the larger incident angle in step S4 is 60° to 90° with respect to the normal, and the incident power is 100W to 300W.

[0020] As a further preferred embodiment, the process gas used for sidewall passivation in step S5 is a mixture of one or more of O2, N2, CO, CO2, and CH3OH.

[0021] As a further preferred option, the etching endpoint in each step can be precisely controlled by an endpoint detection device.

[0022] A memory comprising a SOT-MRAM magnetic tunnel junction, made by the method described in any one of the foregoing.

[0023] Compared with the prior art, the present invention has the following advantages or beneficial effects:

[0024] (1) This invention optimizes the etching process of SOT-MRAM magnetic tunnel junction. By precisely controlling the etching endpoint, etching and sidewall cleaning on the SOT layer are achieved, reducing or avoiding etching of the SOT layer. This can effectively reduce or avoid short circuits and damage caused by metal redeposition on MTJ stacks, thereby improving device performance and extending lifespan.

[0025] (2) Based on the etching process of SOT-MRAM magnetic tunnel junction, the present invention adds a sidewall passivation process, which can further eliminate the short circuit problem caused by the deposition of sidewall conductive material, and improve product yield and reliability. Attached Figure Description

[0026] Figure 1 This is a flowchart of the preparation method of the SOT-MRAM magnetic tunnel junction of the present invention;

[0027] Figure 2 This is a cross-sectional schematic diagram of the MTJ pattern transfer hard mask layer before etching according to the present invention;

[0028] Figure 3 This is a schematic cross-sectional view of the etched tunnel layer to the reference layer after the etched tunnel layer of the present invention has been completely etched;

[0029] Figure 4 This is a cross-sectional schematic diagram of the SOT-MRAM magnetic tunnel junction structure after sidewall cleaning and passivation treatment according to the present invention.

[0030] In the figure, 101 - substrate, 102 - SOT layer, 103 - free layer, 104 - tunnel junction barrier layer, 105 - reference layer, 106 - pinning layer, 107 - capping layer, and 108 - hard mask layer. Detailed Implementation

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0033] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature.

[0034] In this embodiment, combined with Figure 1 and 2 As shown, a method for fabricating a SOT-MRAM magnetic tunnel junction includes the following steps:

[0035] Step S1: Provide a substrate (101), and deposit an SOT layer (102), a free layer (103), a tunnel junction barrier layer (104), a reference layer (105), a pinned layer (106), a capping layer (107), and a hard mask layer (108) on the substrate (101) in sequence.

[0036] Specifically, the free layer (103), tunnel junction barrier layer (104), reference layer (105), pinning layer (106), and capping layer (107) stacked in sequence are collectively referred to as magnetic tunnel junction.

[0037] Step S2: Photolithography is performed on the hard mask layer (108). The hard mask layer (108) is patterned by etching and resist removal. The pattern of the hard mask layer (108) is determined by the pattern of the required magnetic tunnel junction layer.

[0038] Furthermore, as a preferred embodiment, the hard mask layer (108) material includes, but is not limited to, a composite material formed from one or more of tantalum, aluminum, copper, tungsten, tantalum nitride, titanium nitride, silicon oxide, and silicon nitride.

[0039] Furthermore, as a preferred embodiment, the thickness of the hard mask layer (108) is 50nm to 100nm, and the thickness of the photoresist on the hard mask layer (108) is 90nm to 700nm.

[0040] Step S3: For Figure 1 The workpiece to be etched is etched layer by layer at an incident angle close to the normal direction until the reference layer (105) is completely etched and the tunnel junction barrier layer (104) is slightly etched, at which point the etching ends and the etching stops.

[0041] Furthermore, as a preferred embodiment, the incident angle approaching the normal in step S3 is 0° to 30° with the normal, and the incident power is 300W to 600W.

[0042] Furthermore, as a preferred embodiment, the etching gas introduced in step S3 is a mixture of one or more of He, Ne, Ar, Kr, and Xe.

[0043] Specifically, step S3 can be etched using IBE or RIE. After the etching process in step S3, the unnecessary parts of the reference layer (105), pinning layer (106), and capping layer (107) of the magnetic tunnel junction are etched away, leaving only the patterned part covered by the hard mask layer (108). The schematic diagram of the part to be etched at this time is as follows. Figure 3 As shown. Since the magnetic tunnel junction is composed of metallic materials, some of the etching products of the metal are not volatile gases, but solid redeposits. These redeposits are very easy to adhere to the sidewalls of the magnetic tunnel junction, causing short circuits in the device.

[0044] Step S4: For example Figure 3 The workpiece to be etched is cleaned and etched at a larger incident angle to reduce and remove redeposit on the sidewalls. The end point of the etching cleanup is that the tunnel junction barrier layer (104) is completely etched and the free layer (103) is partially etched.

[0045] Furthermore, as a preferred embodiment, the etching gas introduced in step S4 is a mixture of one or more of He, Ne, Ar, Kr, and Xe.

[0046] Furthermore, as a preferred embodiment, the larger incident angle in step S4 is 60° to 90° with respect to the normal, and the incident power is 100W to 300W.

[0047] Specifically, step S4 can be etched using the IBE method. After cleaning and etching through the incident angle in step S4, the sidewall redeposition generated in step S3 is reduced and removed, and the unnecessary parts of the tunnel junction barrier layer (104) are etched away, leaving only the patterned part of the tunnel junction barrier layer (104) covered by the hard mask layer (108).

[0048] Step S5: Apply bias power and introduce process gas to passivate the sidewalls etched in step S4.

[0049] Furthermore, as a preferred embodiment, the process gas used for sidewall passivation in step S5 is a mixture of one or more of O2, N2, CO, CO2, and CH3OH.

[0050] Step S6: Repeat steps S4 and S5 on the etched part after passivation treatment until the free layer (103) on the upper surface of the SOT layer (102) is completely etched to passivate the sidewalls and form an SOT-MRAM magnetic tunnel junction structure.

[0051] Furthermore, as a preferred implementation, the etching endpoint in each step can be precisely controlled by an endpoint detection device.

[0052] Specifically, step S5 can apply bias power using the RIE method. After repeating steps S4 and S5 as described in step S6, the unwanted portion of the free layer (103) on the upper surface of the SOT layer is completely etched away, leaving only the patterned portion of the free layer (103) covered by the hard mask layer (108). Simultaneously, the second repeated step S4 process can further reduce and remove sidewall deposits. Through the above two etching processes to clean the sidewall solid deposits of the magnetic tunnel junction, the purpose of eliminating sidewall solid deposits can be achieved. Finally, after sidewall cleaning and passivation treatment, a layer is formed as shown in the image. Figure 4 The SOT-MRAM magnetic tunnel junction structure is shown.

[0053] The method for preparing SOT-MRAM magnetic tunnel junctions provided by this invention can produce SOT-MRAM memories with high yield, good reliability, and improved performance and lifespan.

[0054] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a SOT-MRAM magnetic tunnel junction, characterized in that, The method comprises the following steps: Step S1: providing a substrate, and sequentially laminating a SOT layer, a free layer, a tunnel junction barrier layer, a reference layer, a pinned layer, a cover layer, and a hard mask layer on the substrate; Step S2: performing photolithography on the hard mask layer, and patterning the hard mask layer by etching and adhesive removal; Step S3: performing layer-by-layer ion beam etching on the etching piece at an incident angle close to the normal, until the reference layer is completely etched and the tunnel junction barrier layer is slightly etched, and the etching is stopped, wherein the incident angle close to the normal is an angle of 0°-30° with the normal; Step S4: performing ion beam cleaning etching on the etching piece at an incident angle greater than that in step S3, to reduce and remove redeposits on the sidewall, and the etching cleaning endpoint is that the tunnel junction barrier layer is completely etched and the free layer is partially etched, wherein the greater incident angle is an angle greater than the incident angle close to the normal with the normal; Step S5: applying a bias power, and introducing a process gas to perform passivation treatment on the sidewall after etching in step S4; Step S6: repeating steps S4 and S5 on the etching piece after the passivation treatment, until the free layer on the upper surface of the SOT layer is completely etched, the sidewall passivation is performed, and a SOT-MRAM magnetic tunnel junction structure is formed.

2. The method of claim 1, wherein the SOT-MRAM magnetic tunnel junction is prepared by, The hard mask layer material is one or more than two composite materials formed of tantalum, aluminum, copper, tungsten, tantalum nitride, titanium nitride, silicon oxide, and silicon nitride.

3. The method of claim 1-2, wherein, The thickness of the hard mask layer is 50-100 nm, and the thickness of the photoresist for performing photolithography on the hard mask layer is 90-700 nm.

4. The method of claim 1, wherein the SOT-MRAM magnetic tunnel junction is prepared by, The etching gas introduced in steps S3 and S4 is one or more than two mixed gases formed of He, Ne, Ar, Kr, and Xe.

5. The method of claim 1, wherein the SOT-MRAM magnetic tunnel junction is prepared by, The incident power in step S3 is 300-600 W.

6. The method of claim 1, wherein the SOT-MRAM magnetic tunnel junction is prepared by, The greater incident angle in step S4 than in step S3 is an angle of 60°-90° with the normal, and the incident power is 100-300 W.

7. The method of claim 1, wherein the SOT-MRAM magnetic tunnel junction is prepared by, The process gas for sidewall passivation in step S5 is one or more than two mixed gases formed of O2, N2, CO, CO2, and CH3OH.

8. The method of claim 1, wherein the SOT-MRAM magnetic tunnel junction is prepared by, The etching endpoint in each step is accurately controlled by an endpoint detection device.

9. A memory including a SOT-MRAM magnetic tunnel junction, characterized in that, The SOT-MRAM magnetic tunnel junction is made by the preparation method in any one of claims 1-8.

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