Oscillator circuit and phase-locked loop circuit

Abstract

The application relates to the technical field of oscillator circuit, and discloses an oscillator circuit. A voltage reference circuit provides a power supply voltage; an input end of a temperature compensation current source circuit is connected with an output end of the voltage reference circuit, the temperature compensation current source circuit generates a temperature compensation current according to the power supply voltage; a ring oscillator is connected with the output end of the voltage reference circuit, the ring oscillator is also connected with an output end of the temperature compensation current source circuit, the ring oscillator carries out current limitation on a constant current provided by the power supply voltage according to the temperature compensation current, and generates a clock signal according to the power supply voltage and the constant current provided by the power supply voltage. Since the ring oscillator carries out current limitation on the constant current provided by the power supply voltage according to the temperature compensation current, the power supply rejection ratio of the ring oscillator is improved, the phase noise of the clock signal generated by the ring oscillator is reduced, and thus a high-precision oscillator circuit is provided. The application also discloses a phase-locked loop circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of oscillator circuit, for example, to an oscillator circuit and a phase-locked loop circuit. BACKGROUND

[0002] Near field communication technology (NFC) is a kind of short-range wireless communication technology, which is developed from radio frequency identification technology, and the communication distance can reach 10 cm, which is suitable for high security and less communication data scenes, so it is widely used in identity recognition, mobile payment and other fields. There are two kinds of modulation methods for transponder in NFC communication, one is passive load modulation, and the transponder couples the carrier signal of the interrogator through the antenna. The other is active load modulation, and the transponder itself generates a carrier signal. The protocol requires that the carrier signal of the transponder and the carrier signal of the interrogator differ by within 30°, and the fixed phase difference means a fixed frequency difference. The radio frequency carrier signal in NFC communication is generated by a phase-locked loop, so higher requirements are put forward for the phase-locked loop, and the oscillator is a key module of the phase-locked loop, which functions to output a clock signal meeting the frequency requirements and phase noise requirements. In order to obtain a high-precision phase-locked loop, a high-precision oscillator circuit is urgently needed. SUMMARY

[0003] The following presents a simplified summary of some aspects of the disclosed embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of the embodiments described in detail in the following detailed description, and is intended neither to identify key or critical elements nor to delineate the scope of such embodiments. Rather, the primary purpose of this summary is to present some concepts of the disclosed embodiments in a simplified form to the reader.

[0004] The present application provides an oscillator circuit and a phase-locked loop circuit to provide a high-precision oscillator circuit.

[0005] In some embodiments, the oscillator circuit comprises: a voltage reference circuit configured to provide a supply voltage; a temperature compensation current source circuit having an input connected to an output of the voltage reference circuit, the temperature compensation current source circuit configured to generate a temperature compensation current based on the supply voltage; and a ring oscillator having an input connected to the output of the voltage reference circuit and an input connected to an output of the temperature compensation current source circuit, the ring oscillator configured to current limit a constant current provided by the supply voltage based on the temperature compensation current and to generate a clock signal based on the supply voltage and the constant current.

[0006] In some embodiments, the phase-locked loop circuit comprises: an oscillator circuit as described above.

[0007] The oscillator circuit and the phase-locked loop circuit provided by the embodiments of the present disclosure can achieve the following technical effects: the ring oscillator performs current limiting on the constant current provided by the power supply voltage according to the temperature compensation current, and generates a clock signal according to the power supply voltage and the constant current. Since the ring oscillator performs current limiting on the constant current provided by the power supply voltage according to the temperature compensation current, the power supply rejection ratio of the ring oscillator is improved, and the phase noise of the clock signal is reduced, thereby providing a high-precision oscillator circuit.

[0008] The foregoing general description and the following description are only exemplary and explanatory, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0009] One or more embodiments are exemplarily illustrated by the corresponding drawings, which do not constitute a limitation on the embodiments, elements with the same reference numerals in the drawings are shown as similar elements, the drawings do not constitute a proportional limitation, and wherein:

[0010] Figure 1 is a structural schematic diagram of an oscillator circuit provided by an embodiment of the present disclosure;

[0011] Figure 2 is a structural schematic diagram of a voltage reference circuit provided by an embodiment of the present disclosure;

[0012] Figure 3 is a structural schematic diagram of a temperature compensation current source circuit provided by an embodiment of the present disclosure;

[0013] Figure 4 is a structural schematic diagram of a ring oscillator provided by an embodiment of the present disclosure;

[0014] Figure 5 is a structural schematic diagram of a differential inverter unit with current limiting provided by an embodiment of the present disclosure;

[0015] Figure 6 is a structural schematic diagram of a phase-locked loop circuit provided by an embodiment of the present disclosure.

[0016] Reference signs:

[0017] 1: voltage reference circuit; 2: temperature compensated current source circuit; 3: ring oscillator; 4: first NMOS (N-Metal-Oxide-Semiconductor) transistor; 5: first PMOS (positive channel Metal Oxide Semiconductor) transistor; 6: second PMOS transistor; 7: first adjustable resistor; 8: second adjustable resistor; 9: amplifier; 10: first current source; 11: second NMOS transistor; 12: third NMOS transistor; 13: third PMOS transistor; 14: first resistor; 15: second resistor; 16: second current source; 17: first differential inverter unit with current limitation; 18: second differential inverter unit with current limitation; 19: third differential inverter unit with current limitation; 20: fourth PMOS transistor; 21: fifth PMOS transistor; 22: fourth NMOS transistor; 23: fifth NMOS transistor; 24: sixth NMOS transistor; 25: seventh NMOS transistor; 26: divider (DIV); 27: phase frequency detector (PFD); 28: charge pump (CP); 29: low-pass filters (LPF); 30: control current generation circuit; 31: voltage-controlled oscillator (VCO); 32: third resistor; 33: capacitor. DETAILED DESCRIPTION

[0018] In order to enable a more detailed understanding of the features and technical content of the disclosed embodiments, the implementation of the disclosed embodiments is described in detail below with reference to the accompanying drawings, which are used only for reference and illustration, and do not limit the disclosed embodiments. In the following technical description, for the convenience of explanation, through multiple details, a full understanding of the disclosed embodiments is provided. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be simplified to illustrate.

[0019] The terms "first", "second", and the like in the specification and claims of the disclosed embodiments and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the disclosed embodiments described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0020] In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "back" and the like indicate the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the embodiments of the present disclosure and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation. In addition, in addition to indicating the orientation or positional relationship, the above-mentioned part of the terms can also be used to represent other meanings, for example, the term "upper" can also be used to represent a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0021] In addition, the terms "set", "connected", "fixed" should be broadly understood. For example, "connected" can be fixedly connected, detachably connected, or integrally configured; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0022] Unless otherwise specified, the term "a plurality of" means two or more.

[0023] In the embodiments of the present disclosure, the character " / " represents an "or" relationship between the objects before and after it. For example, A / B represents: A or B.

[0024] The term "and / or" is a description of the association between objects, which means that there can be three relationships. For example, A and / or B means: A or B, or, A and B, the three relationships.

[0025] It should be noted that the embodiments in the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0026] In combination Figure 1 As shown, the embodiments of the present disclosure provide an oscillator circuit, which includes a voltage reference circuit 1, a temperature compensation current source circuit 2 and a ring oscillator 3. The voltage reference circuit 1 is used to provide a power supply voltage; the input end of the temperature compensation current source circuit 2 is connected to the output end of the voltage reference circuit 1, and the temperature compensation current source circuit 2 is used to generate a temperature compensation current according to the power supply voltage; the ring oscillator 3 is connected to the output end of the voltage reference circuit 1, and the ring oscillator 3 is also connected to the output end of the temperature compensation current source circuit 2. The ring oscillator 3 is used to limit the constant current provided by the power supply voltage according to the temperature compensation current, and generate a clock signal according to the power supply voltage and the constant current provided by the power supply voltage.

[0027] The oscillator circuit provided by the embodiment of the present disclosure has the advantages that the voltage reference circuit provides a power supply voltage, the temperature compensation current source circuit generates a temperature compensation current according to the power supply voltage, and the ring oscillator limits the constant current provided by the power supply voltage according to the temperature compensation current, thereby improving the power supply rejection ratio of the ring oscillator, reducing the phase noise of the clock signal generated by the ring oscillator, and achieving a high-precision oscillator circuit.

[0028] In combination Figure 2 As shown in the figure, the voltage reference circuit comprises a first NMOS tube 4, a first PMOS tube 5, a second PMOS tube 6, a first adjustable resistor 7, a second adjustable resistor 8, an amplifier 9, and a first current source 10. The source of the first NMOS tube 4 is grounded, the gate of the first NMOS tube 4 is connected to the output of the amplifier 9, the drain of the first NMOS tube 4 is connected to the first input of the amplifier 9, the drain of the first PMOS tube 5, the temperature compensation current source circuit, and the ring oscillator, respectively; the gate of the first PMOS tube 5 is connected to the gate of the second PMOS tube 6, and the source of the first PMOS tube 5 is connected to a reference power supply; the source of the second PMOS tube 6 is connected to the reference power supply, and the gate of the second PMOS tube 6 is connected to the drain of the second PMOS tube 6 and one end of the first current source 10, respectively; one end of the first adjustable resistor 7 is grounded, and the other end of the first adjustable resistor 7 is connected to one end of the second adjustable resistor 8; the other end of the second adjustable resistor 8 is connected to the reference power supply; the second input of the amplifier 9 is connected to the other end of the first adjustable resistor 7; and the other end of the first current source 10 is grounded.

[0029] The reference power supply is divided by the first adjustable resistor and the second adjustable resistor, a reference voltage Vref is generated at the connection node of the first adjustable resistor and the second adjustable resistor, the reference voltage is taken as the negative input signal of the amplifier OP, the output of the amplifier stably outputs a constant voltage Vout, i.e., the power supply voltage, and then the power supply voltage is output to the ring oscillator. Since the power supply voltage generated by the amplifier is not affected by the fluctuation of the reference power supply, the influence of the power supply fluctuation on the oscillation frequency of the clock signal is reduced, and the precision of the oscillator circuit is further improved. Meanwhile, the first PMOS tube and the second PMOS tube form a current mirror, and the output current of the first current source is imaged to the drain of the first PMOS tube and the drain of the first NMOS tube. Since the drain current Id1 of the first NMOS tube is large, the driving capability of the subsequent circuit is enhanced, i.e., the driving capability of the temperature compensation current source circuit and the ring oscillator connected to the drain of the first NMOS tube is enhanced.

[0030] In combination Figure 3As shown, the temperature compensation current source circuit comprises a second NMOS transistor 11, a third NMOS transistor 12, a third PMOS transistor 13, a first resistor 14, a second resistor 15 and a second current source 16. The drain of the second NMOS transistor 11 is grounded, the gate of the second NMOS transistor 11 is connected to the gate of the third NMOS transistor 12, and the source of the second NMOS transistor 11 is connected to one end of the first resistor 14 and the gate of the third PMOS transistor 13, respectively; the drain of the third NMOS transistor 12 is grounded, the gate of the third NMOS transistor 12 is connected to the source of the third NMOS transistor 12 and one end of the second current source 16, respectively; the drain of the third PMOS transistor 13 is connected to the ring oscillator, and the source of the third PMOS transistor 13 is connected to one end of the second resistor 15; the other end of the first resistor 14 is connected to the voltage reference circuit; the other end of the second resistor 15 is connected to the voltage reference circuit; and the other end of the second current source 16 is connected to the voltage reference circuit.

[0031] The second NMOS transistor and the third NMOS transistor form a current mirror structure, the output current Iin of the second current source is mirrored to the gate of the third PMOS transistor, and then a temperature compensation current is generated according to the first resistor and the second resistor, so as to temperature compensate the ring oscillator, reduce the influence of temperature on the clock signal, and improve the stability of the clock signal.

[0032] Optionally, the temperature compensation current Iout is obtained by calculating wherein Iout is the temperature compensation current, V2 is the voltage at the connection node between the second resistor and the source of the third PMOS transistor, V1 is the voltage at the connection node between the first resistor and the source of the second NMOS transistor, W is the width of the third PMOS transistor, L is the length of the third PMOS transistor, Vtph is the threshold voltage of the third PMOS transistor, β is a process constant, VDD is a reference power supply, and R2 is the resistance of the second resistor.

[0033] Optionally, the process constant β is obtained by calculating β = μ n Cox, wherein β is the process constant, Cox is the gate oxide capacitance per unit area, μ n is the carrier mobility.

[0034] Optionally, the voltage V1 at the connection node between the first resistor and the source of the second NMOS transistor is obtained by calculating V1 = VDD - Iin * R1; wherein V1 is the voltage at the connection node between the first resistor and the source of the second NMOS transistor, Iin is the output current of the second current source, and R1 is the resistance of the first resistor.

[0035] Optionally, the first resistor and the second resistor have different temperature coefficients. In this way, the frequency variation of the clock signal caused by temperature variation is compensated by adjusting the temperature coefficients of the first resistor and the second resistor, so as to improve the stability of the clock signal output by the ring oscillator.

[0036] Optionally, the ring oscillator comprises N current limited differential inverter units. The N current limited differential inverter units are respectively connected to the voltage reference circuit and the temperature compensation current source circuit, and each of the N current limited differential inverter units is connected in a ring, N≥3, and N is an odd number. In this way, the constant current provided by the power supply voltage in the ring oscillator is limited by the temperature compensation current, the power supply rejection ratio of the ring oscillator is improved, the influence of power supply fluctuation on the frequency of the output clock signal of the ring oscillator is reduced, and the phase noise of the clock signal is reduced, so as to provide a high-precision oscillator circuit.

[0037] In combination with Figure 4 As shown in FIG. 1, in some embodiments, the ring oscillator comprises three current limited differential inverter units, i.e., a current limited first differential inverter unit 17, a current limited second differential inverter unit 18, and a current limited third differential inverter unit 19. The first input end of the current limited first differential inverter unit 17 is connected to the voltage reference circuit, the second input end of the current limited first differential inverter unit 17 is connected to the temperature compensation current source circuit, the non-inverting output end of the current limited first differential inverter unit 17 is connected to the inverting input end of the current limited second differential inverter unit 18, and the inverting output end of the current limited first differential inverter unit 17 is connected to the non-inverting input end of the current limited second differential inverter unit 18; the first input end of the current limited second differential inverter unit 18 is connected to the voltage reference circuit, the second input end of the current limited second differential inverter unit 18 is connected to the temperature compensation current source circuit, the non-inverting output end of the current limited second differential inverter unit 18 is connected to the inverting input end of the current limited third differential inverter unit 19, and the inverting output end of the current limited second differential inverter unit 18 is connected to the non-inverting input end of the current limited third differential inverter unit 19; the first input end of the current limited third differential inverter unit 19 is connected to the voltage reference circuit, the second input end of the current limited third differential inverter unit 19 is connected to the temperature compensation current source circuit, the non-inverting output end of the current limited third differential inverter unit 19 is connected to the inverting input end of the current limited first differential inverter unit 17, and the inverting output end of the current limited third differential inverter unit 19 is connected to the non-inverting input end of the current limited first differential inverter unit 17. In this way, the three current limited differential inverter units are connected in a ring to form a ring oscillator, which occupies a small area and has high integration and a large frequency adjustment range.

[0038] In combination with Figure 5As shown, the current-limited differential inverter unit comprises a fourth PMOS transistor 20, a fifth PMOS transistor 21, a fourth NMOS transistor 22, a fifth NMOS transistor 23, a sixth NMOS transistor 24, and a seventh NMOS transistor 25. The source of the fourth PMOS transistor 20 is connected to a voltage reference circuit, the gate of the fourth PMOS transistor 20 is connected to the gate of the fourth NMOS transistor 22, the drain of the fourth PMOS transistor 20 is connected to the drain of the fourth NMOS transistor 22, the source of the fifth PMOS transistor 21 is connected to the voltage reference circuit, the gate of the fifth PMOS transistor 21 is connected to the gate of the fifth NMOS transistor 23, the drain of the fifth PMOS transistor 21 is connected to the drain of the fifth NMOS transistor 23, the source of the fourth NMOS transistor 22 is connected to the drain of the sixth NMOS transistor 24, the source of the fifth NMOS transistor 23 is connected to the drain of the sixth NMOS transistor 24, the gate of the sixth NMOS transistor 24 is connected to the gate of the seventh NMOS transistor 25, the source of the sixth NMOS transistor 24 is connected to ground, and the gate of the seventh NMOS transistor 25 is connected to the drain of the seventh NMOS transistor 25 and a temperature compensation current source circuit, respectively, and the source of the seventh NMOS transistor 25 is connected to ground.

[0039] Optionally, the connection node IN+ between the gate of the fourth PMOS transistor 20 and the gate of the fourth NMOS transistor 22 is a non-inverting input terminal of the current-limited differential inverter unit; the connection node VO- between the drain of the fourth PMOS transistor 20 and the drain of the fourth NMOS transistor 22 is an inverting output terminal of the current-limited differential inverter unit; the connection node IN- between the gate of the fifth PMOS transistor 21 and the gate of the fifth NMOS transistor 23 is an inverting input terminal of the current-limited differential inverter unit; the connection node VO+ between the drain of the fifth PMOS transistor 21 and the drain of the fifth NMOS transistor 23 is a non-inverting output terminal of the current-limited differential inverter unit; the connection node between the source of the fourth PMOS transistor 20 and the source of the fifth PMOS transistor 21 is a first input terminal of the current-limited differential inverter unit, and the first input terminal of the current-limited differential inverter unit receives a constant voltage Vout; and the drain of the seventh NMOS transistor 25 is a second input terminal of the current-limited differential inverter unit, and the second input terminal of the current-limited differential inverter unit receives a temperature compensation current Iout.

[0040] The current-limited differential inverter unit receives a power voltage provided by a voltage reference circuit, and forms a current provided by the power voltage at a connection node between the source of the fourth NMOS transistor and the source of the fifth NMOS transistor. The sixth NMOS transistor and the seventh NMOS transistor form a current mirror structure, and mirror a temperature compensation current to the drain of the sixth NMOS transistor, so that the current at the connection node between the source of the fourth NMOS transistor and the source of the fifth NMOS transistor is limited to the temperature compensation current, so that the charge and discharge time of the current-limited differential inverter unit is fixed, and the power supply rejection ratio of the current-limited differential inverter unit is improved, and the phase noise of the clock signal is reduced. In the prior art, the connection node of the fourth NMOS transistor and the fifth NMOS transistor is grounded, and the current of the connection branch of the fourth NMOS transistor and the fifth NMOS transistor provided by the embodiment of the present disclosure is limited to the temperature compensation current, so that the current of each branch in the ring oscillator is reduced, and the power consumption of the ring oscillator is reduced.

[0041] Optionally, the phase difference of the clock signal is equal to π / N.

[0042] Firstly, the current provided by the power voltage in the ring oscillator is limited by the temperature compensation current, so that the power supply rejection ratio of the ring oscillator is improved, the phase noise of the clock signal is reduced, and the precision of the oscillator circuit is improved. Secondly, the voltage reference module provides a constant voltage for the ring oscillator which is not affected by the power supply, so that the influence of the power supply noise on the frequency of the output clock signal of the ring oscillator is reduced, and the precision of the oscillator circuit is further improved. Finally, the temperature compensation current source circuit adjusts the first resistor and the second resistor to compensate the temperature of the ring oscillator, reduces the influence of the temperature on the output clock signal of the ring oscillator, and improves the precision of the oscillator circuit again, so that a high-precision low-temperature-drift oscillator circuit is provided.

[0043] Optionally, the output end of the ring oscillator is any output end of each current-limited differential inverter unit.

[0044] The embodiment of the present disclosure provides a phase-locked loop circuit, which comprises the oscillator circuit as described above. The ring oscillator limits the constant current provided by the power voltage according to the temperature compensation current, and generates a clock signal according to the power voltage and the constant current. Since the ring oscillator limits the constant current provided by the power voltage according to the temperature compensation current, the power supply rejection ratio of the ring oscillator is improved, and the phase noise of the clock signal is reduced, so that a high-precision oscillator circuit is provided, and a high-precision phase-locked loop circuit is provided.

[0045] In combination Figure 6As shown, the phase-locked loop circuit further comprises a frequency divider (DIV) 26, a phase frequency detector (PFD) 27, a charge pump (CP) 28, a filter (LPF) 29 and a control current generating circuit 30. An input terminal of the frequency divider 26 is connected to an output terminal of the oscillator circuit 30, the frequency divider 26 is used to divide the clock signal to generate an output signal; an input terminal of the phase frequency detector 27 is connected to an output terminal of the frequency divider 26, an output terminal of the phase frequency detector 27 is connected to an input terminal of the charge pump 28, the phase frequency detector 27 is used to generate a phase difference signal according to the reference signal and the output signal; an output terminal of the charge pump 28 is connected to an input terminal of the filter 29, the charge pump 28 is used to receive the phase difference signal and generate an output current adjusting the phase to align according to the phase difference signal; an output terminal of the filter 29 is connected to an input terminal of the control current generating circuit 30, the filter 29 is used to receive the output current and convert the output current into a voltage control signal; an output terminal of the control current generating circuit 30 is connected to an input terminal of the oscillator circuit (VCO) 31, the control current generating circuit is used to generate a control current according to the voltage control signal.

[0046] The clock signal is generated by the oscillator circuit, the clock signal is divided by the frequency divider to generate an output signal, the phase frequency detector generates a phase difference signal according to the output signal and the reference signal, the charge pump generates an output current adjusting the phase to align according to the phase difference signal, the filter converts the output current into a voltage control signal, and the control current generating circuit generates a control current according to the voltage control signal. In this way, the high-precision oscillator circuit generates the clock signal Fout, and the output signal generated after the clock signal is divided infinitely approaches the reference signal Fref. When the loop is locked, the phase-locked loop circuit outputs a signal with fixed frequency and phase, thereby improving the precision of the output signal of the entire phase-locked loop circuit.

[0047] In combination Figure 6 As shown, optionally, the filter 29 comprises a third resistor 32 and a capacitor 33. One end of the third resistor 32 is grounded, the other end of the third resistor 32 is connected to one end of the capacitor 33, the output terminal of the charge pump 28 and the input terminal of the control current generating circuit 30 respectively, and the other end of the capacitor 33 is grounded.

[0048] Optionally, the output terminal of the control current generating circuit is connected to a ring oscillator in the oscillator circuit. In this way, the control current generating circuit generates a control current according to the voltage control signal, the high-precision oscillator circuit generates a clock signal according to the control current, and the output signal generated after the clock signal is divided infinitely approaches the reference signal Fref. When the loop is locked, the phase-locked loop circuit outputs a signal with fixed frequency and phase, thereby improving the precision of the output signal of the entire phase-locked loop circuit.

[0049] The above description and drawings suffice to fully enable one skilled in the art to practice the embodiments of the present disclosure. Other embodiments can include structural and other changes. The embodiments are merely representative of possible variations. Individual components and functions are optional unless explicitly required, and the order of operations can be varied. Portions and features of some embodiments can be included in, or substituted for, portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the drawings, and can be varied in a variety of ways. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. An oscillator circuit, characterized in that, include: A voltage reference circuit is used to provide the power supply voltage; A temperature-compensated current source circuit, with its input terminal connected to the output terminal of the voltage reference circuit, is used to generate a temperature-compensated current based on the power supply voltage. A ring oscillator is connected to the output of the voltage reference circuit and also to the output of the temperature-compensated current source circuit. The ring oscillator is used to limit the constant current provided by the power supply voltage according to the temperature-compensated current and generate a clock signal according to the power supply voltage and the constant current. The voltage reference circuit includes: a first NMOS transistor with its source grounded, its gate connected to the output of an amplifier, and its drain connected to the first input of the amplifier, the drain of a first PMOS transistor, the temperature-compensated current source circuit, and the ring oscillator; a first PMOS transistor with its gate connected to the gate of a second PMOS transistor, and its source connected to a reference power supply; a second PMOS transistor with its source connected to the reference power supply, and its gate connected to its drain and one end of a first current source; a first adjustable resistor with one end grounded, and its other end connected to one end of a second adjustable resistor; the other end of the second adjustable resistor connected to the reference power supply; the amplifier with its second input connected to the other end of the first adjustable resistor; and the first current source with its other end grounded.

2. The oscillator circuit according to claim 1, characterized in that, The temperature-compensated current source circuit includes: a second NMOS transistor with its drain grounded, the gate of the second NMOS transistor connected to the gate of a third NMOS transistor, and the source of the second NMOS transistor connected to one end of a first resistor and the gate of a third PMOS transistor; the third NMOS transistor with its drain grounded, and its gate connected to the source of the third NMOS transistor and one end of a second current source; the third PMOS transistor with its drain connected to the ring oscillator and its source connected to one end of the second resistor; the first resistor with its other end connected to the voltage reference circuit; the second resistor with its other end connected to the voltage reference circuit; and the second current source with its other end connected to the voltage reference circuit.

3. The oscillator circuit according to claim 2, characterized in that, The first resistor and the second resistor have different temperature coefficients.

4. The oscillator circuit according to claim 1, characterized in that, The ring oscillator includes: N current-limited differential inverter units are connected to the voltage reference circuit and the temperature-compensated current source circuit, respectively. The current-limited differential inverter units are connected in a ring, N≥3, and N is an odd number.

5. The oscillator circuit according to claim 4, characterized in that, The current-limited differential inverter unit includes: The fourth PMOS transistor has its source connected to the voltage reference circuit, its gate connected to the gate of the fourth NMOS transistor, and its drain connected to the drain of the fourth NMOS transistor. The source of the fifth PMOS transistor is connected to the voltage reference circuit, the gate of the fifth PMOS transistor is connected to the gate of the fifth NMOS transistor, and the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor. The source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor; The source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor; The gate of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor, and the source of the sixth NMOS transistor is grounded. The gate of the seventh NMOS transistor is connected to the drain of the seventh NMOS transistor and the temperature compensation current source circuit, and the source of the seventh NMOS transistor is grounded.

6. The oscillator circuit according to claim 4, characterized in that, The output terminal of the ring oscillator is any one of the output terminals of each of the current-limited differential inverter units.

7. A phase-locked loop circuit, characterized in that, Includes the oscillator circuit as described in any one of claims 1 to 6.

8. The phase-locked loop circuit according to claim 7, characterized in that, The phase-locked loop circuit also includes: The frequency divider has its input terminal connected to the output terminal of the oscillator circuit. The frequency divider is used to divide the clock signal to generate an output signal. A frequency and phase detector, with its input connected to the frequency divider and its output connected to the input of a charge pump, is used to generate a phase difference signal based on a reference signal and the output signal. The charge pump has its output terminal connected to the input terminal of the filter. The charge pump is used to receive the phase difference signal and generate an output current that adjusts the phase to align the phases based on the phase difference signal. The filter has its output terminal connected to the input terminal of the control current generation circuit. The filter is used to receive the output current and convert the output current into a voltage control signal. The output terminal of the control current generating circuit is connected to the input terminal of the oscillator circuit, and the control current generating circuit is used to generate a control current according to the voltage control signal.

9. The phase-locked loop circuit according to claim 8, characterized in that, The output of the control current generation circuit is connected to the ring oscillator in the oscillator circuit.

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