Biased gate contact

Abstract

Shifting or modulating the gate position between the two transistors can achieve lower power circuits and higher speed circuits, depending on the new position of the gate. In one example, the gate between the PFET transistor and the NFET transistor can be shifted toward the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located an equal distance between the transistors. In another example, the gate between the PFET transistor and the NFET transistor can be shifted toward the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located an equal distance between the transistors.

Description

[0001] Priority claim

[0002] This disclosure claims priority to application Ser. No. 16 / 578,101, filed on Sep. 20, 2019, entitled “OFFSET GATE CONTACT,” which is assigned to the assignee of the present application and is expressly incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to transistors, and more particularly, but not exclusively, to the location of a gate contact between at least two transistors. Background Art

[0004] As the capabilities of and reliance on mobile devices increase, the amount of time used (battery power versus power consumption rate) becomes a critical factor. For example, in low power applications, the goal is to reduce power consumption by using low leakage transistors in the circuit. For example, in high speed applications, the goal is to increase circuit speed (less time per operation) at the tradeoff of power consumption by using larger transistors. In a circuit with transistors, various metals and other layers define the Vth (threshold voltage) of different transistors. For example, high Vth (HVT), standard or conventional Vth (RVT), low Vth (LVT), and very low or ultra low Vth (SLVT) name the Vth type from high to low. Therefore, the manufacturing process will be different based on the Vth type. Generally, several methods can be used to separate Vth through (1) channel implantation of the metal gate (2) gate oxide thickness (3) gate length modulation (4) eWF, etc. Thus, the front end of line (FEOL) process will be different depending on the definition of Vth. However, conventional low power applications that rely on scaling and gate length shrinkage encounter speed and performance issues, while conventional high speed applications encounter power and performance issues.

[0005] Therefore, there is a need for systems, apparatuses, and methods that overcome the deficiencies of conventional approaches, including the methods, systems, and apparatus provided herein. Summary of the invention

[0006] A simplified overview of one or more aspects and / or examples associated with the apparatus and methods disclosed herein is presented below. Therefore, the following overview should not be considered as a broad overview involving all expected aspects and / or examples, nor should the following overview be considered as identifying key or important elements involving all expected aspects and / or examples or delineating the scope associated with any particular aspect and / or example. Therefore, the sole purpose of the following overview is to present certain concepts related to one or more aspects and / or examples related to the apparatus and methods disclosed herein in a simplified form, to precede the detailed description presented below.

[0007] In one aspect, a circuit includes: a first transistor coupled to a power supply voltage, the first transistor including a gate region, a source contact, and a drain contact; a second transistor coupled to ground, the second transistor including a gate region, a source contact, and a drain contact; and a first gate coupled to the first transistor and the second transistor at a first position, wherein the first position is offset from a center point between the first transistor and the second transistor.

[0008] In another aspect, a circuit includes: a first amplifying device coupled to a supply voltage, the first amplifying device including a gate region, a source contact, and a drain contact; a second amplifying device coupled to ground, the second amplifying device including a gate region, a source contact, and a drain contact; and a first gate coupled to the first amplifying device and the second amplifying device at a first position, wherein the first position is offset from a center point between the first amplifying device and the second amplifying device.

[0009] On the other hand, a method for forming a circuit includes: forming a gate region, a source contact, and a drain contact of a first transistor; forming a gate region, a source contact, and a drain contact of a second transistor; and forming a first gate coupled to the first transistor and the second transistor at a first position, wherein the first position is offset from a center point between the first transistor and the second transistor.

[0010] Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the various aspects of the present invention and many of its attendant advantages will be readily obtained by reference to the following detailed description when considered in conjunction with the accompanying drawings, which are intended to illustrate and not to limit the present invention, wherein:

[0012] Figure 1A and 1B shows an exemplary single-gate circuit according to some examples of the present disclosure;

[0013] Figure 2A and 2B An exemplary dual-gate circuit according to some examples of the present disclosure is shown;

[0014] Figure 3A - 3C shows performance characteristics of exemplary circuits according to some examples of the present disclosure;

[0015] Figure 4A and 4B shows exemplary circuits according to some examples of the present disclosure;

[0016] Figure 5An exemplary partial method according to some examples of the present disclosure is shown;

[0017] Figure 6 An exemplary mobile device according to some examples of the present disclosure is shown; and

[0018] Figure 7 Various electronic devices that may be integrated with any of the aforementioned integrated devices, semiconductor devices, integrated circuits, dies, interposers, packages, or package-on-package (Po) according to some examples of the present disclosure are shown.

[0019] As a matter of convention, features depicted by the drawings may not be drawn to scale. Therefore, the dimensions of the features shown may be arbitrarily expanded or reduced for clarity. As a matter of convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. In addition, throughout the specification and drawings, the same reference numerals represent the same features. DETAILED DESCRIPTION

[0020] The exemplary methods, devices and systems disclosed herein alleviate the shortcomings of conventional methods, devices and systems and other previously unidentified needs. For example, with complementary metal oxide semiconductor (CMOS) technology scaling and gate length shrinkage, the gate contact position will also affect the threshold voltage (Vth) of the transistor. For example, in an inverter RO circuit, when the gate contact is offset from a position closer to the center of the N-type field effect transistor (NFET), the Vth of both the NFET and the P-type field effect transistor (PFET) will increase without a decrease in mobility. Therefore, both the on-current (Ion) and the off-current (Ioff) will decrease relative to the increase in Vth. This feature can be used to reduce leakage current in circuits for low-power applications. On the other hand, when the gate contact is offset from a position close to the center of the PFET, the Vth of both the NFET and the PFET will decrease and cause an increase in Ion and Ioff. Therefore, high-speed or low-power circuits can be realized without changing any front-end process (FEOL) process. In summary, high-speed and low-power circuits can be realized by offsetting or modulating the gate contact position without any FEOL process changes.

[0021] FEOL is the first part of integrated circuit (IC) fabrication where individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor. FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. For CMOS processes, FEOL encompasses all the manufacturing steps required to form fully isolated CMOS components: selection of the type of wafer to be used; chemical mechanical planarization and cleaning of the wafer; shallow trench isolation (STI) (or LOCOS in early processes, with feature sizes > 0.25 μm); well formation; gate module formation; and source and drain module formation.

[0022] Back-end of line (BEOL) is the second part of IC manufacturing where the individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring and metallization layers on the wafer. Common metals are copper and aluminum. BEOL usually starts when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding locations for chip-to-package connections. After the last FEOL steps, there is a wafer with isolated transistors (without any wires). In the BEOL part of the manufacturing stage, contacts (pads), interconnect lines, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in BEOL. The steps of BEOL may include: silicidation of source and drain regions and polysilicon regions; adding dielectric (the first, lower layer is a pre-metal dielectric (PMD) - to isolate the metal from the silicon and polysilicon), which is CMP-processed; making holes in the PMD (making contacts in them); adding a metallization layer 1; adding a second dielectric, called an inter-metal dielectric (IMD); making vias through the dielectric to connect the lower metal to the higher metal (vias filled by a metal CVD process); repeating the above steps to get all the metal layers; and adding a final passivation layer to protect the microchip. After BEOL, there is the "back-end process" (also called post-manufacturing), which includes wafer testing, wafer back grinding, die separation, die testing, IC packaging, and final testing.

[0023] Figure 1A and 1B 2 shows an exemplary single gate circuit according to some examples of the present disclosure. Figure 1A As shown, the circuit 100 may include a first transistor 110 coupled to a power supply voltage (not shown) and including a gate region 120, a source contact 130, and a drain contact 140 (it should be understood that the source and drain contacts may be interchanged depending on the desired transistor type). The circuit 100 may also include a second transistor 150 coupled to ground (not shown) and including a gate region 160, a source contact 170, and a drain contact 180. In addition, the circuit 100 may include a first gate 190 coupled to the first transistor 110 and the second transistor 150 at a first position 192, wherein the first position 192 is offset from a center point 194 between the first transistor 110 and the second transistor 150.

[0024] like Figure 1AAs shown, the first position 192 is closer to the second transistor 150 than to the first transistor 110. The first position 192 can be offset from the center point 194 by a distance 196, and the distance 196 ranges from about 10nm to about 100nm. As shown, the first transistor 110 is a PFET and the second transistor 150 is an NFET. It should be understood that these positions can be switched, or the circuit can contain all PFETs or all NFETs or a combination of multiple PFETs and / or NFETs. It should also be understood that the first transistor 110 and the second transistor 150 can be used in many different types of circuits, including but not limited to inverter circuits or NOR circuits, wherein the first transistor 110 can be a pair of PFETs and the second transistor 150 can be a pair of NFETs.

[0025] like Figure 1B As shown, the circuit 100 may include a first transistor 110 coupled to a power supply voltage (not shown) and including a gate region 120, a source contact 130, and a drain contact 140 (it should be understood that the source and drain contacts may be interchanged depending on the desired transistor type). The circuit 100 may also include a second transistor 150 coupled to ground (not shown) and including a gate region 160, a source contact 170, and a drain contact 180. In addition, the circuit 100 may include a first gate 190 coupled to the first transistor 110 and the second transistor 150 at a first position 192, wherein the first position 192 is offset from a center point 194 between the first transistor 110 and the second transistor 150.

[0026] like Figure 1B As shown, the first position 192 is closer to the first transistor 110 than to the second transistor 150. The first position 192 can be offset from the center point 194 by a distance 196, and the distance 196 ranges from about 10nm to about 100nm. As shown, the first transistor 110 is a PFET and the second transistor 150 is an NFET. It should be understood that these positions can be switched, or the circuit can contain all PFETs or all NFETs or a combination of multiple PFETs and / or NFETs. It should also be understood that the first transistor 110 and the second transistor 150 can be used in many different types of circuits, including but not limited to inverter circuits or NOR circuits, wherein the first transistor 110 can be a pair of PFETs and the second transistor 150 can be a pair of NFETs.

[0027] Moving the first gate 190 closer to the NFET may result in reduced leakage current in the transistor (ie, Ioff), which will reduce power consumption of the circuit 100. Moving the first gate 190 closer to the PFET may result in increased on-current (ie, Ion) and increased speed.

[0028] Figure 2A and 2B An exemplary dual-gate circuit according to some examples of the present invention is shown. Figure 2A As shown, the circuit 200 may include a first transistor 210 coupled to a power supply voltage (not shown) and including a gate region 220, a source contact 230, and a drain contact 240 (it should be understood that the source and drain contacts may be interchanged depending on the desired transistor type). The circuit 200 may also include a second transistor 250 coupled to a ground (not shown) and including a gate region 260, a source contact 270, and a drain contact 280. Additionally, the circuit 200 may include a first gate 290 coupled to the first transistor 210 and the second transistor 250 at a first position 292, wherein the first position 292 is offset from a center point 294 between the first transistor 210 and the second transistor 250. Moreover, the circuit 200 may include a second gate 298 coupled to the first transistor 210 and the second transistor 250 at a second position 299, wherein the second position 299 is offset from the center point 294 relative to the first position 292.

[0029] like Figure 2A As shown, the first position 292 is closer to the second transistor 250 than to the first transistor 210. The first position 292 can be offset from the center point 294 by a distance 296, and the range of the distance 296 is from about 10nm to about 100nm. The second position 299 can be offset by a distance 296 substantially the same as the first position 292 or a different distance. As shown, the first transistor 210 is a PFET and the second transistor 250 is an NFET. It should be understood that these positions can be switched, or the circuit can contain all PFETs or all NFETs or a combination of multiple PFETs and / or NFETs. It should also be understood that the first transistor 210 and the second transistor 250 can be used in many different types of circuits, including but not limited to inverter circuits or NOR circuits, wherein the first transistor 210 can be a pair of PFETs and the second transistor 250 can be a pair of NFETs.

[0030] like Figure 2BAs shown, the circuit 200 may include a first transistor 210 coupled to a power supply voltage (not shown) and including a gate region 220, a source contact 230, and a drain contact 240 (it should be understood that the source and drain contacts may be interchanged depending on the desired transistor type). The circuit 200 may also include a second transistor 250 coupled to a ground (not shown) and including a gate region 260, a source contact 270, and a drain contact 280. Additionally, the circuit 200 may include a first gate 290 coupled to the first transistor 210 and the second transistor 250 at a first position 292, wherein the first position 292 is offset from a center point 294 between the first transistor 210 and the second transistor 250. Moreover, the circuit 200 may include a second gate 298 coupled to the first transistor 210 and the second transistor 250 at a second position 299, wherein the second position 299 is offset from the center point 294 relative to the first position 292.

[0031] like Figure 2B As shown, the first position 292 is closer to the first transistor than to the second transistor 250. The first position 292 can be offset from the center point 294 by a distance 296, and the distance 296 ranges from about 10nm to about 100nm. The second position 299 can be offset by a distance 296 substantially the same as the first position 292 or a different distance. As shown, the first transistor 210 is a PFET and the second transistor 250 is an NFET. It should be understood that these positions can be switched, or the circuit can contain all PFETs or all NFETs or a combination of multiple PFETs and / or NFETs. It should also be understood that the first transistor 210 and the second transistor 250 can be used in many different types of circuits, including but not limited to inverter circuits or NOR circuits, wherein the first transistor 210 can be a pair of PFETs and the second transistor 250 can be a pair of NFETs.

[0032] Moving the first gate 290 closer to the NFET can result in reduced leakage current (i.e., Ioff) in the transistor, which will reduce power consumption of the circuit 200. Moving the first gate 290 closer to the PFET can result in an increase in on-current (i.e., Ion) and an increase in speed. The second gate 298 can be a dummy gate that is not connected to any metal layer above the second gate 298 layer.

[0033] Figure 3A 3C shows the performance characteristics of an exemplary circuit according to some examples of the present disclosure. Figure 3AAs shown, when the gate contact (e.g., first gate 190 and first gate 290) moves closer to the edge of the PFET transistor (closer to the edge or boundary of the active gate region) (e.g., first transistor 110 and first transistor 210), the on-current (Ion) 310 of the PFET increases, resulting in a higher speed circuit than a circuit with a lower Ion. In addition, the Ion 310 of the PFET is higher than the increased value of the Ion 320 of the NFET (e.g., second transistor 150 and second transistor 250). Figure 3B The results of the relative positioning of the gate contacts are shown in Figure 3B As shown, the gate contacts (e.g., first gate 190 and first gate 290) are moved closer to the edge of the NFET transistor, and the off current (Ioff) 330 of the PFET is reduced, resulting in lower leakage current and lower power consumption. In addition, the Ioff 340 of the NFET is also reduced. Figure 3C , the response of current Iddq (in nA) 350 to frequency (in GHz) 360 is shown for various configurations. In the ultra-low Vth configuration (SLVT) 370, response 372 shows the result of moving the gate contact closer to the NFET transistor, response 374 shows the result of positioning the gate at the center point, and response 376 shows the result of moving the gate contact closer to the PFET transistor. In the low Vth configuration (LVT) 380, response 382 shows the result of moving the gate contact closer to the NFET transistor, response 384 shows the result of positioning the gate at the center point, and response 386 shows the result of moving the gate contact closer to the PFET transistor. In the conventional or standard Vth configuration (RVT) 390, response 392 shows the result of moving the gate contact closer to the NFET transistor, response 394 shows the result of positioning the gate at the center point, and response 396 shows the result of moving the gate contact closer to the PFET transistor.

[0034] Figure 4A and 4B illustrative circuits according to some examples of the present disclosure are shown. Figure 4AAs shown in FIG. 1 , a NOR circuit 400 (e.g., circuits 100 and 200) may include a first PFET transistor 410 coupled to a power supply voltage 420, a second PFET 430 connected in series with the first PFET 410 and coupled to an output node 440 of the NOR circuit 400, a first NFET transistor 450 connected in parallel with a second NFET 460, and both the second NFET 460 and the first NFET 450 are coupled between the output node 440 and a ground 470. In the NOR circuit 400, the resistance of the PFETs 410 and 430 is greater than the resistance of the NFETs 450 and 460. Therefore, the two PFETs 410 and 430 act as pull-up transistors for the output node 440, and the two NFETs 450 and 460 act as pull-down transistors for the output node 440. In this configuration, the speed of the NOR circuit 400 is dominated by the resistance of the PFETs 410 and 430. By positioning the gate contacts closer to PFETs 410 and 430, the PMOS current will increase, resulting in lower PFET resistance and faster speed (e.g., 7% speed increase) than conventional configurations. Figure 4B As shown in , inverter RO circuit 405 can achieve approximately a 3% speed increase over inverter RO circuit 415 when gate contact 425 of circuit 405 is moved closer to PFET 435 than positioning gate contact 425 of circuit 415 at a center point.

[0035] Figure 5 An exemplary partial method that can be used in accordance with any of the example circuits herein is shown. Figure 5 As shown, a portion of the method 500 for forming a circuit may begin at block 502, forming a gate region, a source contact, and a drain contact of a first transistor. The portion of the method 500 may continue at block 504, forming a gate region, a source contact, and a drain contact of a second transistor. The portion of the method 500 may end at block 506, wherein a first gate coupled to the first transistor and the second transistor is formed at a first position, wherein the first position is offset from a center point between the first transistor and the second transistor. Alternatively, the portion of the method 500 may end at block 508, wherein a second gate coupled to the first transistor and the second transistor is formed at a second position, wherein the second position is offset from a center point relative to the first position.

[0036] Figure 6 An exemplary mobile device according to some examples of the present disclosure is shown. Figure 6, depicts a block diagram of a mobile device configured according to exemplary aspects, and generally designated as 600. In some aspects, the mobile device 600 may be configured as a wireless communication device. As shown, the mobile device 600 includes a processor 601, which may be configured to implement the methods described herein in some aspects. The processor 601 is shown to include an instruction pipeline 612, a buffer processing unit (BPU) 608, a branch instruction queue (BIQ) 611, and a throttle 610 as is known in the art. For clarity, other known details of these blocks (e.g., counters, entries, confidence fields, weighted sums, comparators, etc.) are omitted from this view of the processor 601.

[0037] The processor 601 may be communicatively coupled to the memory 632 via a link, which may be a die-to-die or chip-to-chip link. The mobile device 600 also includes a display 628 and a display controller 626 , wherein the display controller 626 is coupled to the processor 601 and the display 628 .

[0038] In some aspects, Figure 6 Can include a coder / decoder (CODEC) 634 (e.g., an audio and / or voice CODEC) coupled to the processor 601; a speaker 636 and a microphone 638 coupled to the CODEC 634; and a wireless controller 640 (which can include a modem) coupled to a wireless antenna 642 and the processor 601.

[0039] In certain aspects, where one or more of the above blocks are present, the processor 601, display controller 626, memory 632, CODEC 634, and wireless controller 640 may be included in a system-in-package or system-on-chip device 622. The input device 630 (e.g., a physical or virtual keyboard), power source 644 (e.g., a battery), display 628, input device 630, speaker 636, microphone 638, wireless antenna 642, and power source 644 may be external to the system-on-chip device 622 and may be coupled to a component of the system-on-chip device 622, such as an interface or controller.

[0040] It should be noted that although Figure 6 A mobile device is depicted, but the processor 601 and memory 632 may also be integrated into a set-top box, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop, tablet computer, communication device, mobile phone, or other similar device.

[0041] Figure 7Various electronic devices that can be integrated with any of the aforementioned integrated devices, semiconductor devices, integrated circuits, dies, interposers, packages, or packages on packages (PoP) according to some examples of the present disclosure are shown. For example, a mobile phone device 702, a laptop device 704, and a fixed location terminal device 706 may include an integrated device 700 as described herein. The integrated device 700 may be, for example, any of the integrated circuits, bare chips, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and package-on-package devices described herein. Figure 7 The devices 702, 704, 706 shown are merely exemplary. Other electronic devices may also feature the integrated device 700, including but not limited to a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading devices, communication devices, smart phones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0042] It should be understood that the various aspects disclosed herein may be described as functional equivalents of structures, materials, and / or devices described and / or recognized by a person skilled in the art. It should also be noted that the methods, systems, and devices disclosed in the specification or claims can be implemented by a device including a device for performing the corresponding actions of the method. For example, in one aspect, a circuit includes: a first amplifying device coupled to a power supply voltage, the first amplifying device including a gate region, a source contact, and a drain contact; a second amplifying device coupled to ground, the second amplifying device including a gate region, a source contact, and a drain contact; and a first gate coupled to the first amplifying device and the second amplifying device at a first position, wherein the first position is offset from a center point between the first amplifying device and the second amplifying device. It should be understood that the foregoing aspects are provided only as examples, and the various aspects claimed are not limited to the specific references and / or descriptions cited as examples.

[0043] One or more of the components, processes, features, and / or functions shown in Figures 1-7 may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figures 1-7 and their corresponding descriptions in the present disclosure are not limited to dies and / or ICs. In some embodiments, Figures 1-7 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce integrated devices. In some implementations, the device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (pop) device, and / or an interposer.

[0044] As used herein, the terms "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal" and variations thereof may interchangeably refer to any suitable mobile or fixed device that can receive wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smart phones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in motor vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with another device that receives wireless communications and / or navigation signals, such as through a short-range wireless, infrared, wired connection or other connection, regardless of whether satellite signal reception, assistance data reception and / or location-related processing occurs at the device or other device. In addition, these terms are intended to include all devices capable of communicating with the core network via a radio access network (RAN), including wireless and wired communication devices, and through the core network, the UE can be connected to external networks such as the Internet and other UEs. Of course, other mechanisms for connecting to the core network and / or the Internet are also possible for the UE, such as through a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE802.11, etc.), etc. The UE can be implemented by any of a variety of types of devices, including but not limited to: a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smart phone, a graphics tablet, a tracking device, an asset tag, etc. The communication link through which the UE can send a signal to the RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). The communication link through which the RAN can send a signal to the UE is called a downlink or forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). The term traffic channel (TCH) used here can refer to an uplink / reverse or downlink / forward traffic channel.

[0045] Wireless communication between electronic devices can be based on different technologies, such as: Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE802.11 (wifi) and IEEE802.15.4 (Zigbee / Thread) or other protocols that can be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group to provide significantly reduced power consumption and cost while maintaining a similar communication range. BLE was merged into the main Bluetooth standard in 2010 with Bluetooth Core Specification Version 4.0 and updated in Bluetooth 5 (both of which are expressly incorporated herein in their entirety).

[0046] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as preferred over other examples. Likewise, the term "example" does not mean that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Furthermore, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0047] The terms used herein are for the purpose of describing specific examples and are not intended to limit the examples of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "include", "comprise", "comprising" and / or "comprising" when used herein specify the presence of stated features, integers, actions, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, actions, operations, elements, components and / or groups thereof.

[0048] It should be noted that the terms “connected”, “coupled” or any variations thereof refer to any direct or indirect connection or coupling between elements, and may encompass the presence of intermediate elements between two elements that are “connected” or “coupled” together via intermediate elements.

[0049] Any reference to an element using names such as "first", "second", etc. herein does not limit the quantity and / or order of these elements. Instead, these designations are used as a convenient method of distinguishing two or more elements and / or element instances. In addition, unless otherwise stated, a group of elements may include one or more elements.

[0050] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0051] Nothing described or illustrated in this application is intended to dedicate any component, act, feature, benefit, advantage, or equivalent to the public regardless of whether the component, act, feature, benefit, advantage, or equivalent is recited in the claims.

[0052] In addition, it will be appreciated by those skilled in the art that the various illustrative logic blocks, modules, circuits, and algorithmic actions described in conjunction with the examples disclosed herein may be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and actions have been described above generally in terms of their functions. Whether such functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0053] The methods, sequences and / or algorithms described in conjunction with the examples disclosed herein may be incorporated directly into hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art (including non-transitory types of memory or storage media). The exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated with the processor.

[0054] Although some aspects have been described in conjunction with devices, it goes without saying that these aspects also constitute a description of the corresponding methods, and therefore the blocks or components of the devices should also be understood as the corresponding method actions or features of the method actions. Similarly, the aspects described in conjunction with method actions or as method actions also constitute a description of the corresponding blocks or details or features of the corresponding devices. Some or all of these method actions can be performed by hardware devices (or using hardware devices), such as microprocessors, programmable computers or electronic circuits. In some examples, some or more of the most important method actions can be performed by such devices.

[0055] As can be seen in the above detailed description, different features are combined together in the examples. This manner of disclosure should not be interpreted as an example that the claimed examples have more features than those explicitly mentioned in the corresponding claims. On the contrary, the present disclosure may include less than all the features of a single disclosed example. Therefore, the following claims should be considered to be incorporated in the specification, with each claim itself being a separate example. Although each claim itself can be a separate example, it should be noted that although a dependent claim can be cited in a claim as a specific combination with one or more claims, other examples may also contain or include a combination of the dependent claim with the subject matter of any other dependent claim or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein unless it is explicitly stated that a specific combination is not intended. In addition, features of a claim may also be included in any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0056] In addition, in some examples, a single action may be subdivided into or include multiple sub-actions. These sub-actions may be included in the disclosure of a single action and be part of the disclosure of a single action.

[0057] Although the foregoing disclosure shows illustrative examples of the present disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or actions of the method claims according to the examples of the present disclosure described herein do not need to be performed in any particular order. In addition, well-known elements will not be described in detail or may be omitted to avoid confusion regarding the relevant details of the aspects and examples disclosed herein. In addition, although elements of the present disclosure may be described or claimed in the singular, the plural form is encompassed unless explicitly stated to be limited to the singular.

Claims

1. A circuit comprising: a first transistor coupled to a supply voltage, the first transistor comprising a gate region, a source contact, and a drain contact; a second transistor coupled to ground, the second transistor comprising a gate region, a source contact, and a drain contact; a first gate contact coupled to the first transistor and the second transistor, wherein the first gate contact is at a first position offset from a center point between the first transistor and the second transistor; as well as A second gate contact is coupled to the first transistor and the second transistor, wherein the second gate contact is at a second position, the second position is offset from the center point opposite to the first position, and the second gate contact is not connected to any metal layer above the layer of the second gate contact. 2 . The circuit of claim 1 , wherein the first location is closer to the first transistor than to the second transistor. 3 . The circuit of claim 1 , wherein the first location is closer to the second transistor than to the first transistor.

4. The circuit of claim 1, wherein the first transistor is a PFET and the second transistor is a NFET. 5 . The circuit of claim 1 , wherein the first position is offset from the center point by 10 nm to 100 nm.

6. The circuit of claim 1, wherein the first transistor is a PFET and the second transistor is an NFET, and the circuit is an inverter circuit.

7. The circuit of claim 1, wherein the first transistor is a pair of PFETs and the second transistor is a pair of NFETs, and the circuit is a NOR circuit.

8. The circuit of claim 1, wherein the circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

9. A circuit comprising: a first amplifying device coupled to a supply voltage, the first amplifying device comprising a gate region, a source contact, and a drain contact; a second amplifying device coupled to ground, the second amplifying device comprising a gate region, a source contact, and a drain contact; a first gate contact coupled to the first amplifying device and the second amplifying device, wherein the first gate contact is at a first position offset from a center point between the first amplifying device and the second amplifying device; and A second gate contact is coupled to the first amplifying device and the second amplifying device, wherein the second gate contact is at a second position, the second position is offset from the center point opposite to the first position, and the second gate contact is not connected to any metal layer above the layer of the second gate contact.

10. The circuit of claim 9, wherein the first position is closer to the first amplifying device than to the second amplifying device.

11. The circuit of claim 9, wherein the first position is closer to the second amplifying device than to the first amplifying device.

12. The circuit of claim 9, wherein the first amplifying device is a PFET and the second amplifying device is a NFET.

13. The circuit of claim 9, wherein the first position is offset from the center point by 10 nm to 100 nm.

14. The circuit of claim 9, wherein the first amplifying device is a PFET and the second amplifying device is a NFET, and the circuit is an inverter circuit.

15. The circuit of claim 9, wherein the first amplifying means is a pair of PFETs and the second amplifying means is a pair of NFETs, and the circuit is a NOR circuit.

16. The circuit of claim 9, wherein the circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a motor vehicle.

17. A method for forming a circuit, the method comprising: forming a gate region, a source contact, and a drain contact of a first transistor; forming a gate region, a source contact, and a drain contact of a second transistor; forming a first gate contact coupled to the first transistor and the second transistor at a first location, wherein the first location is offset from a center point between the first transistor and the second transistor; as well as A second gate contact coupled to the first transistor and the second transistor is formed at a second position, wherein the second position is offset from the center point opposite to the first position and the second gate contact is not connected to any metal layer above a layer of the second gate contact.

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