Antenna device with integrated antenna array and low-loss multilayer interposer

Abstract

The present invention discloses an antenna device, comprising: a radiating layer having a plurality of antenna elements forming an antenna array; a semiconductor wafer including a plurality of blocks each having a beamforming circuit; and a multilayer interposer. The multilayer interposer may include: a lower dielectric layer adjacent to a substrate; an upper dielectric layer adjacent to the radiating layer; a metal layer located between the lower and upper layers and including a plurality of conductive traces; a plurality of first vias extending through both the upper and lower layers and electrically coupling the beamforming circuit to the plurality of antenna elements; and a plurality of second vias extending between the beamforming circuit and the conductive traces to interconnect the blocks.

Description

Technical Field

[0001] The present disclosure relates generally to antennas, and more particularly to compact configurations of antenna arrays integrated with beamforming circuitry.

[0002] Discussions in related fields

[0003] Antenna arrays are currently being deployed at microwave and millimeter wave frequencies in a variety of applications, including in aircraft, satellites, vehicles, and base stations for general land-based communications. Such antenna arrays typically include patch radiating elements driven with phase-shifted beamforming circuitry to generate a phased array for beam steering. In many cases, it is desirable for the entire antenna system (including the antenna array and beamforming circuitry) to occupy a low-profile, minimal space while still meeting the necessary performance metrics. Especially at high millimeter wave frequencies, there are challenges in limiting undesirable reactance and losses due to the extremely small wavelength and size / spacing of components. Summary of the Invention

[0004] In one aspect of the technology disclosed herein, an antenna device includes: a radiating layer including a plurality of antenna elements forming an antenna array; a semiconductor wafer including a plurality of blocks each having beamforming circuitry; and a multilayer interposer. The multilayer interposer may include: a lower dielectric layer adjacent to the wafer; an upper dielectric layer adjacent to the radiating layer; a metal layer located between the lower and upper dielectric layers and including a plurality of conductive traces; a plurality of first vias extending through both the upper and lower dielectric layers and electrically coupling the beamforming circuitry to the plurality of antenna elements; and a plurality of second vias extending between the beamforming circuitry and the conductive traces to interconnect the blocks.

[0005] In another aspect, an antenna device includes: a radiating layer having a plurality of antenna elements forming an antenna array; a semiconductor wafer including a plurality of RF beamforming circuits, each having a transistor region formed within the semiconductor wafer, each beamforming circuit having at least one phase shifter and a transmit path amplifier and / or a receive path amplifier; and a multilayer interposer. The multilayer interposer includes: a lower dielectric layer adjacent to a substrate; an upper dielectric layer adjacent to the radiating layer; a metal layer located between the lower and upper layers and including a plurality of conductive traces forming a combiner / divider network that combines and / or divides signals between the plurality of RF beamforming circuits and input / output connection points of the interposer; and a plurality of first vias extending through both the upper and lower layers and electrically coupling the plurality of RF beamforming circuits to the plurality of antenna elements. A plurality of second vias extend between the RF beamforming circuitry and the conductive traces, some of which interconnect the antenna elements with the combiner / divider network via the RF beamforming circuitry. The wafer also includes at least one intermediate amplifier that amplifies a transmit signal or a receive signal routed to or from an intermediate point in the combiner / divider network via another second via among the second vias, and outputs the amplified transmit signal or receive signal back to the combiner / divider network via yet another second via among the second vias.

[0006] In another aspect, a method for manufacturing an antenna device involves sequentially applying the same reticle image to each of a plurality of regions of a semiconductor wafer, thereby forming a corresponding block within each region, each block including an RF beamforming circuit having an ion-implanted transistor region located within the wafer and a metallization pattern located on a surface of the wafer; and attaching an interposer to the wafer. The interposer includes a lower dielectric layer adjacent to the wafer, an upper dielectric layer, a metal layer located between the lower and upper dielectric layers and including a plurality of conductive traces, a plurality of first vias extending through both the upper and lower layers, and a plurality of second vias extending between a lower surface of the interposer and the metal layer to interconnect the plurality of blocks. A radiating layer including a plurality of antenna elements is attached to or formed on the upper surface of the interposer, such that the antenna elements are electrically coupled to the RF beamforming circuit through the plurality of first vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects and features of the disclosed technology will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which the same reference numerals indicate the same elements or features. Various elements of the same or similar type can be distinguished by attaching a dash and a second label (e.g., -1, -2) to the reference label to distinguish the same / similar elements, or by simply attaching the second label to the reference label. However, if a given description uses only the first reference label, it applies to any of the same / similar elements having the same first reference label, regardless of the second label. In the drawings, elements and features may not be drawn to scale.

[0008] Figure 1 is an exploded perspective view of an exemplary antenna apparatus according to one embodiment.

[0009] Figure 2 Shown in a cross-sectional view in an assembled state Figure 1 An exemplary configuration of an antenna device.

[0010] Figure 3 Another exemplary configuration of an antenna device is shown in an assembled state, depicted in cross-section.

[0011] Figure 4 An exemplary block arrangement on a wafer and a block configuration of an antenna device are shown.

[0012] Figure 5 The manner in which a block of a wafer of antenna devices may be formed using a reticule is schematically shown.

[0013] Figure 6 An exemplary layout of contiguous blocks on a wafer is depicted.

[0014] Figure 7A An exemplary connection configuration and signal routing between sub-circuits of a common block in an antenna device according to one embodiment is shown.

[0015] Figure 7B It is a depiction Figure 7A Functional diagram of signal splitting and routing in an implementation scheme.

[0016] Figure 8 An exemplary connection configuration and signal routing between sub-circuits of different blocks in an antenna device according to one embodiment is shown.

[0017] Figure 9 An exemplary block layout with signal routing examples is shown according to one embodiment.

[0018] Figure 10 is a flow chart of an exemplary method for forming an antenna apparatus according to one embodiment.

[0019] Figure 11 is a flow chart of an exemplary method for forming an interposer for an antenna device. DETAILED DESCRIPTION

[0020] For illustrative purposes, the following description is provided with reference to the accompanying drawings to facilitate a more comprehensive understanding of certain exemplary embodiments of the technology disclosed herein. This description includes various specific details to assist one of ordinary skill in the art in understanding the technology, but these details should be considered merely exemplary. Where the inclusion of a description of well-known functions and structures might obscure a skilled artisan's understanding of the technology, such descriptions may be omitted for clarity and brevity.

[0021] As used herein, a substrate may be considered to "include" circuitry, or "include circuitry formed therein," etc., even though the circuitry may be only partially formed within the substrate (e.g., as a doped region of a transistor or an embedded conductor). A substrate considered to include circuitry may also have conductive elements partially formed on a surface of the substrate.

[0022] As used herein, "beamforming circuitry" can be any circuitry that helps form an antenna beam. Beamforming circuitry can be comprised of one or more active components and / or one or more passive components. Examples of active components include amplifiers, phase shifters, and switches; examples of passive components include filters and a length of transmission line. Multiple interconnected beamforming circuits can together form an RF front end coupled to an antenna array.

[0023] As used herein, the term "through-hole transition" means a group of two or more connections including at least one through-hole, wherein the group of connections collectively make a transition from one transmission line or transmission mechanism to another transmission line or mechanism. A through-hole transition can be a group of three through-holes making a ground-signal-ground (GSG) connection between a coplanar waveguide (CPW), microstrip line, or stripline to a probe feed connected to an antenna element. A through-hole transition can also be a GSG connection between a CPW or microstrip line to a stripline, in which case the GSG connection includes two through-holes and a ground-ground connection. In other examples, a through-hole transition connecting a microstrip line or CPW in one layer to a microstrip line in another layer can have only one through-hole and one direct connection.

[0024] Figure 1is an exploded perspective view of an antenna device 10 according to one embodiment. The antenna device 10 includes a radiating layer 20, a wafer 40, and a multilayer interposer 30 located between the radiating layer 20 and the wafer 40. The antenna element 22 of the radiating layer 20 is coupled to the beamforming circuit within the wafer 40 through the interposer 30. The wafer 40 is composed of a semiconductor material such as silicon, silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). The interposer 30 can be composed of a material having a lower loss tangent than the wafer 40, such as quartz or fused silica. The interposer 30 provides low-loss routing and frequency division / combining of RF signals between connection points within the wafer 40 and also between the wafer 40 and the antenna element 22. In one example, the antenna device 10 is configured to operate in the millimeter (mm) wave band, which is generally defined as a frequency band in the range of 30 GHz to 300 GHz. In other examples, the antenna device 10 operates in the microwave range of approximately 1 GHz to 30 GHz or in the sub-microwave range below 1 GHz.Herein, a radio frequency (RF) signal refers to a signal having any frequency from below 1 GHz to 300 GHz.

[0025] The radiating layer 20 may include "n" antenna elements 22-1 to 22-n defining an antenna array 23 formed on the upper surface of a dielectric 25. The number n of antenna elements 22, their type, size, shape, inter-element spacing, and the manner in which they are fed from the beamforming circuitry may be varied by design to achieve target performance metrics. Examples of such performance metrics include beamwidth, pointing direction, polarization, side lobes, power loss, beam shape, etc. over a necessary frequency band. The antenna elements 22 may be, for example, Figure 1 The antenna element 22 may be a microstrip line patch antenna element, or other radiator types, such as a printed dipole or slotted element, as shown. Depending on the application, the antenna element 22 may be connected to a beamforming component for transmitting and / or receiving RF signals. Connections to the beamforming circuitry of the antenna elements 22-1 through 22-n may be through probe feeds 27-1 through 27-n, respectively, formed within the dielectric 25 and connected to other vias within the interposer 30. The dielectric 25 may be a low-loss material, such as air / honeycomb material, that may be atomically grown layer by layer on the interposer 30. As another example, other materials, such as liquid crystal polymers or quartz, may be used.

[0026] Interposer 30 may comprise a low-loss dielectric material such as quartz or fused silica. In one embodiment, interposer 30 has a stripline configuration, in which case interposer 30 includes: an upper metal layer 36 formed on the top surface of upper dielectric layer 33 and serving as both the upper ground plane of the stripline and the ground plane of antenna element 22; a lower metal layer (lower ground plane) 39 formed on the bottom surface of lower dielectric layer 31; and a metal (conductive) layer 37 positioned between upper dielectric layer 33 and lower dielectric layer 31 to form the center conductor of the stripline configuration. Each of metal layers 39, 37, and 36 may be a thin film metal layer. Upper metal layer 36 has an opening therein through which probe feed 27 is connected to the upper end of via 72s and isolated from the ground plane. Lower metal layer 39 also has an opening through which the lower ends of vias 72s and 82s pass. Vias 72s connect probe feed 27 to connection points on wafer 40. Vias 72s are each part of a corresponding GSG via transition 72, discussed below. Vias 82s are blind vias that connect a point on layer 37's center conductor to another connection point on wafer 40. Vias 82s are each part of a corresponding via transition 82, also described later. Metal layer 37 is patterned to form a combiner / divider network 35 having a plurality of interconnected conductive traces, each of which routes an RF signal. Combiner / divider network 35 combines and / or divides RF signals propagating between input / output (I / O) connection point p4 and connection points on wafer 40 for further routing to / from antenna element 22. For example, in the transmit direction, combiner / divider network 35 acts as a frequency divider to divide the input transmit signal at I / O point p4 into a plurality of divided frequency signal paths, thereby providing corresponding multiple divided frequency transmit signals at network endpoints 35e, such as 35e1 and 35e2. In the receive direction, the combiner / divider network 35 acts as a combiner to combine the receive signals received at endpoint 35e into a composite receive signal that is output at I / O point p4.

[0027] In other embodiments, interposer 30 has a microstrip configuration, in which case lower ground plane 39 can be replaced by a patterned metal layer that forms the conductor of the microstrip transmission line. In this case, center metal layer 37 can be omitted, and upper ground plane 36 can serve as both the microstrip ground plane and the ground plane for antenna element 22. In other embodiments, a coplanar waveguide (CPW) transmission line is used within interposer 30, in which case lower ground plane 39 is replaced by a CPW conductor, center metal layer 37 can be omitted, and upper ground plane 36 remains. In another embodiment, center metal layer 37 is patterned to form the conductor of the microstrip transmission line of interposer 30, and lower ground plane 39 serves as the ground for the microstrip transmission line. In this case, vias 82s connect the microstrip conductor to the signal line within wafer 40, and a direct ground-to-ground connection is made between ground plane 39 and the ground of wafer 40. In another example, the center metal layer 37 is a CPW, and three vias are used in the GSG connection between the CPW and the CPW or microstrip line within the wafer 40 .

[0028] Wafer 40 is an example of a semiconductor substrate within which all active beamforming circuitry between a single RF input / output port (e.g., p4) and the antenna array 23 is housed. This approach is in contrast to conventional configurations in which a single chip with beamforming circuitry is attached to the substrate. In one embodiment, wafer 40 is considered an "array-sized" substrate by having a form factor approximately equal to the form factor of the antenna array 23. For example, the antenna array 23 may be comprised of tens, hundreds, or more than thousands of antenna elements 22, all coupled to the beamforming circuitry of a single wafer 40 via an interposer 30. Wafer 40 may include "k" "blocks" 42-1 through 42-k formed therein, wherein each block 42 includes one or more sub-circuits 48 (interchangeably, "beamforming circuitry"), such as "w" sub-circuits 48-1 through 48-w included within block 42-1. As used herein, a block represents circuitry formed within the wafer using a reticle-based image applied to a single area (hereinafter, a "block area"). (hereinafter in conjunction with Figure 5An example of block formation using a shrink mask is described.) In one embodiment, all blocks 42 have the same design, with the same overall circuit configuration, number of sub-circuits 48, and physical layout. In other embodiments, some of the blocks 42 are different from each other. "Saw streets" 55 exist between adjacent blocks 42, which are isolated areas on the wafer 40 without metallization. Interconnects can be provided within the interposer 30 to connect adjacent blocks 42 across the saw streets 55. For example, the conductive traces of the combiner / divider 35 in combination with the through-hole transitions 82 can be used as such interconnects, which effectively interconnect the sub-circuits 48 of different blocks of the wafer 40. In combination with such interposer interconnects for interconnecting the blocks 42 across the saw streets 55, a large number of beamforming circuits 48 can be formed integrally within a single wafer 40 without having to cut and reattach individual chips, thereby facilitating the manufacturing process. In addition, the wafer footprint that would have been allocated to the combiner / divider network can be freed up for other circuits or uses.

[0029] It should be noted here that in other examples of large antenna arrays, multiple wafers 40 are arranged side by side to form a multi-wafer subassembly, and a single interposer 30 is bonded to the multiple wafers 40 to interconnect a large number of antenna elements to beamforming circuits distributed across the multi-wafer subassembly.

[0030] Any of the sub-circuits 48 may include beamforming circuitry having ion-implanted transistor regions formed internally within the wafer 40. The beamforming circuitry includes front-end beamforming components such as a transmit path amplifier, a transmit path phase shifter, a bandpass filter, a receive path low noise amplifier (LNA), a receive path phase shifter, a transmit / receive (T / R) switch, and / or an "on-wafer" combiner / divider, or portions thereof. Any of the sub-circuits 48 may be referred to as a "chip unit" having beamforming circuitry that would traditionally be incorporated into a single chip that is cut from the wafer and reattached to a substrate. Through the techniques of the present invention, the manufacturing process for forming the antenna device 10 is simplified by forming many of the sub-circuits 48 within a single wafer 40 rather than cutting the chips from the wafer and reattaching them to the substrate. In addition, interconnects, such as wire bonds, are not required to connect the individual chips to the substrate, thereby reducing inductance and improving reliability.

[0031] Any subcircuit 48 can be electrically connected to one or more antenna elements 22 via one or more corresponding vias 72s. For example, subcircuit 48-1 of block 42-1 may have a connection point p1 that is connected to connection point p2 of probe feed 27-1 of antenna element 22-1 via via 72s (part of via transition 72). In one embodiment, some or all of the endpoints 35e of combiner / divider 35 are connected to an "on-wafer" combiner / divider 49 via corresponding vias 82s, which in turn routes signals to and from two or more subcircuits 48. For example, endpoint 35e1 is connected to connection point p3 of combiner / divider 49 via a first via 82s, while endpoint 35e2 is connected to a second via 82s of another combiner / divider 49 (not shown). To divide the transmit signal, such an on-wafer combiner / divider 49 receives the transmit signal at an input path and divides the signal between multiple output paths, each of which is connected to a corresponding subcircuit 48. A reciprocating combining operation may be performed for the receive path signal.In other embodiments, the combiner / divider 49 is omitted and each terminal 35e is directly connected to the corresponding sub-circuit 48 through a via 82.

[0032] In one embodiment, some or all of the blocks 42 include at least one sub-circuit 65 that functions as an intermediate amplifier. The sub-circuit 65 amplifies a transmit signal or a receive signal that is routed to / from an intermediate point (other than the terminal 35e) of the combiner / divider 35 through a via 82s, and then outputs / reroutes the amplified signal back to the combiner / divider 35 through another via 82s at another intermediate point.

[0033] Figure 2 An exemplary configuration of a portion of the antenna device 10 in an assembled state is shown in a cross-sectional view. Figures 6 to 9 Detailed examples of interconnections and operational signal flows within antenna device 10 are described. In this example, wafer 40 is electrically and mechanically connected to interposer 30 via a large number of solder balls (or copper pillars) 59 connected between the lower metal layer 39 of interposer 30 and the top surface 41 of wafer 40. For example, for a large antenna array 23, the number of solder balls 59 may be in the thousands. Interposer 30 also includes a thin-film metal layer 36, which may be formed by electroplating on the top surface of upper layer 33. Radiating layer 20 may be bonded to metal layer 36 by atomically growing multiple layers of air / honeycomb dielectric material of dielectric 25 atop metal layer 36. Alternatively, a pre-cut flat sheet of dielectric 25 may be fused to metal layer 36 via direct bond interconnect (DBI) bonding, thermocompression bonding, or other suitable processes. If a fusion bonding method is used, metal layer 36 may alternatively be formed first on the lower surface of dielectric 25 rather than on the top surface of interposer 30.

[0034] Figure 2 The example depicts two sub-circuits 48-1 and 48-2 (which are part of the same block 42) and a sub-circuit 65 (which can be part of the same block or a different block 42). The radiating layer 20 includes antenna elements 22-1, 22-2 connected to probe feeds 27-1, 27-2, each of which is in turn connected to a via 72s. The example shows a via transition 72 embodied as a set of three vias forming part of a GSG connection: a "signal via" 72s, a first "ground via" 72g1, and a second ground via 72g2. The signal via 72s is connected on one end to the probe feed 27-1 and on the opposite end to a "signal contact" 51s of the sub-circuit 48-1 through a solder ball 59. The signal contact 51s joins a first ground contact 51g1 and a second ground contact 51g2 located on opposite sides thereof to form a set of GSG contacts 51. First ground via 72g1 and second ground via 72g2 are connected to first ground contact 51g1 and second ground contact 51g2, respectively, at one end via corresponding solder balls 59, and to ground plane 36 at opposite ends. In a stripline configuration, via transitions 82 can function as stripline-to-CPW, stripline-to-microstrip, or stripline-to-stripline transitions, depending on the type of transmission line interface within wafer 40. In either case, each via transition 82 can include: a signal via 82s (blind via) connecting between the center conductor within layer 37 and signal contact 51; a ground via 82g1 connecting between ground plane 36 and ground contact 51g1; and an adjacent connection (via solder balls 59) between ground contact 51g2 and lower ground plane 39. In this way, signal energy flows freely between the stripline of interposer 30 and the CPW, microstrip, or stripline interface of wafer 40. Herein, the signal via 72 s is an example of a “first via,” and the signal via 82 s is an example of a “second via.”

[0035] Each subcircuit 48 includes one or more beamforming components, such as an amplifier 52 and a phase shifter 54. The subcircuits 48 of different blocks 42 are effectively interconnected via vias 82s connected to the combiner / divider 35. Any subcircuit 48 can receive a control signal or bias signal CNT on a control line 47 to control one or more active components therein. The control line 47 can be connected to external components via input terminals on the bottom surface 44 of the wafer 40. The beamforming components of the subcircuit 48 can modify (e.g., amplify, phase shift, and / or filter) the transmit signal received from the combiner / divider 35 via the on-wafer combiner / divider 49 and output the modified transmit signal to the corresponding antenna element 22. By using a T / R switch (not shown) and / or circuit, a reciprocating operation can occur in the receive path direction to achieve full duplex or other transmit-receive isolation schemes. If combiner / divider 49 is implemented as a CPW, the CPW conductor or microstrip conductor may have been formed on surface 41 of wafer 40, as shown. Because solder balls 59 have a diameter large enough to form gap 77 between the opposing surfaces of wafer 40 and interposer 30, gap 77 may be sufficient to prevent ground plane 39 from shorting or adversely affecting the signals carried by the CPW or microstrip conductor.

[0036] In some examples, subcircuit 48 may also include a frequency divider (not shown) that divides the modified transmit signal (e.g., output by amplifier 52) to feed two or more antenna elements 22. Such a frequency divider may perform a reciprocating combining operation in the receive direction.

[0037] exist Figure 2In the example shown, combiner / divider 35 has an input signal path 35a that is disconnected at the metal layer 37 level and routed downward to transmit amplifier 62 of sub-circuit 65 via a via transition 82. The amplified transmit signal output by amplifier 62 is then routed back to combiner / divider 35 via another via transition 82. For example, if input signal path 35 is relatively long and lossy, amplifier 62 can restore the magnitude of the transmit signal to a desired level. In the receive direction, a receive path amplifier (not shown) can be similarly deployed within sub-circuit 65. In this case, a T / R switch or other isolation circuitry can be included within sub-circuit 65 to isolate the transmit and receive signals. I / O point p4 can receive input transmit signals and / or output receive signals via a connector (not shown) attached to a side surface of interposer 30. In another example, an I / O connector (not shown) is attached to bottom surface 44 of wafer 40. In this case, I / O point p4 can be connected to the I / O connector via another via transition 82. The latter through-hole transition 82 will connect to the wafer 40 at a connection point corresponding to the top end of a through-hole in the wafer 40 or a coaxial through-section in the wafer 40. The bottom end of the through-hole or through-section in the wafer 40 will connect to the I / O connector at the bottom surface 44.

[0038] Typically, sub-circuits 48 of the same or different blocks may be connected to each other for routing RF signals and / or control signals through interconnection paths of interposer 30. Interconnection paths between sub-circuits 48 may be formed at metal layer 37 using blind vias such as 82s, and / or at another metal layer located at a different level (not shown) within interposer 30. Figure 2 Alternatively, if subcircuits 48-1 and 48-2 are subcircuits of different blocks 42, then saw street regions 55 exist between blocks 42. Since no metallization is applied to top surface 41 of wafer 40 in saw street regions 55, “inter-block” connections between subcircuits 48 can be made through interposer 30 through layer 37 in this manner.

[0039] Figure 3 Another exemplary configuration of the antenna device 10 in an assembled state is shown. Figure 2 The configuration of FIG. 1 differs in that the solder balls 59 are omitted, and instead a direct bond is formed between the interposer 30 and the wafer 40, for example, by a DBI bonding method. This forms a direct bond from the through-hole transitions 72, 82 of the interposer 30 to the metal contacts 51 of the wafer 40. In large antenna arrays, this approach eliminates thousands of solder balls 59, thereby improving the reliability of the antenna device 10. To avoid shorts between the ground plane 39 and conductive elements on the surface 41 (e.g., CPW or microstrip line inner conductors on the surface 41), an isolation layer may be deposited on top of any conductors on or near the wafer surface 41.

[0040] Figure 4 An exemplary block arrangement on a wafer and an exemplary block configuration of the antenna device 10 are shown. As mentioned, a block represents a circuit formed within a wafer using a reticle-based image applied to a particular physical surface (referred to herein as a "block area"). As shown, a disk-shaped wafer 40 may have blocks 42 formed into rows and columns, with saw streets 55 between adjacent blocks 42. However, in contrast to conventional designs, the blocks 42 are not cut from the wafer along the saw streets 55. Blocks such as 42-1 may include a grid layout of subcircuits 48-1 to 48-w (one or more of which may be the subcircuits 65 discussed previously). In some examples, only complete rectangular or square blocks 42 are formed as part of the wafer 40, leaving some axial surface area of the wafer 40 unused. In other examples, additional subcircuits may be formed at the circular perimeter of the wafer.

[0041] Figure 5 The manner in which a block of wafer 40 may be formed using a reticle is schematically shown. Reticle 90 is a tool that produces a photolithographic image 91 that patterns a film or mask (already deposited on the wafer) to expose areas for processing and ultimately form a complete circuit after a number of process steps. Image 91 has a span "d" that is typically limited to a portion of the diameter of wafer 40 to some extent. Typically, span d is less than half the diameter of wafer 40 in order to produce an image of the circuit at the surface of wafer 40 at a target resolution. In some cases, the same image can be produced in a block area across wafer 40 by stepping reticle 90 laterally and repeatedly illuminating it with the same image 91. (In other examples, different images may be used in different corresponding areas of wafer 40 as part of the same processing stage.) Thus, in Figure 5 In FIG. 4 , as part of a first exposure step, reticle 90 initially produces a first image 91 to produce a first exposure of block 42-i. Reticle 90 is then laterally translated as indicated by path 93 and produces a second image 91, generally identical to the first image, to produce a first exposure of a second block 42-(i+1). This process can be repeated for all block regions of wafer 40. A first processing step, such as ion implantation for doping transistor regions or electroplating for depositing a first metallization layer, can then be performed simultaneously on all block regions on wafer 40. Next, another mask or film can be deposited on the surface of wafer 40, and reticle 90 can be again controlled to begin a second round of block-to-block exposures corresponding to a second processing step, and so on, until all processing steps are completed. Throughout this process, saw streets 55 are formed between adjacent blocks. These saw streets are metal-free isolation areas that are conventionally used to cut blocks or individual chips from the wafer. In embodiments of the present invention, no cutting is performed between blocks 42, resulting in wafer 40 in the form of a continuous substrate with many blocks 42 formed therein.

[0042] Figure 6 An exemplary layout of consecutive blocks on a wafer 40 of an antenna device 10 according to one example is depicted. Blocks 42-i, 42-(i+1), and 42-(i+2) are arranged in a given row of the wafer 40, with saw streets 55 between adjacent blocks. Each block 42 may have a plurality of interconnected subcircuits 48-1 to 48-w, which are cut from the wafer along regions 66 (and also along saw streets 55) to form individual chips that are reattached to the substrate in order to form conventional devices. In an embodiment of the present invention, no chips are cut, and each block, such as 42-i, may have a plurality of on-wafer combiners / dividers, such as 49-1 and 49-2.

[0043] Figure 7A Schematically showing identical blocks such as Figure 6 42 - i exemplarily connect and signal flow between sub-circuits 48 within . Figure 7B is a functional block diagram of this example. In the transmit direction, the RF signal output from subcircuit 48-j is divided between paths 35c and 35d of combiner / divider 35 within interposer 30. The divided signals are rerouted back to wafer 40 via corresponding paths 722, 724 (e.g., through-hole transition 82) connected to on-wafer dividers 49-1, 49-2 at points p6 and p7, respectively. The on-wafer dividers 49-1, 49-2 each divide the signal between multiple paths, and these divided signals are provided to adjacent subcircuit pairs (48-(j-2), 48-(j-1)) and (48-(j+1), 48-(j+2)), respectively. Each subcircuit 48 can modify the input signal and output the modified signal to antenna element 22 through interposer 30, as depicted by path 713. Reciprocating signal traffic can occur in the receive direction.

[0044] Figure 8 The schematic diagram shows an exemplary connection configuration between sub-circuits of different blocks in the antenna device 10 according to one embodiment and the signal routing across the blocks. In the transmit direction, the RF signal originating from the sub-circuit 48-P of the block 42-(i+1) is output through the interposer 30 and split between the paths 35f and 35g of the combiner / divider 35. The path 35f crosses the saw street 55 and is connected to the on-wafer divider 49-u of the adjacent block 42-i through a through-hole transition 82. The path 35g crosses the block 42-(i+1) and is connected to the on-wafer divider 49-v through another through-hole transition 82. The on-wafer dividers 49-u, 49-v again split the signal between the adjacent sub-circuits 48 for modification and output to the antenna array 23. Reciprocating signal traffic can occur in the receive direction.

[0045] Figure 9An exemplary block layout and signal routing example according to an embodiment of the antenna device 10 is shown. In this example, the wafer 40 includes a grid layout of sixty blocks 42-1 to 42-60, with one block omitted from each corner of the square outline. Each block, such as 42-j (j = any number from 1 to 60), can have the same design and include sub-circuits 48-1 to 48-16 with RF front-end circuitry, and another sub-circuit 65 (hereinafter simply referred to as "amplifier 65") with an intermediate amplifier 62 to provide intermediate amplification. Each sub-circuit 48 may include a set of contacts 51 as described above to connect to a corresponding antenna element 22 via a through-hole transition 72. Figure 9 The bold lines in FIG. 3 represent the paths of an exemplary combiner / divider 35 within the interposer 30. RF I / O connection point p4 within the interposer 30, located near the concentrated edge of the wafer 40, connects to input path 35a. Input path 35a extends to a concentrated point p8 of the interposer 30, where it is divided to feed the left and right blocks 42. In the transmit path example, the transmit signal is rerouted via a via transition 82 from the combiner / divider 35 to amplifier 65-1 of a block 42 on each side. Here, the transmit signal is amplified and routed back to the combiner / divider 35 via another via transition 82 for further division at point p9 toward the blocks in the upper and lower quadrants. Downstream, further division by the combiner / divider 35 and amplification by amplifiers such as 65-2 can occur as needed or desired to restore the divided transmit signal to a suitable level.

[0046] As seen in the enlarged view of block 42-j, the transmit signal destined for block 42-j can be routed from interposer 30 to intermediate amplifier 65 via via transition 82 and amplified. The amplified output can be routed back to combiner / divider 35, where it can be divided into two paths, one of which can terminate at endpoint 35ej. From there, another via transition 82 can route the signal back to on-wafer combiner / divider 49-j. In this example, combiner / divider 49-j is a 1:16 power divider / combiner with 16 termination points connected to respective subcircuits 48-1 through 48-16 for transmission via antenna element 22. This reciprocating operation can occur in the receive path from antenna element 22. It should be noted that while the same amplifier(s) 65 can be provided in each block 42, some amplifiers 65 can be actively used while others are not (unconnected and / or turned off). The selection of which amplifiers 65 to use, and how to bias them for variable amplification, may depend on the overall layout of block 42 and the target electric field (antenna current) distribution across the aperture of antenna array 23. For example, rather than designing for a uniform electric field distribution, the outer antenna elements may be fed with lower RF power to achieve a target antenna pattern with lower sidelobes.

[0047] Figure 10 is a flow chart of an exemplary method of forming an antenna device 10 having an interposer with a stripline configuration. The order of the various process steps of the method may be changed as desired. Figure 5 The shrink mask forms a wafer 40 having a plurality of blocks (S102). An interposer 30 having a stripline configuration is formed (S104), wherein the interposer includes upper and lower ground planes and vias (e.g., blind vias 82s and "full vias" 82g1, 72s, 72g1, 72g2 extending completely between the lower and upper surfaces of the interposer).

[0048] Using the solder ball connection scheme ( Figure 2 ) or the previously described direct attachment method ( Figure 3 ) The wafer is attached to the lower ground plane of the interposer (S106). The dielectric layer of the radiating layer 20 can be grown on top of the upper ground plane (S108). The material of the dielectric layer can be an air / honeycomb material that is grown atomically layer by layer. Once the dielectric layer is completed, the antenna element can be formed on top of the dielectric layer, and the probe feed via can be formed through the dielectric layer (S110), thereby completing the manufacture of the antenna device 10. The probe feed via is connected to the antenna element metallization at one end and to the top metallization of the interposer signal via 72s on the opposite end.

[0049] Figure 11 is used to form Figure 10 Flowchart of exemplary process steps for an interposer of a method, showing an example of process S104. The order of the various process steps of the method can be changed as needed. A lower dielectric layer of the interposer is provided (S112). The top surface of the lower dielectric layer is metallized in a pattern (S114) to form a combiner / divider 35; and the bottom surface of the lower dielectric layer is metallized in a pattern to form a lower ground plane 39 having apertures for signal vias 72s and 82s. The apertures prevent the signal vias from shorting to the lower ground plane. Thus, in the area of each signal via 72s and 82s, the metallization pattern can be formed as a centralized metal disk or square for the via pad, which is surrounded by an isolation ring with the metal removed, which is in turn surrounded by the ground plane metal.

[0050] Blind vias 82s of the through-hole transition 82 connected to the point of the combiner / divider 35 may be formed (S116). An upper dielectric layer of the stripline may then be formed or attached on the metallized top surface of the lower substrate (S118). The top surface of the dielectric layer may be metallized in a pattern to form an upper ground plane with similar apertures, thereby allowing isolated connections between the probe feed through-holes and the signal vias 72s. Holes may then be drilled to obtain complete through-holes 82g1 for the through-hole transition 72 and the through-hole transition 82; and the holes may be filled with metal to complete the formation of the through-holes (S120), thereby completing the fabrication of the interposer 30.

[0051] Compared to conventional designs, embodiments of the antenna device described above can be formed to have a thin profile and achieve superior performance (e.g., lower loss and higher frequency operation). In addition, the construction enables a convenient manufacturing process. By providing through-holes for the interposer to interconnect blocks based on the scaled mask image across the saw street isolation area, a large amount of beamforming circuitry can be formed internally within a single wafer. Array-sized wafers with beamforming circuitry can thus be manufactured without having to cut individual chips and reattach them to the substrate. In addition, area within the wafer that would have been allocated to the combiner / divider network can be freed up for other uses.

[0052] While the technology described herein has been particularly shown and described with reference to exemplary embodiments of the technology described herein, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the claimed subject matter as defined by the following claims and their equivalents.

Claims

1. An antenna device (10), comprising: a radiating layer (20), the radiating layer comprising a plurality of antenna elements (22) forming an antenna array; a semiconductor wafer (40) comprising a plurality of blocks (42) each having a beamforming circuit (48); as well as A multilayer interposer (30), comprising: a lower dielectric layer (31), the lower dielectric layer being adjacent to the wafer; an upper dielectric layer (33), the upper dielectric layer being adjacent to the radiation layer; a metal layer (37) located between the lower dielectric layer and the upper dielectric layer and comprising a plurality of conductive traces (35); a plurality of first vias (72) extending through both the upper dielectric layer and the lower dielectric layer and electrically coupling the beamforming circuitry to the plurality of antenna elements; and a plurality of second vias (82) extending between the beamforming circuit and the conductive traces to interconnect the plurality of blocks, Each of the plurality of blocks has the same circuit configuration formed by generating an image (91) using the same reticle.

2. The antenna device (10) according to claim 1, wherein the wafer further comprises saw streets (55) separating the plurality of blocks from each other.

3. The antenna device (10) of claim 1, wherein the first vias are each a signal via (72s) of a ground-signal-ground (GSG) via transition, the GSG via transition further comprising a first ground via (72g1) on one side of the signal via and a second ground via (72g2) on the other side of the signal via.

4. The antenna device (10) according to claim 3, wherein: The multilayer interposer (30) has a stripline configuration including a first dielectric layer, a second dielectric layer, a lower ground plane (39) located between the wafer and the lower dielectric layer, and an upper ground plane (36) located between the upper dielectric layer and the radiating layer, the upper ground plane serving as a ground plane for the antenna element; The first ground via and the second ground via are connected to corresponding first ground contacts (51g1) and second ground contacts (51g2) on the wafer at one end, and are connected to the upper ground plane at opposite ends.

5. The antenna device (10) of claim 4, wherein the second vias (82s) are each a signal via of a via transition, the via transition further comprising a ground via (82g1) connecting a third ground contact of the wafer to the upper ground plane and a ground-to-ground connection connecting a fourth ground contact of the wafer to the lower ground plane.

6. The antenna device (10) of claim 1, wherein the conductive trace of the metal layer is part of a combiner / divider network (35) that divides a radio frequency (RF) transmit signal received at an input / output (I / O) connection point (P4) of the interposer into a plurality of divided-frequency RF transmit signals, each divided-frequency RF transmit signal being routed to one or more of the beamforming circuits using a respective one of the second vias located at a respective endpoint (35e) of the combiner / divider network.

7. The antenna device (10) of claim 6, wherein the RF transmit signal is received from a connection point on the wafer at the I / O connection point using a further through-via (82) within the interposer.

8. The antenna device (10) according to claim 6, wherein: Each of the divided frequency transmit signals is routed to a respective one of the plurality of blocks at the respective endpoint of the combiner / divider network; and The respective block further includes an on-wafer combiner / divider electrically connected to the respective endpoints, the on-wafer combiner / divider further dividing the divided signal into at least two further divided signals and routing each of the further divided signals to a respective beamforming circuit in the beamforming circuits of the respective block.

9. The antenna device (10) of claim 1, wherein the plurality of conductive traces form a combiner / divider network (35), and at least one of the plurality of blocks includes an intermediate amplifier that amplifies a transmit signal or a receive signal of the combiner / divider network routed to / from an intermediate point of the combiner / divider network through another through-hole within the interposer, and outputs the amplified transmit signal or receive signal back to the combiner / divider network through yet another through-hole (82).

10. The antenna device (10) of claim 1, wherein the plurality of conductive traces form a combiner / divider network (35), and each of the plurality of blocks comprises an intermediate amplifier (65) connectable on an input side to a respective intermediate point of the combiner / divider via another through-hole (82) within the interposer and connectable on an output side to another respective intermediate point of the combiner / divider via yet another through-hole, each intermediate amplifier being configured to selectively amplify a transmit signal or a receive signal routed by the combiner / divider network.

11. The antenna device (10) of claim 1, wherein the plurality of conductive traces form a combiner / divider network (35) that combines a plurality of radio frequency (RF) receive signals received by the antenna elements and conditioned by the beamforming circuitry into a combined RF receive signal that is output to a connection point on the wafer using a further through-hole within the interposer.

12. The antenna device (10) of claim 1, further comprising a plurality of solder bumps (59), each solder bump electrically connecting a corresponding one of the first or second vias to the wafer.

13. The antenna device (10) of claim 1, wherein the wafer is directly bonded to the multilayer interposer.

14. The antenna device (10) of claim 1, wherein the radiating layer comprises an air dielectric material grown on the interposer and supporting the antenna element.

15. The antenna device of claim 1, wherein the antenna elements are patch antenna elements, each patch antenna element being driven by a probe feed (27) electrically coupled to one of the first vias.

16. An antenna device (10), comprising: a radiating layer (20), the radiating layer comprising a plurality of antenna elements (22) forming an antenna array; a semiconductor wafer (40) comprising a plurality of radio frequency (RF) beamforming circuits (48) each having a transistor region formed internally within the semiconductor wafer, each beamforming circuit comprising at least one phase shifter (54) and at least one of a transmit path amplifier (52) and a receive path amplifier (52); as well as A multilayer interposer (30), comprising: a lower dielectric layer (31), the lower dielectric layer being adjacent to the substrate; an upper dielectric layer (33), the upper dielectric layer being adjacent to the radiation layer; a metal layer (37) located between the lower layer and the upper layer and comprising a plurality of conductive traces forming a combiner / divider network (35) that combines and / or divides signals between the plurality of RF beamforming circuits and the input / output connection points (P4) of the interposer; a plurality of first vias (72) extending through both the upper layer and the lower layer and electrically coupling the plurality of RF beamforming circuits to the plurality of antenna elements; and a plurality of second vias (82) extending between the RF beamforming circuit and the conductive trace, some of the second vias interconnecting the antenna element with the combiner / divider network through the RF beamforming circuit; The wafer includes at least one intermediate amplifier (62), which amplifies a transmit signal or a receive signal routed to / from an intermediate point of the combiner / divider network through another second through-hole among the second through-holes, and outputs the amplified transmit signal or receive signal back to the combiner / divider network through another second through-hole among the second through-holes.

17. The antenna device (10) according to claim 16, wherein: The multilayer interposer has a stripline structure including a first dielectric layer, a second dielectric layer, a lower ground plane (39) located between the wafer and the lower dielectric layer, and an upper ground plane (36) located between the upper dielectric layer and the radiating layer, the upper ground plane serving as a ground plane for the antenna element.

18. The antenna device (10) according to claim 16, wherein: The combiner / divider network divides the transmit signal into a plurality of divided frequency transmit signals at respective endpoints of the combiner / divider network; Each of the divided frequency transmit signals is routed to the wafer at a corresponding one of the endpoints; and The wafer also includes a plurality of on-wafer combiners / dividers (49) each electrically connected to one of the endpoints, the plurality of on-wafer combiners / dividers further dividing the divided transmit signal into at least two further divided signals and routing each further divided signal to a corresponding one of the RF beamforming circuits.

19. The antenna apparatus (10) of claim 16, wherein each of the transmit path amplifier and the receive path amplifier is a millimeter wave amplifier.

20. The antenna device (10) of claim 16, wherein the multilayer interposer is composed of quartz or fused silica.

21. A method of manufacturing an antenna device (10), the method comprising: applying the same scaled mask image (91) sequentially to each of a plurality of regions of a semiconductor wafer (40), thereby forming a corresponding block (42) in each region, each block including a radio frequency (RF) beamforming circuit (48) having an ion implanted transistor region within the wafer and a metallization pattern on a surface of the wafer (S102); attaching an interposer (30) to the wafer (S104, S106), the interposer comprising a lower dielectric layer adjacent to the wafer, an upper dielectric layer, a metal layer located between the lower dielectric layer and the upper dielectric layer and comprising a plurality of conductive traces, a plurality of first through-holes extending through both the upper layer and the lower layer, and a plurality of second through-holes extending between a lower surface of the interposer and the metal layer to interconnect the plurality of blocks; as well as A radiating layer including a plurality of antenna elements is attached to an upper surface of the interposer such that the antenna elements are electrically coupled to the RF beamforming circuit through the plurality of first vias ( S108 , S110 ).

22. The method of claim 21 , wherein the attaching of the radiative layer to the upper surface of the interposer comprises: growing an air dielectric material on the interposer ( S108 ); forming a probe feed via (27) within the grown air dielectric material, the probe feed via being electrically connected at a first end thereof to a corresponding first via among the first vias (S110); and The antenna element is formed on or in the air dielectric material, and the antenna element is electrically connected to opposite ends of the probe feed through hole ( S110 ).

23. The method of claim 21 , wherein the attaching of the interposer to the wafer comprises attaching a plurality of solder bumps (59) to the lower surface of the interposer and / or the wafer, and soldering electrical contacts (51) of each of the wafer and the interposer to opposite sides of the plurality of solder bumps.

24. The method of claim 21, wherein the attaching of the interposer to the substrate comprises directly attaching the lower surface of the interposer to the major surface (41) of the wafer using a direct bonding interface bonding method.

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