Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the method comprising: providing a substrate; forming a dielectric layer and a conductive layer located in the dielectric layer on the substrate, wherein the top surface of the conductive layer is lower than the top surface of the dielectric layer, and the conductive layer has a groove located in the dielectric layer; forming an initial protective layer on the bottom surface and side wall surface of the groove, wherein the thickness of the initial protective layer on the side wall surface of the groove is less than the thickness of the initial protective layer on the bottom surface of the groove; modifying the initial protective layer on the side wall surface of the groove and part of the initial protective layer on the bottom surface of the groove, forming a protective layer on the bottom surface of the groove, and forming a modified layer on the protective layer surface on the side wall surface of the groove and the bottom of the groove; removing the modified layer until the dielectric layer on the side wall of the groove is exposed. The performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] The metal interconnection structure is an indispensable structure in semiconductor devices, which is used to realize the interconnection between active areas, between transistors, or between metal lines of different layers, and complete the transmission and control of signals. Therefore, in the semiconductor manufacturing process, the formation of the metal interconnection structure has a great influence on the performance of semiconductor devices and the semiconductor manufacturing cost. In order to increase the density of devices, the size of semiconductor devices in integrated circuits has been continuously reduced. In order to realize the electrical connection of each semiconductor device, a multi-layer interconnection structure is usually required.

[0003] Generally, in the back-end interconnection process of the semiconductor device manufacturing process, the first metal layer (M1) needs to form an electrical connection with the active device structure (including the source and drain regions and the gate structure region) of the lower layer. Therefore, before forming the first metal layer, it is usually necessary to pre-form a local interconnection structure (Local Interconnect) of the semiconductor device. The local interconnection structure includes: a zeroth metal layer (M0) electrically connected to the source and drain regions of the lower layer, and a zeroth gate metal layer (M0G) electrically connected to the gate structure.

[0004] However, the manufacturing process of the local interconnect structure in the prior art needs to be improved, and the performance of the formed semiconductor structure needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a dielectric layer located on the substrate and a conductive layer located in the dielectric layer, the top surface of the conductive layer is lower than the top surface of the dielectric layer, and the conductive layer has a groove located in the dielectric layer; a protective layer is located on the surface of the conductive layer at the bottom of the groove.

[0007] Optionally, the material of the protective layer includes titanium.

[0008] Optionally, the protective layer also has an oxide layer.

[0009] Optionally, the thickness of the oxide layer ranges from 1 nanometer to 2 nanometers.

[0010] Optionally, the material of the oxide layer includes titanium oxide.

[0011] Optionally, it also includes: a barrier layer located on the protective layer in the groove.

[0012] Optionally, the substrate includes: a base; a gate structure located on the base; source and drain doped regions located in the base on both sides of the gate structure; the conductive layer is located on the source and drain doped regions; and the dielectric layer is located on the top and sidewalls of the gate structure.

[0013] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dielectric layer and a conductive layer located in the dielectric layer on the substrate, wherein the top surface of the conductive layer is lower than the top surface of the dielectric layer, and the conductive layer has a groove located in the dielectric layer; forming an initial protective layer on the bottom surface and side wall surface of the groove, and the thickness of the initial protective layer on the side wall surface of the groove is less than the thickness of the initial protective layer on the bottom surface of the groove; modifying the initial protective layer on the side wall surface of the groove and part of the initial protective layer on the bottom surface of the groove to form a protective layer on the bottom surface of the groove, and forming a modified layer on the protective layer surface on the side wall surface of the groove and the bottom of the groove; removing the modified layer until the dielectric layer on the side wall of the groove is exposed.

[0014] Optionally, the process for forming the initial protective layer includes a physical vapor deposition process; the process parameters of the physical vapor deposition process include: the target material is a titanium target, the power is 6 kW to 8 kW, the gas is argon, and the argon flow rate is 250 sccm to 300 sccm.

[0015] Optionally, the method further includes: forming an oxide layer on the protective layer.

[0016] Optionally, the method for modifying the initial protective layer on the surface of the side wall of the groove and part of the initial protective layer on the surface of the bottom of the groove includes: oxidizing the initial protective layer on the surface of the side wall of the groove and part of the initial protective layer on the surface of the bottom of the groove to form a protective layer at the bottom of the groove, and forming an initial oxide layer on the protective layer; nitriding the initial oxide layer on the side wall of the groove and part of the initial oxide layer at the bottom of the groove to form a modified layer on the side wall of the groove, and forming an oxide layer located on the protective layer at the bottom of the groove and the modified layer located on the oxide layer.

[0017] Optionally, the thickness of the initial oxide layer ranges from 3 nanometers to 4 nanometers; the thickness of the modified layer ranges from 2 nanometers to 3 nanometers.

[0018] Optionally, the material of the initial protective layer includes titanium.

[0019] Optionally, the material of the oxide layer includes titanium oxide.

[0020] Optionally, the material of the modified layer includes titanium nitride.

[0021] Optionally, the process of removing the modified layer includes a wet etching process; and an etching solution of the wet etching process includes a mixed solution of ammonia water and hydrogen peroxide.

[0022] Optionally, the material of the modified layer and the material of the oxide layer have different etching rates.

[0023] Optionally, the thickness of the oxide layer ranges from 1 nanometer to 2 nanometers.

[0024] Optionally, the process of oxidizing the initial protective layer on the surface of the side wall of the groove and part of the initial protective layer on the surface of the bottom of the groove includes plasma oxidation treatment, and the plasma is a plasma containing oxygen ions; the process parameters of the plasma oxidation treatment include: an oxygen flow rate of 200sccm to 400sccm, a temperature of 100 degrees Celsius to 300 degrees Celsius, a power of 800 watts to 1200 watts, and a time of 40 seconds to 80 seconds.

[0025] Optionally, the process of nitriding the initial oxide layer on the side wall of the groove and part of the initial oxide layer at the bottom of the groove includes a plasma nitridation process, and the gas of the plasma nitridation process includes nitrogen, or a mixed gas of hydrogen and nitrogen; the parameters of the plasma nitridation process include: power of 2500 watts to 4000 watts, gas flow of 80 sccm to 120 sccm, and temperature of 300°C to 400°C.

[0026] Optionally, the process of removing the modified layer includes a wet etching process; and an etching solution of the wet etching process includes a mixed solution of ammonia water and hydrogen peroxide.

[0027] Optionally, the material of the modified layer and the material of the protective layer have different etching rates.

[0028] Optionally, the thickness of the initial protective layer on the side wall surface of the groove is in the range of 0 nanometers to 2 nanometers; the thickness of the initial protective layer on the bottom surface of the groove is in the range of 5 nanometers to 8 nanometers.

[0029] Optionally, after removing the modified layer, the method further includes: forming a barrier layer in the groove.

[0030] Optionally, the substrate includes: a base; a gate structure located on the base; source and drain doped regions located in the base on both sides of the gate structure; the conductive layer is located on the source and drain doped regions; and the dielectric layer is located on the top and sidewalls of the gate structure.

[0031] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0032] The method for forming a semiconductor structure in the technical solution of the present invention forms an initial protective layer on the bottom surface and side wall surface of the groove, wherein the thickness of the initial protective layer on the side wall surface of the groove is less than the thickness of the initial protective layer on the bottom surface of the groove, and then the initial protective layer on the side wall surface of the groove and part of the initial protective layer on the bottom surface of the groove are modified to form a modified layer on the side wall surface and the bottom surface of the groove, and finally the modified layer is removed to form a protective layer on the bottom surface of the groove, wherein the protective layer exposes the dielectric layer on the side wall of the groove. The modification process completely modifies the initial protective layer on the side wall of the groove and partially modifies the initial protective layer on the bottom of the groove. Therefore, when the modified layer is removed, the modified layer on the side wall of the groove can be completely removed, and a protective layer is only formed on the bottom surface of the groove. Thus, the effect of forming a protective layer only on the top surface of the conductive layer is achieved, and the situation that when the protective layer is located on the side wall of the groove, when a conductive structure located on the gate structure is subsequently formed, the protective layer on the side wall of the groove is easily in contact with the conductive structure to cause a short circuit, thereby affecting the performance of the semiconductor structure.

[0033] Furthermore, the process of forming the initial protective layer includes a physical vapor deposition process. The process characteristics of the physical vapor deposition process make the thickness of the initial protective layer formed on the bottom surface of the groove greater than the thickness of the initial protective layer formed on the side wall surface of the groove, so that when the initial protective layer on the side wall of the groove and part of the initial protective layer on the bottom of the groove are subsequently modified, the initial protective layer on the side wall of the groove can be completely modified.

[0034] Furthermore, the method for modifying the initial protective layer on the surface of the sidewall of the groove and the protective layer on part of the bottom surface of the groove includes: oxidizing the initial protective layer on the surface of the sidewall of the groove and the protective layer on part of the bottom surface of the groove to form an initial oxide layer; nitriding the initial oxide layer on the sidewall of the groove and part of the initial oxide layer on the bottom of the groove to form the modified layer. Oxidation followed by nitridation allows the initial protective layer on the sidewall of the groove to be completely modified, while oxidation of part of the initial protective layer at the bottom of the groove first forms an initial oxide layer, and then nitriding of part of the initial oxide layer at the bottom of the groove forms an oxide layer and a modified layer on the oxide layer. The modified layer and the oxide layer have a large etching selectivity ratio, so when removing the modified layer, the oxide layer at the bottom of the groove can protect the protective layer at the bottom of the groove, thereby preventing the protective layer at the bottom of the groove from being damaged by the process of removing the modified layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 and Figure 2 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0036] Figures 3 to 9It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, the manufacturing process of the local interconnect structure in the prior art needs to be improved, and the performance of the formed semiconductor structure needs to be further improved. Now, an analysis and description will be given in conjunction with specific embodiments.

[0038] Figure 1 and Figure 2 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment.

[0039] Please refer to Figure 1 , providing a substrate 100; forming a gate structure 101 on the substrate 100; forming source-drain doped regions 102 in the substrate on both sides of the gate structure 101; forming a dielectric layer 103 on the substrate 100; forming an opening (not shown) in the dielectric layer 103, wherein the opening exposes the surface of the source-drain doped region 102; and forming an initial first conductive structure 104 in the opening.

[0040] Please refer to Figure 2 , the initial first conductive structure 104 is etched back to form a first conductive structure 105 and a groove (not shown) located in the dielectric layer 103; a protective layer 106 is formed on the top surface of the first conductive structure 105; and a barrier layer 107 is formed on the protective layer 106.

[0041] During the formation of the semiconductor structure, the material of the barrier layer 107 is different from that of the dielectric layer 103. The barrier layer 107 is used for the subsequent formation of a second conductive structure electrically connected to the gate structure 101, so that the second conductive structure can be self-aligned and formed on the gate structure. The initial first conductive structure 104 is crystalline after annealing, and the surface crystalline state of the first conductive structure 105 formed after back etching is damaged. In addition, the material of the initial first conductive structure 104 is usually cobalt, and the ions of metal cobalt are relatively active, so the cobalt ions of the first conductive structure 105 with damaged surface crystalline state are easy to migrate to the barrier layer 107, making the electrical properties of the semiconductor structure unstable and there is a risk of leakage. Therefore, a protective layer 106 is usually formed on the surface of the first conductive structure 105 to prevent the cobalt ions of the first conductive structure 105 from diffusing into the barrier layer 107. The material of the protective layer 106 is usually titanium, which has good stability. The formation process of the protective layer 106 usually adopts a selective deposition process or a selective electroplating process.

[0042] However, the existing selective deposition process or selective electroplating process will also grow the protection layer 106 on the sidewall of the groove, and it is difficult to form the protection layer 106 located only on the surface of the first conductive structure 105. When the protection layer 106 is located on the sidewall of the groove, since the protection layer 106 is conductive, the protection layer 106 is easy to contact with the second conductive structure formed subsequently and cause a short circuit, thereby affecting the performance of the semiconductor structure.

[0043] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, wherein an initial protective layer is formed on the bottom surface and side wall surface of the groove, wherein the thickness of the initial protective layer on the side wall surface of the groove is less than the thickness of the protective layer on the bottom surface of the groove, and then the initial protective layer on the side wall surface of the groove and the protective layer on part of the bottom surface of the groove are modified to form a modified layer on the side wall surface and the bottom surface of the groove, and finally the modified layer is removed to form a protective layer on the bottom surface of the groove, wherein the protective layer exposes the dielectric layer on the side wall of the groove. The modification process completely modifies the initial protective layer on the side wall of the groove and partially modifies the initial protective layer on the bottom of the groove, so that when the modified layer is removed, the modified layer on the side wall of the groove can be completely removed, and a protective layer is only formed on the bottom surface of the groove. Thus, the effect of forming a protective layer only on the top surface of the conductive layer is achieved, and the situation that when the protective layer is located on the side wall of the groove, when a conductive structure located on the gate structure is subsequently formed, the protective layer on the side wall of the groove is easily in contact with the conductive structure to cause a short circuit, thereby affecting the performance of the semiconductor structure.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 3 to 9 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0046] Please refer to Figure 3 , providing a substrate.

[0047] The substrate includes: a base 200 ; a gate structure 201 located on the base 200 ; and source / drain doped regions 202 located in the base 200 on both sides of the gate structure 201 .

[0048] In this embodiment, the material of the substrate 200 is silicon.

[0049] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0050] The source-drain doping region 202 has doping ions therein, and the doping ions are of N-type or P-type. The N-type ions include phosphorus ions, arsenic ions, or antimony ions. The P-type ions include boron ions, boron fluoride ions, or indium ions.

[0051] The gate structure 201 includes: a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer. In this embodiment, the gate structure 201 further includes a work function layer (not shown), which is located between the gate dielectric layer and the gate layer.

[0052] In this embodiment, the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate layer includes a metal, and the metal includes tungsten; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0053] In other embodiments, the material of the gate dielectric layer includes silicon oxide or a low-K (K is less than 3.9) material; and the material of the gate layer includes polysilicon.

[0054] In this embodiment, the substrate 200 is a planar substrate; in other embodiments, the substrate further has a fin structure, the gate structure spans the fin structure, and the source and drain doping regions are located in the fin structure on both sides of the gate structure.

[0055] Please continue to refer to Figure 3 , a dielectric layer 203 is formed on the substrate, and the dielectric layer 203 is located on the top and sidewalls of the gate structure 201.

[0056] The method for forming the dielectric layer 203 includes: forming a dielectric material layer (not shown) on a substrate; and planarizing the dielectric material layer to form the dielectric layer 203 .

[0057] The process of forming the dielectric material layer includes a chemical vapor deposition process, an atomic layer deposition process or a thermal treatment process. In this embodiment, the process of forming the dielectric material layer includes a chemical vapor deposition process, which can quickly form a dielectric material layer with a thick thickness and good quality.

[0058] The material of the dielectric layer 203 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the dielectric layer 203 includes silicon oxide.

[0059] Please refer to Figure 4 , a conductive layer 205 is formed in the dielectric layer 203 , the top surface of the conductive layer 205 is lower than the top surface of the dielectric layer 203 , and the conductive layer 205 has a groove 204 located in the dielectric layer 203 .

[0060] The conductive layer 205 is located on the source-drain doped region 202 .

[0061] The method for forming the conductive layer 205 includes: forming a patterned layer (not shown) on the dielectric layer 203, wherein the patterned layer exposes the surface of the dielectric layer 203 on the source-drain doped region 202; using the patterned layer as a mask, etching the dielectric layer 203 until the surface of the source-drain doped region 202 is exposed, and forming an opening (not shown) in the dielectric layer 203; forming an initial conductive layer (not shown) in the opening; and etching back the initial conductive layer to form the conductive layer 205.

[0062] The process of etching the dielectric layer 203 includes a dry etching process. The dry etching process has high directional selectivity and can form an opening with a good sidewall morphology.

[0063] The material of the conductive layer 205 includes metal, and the metal includes cobalt.

[0064] In this embodiment, before forming the initial conductive layer in the opening, the method further includes: forming a liner layer (not shown) on the sidewall surface and the bottom surface of the opening. The material of the liner layer includes titanium, tantalum, titanium nitride or tantalum nitride.

[0065] Please refer to Figure 5 An initial protection layer 206 is formed on the bottom surface and the side wall surface of the groove 204 , and the thickness of the initial protection layer 206 on the side wall surface of the groove 204 is less than the thickness of the initial protection layer 206 on the bottom surface of the groove 204 .

[0066] In this embodiment, the material of the initial protective layer 206 includes titanium. The initial protective layer 206 is used to form a protective layer at the bottom of the groove 204 later, and the protective layer can prevent the ions of the conductive layer 205 from diffusing into the barrier layer formed later, thereby reducing the leakage of the conductive layer 205 after the ions diffuse into the barrier layer.

[0067] The process of forming the initial protective layer 206 includes a physical vapor deposition process; the process parameters of the physical vapor deposition process include: the target material is a titanium target, the power is 6 kW to 8 kW, the gas is argon, and the argon flow rate is 250 sccm to 300 sccm.

[0068] The process of forming the initial protection layer 206 includes a physical vapor deposition process. The process characteristics of the physical vapor deposition process make the thickness of the initial protection layer 206 formed on the bottom surface of the groove 204 greater than the thickness of the initial protection layer 206 formed on the sidewall surface of the groove 204, so that when the initial protection layer 206 on the sidewall of the groove 204 and part of the initial protection layer 206 at the bottom of the groove are subsequently modified, the initial protection layer 206 on the sidewall of the groove 204 can be completely modified.

[0069] In this embodiment, the thickness of the initial protection layer 206 on the sidewall surface of the groove 204 ranges from 0 nanometers to 2 nanometers; the thickness of the initial protection layer 206 on the bottom surface of the groove 204 ranges from 5 nanometers to 8 nanometers.

[0070] Next, the initial protective layer 206 on the sidewall surface of the groove 204 and part of the initial protective layer 206 on the bottom surface of the groove 204 are modified to form a protective layer 208 on the bottom surface of the groove 204, and a modified layer 209 is formed on the sidewall surface of the groove 204 and the surface of the protective layer 208 at the bottom of the groove 204. The formation process of the protective layer 208 and the modified layer 209 can be found in Figure 6 and Figure 7 .

[0071] The protection layer 208 is used to protect the conductive layer 205 and can prevent the ions in the conductive layer 205 from diffusing into the subsequently formed barrier layer, thereby improving the stability of the semiconductor structure.

[0072] Please refer to Figure 6 The initial protective layer 206 on the side wall surface of the groove 204 and part of the initial protective layer 206 on the bottom surface of the groove 204 are oxidized to form a protective layer 208 at the bottom of the groove 204 , and an initial oxide layer 207 is formed on the protective layer 208 .

[0073] In this embodiment, the material of the initial oxide layer 207 includes titanium oxide.

[0074] The thickness of the initial oxide layer 207 is in the range of 3 nm to 4 nm. The initial protection layer 206 on the sidewall surface of the groove 204 is completely oxidized, and the initial protection layer 206 on the bottom surface of the groove 204 is partially oxidized.

[0075] The process of oxidizing the initial protective layer 206 on the sidewall surface of the groove 204 and part of the initial protective layer 206 on the bottom surface of the groove 204 includes plasma oxidation, wherein the plasma is a plasma containing oxygen ions; the process parameters of the plasma oxidation include: an oxygen flow rate of 200 sccm to 400 sccm, a temperature of 100 degrees Celsius to 300 degrees Celsius, a power of 800 watts to 1200 watts, and a time of 40 seconds to 80 seconds. The oxidation depth of the initial protective layer 206 is controlled by controlling the reaction time.

[0076] The thickness of the initial protective layer 206 on the sidewall surface of the groove 204 is less than the thickness of the initial protective layer 206 on the bottom surface of the groove 204. Therefore, under the same oxidation process conditions, the oxidation process can completely oxidize the initial protective layer 206 on the sidewall surface of the groove 204, and can oxidize part of the initial protective layer 206 on the bottom surface of the groove 204, so as to form a protective layer 208 at the bottom of the groove 204. Therefore, the formed protective layer 208 is only located on the top surface of the conductive layer 205, so as to avoid the situation that when the protective layer 208 is located on the sidewall of the groove 204, when a conductive structure located on the gate structure 201 is subsequently formed, the protective layer 208 on the sidewall of the groove 204 is easily in contact with the conductive structure to cause a short circuit, thereby affecting the performance of the semiconductor structure.

[0077] Please refer to Figure 7 The initial oxide layer 207 on the side wall of the groove 204 and part of the initial oxide layer 207 at the bottom of the groove 204 are nitrided to form a modified layer 209 on the side wall of the groove 204, and a protective layer 208, an oxide layer 210 located on the protective layer 208, and the modified layer 209 located on the oxide layer 210 are formed at the bottom of the groove 204.

[0078] In this embodiment, the material of the modified layer 209 includes titanium nitride.

[0079] In this embodiment, the method further includes: forming an oxide layer 210 on the protection layer 208 , and the modified layer 209 at the bottom of the groove 204 is located on the oxide layer 210 .

[0080] The process of nitriding the initial oxide layer 207 on the sidewall of the groove 204 and part of the initial oxide layer 207 at the bottom of the groove 204 includes a plasma nitridation process, wherein the gas of the plasma nitridation process includes nitrogen or a mixed gas of hydrogen and nitrogen; the parameters of the plasma nitridation process include: power of 2500 watts to 4000 watts, gas flow of 80 sccm to 120 sccm, and temperature of 300° C. to 400° C. The nitridation process allows the initial oxide layer 207 on the sidewall of the groove 204 to be completely nitrided, and allows the initial oxide layer 207 at the bottom of the groove 204 to be partially nitrided.

[0081] In this embodiment, the thickness of the modified layer 209 is in the range of 2 nanometers to 3 nanometers, and the thickness of the oxide layer 210 is in the range of 1 nanometer to 2 nanometers.

[0082] In other embodiments, the initial oxide layer at the bottom of the groove is completely nitrided, so that no oxide layer is formed on the protective layer.

[0083] Please refer to Figure 8 , removing the modified layer 209 until the dielectric layer 203 on the sidewall of the groove 204 is exposed.

[0084] The process of removing the modified layer 209 includes a wet etching process; the etching solution of the wet etching process includes a mixed solution of ammonia water and hydrogen peroxide.

[0085] The material of the modified layer 209 and the material of the oxide layer 210 have different etching rates, so that the wet etching process causes less damage to the oxide layer 210 when removing the modified layer 209, thereby preventing the protective layer 208 and the conductive layer 205 at the bottom of the groove 204 from being damaged by the process of removing the modified layer 209.

[0086] At this point, oxidation followed by nitridation allows the initial protective layer 206 on the side wall of the groove 204 to be completely modified, and part of the initial protective layer 206 at the bottom of the groove 204 is oxidized to first form an initial oxide layer 207, and then part of the initial oxide layer 207 at the bottom of the groove 204 is nitrided to form an oxide layer 210 and a modified layer 209 located on the oxide layer 210. The material of the modified layer 209 and the oxide layer 210 has a large etching selectivity. Therefore, when the modified layer 209 is removed, the oxide layer 210 at the bottom of the groove 204 can protect the protective layer 208 at the bottom of the groove 204, thereby preventing the protective layer 208 at the bottom of the groove 204 from being damaged by the process of removing the modified layer 209.

[0087] In other embodiments, the initial oxide layer at the bottom of the groove is completely nitrided, so that no oxide layer is formed on the protective layer.

[0088] The process of removing the modified layer includes a wet etching process; the etching solution of the wet etching process includes a mixed solution of ammonia water and hydrogen peroxide.

[0089] The etching rates of the modified layer material and the protective layer material are different, so that the wet etching process causes less damage to the protective layer when removing the modified layer, thereby preventing the conductive layer at the bottom of the groove from being damaged by the process of removing the modified layer.

[0090] Please refer to Fig. 9After removing the modified layer 209 , a barrier layer 211 is formed in the groove 204 .

[0091] The method for forming the barrier layer 211 includes: forming a barrier material layer (not shown) in the groove 204 and on the dielectric layer 203 ; and planarizing the barrier material layer until the surface of the dielectric layer 203 is exposed to form the barrier layer 211 .

[0092] The material of the barrier layer 211 includes a dielectric material, and the dielectric material includes silicon nitride, silicon oxynitride, silicon carbide or silicon carbide. In this embodiment, the material of the barrier layer 211 includes silicon nitride.

[0093] The material of the blocking layer 211 is different from that of the dielectric layer 203 , so that when a conductive structure is subsequently formed in the dielectric layer 203 on top of the gate structure 201 , the conductive structure can be formed on the gate structure in a self-aligned manner.

[0094] Since the formed protection layer 208 is only located on the top surface of the conductive layer 205 , the protection layer 208 can block the ions of the conductive layer 205 from diffusing into the blocking layer 211 , thereby improving the stability of the performance of the semiconductor structure.

[0095] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig. 9 ,include;

[0096] substrate;

[0097] A dielectric layer 203 located on the substrate and a conductive layer 205 located in the dielectric layer 203 , wherein the top surface of the conductive layer 205 is lower than the top surface of the dielectric layer 203 , and the conductive layer 205 has a groove (not shown) located in the dielectric layer 203 ;

[0098] A protection layer 208 is located on the surface of the conductive layer 205 at the bottom of the groove.

[0099] In this embodiment, the material of the protection layer 208 includes titanium.

[0100] In this embodiment, an oxide layer 210 is further formed on the protection layer 208 .

[0101] In this embodiment, the thickness of the oxide layer 210 is in the range of 1 nanometer to 2 nanometers.

[0102] In this embodiment, it further includes: a barrier layer 211 located on the protection layer 208 in the groove.

[0103] In this embodiment, the substrate includes: a base 200; a gate structure 201 located on the base 200; source and drain doped regions 202 located in the base 200 on both sides of the gate structure 201; the conductive layer 205 is located on the source and drain doped regions 202; and the dielectric layer 203 is located on the top and sidewalls of the gate structure 201.

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A dielectric layer and a conductive layer located in the dielectric layer are formed on a substrate, wherein a top surface of the conductive layer is lower than a top surface of the dielectric layer, and the conductive layer has a groove located in the dielectric layer; forming an initial protective layer on the bottom surface and the side wall surface of the groove, wherein the thickness of the initial protective layer on the side wall surface of the groove is smaller than the thickness of the initial protective layer on the bottom surface of the groove; Performing modification treatment on the initial protective layer on the surface of the side wall of the groove and part of the initial protective layer on the surface of the bottom of the groove to form a protective layer on the surface of the bottom of the groove, and forming a modified layer on the surface of the protective layer on the surface of the side wall of the groove and the bottom of the groove, wherein the modified layer is obtained by sequentially performing oxidation treatment and nitridation treatment on the initial protective layer; The modified layer is removed until the dielectric layer on the sidewall of the groove is exposed.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming the initial protective layer includes a physical vapor deposition process; the process parameters of the physical vapor deposition process include: the target material is a titanium target, the power is 6 kW to 8 kW, the gas is argon, and the argon flow rate is 250 sccm to 300 sccm.

3. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: An oxide layer is formed on the protective layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method for modifying the initial protective layer on the surface of the side wall of the groove and part of the initial protective layer on the surface of the bottom of the groove comprises: oxidizing the initial protective layer on the surface of the side wall of the groove and part of the initial protective layer on the surface of the bottom of the groove to form a protective layer at the bottom of the groove, and forming an initial oxide layer on the protective layer; nitriding the initial oxide layer on the side wall of the groove and part of the initial oxide layer at the bottom of the groove to form a modified layer on the side wall of the groove, and forming an oxide layer located on the protective layer at the bottom of the groove and the modified layer located on the oxide layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The thickness of the initial oxide layer ranges from 3 nanometers to 4 nanometers; the thickness of the modified layer ranges from 2 nanometers to 3 nanometers.

6. The method for forming a semiconductor structure according to claim 4, wherein: The material of the initial protective layer includes titanium.

7. The method for forming a semiconductor structure according to claim 6, wherein: The material of the oxide layer includes titanium oxide.

8. The method for forming a semiconductor structure according to claim 6, wherein: The material of the modified layer includes titanium nitride.

9. The method for forming a semiconductor structure according to claim 6, wherein: The process of removing the modified layer includes a wet etching process; the etching solution of the wet etching process includes a mixed solution of ammonia water and hydrogen peroxide.

10. The method for forming a semiconductor structure according to claim 9, wherein: The material of the modified layer and the material of the oxide layer have different etching rates.

11. The method for forming a semiconductor structure according to claim 3, wherein: The thickness of the oxide layer ranges from 1 nanometer to 2 nanometers.

12. The method for forming a semiconductor structure according to claim 4, wherein: The process of oxidizing the initial protective layer on the surface of the sidewall of the groove and part of the initial protective layer on the surface of the bottom of the groove comprises plasma oxidation treatment, wherein the plasma is a plasma containing oxygen ions; The process parameters of the plasma oxidation treatment include: an oxygen flow rate of 200 sccm to 400 sccm, a temperature of 100 degrees Celsius to 300 degrees Celsius, a power of 800 watts to 1200 watts, and a time of 40 seconds to 80 seconds.

13. The method for forming a semiconductor structure according to claim 4, wherein: The process of nitriding the initial oxide layer on the sidewall of the groove and part of the initial oxide layer at the bottom of the groove comprises a plasma nitridation process, wherein the gas of the plasma nitridation process comprises nitrogen, or a mixed gas of hydrogen and nitrogen; The parameters of the plasma nitridation process include: power of 2500W to 4000W, gas flow of 80sccm to 120sccm, and temperature of 300°C to 400°C.

14. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the modified layer includes a wet etching process; the etching solution of the wet etching process includes a mixed solution of ammonia water and hydrogen peroxide.

15. The method for forming a semiconductor structure according to claim 14, wherein: The material of the modified layer and the material of the protective layer have different etching rates.

16. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the initial protective layer on the side wall surface of the groove is in the range of 0 nanometers to 2 nanometers; the thickness of the initial protective layer on the bottom surface of the groove is in the range of 5 nanometers to 8 nanometers.

17. The method for forming a semiconductor structure according to claim 1, wherein: After removing the modified layer, the method further includes: forming a barrier layer in the groove.

18. The method for forming a semiconductor structure according to claim 1, wherein: The substrate comprises: a base; a gate structure on the base; source-drain doped regions in the base on both sides of the gate structure; the conductive layer on the source-drain doped regions; and the dielectric layer on the top and sidewalls of the gate structure.

19. A semiconductor structure formed by the forming method according to any one of claims 1 to 18, characterized in that: include: substrate; A dielectric layer located on the substrate and a conductive layer located in the dielectric layer, wherein the top surface of the conductive layer is lower than the top surface of the dielectric layer, and the conductive layer has a groove located in the dielectric layer; A protective layer located on the surface of the conductive layer at the bottom of the groove; A barrier layer is located on the oxide layer in the recess.

20. The semiconductor structure according to claim 18, wherein: The material of the protection layer includes titanium.

21. The semiconductor structure according to claim 18, wherein: The protective layer also has an oxide layer.

22. The semiconductor structure according to claim 21, wherein: The thickness of the oxide layer ranges from 1 nanometer to 2 nanometers.

23. The semiconductor structure according to claim 21, wherein: The material of the oxide layer includes titanium oxide.

24. The semiconductor structure according to claim 18, wherein: Also includes: A barrier layer is located on the protective layer within the groove.

25. The semiconductor structure according to claim 18, wherein: The substrate comprises: a base; a gate structure on the base; source-drain doped regions in the base on both sides of the gate structure; the conductive layer on the source-drain doped regions; and the dielectric layer on the top and sidewalls of the gate structure.

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