An automatic power equalization control circuit for a multi-phase interleaved flyback converter

Abstract

The present invention discloses an automatic power equalization control circuit for a multi-phase interleaved flyback converter, belonging to the field of electronic technology, which includes a VIN sampling circuit, a primary current sampling circuit ISEN, an integrating circuit U1, a multiplying circuit U2, a comparator U3, an error amplifier U4, a phase controller, a gate driving circuit, a power MOS transistor Q1, a transformer T, a diode D1, an output capacitor Co and a load module. The VIN sampling circuit is connected to each phase integrating circuit U1. The present invention can solve the problem of large output power deviation among phases of a multi-phase interleaved flyback converter, prevent a certain phase from being damaged due to excessive output power, and the circuit can quickly achieve accurate equalization control of the output power of each phase of the converter.

Description

Technical Field

[0001] The invention relates to the field of electronic technology, in particular to an automatic power balancing control circuit for a multi-phase interleaved flyback converter. Background Art

[0002] Flyback converters are widely used due to their simple structure and low cost. However, flyback converters have problems such as large output current spikes and limited output power. The introduction of multi-phase interleaved flyback converters can better solve the above shortcomings of flyback converters. When the multi-phase interleaved flyback converter is working, the power switches of each phase are switched on and off alternately, and energy is provided to the load end through the transformer. However, due to the production process deviation of the key component flyback transformer and the magnetic permeability deviation of the magnetic core, the discreteness of the transformer inductance can reach ±20%, resulting in a large deviation in the output power of each phase of the converter, which may cause a phase to be damaged due to excessive output power. Therefore, power balancing control technology is very important to improve the balance of the output power of each phase of the converter and the system reliability of the multi-phase interleaved converter.

[0003] At present, multi-phase interleaved flyback converters mostly use the production process of key components such as control transformers to reduce the output power deviation of each phase. However, strict control of the production process will greatly increase the production cost and reduce production efficiency, and the power deviation can only be controlled within about ±10%. Average current automatic current balancing technology is a commonly used power balancing control technology in multi-channel converter parallel systems, that is, by detecting the output current signals of each converter and taking their average values as common signals, the difference between a certain output current signal and the average value common signal represents the power balancing error of the channel. The reference voltage of the converter is adjusted by the error signal, and its output voltage is fine-tuned to achieve the purpose of balanced output power. Average current automatic current balancing technology is very effective for power balancing in multi-channel converter parallel systems, but when this control technology is used in multi-phase interleaved flyback converters, since each phase shares an output port, it is impossible to achieve the purpose of individually controlling the output voltage of each phase to adjust the output power of the phase. However, in the average current automatic current balancing technology, the idea of using the current average value as the common signal for multi-channel converters is worth learning from. Summary of the invention

[0004] The object of the present invention is to provide an automatic power balancing control circuit for a multi-phase interleaved flyback converter to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A multi-phase interleaved flyback converter automatic power balancing control circuit, comprising a VIN sampling circuit, a primary current sampling circuit ISEN, an integrating circuit U1, a multiplying circuit U2, a comparator U3, an error amplifier U4, a phase controller, a gate driving circuit, a power MOS transistor Q1, a transformer T, a diode D1, an output capacitor Co, and a load module. The VIN sampling circuit is connected to each phase of the integrating circuit U1; the phase controller is connected to each phase of the gate driving circuit; the output terminal of the error amplifier U4 is connected to the non-inverting input terminal of each phase of the comparator U3; the inverting input terminal of the error amplifier U4 circuit is connected to the positive electrode of the output capacitor Co; the non-inverting input terminal of the error amplifier U4 is connected to the reference voltage Vref; the output capacitor Co is connected in parallel with the load module, the positive electrode of the output capacitor Co is connected to the cathode of each phase of the diode D1, and the negative electrode of the output capacitor Co is connected to the output ground; the primary current sampling circuit ISEN is connected to the input terminal of the multiplying circuit U2; the integrating circuit U1 is connected to the other input terminal of the multiplying circuit U2; the output terminal of the multiplying circuit U2 is connected to the inverting input terminal of the comparator U3, and the output terminal of the comparator U3 is connected to the gate driving circuit; the output terminal of the gate driving circuit is connected to the gate of the power MOS transistor; the source of the power MOS transistor is connected to the ground through the primary current sampling circuit ISEN; the same-name end of the primary winding of the transformer T is connected to the input voltage VIN, and the other end is connected to the drain of the power MOS transistor; the same-name end of the secondary winding of the transformer T is connected to the output ground, and the other end is connected to the anode of the diode D1.

[0007] As a further solution of the present invention: the integrating circuit U1 and the multiplying circuit U2 form an LII circuit.

[0008] As a further solution of the present invention: the phase controller also generates clock signals required for each phase and is connected to each phase of the gate driving circuit.

[0009] As a further solution of the present invention: the integrating circuit U1 performs an integration operation on the signal of the VIN sampling circuit within the time period [t, t+Ton], where t is the turn-on moment of the power MOS transistor Q1 of a certain phase of the converter, and Ton is the turn-on duration of the power MOS transistor Q1. The output signal of the integrating circuit U1 and the primary current sampling signal ISEN are operated by the multiplying circuit U2 to generate a rising signal K1K2LmIp 2 , that is, the LII circuit finally generates a parabolic rising signal K1K2LmIp 2 , and then compares it with the output signal of the error amplifier U4 to generate a driving turn-off signal. The phase controller generates clock signals for each phase to ensure that the converter has the same operating frequency and a fixed and reasonable phase shift interval between each phase. The corresponding clock signals of each phase of the converter and the above driving turn-off signal jointly act on the gate driving circuit to generate PWM driving pulses to control the on and off of the power MOS transistor Q1 for power conversion.

[0010] As a further solution of the present invention: The signals sampled by the VIN sampling circuit include the input voltage sampling linear coefficient K1 and the converter input DC voltage VIN.

[0011] As a further solution of the present invention: The signals sampled by the primary side current sampling circuit ISEN include the primary side current sampling linear coefficient K2 and the primary side current Ip.

[0012] Compared with the prior art, the beneficial effects of the present invention are:

[0013] 1. Realize the automatic balanced control of the output power of each phase of the multi-phase interleaved converter, prevent the output power of a certain phase from being too large and causing damage, and improve the working reliability of the converter;

[0014] 2. The output power of each phase of the converter is controlled cycle by cycle, which can quickly respond to the dynamic changes of the load and realize the fast and accurate balanced control of the output power of each phase. Description of the Drawings

[0015] Figure 1 is the circuit schematic diagram of the present invention;

[0016] Figure 2 is the key signal waveform diagram of the present invention taking the dual-phase interleaved flyback converter as an example. Detailed Embodiments

[0017] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0018] Please refer to Figure 1-2, A multi-phase interleaved flyback converter automatic power balancing control circuit, comprising a VIN sampling circuit, a primary current sampling circuit ISEN, an integrating circuit U1, a multiplying circuit U2, a comparator U3, an error amplifier U4, a phase controller, a gate driving circuit, a power MOS transistor Q1, a transformer T, a diode D1, an output capacitor Co, and a load module. The VIN sampling circuit is connected to each phase of the integrating circuit U1; the phase controller is connected to each phase of the gate driving circuit; the output end of the error amplifier U4 is connected to the non-inverting input end of each phase of the comparator U3; the inverting input end of the error amplifier U4 circuit is connected to the positive electrode of the output capacitor Co; the non-inverting input end of the error amplifier U4 is connected to the reference voltage Vref; the output capacitor Co is connected in parallel with the load module, the positive electrode of the output capacitor Co is connected to the cathode of each phase of the diode D1, and the negative electrode of the output capacitor Co is connected to the output ground; the primary current sampling circuit ISEN is connected to the input end of the multiplying circuit U2; the integrating circuit U1 is connected to the other input end of the multiplying circuit U2; the output end of the multiplying circuit U2 is connected to the inverting input end of the comparator U3, and the output end of the comparator U3 is connected to the gate driving circuit; the output end of the gate driving circuit is connected to the gate of the power MOS transistor; the source of the power MOS transistor is connected to the ground through the primary current sampling circuit ISEN; the same-name end of the primary winding of the transformer T is connected to the input voltage VIN, and the other end is connected to the drain of the power MOS transistor; the same-name end of the secondary winding of the transformer T is connected to the output ground, and the other end is connected to the anode of the diode D1.

[0019] Figure 1 Among them, Vref is the reference voltage; Vo is the output voltage of the multi-phase interleaved converter; K1 is the linear coefficient of input voltage sampling; K2 is the linear coefficient of primary current sampling; Ip is the primary current; VIN is the input DC voltage of the converter; Lm is the primary excitation inductance of the transformer T.

[0020] The LII circuit is jointly composed of the integrating circuit U1 and the multiplying circuit U2. The integrating circuit U1 performs an integration operation on the signal K1VIN of the VIN sampling circuit within the time interval [t, t+Ton] (t is the turn-on moment of the power MOS transistor Q1 of a certain phase of the converter, and Ton is the turn-on duration of the power MOS transistor Q1). The output signal of the integrating circuit U1 and the primary current sampling signal ISEN are operated by the multiplying circuit U2 to generate Figure 1 The parabolic rising signal K1K2LmIp in 2 , that is, the LII circuit finally generates the parabolic rising signal K1K2LmIp 2 , and then compares it with the output signal COM of the error amplifier to generate a drive turn-off signal. The phase controller generates clock signals for each phase to ensure that each phase of the converter has the same operating frequency and a fixed and reasonable phase shift interval. The corresponding clock signals of each phase of the converter and the above drive turn-off signal jointly act on the gate driving circuit to generate PWM drive pulses to control the on and off of the power MOS transistor Q1 for power conversion.

[0021] Taking the dual-phase interleaved flyback converter as an example, the key waveform diagram is shown in Figure (2) to describe the above working process.

[0022] The specific principle derivation is as follows:

[0023] During the conduction period of the power MOS transistor Q1, according to Faraday's law of electromagnetic induction, the voltage of the primary winding of the transformer T is:

[0024]

[0025] In the time period of [t, t+Ton], the sampling signal K1VIN of VIN is integrated. After the power MOS transistor Q1 is turned off in each phase of the converter, the integration circuit U1 in the LII circuit is reset, and the output is cleared to prepare for the integration operation in the next switching period. Multiply both sides of Equation (1) by K1 and perform integration to obtain:

[0026] K1VIN*Ton = K1Lm(Ip max ) (2)

[0027] The output signal of the integration circuit U1 in Equation (2) and the primary current sampling signal ISEN K2Ip are subjected to real-time multiplication operation through the multiplication circuit U2. The operation result at the moment of t+Ton is:

[0028] K1Lm(Ip max )*K2(Ip max ) = K1K2Lm(Ip max ) 2 (3)

[0029] Equation (3) is the operation result of the LII circuit, which represents the energy transferred by a certain phase of the multi-phase interleaved converter in a unit switching period, that is, the output power of this phase.

[0030] Each phase of the multi-phase interleaved flyback converter operates in the discontinuous conduction mode (DCM, Discontinuous Conduction Mode). In each switching period, the primary current Ip starts to increase linearly from zero at the starting moment. According to the principle of energy conservation, the energy provided by a certain phase of the converter to the multi-phase interleaved flyback converter system within a unit switching period is 1 / 2*Lm(Ip max ) 2 . Since each phase of the converter uses the same clock frequency, only the phases are different. Therefore, as long as it is ensured that each phase provides the same energy to the multi-phase interleaved flyback converter system within a unit switching period, the output powers of each phase of the converter can be accurately ensured to be equal. Therefore, ensuring that the output results of the LII circuits of each phase of the converter are equal is the key to realizing the output power balance of each phase of the converter.

[0031] Such as Figure 1, the same output signal COM of the voltage error amplifier U4 is adopted for each phase of the converter as the reference voltage of the comparator U3 of this phase, so as to ensure that the output results of the LII circuit are the same when the driving and turning-off signals of each phase of the converter are generated. The driving and turning-off signals and the clock signal of the corresponding phase jointly generate PWM driving pulses to control the normal operation of this phase. Also, since the same VIN sampling coefficient K1 and primary current sampling coefficient K2 are adopted for each phase of the converter, it can accurately ensure that in a unit switching period, each phase of the converter outputs the same energy 1 / 2*Lm(Ip max ) 2 , thus ensuring that the output powers of each phase of the converter are the same, and achieving the purpose of accurate power balance control for each phase of the multi-phase interleaved flyback converter. In addition, due to the adoption of the hardware multiplication circuit U2 with small delay, and combined with the fast comparator U3, the per-cycle control of the output power of each phase of the converter can be realized, quickly responding to the dynamic changes of the load, and achieving fast and accurate power balance control for the output power of each phase of the converter.

[0032] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0033] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An automatic power equalization control circuit for a multi-phase interleaved flyback converter, characterized in that It includes a VIN sampling circuit, a primary current sampling circuit ISEN, an integrating circuit U1, a multiplying circuit U2, a comparator U3, an error amplifier U4, a phase controller, a gate drive circuit, a power MOS transistor Q1, a transformer T, a diode D1, an output capacitor Co, and a load module. The VIN sampling circuit is connected to each phase of the integrating circuit U1; the phase controller is connected to each phase of the gate drive circuit; the output terminal of the error amplifier U4 is connected to the non-inverting input terminal of each phase of the comparator U3; the inverting input terminal of the error amplifier U4 circuit is connected to the positive electrode of the output capacitor Co; the non-inverting input terminal of the error amplifier U4 is connected to the reference voltage Vref; the output capacitor Co is connected in parallel with the load module, the positive electrode of the output capacitor Co is connected to the cathode of each phase of the diode D1, and the negative electrode of the output capacitor Co is connected to the output ground; the primary current sampling circuit ISEN is connected to the input terminal of the multiplying circuit U2; the integrating circuit U1 is connected to the other input terminal of the multiplying circuit U2; the output terminal of the multiplying circuit U2 is connected to the inverting input terminal of the comparator U3, and the output terminal of the comparator U3 is connected to the gate drive circuit; the output terminal of the gate drive circuit is connected to the gate of the power MOS transistor Q1; the source of the power MOS transistor Q1 is connected to the ground through the primary current sampling circuit ISEN; the same-name end of the primary winding of the transformer T is connected to the input voltage VIN, and the other end is connected to the drain of the power MOS transistor Q1; the same-name end of the secondary winding of the transformer T is connected to the output ground, and the other end is connected to the anode of the diode D1.

2. The automatic power equalization control circuit of a multi-phase interleaved flyback converter according to claim 1, wherein The integrating circuit U1 and the multiplying circuit U2 form an LII circuit.

3. The automatic power equalization control circuit of a multi-phase interleaved flyback converter according to claim 1, wherein, The phase controller also generates clock signals required for each phase and is connected to each phase of the gate drive circuit.

4. The automatic power equalization control circuit of a multi-phase interleaved flyback converter according to claim 1, wherein The integrating circuit U1 performs an integrating operation on the signal of the VIN sampling circuit within the time interval [t, t+Ton], where t is the turn-on moment of the power MOS transistor Q1 of a certain phase of the converter, and Ton is the turn-on duration of the power MOS transistor Q1. The output signal of the integrating circuit U1 and the primary-side current sampling signal ISEN are operated on by the multiplication circuit U2 to generate a rising signal K1K2LmIp 2 , that is, the LII circuit finally generates a parabolic rising signal K1K2LmIp 2 , and then it is compared with the output signal of the error amplifier U4 to generate a drive-off signal. The phase controller generates clock signals for each phase to ensure that the converter has the same operating frequency and a fixed and reasonable phase offset interval among each phase. The corresponding clock signals of each phase of the converter and the above drive-off signal act together on the gate drive circuit to generate PWM drive pulses to control the on and off of the power MOS transistor Q1 for power conversion.

5. The automatic power balancing control circuit of a multi-phase interleaved flyback converter according to claim 1, characterized in that, The signals sampled by the VIN sampling circuit include the input voltage sampling linear coefficient K1 and the converter input DC voltage VIN.

6. The automatic power equalization control circuit of a multi-phase interleaved flyback converter according to claim 1, characterized in that The signals sampled by the primary current sampling circuit ISEN include the primary current sampling linear coefficient K2 and the primary current Ip.

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