Oscillation circuit, oscillator, and control method for an oscillation circuit

Abstract

Oscillation circuit, oscillator, and control method of oscillation circuit. Even if there is a deviation in the characteristics of a connected vibrator, the possibility of abnormal oscillation can be reduced. An oscillation circuit has an oscillation circuit connected to a vibrator, and a control circuit that controls the oscillation circuit, the oscillation circuit having a normal operation mode in which the oscillation circuit oscillates in a state in which a negative resistance value becomes a first value, and a startup mode in which a state in which the oscillation circuit stops oscillating is shifted to the normal operation mode, the control circuit controlling in the startup mode so that the negative resistance value increases from a second value smaller than the first value.

Description

TECHNICAL FIELD

[0001] The present application relates to an oscillation circuit, an oscillator, and a control method of an oscillation circuit. BACKGROUND

[0002] Patent Document 1 describes an oscillation circuit in which a control circuit that increases a load capacitance of an oscillation circuit only at the time of oscillation startup is provided, and a growth coefficient of a main vibration at the time of oscillation startup is larger than a growth coefficient of a parasitic vibration.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 62-109511

[0004] However, in the case of a structure in which the load capacitance is made different at the time of startup and at other times, as in the oscillation circuit described in Patent Document 1, due to a deviation in the characteristics of the vibrator, it can not be possible to ensure normal oscillation. That is, in the case of using such a vibrator, it can be possible to perform abnormal oscillation in which, if it is the load capacitance at the time of oscillation startup, both the main vibration and a side vibration such as a parasitic vibration do not resonate, and if it is the load capacitance at the time of normal operation, both the main vibration and the side vibration resonate. SUMMARY

[0005] One embodiment of the oscillation circuit of the present application has an oscillation circuit that has an oscillation circuit connected to a vibrator, and a control circuit that controls the oscillation circuit, the oscillation circuit having a normal operation mode in which the oscillation circuit oscillates in a state in which a negative resistance value is a first value, and a startup mode in which a state in which the oscillation circuit stops oscillating is shifted to the normal operation mode, the control circuit controlling in the startup mode in such a way that the negative resistance value increases from a second value that is smaller than the first value.

[0006] One embodiment of the oscillator of the present application has one embodiment of the oscillation circuit and the vibrator.

[0007] In one embodiment of the control method of the oscillation circuit of the present application, the oscillation circuit has an oscillation circuit connected to a vibrator, the oscillation circuit having a normal operation mode in which the oscillation circuit oscillates in a state in which a negative resistance value is a first value, and a startup mode in which a state in which the oscillation circuit stops oscillating is shifted to the normal operation mode, wherein, in the startup mode, the negative resistance value is controlled in such a way that it increases from a second value that is smaller than the first value. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a perspective view of the oscillator of the present embodiment.

[0009] Figure 2 is a cross-sectional view of the oscillator of the present embodiment.

[0010] Figure 3 is a bottom view of the oscillator of the present embodiment.

[0011] Figure 4 is a functional block diagram of the oscillator of the first embodiment.

[0012] Figure 5 is a diagram showing a structure example of the oscillation circuit.

[0013] Figure 6 is a diagram showing a structure example of the variable current source.

[0014] Figure 7 is a diagram showing an example of the current adjustment data.

[0015] Figure 8 is a diagram showing an example of the capacitance adjustment data.

[0016] Figure 9 is a diagram showing another structure example of the variable capacitance circuit.

[0017] Figure 10 is a waveform diagram showing an example of the sequence in the first embodiment.

[0018] Figure 11 is a waveform diagram showing another example of the sequence in the first embodiment.

[0019] Figure 12 is a flowchart showing an example of the steps of the control method of the oscillation circuit.

[0020] Figure 13 is a flowchart showing an example of the steps of the start-up step in the first embodiment.

[0021] Figure 14 is a flowchart showing another example of the steps of the start-up step in the first embodiment.

[0022] Figure 15 is a waveform diagram showing an example of the sequence in the second embodiment.

[0023] Figure 16 is a flowchart showing an example of the steps of the start-up step in the second embodiment.

[0024] Figure 17 is a diagram showing a structure example of the voltage control circuit in the third embodiment.

[0025] Figure 18 is a waveform diagram showing an example of the sequence in the third embodiment.

[0026] Figure 19 is a flowchart showing an example of the steps of the start-up step in the third embodiment.

[0027] Figure 20 is a waveform chart showing an example of the sequence in the fourth embodiment.

[0028] Figure 21 is a flowchart showing an example of the steps of the start-up step in the fourth embodiment.

[0029] Figure 22 is a functional block diagram of the oscillator of the fifth embodiment.

[0030] Figure 23 is a diagram showing an example of the structure of the oscillation detection circuit.

[0031] Figure 24 is a waveform chart showing an example of the sequence in the fifth embodiment.

[0032] Figure 25 is a flowchart showing an example of the steps of the start-up step in the fifth embodiment.

[0033] Figure 26 is a diagram showing an example of the structure of the control circuit in the sixth embodiment.

[0034] Figure 27 is a diagram showing an example of the structure of the delay circuit.

[0035] Figure 28 is a diagram showing an example of the waveforms of the bits of the current adjustment data.

[0036] Figure 29 is a diagram showing an example of the structure of the variable current source in the seventh embodiment.

[0037] Figure 30 is a diagram showing an example of the current adjustment data in the seventh embodiment.

[0038] Explanation of Reference Signs

[0039] 1: oscillator; 2: oscillation circuit; 3: vibrator; 3a: excitation electrode; 3b: excitation electrode; 4: package; 5: lid; 6: external terminal; 7: housing chamber; 10: oscillation circuit; 11: amplification element; 12: variable current source; 13: resistor; 14: variable capacitance circuit; 15: variable capacitance circuit; 16: variable capacitance circuit; 17: variable capacitance circuit; 20: power supply circuit; 30: power-on reset circuit; 40: control circuit; 41: voltage control circuit; 42: logic circuit; 50: reference voltage generation circuit; 60: output circuit; 70: storage circuit; 71: nonvolatile memory; 72: register; 80: oscillation detection circuit; 100, 101, 102, 103, 104, 110, 111, 112, 113, 114: CMOS inverter; 120, 121, 122, 123, 124: current source; 125, 126, 127, 128, 129: switching element; 130: current source; 131, 132: P-channel MOS transistor; 133, 134: P-channel MOS transistor; 135: current source; 136-0 to 136-31: current source; 137-0 to 137-31: switching element; 140, 141, 142, 143, 144: capacitance element; 145, 146, 147, 148, 149: switching element; 150, 151, 152, 153, 154: capacitance element; 155, 156, 157, 158, 159: switching element; 160: variable capacitance element; 161-1 to 161-n: variable capacitance element; 162-1 to 162-n: capacitance element; 163-1 to 163-n: capacitance element; 170: variable capacitance element; 171-1 to 171-n: variable capacitance element; 172-1 to 172-n: capacitance element; 173-1 to 173-n: capacitance element; 200: control voltage generation circuit; 210: filter circuit; 211: resistor; 212: capacitance element; 220: switching circuit; 230: filter circuit; 231: resistor; 232: capacitance element; 240: switching circuit; 250: resistor; 260: resistor; 300: current source; 301: capacitance element; 302, 303, 304: variable resistor; 305, 306, 307, 308, 309: N-channel MOS transistor; 310: comparator; 311, 312: CMOS inverter; 313: N-channel MOS transistor; 314, 315: capacitance element; 401, 402, 403, 404: CMOS inverter; 411, 421, 422, 431, 432, 433, 441, 442, 443, 444: delay circuit. DETAILED DESCRIPTION

[0040] Next, a preferred embodiment of the present application will be described in detail using the accompanying drawings. Note that the following description of the embodiment is not intended to limit the scope of the application unnecessarily. Furthermore, not all of the structures described below are necessarily essential structural elements of the present application.

[0041] 1. First Embodiment

[0042] 1-1. Structure of Oscillator

[0043] Figure 1 、 Figure 2 and Figure 3 is a diagram showing an example of the configuration of the oscillator 1 of the present embodiment. Figure 1 is a perspective view of the oscillator 1. Figure 2 is a cross-sectional view of the oscillator 1 taken along the line A-A of Figure 1 . Figure 3 is a bottom view of the oscillator 1.

[0044] As shown in Figure 1 , Figure 2 and Figure 3 , the oscillator 1 includes an oscillation circuit 2, an oscillator 3, a package 4, a lid 5, and a plurality of external terminals 6. In the present embodiment, the oscillator 3 is a quartz oscillator using quartz as a substrate material, such as an AT-cut quartz oscillator or a tuning fork type quartz oscillator. The oscillator 3 can also be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) oscillator. Note that SAW is an abbreviation of Surface Acoustic Wave. Furthermore, MEMS is an abbreviation of Micro Electro Mechanical Systems. As the substrate material of the oscillator 3, in addition to quartz, a piezoelectric single crystal such as lithium tantalate or lithium niobate, a piezoelectric ceramic such as lead zirconate titanate, or a silicon semiconductor material, or the like can be used. As the excitation means of the oscillator 3, a means based on the piezoelectric effect can be used, or electrostatic driving based on the Coulomb force can be used. Furthermore, in the present embodiment, the oscillation circuit 2 is realized by a single-chip integrated circuit. However, at least a part of the oscillation circuit 2 can also be constituted by discrete components.

[0045] The package 4 houses the oscillation circuit 2 and the oscillator 3 in the same space. Specifically, a recess is provided in the package 4, and the recess is covered with the lid 5, thereby becoming a housing chamber 7. A wiring, not shown, for connecting two terminals of the oscillation circuit 2, specifically, the external terminals 6 described later, is provided on the surface of the package 4 or the recess. Figure 4The XI terminal and the XO terminal are electrically connected to the two excitation electrodes 3a, 3b of the vibrator 3, respectively. Further, inside the package 4 or on the surface of the recess, wiring not shown for electrically connecting the terminals of the oscillation circuit 2 to the external terminals 6 provided on the bottom surface of the package 4 is provided. Note that the package 4 is not limited to the structure in which the oscillation circuit 2 and the vibrator 3 are housed in the same space. For example, it can be a so-called H-shaped package in which the oscillation circuit 2 is mounted on one face of the substrate of the package and the vibrator 3 is mounted on the other face.

[0046] The vibrator 3 has the excitation electrodes 3a, 3b of metal on the front and back surfaces thereof to oscillate at a desired frequency corresponding to the shape or mass of the vibrator 3 including the excitation electrodes 3a, 3b.

[0047] As shown in FIG. 1, the oscillator 1 of the present embodiment is provided with four external terminals 6, namely, a power supply terminal, namely, an external terminal VDD1, a ground terminal, namely, an external terminal VSS1, a terminal to which a signal for controlling the frequency of the oscillation circuit 2 is input, namely, an external terminal VC1, and an output terminal, namely, an external terminal OUT1, on the bottom surface, specifically, the back surface of the package 4. The external terminal VDD1 is supplied with a power supply voltage, and the external terminal VSS1 is grounded. Figure 3

[0048] Figure 4 is a functional block diagram of the oscillator 1 of the first embodiment. As shown in FIG. 1, the oscillator 1 of the present embodiment includes an oscillation circuit 2 and a vibrator 3. The oscillation circuit 2 has a VDD terminal, a VSS terminal, an OUT terminal, a VC terminal, an XI terminal, and an XO terminal as external connection terminals. The VDD terminal, the VSS terminal, the OUT terminal, and the VC terminal are electrically connected to the four external terminals 6, namely, the external terminal VDD1, the external terminal VSS1, the external terminal OUT1, and the external terminal VC1 of the oscillator 1 shown in FIG. 1, respectively. The XI terminal is electrically connected to one end, namely, the excitation electrode 3a of the vibrator 3, and the XO terminal is electrically connected to the other end, namely, the excitation electrode 3b of the vibrator 3. Figure 4 Figure 3

[0049] In the present embodiment, the oscillation circuit 2 includes an oscillation circuit 10, a power supply circuit 20, a power-on reset circuit 30, a control circuit 40, a reference voltage generation circuit 50, an output circuit 60, and a storage circuit 70. Note that the oscillation circuit 2 can also be configured to omit or change a part of these elements or add other elements.

[0050] The power supply circuit 20 generates various voltages including a power supply voltage Vdd of the logic circuit 42 from an external power supply voltage input from the external terminal VDD1 and supplied via the VDD terminal, and supplies the generated various voltages to each circuit. Further, a ground voltage Vss is supplied to each circuit via the VSS terminal. ​​​

[0051] When the oscillator 1 is powered on, the power supply voltage Vdd output from the power supply circuit 20 rises from 0 V to a prescribed voltage value. The power-on reset circuit 30 generates a power-on reset signal POR which becomes a high level for a certain time when the power supply voltage Vdd reaches a prescribed threshold voltage. By the power-on reset signal POR, the logic circuit 42 is initialized to a desired state. When the power-on reset signal POR changes from a high level to a low level, the logic circuit 42 starts to operate.

[0052] The oscillation circuit 10 is a circuit which is connected to the vibrator 3 via the XI terminal and the XO terminal, amplifies a signal output from the vibrator 3 by an amplifying element and supplies it to the vibrator 3, and makes the vibrator 3 oscillate. The amplifying element can be a bipolar transistor, for example, or a MOS transistor, or a CMOS inverter. MOS is an abbreviation for Metal Oxide Semiconductor. Further, CMOS is an abbreviation for Complementary Metal Oxide Semiconductor. The oscillation circuit 10 is adjusted in accordance with various setting signals supplied from the logic circuit 42 so that the oscillation frequency becomes a target frequency.

[0053] The output circuit 60 buffers and outputs the oscillation signal CK output from the oscillation circuit 10. The oscillation signal CKO output from the output circuit 60 is output to the outside of the oscillator 1 via the OUT terminal and the external terminal OUT1. In addition, the output circuit 60 can also output a differential oscillation signal. That is, the output circuit 60 can also output an oscillation signal XCKO in which the polarity of the oscillation signal CKO is inverted, together with the oscillation signal CKO. In this case, the oscillation circuit 2 also has an XOUT terminal for outputting the oscillation signal XCKO, and the oscillator 1 also has an external terminal XOUT1 for outputting the oscillation signal XCKO.

[0054] The control circuit 40 controls the oscillation circuit 10. In the present embodiment, the control circuit 40 includes the voltage control circuit 41 and the logic circuit 42.

[0055] The voltage control circuit 41 generates a control voltage for changing the oscillation frequency of the oscillation circuit 10 in accordance with the voltage level of the frequency control signal supplied from the external terminal VC1 via the VC terminal, and supplies it to the oscillation circuit 10. That is, the frequency of the oscillation signal CKO output from the external terminal OUT1 is changed in accordance with the voltage level of the frequency control signal input from the external terminal VC1.

[0056] The logic circuit 42 outputs an oscillation enable signal en osc to the oscillation circuit 10, and controls the operation of the oscillation circuit 10. Specifically, the logic circuit 42 causes the oscillation circuit 10 to oscillate by making the oscillation enable signal en osc high, and causes the oscillation circuit 10 to stop oscillating by making the oscillation enable signal en osc low. In addition, the logic circuit 42 outputs various setting signals to the oscillation circuit 10, and controls the oscillation frequency of the oscillation circuit 10. Further, the logic circuit 42 outputs an output enable signal en out to the output circuit 60, and controls the operation of the output circuit 60. Specifically, the logic circuit 42 controls the output circuit 60 to output the oscillation signal CKO by making the output enable signal en out high, and controls the output circuit 60 to stop outputting the oscillation signal CKO by making the output enable signal en out low.

[0057] The reference voltage generating circuit 50 generates various reference voltages from the voltage output from the power supply circuit 20, and outputs them to the oscillation circuit 10.

[0058] The storage circuit 70 is a circuit that stores various information, and has a nonvolatile memory 71 and a register 72. The nonvolatile memory 71 can be, for example, a FAMOS, a MONOS type memory, an EEPROM, or the like. In addition, FAMOS is an abbreviation for Floating gate Avalanche injection Metal Oxide Semiconductor. Further, MONOS is an abbreviation for Metal Oxide Nitride Oxide Silicon. Furthermore, EEPROM is an abbreviation for Electrically Erasable Programmable Read-Only Memory. In the manufacturing step of the oscillator 1, various information is stored in the nonvolatile memory 71. Then, when the oscillator 1 is powered on, the various information stored in the nonvolatile memory 71 is transferred to the register 72, and the various information stored in the register 72 is appropriately supplied to each circuit. For example, information for adjusting the oscillation frequency, which is transferred from the nonvolatile memory 71 to the register 72, is supplied to the oscillation circuit 10 as various setting signals via the logic circuit 42. The information for adjusting the oscillation frequency is current adjustment data or capacitance adjustment data, which will be described later.

[0059] 1-2. Structure of the oscillation circuit

[0060] Figure 5 is a diagram showing an example of the structure of the oscillation circuit 10. In Figure 5In the example, the oscillation circuit 10 includes an amplifying element 11, a variable current source 12, a resistor 13, a variable capacitor circuit 14, a variable capacitor circuit 15, a variable capacitor circuit 16, and a variable capacitor circuit 17. Furthermore, the oscillation circuit 10 includes ten CMOS inverters 100, 101, 102, 103, 104, 110, 111, 112, 113, and 114.

[0061] Amplifying element 11 is an NPN bipolar transistor, with its base terminal connected to the XI terminal, its collector terminal connected to the XO terminal, and its emitter terminal grounded. Furthermore, a resistor 13 is connected between the base and collector terminals of amplifying element 11. Moreover, an oscillation stage current Iosc is supplied to the collector terminal of amplifying element 11 from a variable current source 12, and the signal at the collector terminal is output as the oscillation signal CK. Alternatively, a MOS transistor or a CMOS inverter can be used for amplifying element 11.

[0062] The variable current source 12 generates an oscillation stage current Iosc corresponding to the magnitude of the 5-bit current adjustment data trimI[4:0] supplied from the logic circuit 42 as a setting signal, based on the voltage Vreg generated by the reference voltage generation circuit 50. Then, the variable current source 12 supplies the oscillation stage current Iosc to the amplification element 11. In addition, the number of bits of the current adjustment data trimI is not limited to 5.

[0063] Figure 6 This is a diagram showing an example of the structure of the variable current source 12. Figure 6 In the example, the variable current source 12 includes six current sources 120, 121, 122, 123, 124, and 130, five switching elements 125, 126, 127, 128, and 129, and two P-channel MOS transistors 131 and 132.

[0064] The gate and drain of P-channel MOS transistor 131 are connected, and the source is supplied with a voltage Vreg. The gate of P-channel MOS transistor 132 is connected to the gate of P-channel MOS transistor 131, and the source is supplied with a voltage Vreg, while the drain is connected to... Figure 5 The collector of the amplifying element 11 is connected.

[0065] One end of the current source 130 is connected to the drain of the P-channel MOS transistor 131, and the other end is grounded, through which a fixed bias current I flows. bOne end of the current source 120 is connected to the drain of the P-channel MOS transistor 131 via a switching element 125, and the other end is grounded. When the switching element 125 is in an on state, a fixed current I0flows. One end of the current source 121 is connected to the drain of the P-channel MOS transistor 131 via a switching element 126, and the other end is grounded. When the switching element 126 is in an on state, a current of a size twice that of I0flows. One end of the current source 122 is connected to the drain of the P-channel MOS transistor 131 via a switching element 127, and the other end is grounded. When the switching element 127 is in an on state, a current of a size four times that of I0flows. One end of the current source 123 is connected to the drain of the P-channel MOS transistor 131 via a switching element 128, and the other end is grounded. When the switching element 128 is in an on state, a current of a size eight times that of I0flows. One end of the current source 124 is connected to the drain of the P-channel MOS transistor 131 via a switching element 129, and the other end is grounded. When the switching element 129 is in an on state, a current of a size sixteen times that of I0flows. The current sources 120, 121, 122, 123, 124, and 130 can be constituted by N-channel MOS transistors of depletion type, or can be constituted by current mirror circuits, for example.

[0066] The control terminal of the switching element 125 is input with data triml[0] of bit 0 of the current adjustment data triml[4:0], and is in an on state when data triml[0] is at a high level, and is in an off state when data triml[0] is at a low level. The control terminal of the switching element 126 is input with data triml[l] of bit 1 of the current adjustment data triml[4:0], and is in an on state when data triml[l] is at a high level, and is in an off state when data triml[l] is at a low level. The control terminal of the switching element 127 is input with data triml[2] of bit 2 of the current adjustment data triml[4:0], and is in an on state when data triml[2] is at a high level, and is in an off state when data triml[2] is at a low level. The control terminal of the switching element 128 is input with data triml[3] of bit 3 of the current adjustment data triml[4:0], and is in an on state when data triml[3] is at a high level, and is in an off state when data triml[3] is at a low level. The control terminal of the switching element 129 is input with data triml[4] of bit 4 of the current adjustment data triml[4:0], and is in an on state when data triml[4] is at a high level, and is in an off state when data triml[4] is at a low level. The switching elements 125, 126, 127, 128, and 129 can be N-channel MOS transistors, or can be transmission gates, for example.

[0067] Figure 7is a graph showing a relationship between a value of the current adjustment data triml[4:0] expressed by a decimal number and a value of each bit of the current adjustment data triml[4:0] expressed by a binary number. 0 of each bit corresponds to a low level, and 1 of each bit corresponds to a high level. For example, if the current adjustment data triml[4:0] is 1, bit 0 is 1, and bits 1, 2, 3, and 4 are 0. Therefore, the switching element 125 is turned on, and the current lo flows through the current source 120. Further, for example, if the current adjustment data triml[4:0] is 2, bit 1 is 1, and bits 0, 2, 3, and 4 are 0. Therefore, the switching element 126 is turned on, and a current of 2 times the size of the current lo flows through the current source 121.

[0068] The current flowing between the source and the drain of the P-channel MOS transistor 131 is the bias current I b The current obtained by adding the currents flowing through the current sources 120, 121, 122, 123, and 124, respectively. For example, when the current adjustment data triml[4:0] is 1, the current lo flows through the current source 120, and the currents flowing through the current sources 121, 122, 123, and 124, respectively, are zero. Therefore, the current flowing between the source and the drain of the P-channel MOS transistor 131 is the bias current I b The current obtained by adding the currents flowing through the current sources 120, 121, 122, 123, and 124, respectively. For example, when the current adjustment data triml[4:0] is 1, the current lo flows through the current source 120, and the currents flowing through the current sources 121, 122, 123, and 124, respectively, are zero. Therefore, the current flowing between the source and the drain of the P-channel MOS transistor 131 is the bias current I b The current obtained by adding the currents flowing through the current sources 120, 121, 122, 123, and 124, respectively. For example, when the current adjustment data triml[4:0] is 1, the current lo flows through the current source 120, and the currents flowing through the current sources 121, 122, 123, and 124, respectively, are zero. Therefore, the current flowing between the source and the drain of the P-channel MOS transistor 131 is the bias current I

[0069] In the manufacturing step of the oscillator 1, the value of the current adjustment data triml[4:0] for making the oscillation stage current Iosc a desired value corresponding to the resonance frequency of the resonator 3 is written in the nonvolatile memory 71.

[0070] Returning to Figure 5The CMOS inverter 100 outputs data trimCNl[0] which is the data after logical inversion of bit 0 of the 5-bit capacitive adjustment data trimCl[4:0] supplied from the logic circuit 42 as a set signal. The CMOS inverter 101 outputs data trimCNl[l] which is the data after logical inversion of bit 1 of the capacitive adjustment data trimCl[4:0]. The CMOS inverter 102 outputs data trimCNl[2] which is the data after logical inversion of bit 2 of the capacitive adjustment data trimCl[4:0]. The CMOS inverter 103 outputs data trimCNl[3] which is the data after logical inversion of bit 3 of the capacitive adjustment data trimCl[4:0]. The CMOS inverter 104 outputs data trimCNl[4] which is the data after logical inversion of bit 4 of the capacitive adjustment data trimCl[4:0].

[0071] The variable capacitive circuit 14 is a capacitive circuit having a capacitive value Cl corresponding to the size of the capacitive adjustment data trimCNl[4:0] after logical inversion of each bit of the capacitive adjustment data trimCl[4:0] by the CMOS inverters 100, 101, 102, 103, 104. The variable capacitive circuit 14 includes five capacitive elements 140, 141, 142, 143, 144 and five switching elements 145, 146, 147, 148, 149.

[0072] One end of the capacitive element 140 is connected to the XI terminal and the other end is grounded via the switching element 145, and the capacitive value thereof is CO. One end of the capacitive element 141 is connected to the XI terminal and the other end is grounded via the switching element 146, and the capacitive value thereof is 2 times CO. One end of the capacitive element 142 is connected to the XI terminal and the other end is grounded via the switching element 147, and the capacitive value thereof is 4 times CO. One end of the capacitive element 143 is connected to the XI terminal and the other end is grounded via the switching element 148, and the capacitive value thereof is 8 times CO. One end of the capacitive element 144 is connected to the XI terminal and the other end is grounded via the switching element 149, and the capacitive value thereof is 16 times CO. For example, the capacitive elements 140, 141, 142, 143, 144 can be MIM (Metal Insulator Metal) type capacitive elements using metal for both electrodes, or PIP (Poly Insulator Poly) type capacitive elements using polysilicon for both electrodes. MIM is an abbreviation of Metal Insulator Metal. Further, PIP is an abbreviation of Poly Insulator Poly.

[0073] The control terminal of the switching element 145 is input with data trimCNl[0] of bit 0 of the capacitance adjustment data trimCNl[4:0], the switching element 145 is turned on when the data trimCNl[0] is high, and the switching element 145 becomes non-conductive when the data trimCNl[0] is low. The control terminal of the switching element 146 is input with data trimCNl[l] of bit 1 of the capacitance adjustment data trimCNl[4:0], the switching element 146 is turned on when the data trimCNl[l] is high, and the switching element 146 becomes non-conductive when the data trimCNl[l] is low. The control terminal of the switching element 147 is input with data trimCNl[2] of bit 2 of the capacitance adjustment data trimCNl[4:0], the switching element 147 is turned on when the data trimCNl[2] is high, and the switching element 147 becomes non-conductive when the data trimCNl[2] is low. The control terminal of the switching element 148 is input with data trimCNl[3] of bit 3 of the capacitance adjustment data trimCNl[4:0], the switching element 148 is turned on when the data trimCNl[3] is high, and the switching element 148 becomes non-conductive when the data trimCNl[3] is low. The control terminal of the switching element 149 is input with data trimCNl[4] of bit 4 of the capacitance adjustment data trimCNl[4:0], the switching element 149 is turned on when the data trimCNl[4] is high, and the switching element 149 becomes non-conductive when the data trimCNl[4] is low. The switching elements 145, 146, 147, 148, 149 can be N-channel MOS transistors, for example, or can be transmission gates.

[0074] Figure 8 FIG. 6 is a diagram showing the relationship between the value of the capacitance adjustment data trimCl[4:0] expressed by a decimal number and the value of each bit of the capacitance adjustment data trimCNl[4:0] expressed by a binary number after the capacitance adjustment data trimCl[4:0] is logically inverted. 0 of each bit corresponds to low, and 1 of each bit corresponds to high. For example, if the capacitance adjustment data trimCl[4:0] is 1, bits 1, 2, 3, 4 of the capacitance adjustment data trimCNl[4:0] are 1, and bit 0 is 0. Therefore, the switching elements 146, 147, 148, 149 are turned on, and the other ends of the capacitance elements 141, 142, 143, 144 are grounded. Also, for example, if the capacitance adjustment data trimCl[4:0] is 2, bits 0, 2, 3, 4 of the capacitance adjustment data trimCNl[4:0] are 1, and bit 1 is 0. Therefore, the switching elements 145, 147, 148, 149 are turned on, and the other ends of the capacitance elements 140, 142, 143, 144 are grounded.

[0075] The capacitance value Cl of the variable capacitance circuit 14 becomes a value obtained by adding the capacitance values of the capacitance elements 140, 141, 142, 143, 144 whose other ends are grounded when the switching elements 145, 146, 147, 148, 149 are turned on, respectively. For example, when the capacitance adjustment data trimCl [4:0] is 1, the other ends of the capacitance elements 141, 142, 143, 144 are grounded, and the other end of the capacitance element 140 is not grounded, and thus the capacitance value Cl of the variable capacitance circuit 14 becomes 2C0+4C0+8C0+16C0=30C0. Further, for example, when the capacitance adjustment data trimCl [4:0] is 2, the other ends of the capacitance elements 140, 142, 143, 144 are grounded, and the other end of the capacitance element 141 is not grounded, and thus the capacitance value Cl of the variable capacitance circuit 14 becomes C0+4C0+8C0+16C0=29C0. In this way, the capacitance value Cl of the variable capacitance circuit 14 varies depending on the value of the capacitance adjustment data trimCl [4:0]. Specifically, the larger the value of the capacitance adjustment data trimCl [4:0], the smaller the capacitance value Cl of the variable capacitance circuit 14.

[0076] The CMOS inverter 110 outputs data trimCN2[0] obtained by logically inverting data trimC2[0] of bit 0 of the 5-bit capacitance adjustment data trimC2[4:0] supplied from the logic circuit 42 as a set signal. The CMOS inverter 111 outputs data trimCN2[1] obtained by logically inverting data trimC2[1] of bit 1 of the capacitance adjustment data trimC2[4:0]. The CMOS inverter 112 outputs data trimCN2[2] obtained by logically inverting data trimC2[2] of bit 2 of the capacitance adjustment data trimC2[4:0]. The CMOS inverter 113 outputs data trimCN2[3] obtained by logically inverting data trimC2[3] of bit 3 of the capacitance adjustment data trimC2[4:0]. The CMOS inverter 114 outputs data trimCN2[4] obtained by logically inverting data trimC2[4] of bit 4 of the capacitance adjustment data trimC2[4:0].

[0077] The variable capacitance circuit 15 is a capacitance circuit having a capacitance value C2 corresponding to the size of the capacitance adjustment data trimCN2[4:0] obtained by logically inverting each bit of the capacitance adjustment data trimC2[4:0] by the CMOS inverters 110, 111, 112, 113, 114. The variable capacitance circuit 15 includes five capacitance elements 150, 151, 152, 153, 154 and five switching elements 155, 156, 157, 158, 159.

[0078] One end of the capacitor element 150 is connected to the XO terminal, and the other end is grounded via the switching element 155, and the capacitance value thereof is C0. One end of the capacitor element 151 is connected to the XO terminal, and the other end is grounded via the switching element 156, and the capacitance value thereof is twice C0. One end of the capacitor element 152 is connected to the XO terminal, and the other end is grounded via the switching element 157, and the capacitance value thereof is four times C0. One end of the capacitor element 153 is connected to the XO terminal, and the other end is grounded via the switching element 158, and the capacitance value thereof is eight times C0. One end of the capacitor element 154 is connected to the XO terminal, and the other end is grounded via the switching element 159, and the capacitance value thereof is sixteen times C0. The capacitor elements 150, 151, 152, 153, 154 can be, for example, MIM (Metal Insulator Metal) type capacitor elements using metal for two electrodes, or PIP (Poly Insulator Poly) type capacitor elements using polysilicon for two electrodes. Furthermore, MIM is an abbreviation for Metal Insulator Metal, and PIP is an abbreviation for Poly Insulator Poly.

[0079] The control terminal of the switching element 155 is input with data trimCN2[0] of bit 0 of the capacitance adjustment data trimCN2[4:0], and the switching element 155 is turned on when data trimCN2[0] is at a high level, and the switching element 155 becomes non-conductive when data trimCN2[0] is at a low level. The control terminal of the switching element 156 is input with data trimCN2[l] of bit 1 of the capacitance adjustment data trimCN2[4:0], and the switching element 156 is turned on when data trimCN2[l] is at a high level, and the switching element 156 becomes non-conductive when data trimCN2[l] is at a low level. The control terminal of the switching element 157 is input with data trimCN2[2] of bit 2 of the capacitance adjustment data trimCN2[4:0], and the switching element 157 is turned on when data trimCN2[2] is at a high level, and the switching element 157 becomes non-conductive when data trimCN2[2] is at a low level. The control terminal of the switching element 158 is input with data trimCN2[3] of bit 3 of the capacitance adjustment data trimCN2[4:0], and the switching element 158 is turned on when data trimCN2[3] is at a high level, and the switching element 158 becomes non-conductive when data trimCN2[3] is at a low level. The control terminal of the switching element 159 is input with data trimCN2[4] of bit 4 of the capacitance adjustment data trimCN2[4:0], and the switching element 159 is turned on when data trimCN2[4] is at a high level, and the switching element 159 becomes non-conductive when data trimCN2[4] is at a low level. The switching elements 155, 156, 157, 158, 159 can be, for example, N-channel MOS transistors, or transmission gates.

[0080] The relationship between the value of the capacitance adjustment data trimC2[4:0] expressed by a decimal number and the value of each bit of the capacitance adjustment data trimCN2[4:0] expressed by a binary number after being logically inverted is the same as that shown in FIG. 8, and thus the illustration thereof is omitted. For example, if the capacitance adjustment data trimC2[4:0] is 1, then bits 1, 2, 3, and 4 of the capacitance adjustment data trimCN2[4:0] are 1, and bit 0 is 0. Therefore, the switching elements 156, 157, 158, and 159 are turned on, and the other ends of the capacitance elements 151, 152, 153, and 154 are grounded. Further, for example, if the capacitance adjustment data trimC2[4:0] is 2, then bits 0, 2, 3, and 4 of the capacitance adjustment data trimCN2[4:0] are 1, and bit 1 is 0. Therefore, the switching elements 155, 157, 158, and 159 are turned on, and the other ends of the capacitance elements 150, 152, 153, and 154 are grounded. Figure 8 The relationship between the value of the capacitance adjustment data trimC2[4:0] expressed by a decimal number and the value of each bit of the capacitance adjustment data trimCN2[4:0] expressed by a binary number after being logically inverted is the same as that shown in FIG. 8, and thus the illustration thereof is omitted. For example, if the capacitance adjustment data trimC2[4:0] is 1, then bits 1, 2, 3, and 4 of the capacitance adjustment data trimCN2[4:0] are 1, and bit 0 is 0. Therefore, the switching elements 156, 157, 158, and 159 are turned on, and the other ends of the capacitance elements 151, 152, 153, and 154 are grounded. Further, for example, if the capacitance adjustment data trimC2[4:0] is 2, then bits 0, 2, 3, and 4 of the capacitance adjustment data trimCN2[4:0] are 1, and bit 1 is 0. Therefore, the switching elements 155, 157, 158, and 159 are turned on, and the other ends of the capacitance elements 150, 152, 153, and 154 are grounded.

[0081] The capacitance value C2 of the variable capacitance circuit 15 becomes a value obtained by adding the capacitance values of the capacitance elements 150, 151, 152, 153, and 154 whose other ends are grounded due to the switching elements 155, 156, 157, 158, and 159 being turned on, respectively. For example, when the capacitance adjustment data trimC2[4:0] is 1, the other ends of the capacitance elements 151, 152, 153, and 154 are grounded, and the other end of the capacitance element 150 is not grounded, and thus the capacitance value C2 of the variable capacitance circuit 15 becomes 2C0+4C0+8C0+16C0=30C0. Further, for example, when the capacitance adjustment data trimC2[4:0] is 2, the other ends of the capacitance elements 150, 152, 153, and 154 are grounded, and the other end of the capacitance element 151 is not grounded, and thus the capacitance value C2 of the variable capacitance circuit 15 becomes C0+4C0+8C0+16C0=29C0. In this way, the capacitance value C2 of the variable capacitance circuit 15 changes depending on the value of the capacitance adjustment data trimC2[4:0]. Specifically, the larger the value of the capacitance adjustment data trimC2[4:0], the smaller the capacitance value C2 of the variable capacitance circuit 15.

[0082] Variable capacitor circuit 14 is connected to the excitation electrode 3a of oscillator 3 via terminal XI, and variable capacitor circuit 15 is connected to the excitation electrode 3b of oscillator 3 via terminal XO. That is, variable capacitor circuits 14 and 15 are connected to the node connected to oscillator 3, becoming part of the load capacitance of oscillator 3. In the manufacturing step of oscillator 1, the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] used to make the frequency of the oscillation signal CK output from oscillation circuit 10 the target frequency are written into non-volatile memory 71.

[0083] The variable capacitor circuit 16 is a capacitor circuit with a capacitance value C3 corresponding to the control voltage Vcnt1 supplied from the voltage control circuit 41. The variable capacitor circuit 16 includes a variable capacitor element 160. For example, the variable capacitor element 160 is a varactor diode with its source and drain connected to an NMOS transistor, the gate of which is connected to the XI terminal, the back gate supplied with a ground voltage Vss, and the source and drain supplied with the control voltage Vcnt1. The larger the control voltage Vcnt1, the smaller the capacitance value C3 of the variable capacitor circuit 16.

[0084] The variable capacitor circuit 17 is a capacitor circuit with a capacitance value C4 corresponding to the control voltage Vcnt2 supplied from the voltage control circuit 41. The variable capacitor circuit 17 includes a variable capacitor element 170. For example, the variable capacitor element 170 is a varactor diode with its source and drain connected to an NMOS transistor. The gate of the NMOS transistor is connected to the XO terminal, the back gate is supplied with a ground voltage Vss, and the source and drain are supplied with the control voltage Vcnt2. The larger the control voltage Vcnt2, the smaller the capacitance value C4 of the variable capacitor circuit 17.

[0085] Figure 9 This is a diagram showing another structural example of variable capacitor circuits 16 and 17. Figure 9 In the example, the variable capacitor circuit 16 includes n variable capacitor elements 161-1 to 161-n, n capacitor elements 162-1 to 162-n, and n capacitor elements 163-1 to 163-n. n is an integer greater than or equal to 2. For each integer i greater than or equal to 1 and less than n, the variable capacitor element 161-i is a varactor diode connected to the source and drain of an NMOS transistor. The source and drain of the NMOS transistor are connected to the XI terminal via capacitor element 163-i. The back gate is supplied with a ground voltage Vss, and the gate is grounded via capacitor element 162-i. Furthermore, the gate of this NMOS transistor is supplied with a reference voltage Vref1-i generated by the reference voltage generation circuit 50, and the source and drain are supplied with a control voltage Vcnt1. The larger the control voltage Vcnt1, the smaller the capacitance value C3 of the variable capacitor circuit 16.

[0086] Further, the variable capacitance circuit 17 includes n variable capacitance elements 171-1 to 171-n, n capacitance elements 172-1 to 172-n, and n capacitance elements 173-1 to 173-n. n is an integer of 2 or more. For each integer i of 1 or more and n or less, the variable capacitance element 171-i is a varactor diode in which the source and the drain of an NMOS transistor are connected, the source and the drain of the NMOS transistor are connected to the XI terminal via the capacitance element 173-i, the back gate is supplied with the ground voltage Vss, and the gate is grounded via the capacitance element 172-i. Further, the gate of the NMOS transistor is supplied with the reference voltage Vref2-i generated by the reference voltage generation circuit 50, and the source and the drain are supplied with the control voltage Vcnt2. The greater the control voltage Vcnt2, the smaller the capacitance value C4 of the variable capacitance circuit 17.

[0087] In Figure 5 , In any one of the drawings of Figure 9 , the variable capacitance circuit 16 is connected to the exciting electrode 3a of the vibrator 3 via the XI terminal, and the variable capacitance circuit 17 is connected to the exciting electrode 3b of the vibrator 3 via the XO terminal. That is, the variable capacitance circuits 16, 17 are connected to the node to which the vibrator 3 is connected, and become part of the load capacitance of the vibrator 3. The capacitance values C3, C4 of the variable capacitance circuits 16, 17 vary according to the control voltages Vcnt1, Vcnt2, respectively, and the control voltages Vcnt1, Vcnt2 vary according to the voltage level of the frequency control signal input from the external terminal VC1 via the VC terminal. Therefore, by the frequency control signal input from the external terminal VC1, it is possible to vary the oscillation frequency of the oscillation circuit 10. In this way, in the present embodiment, the voltage control circuit 41 generates the control voltages Vcnt1, Vcnt2 corresponding to the voltage level of the frequency control signal input from the external terminal VC1, but the voltage control circuit 41 can also be a temperature compensation circuit, and the control voltages Vcnt1, Vcnt2 are temperature compensation voltages.

[0088] Further, in Figure 5 , the illustration of a circuit for stopping oscillation when the oscillation enable signal en_osc is at the low level is omitted, but the circuit can be, for example, a switching circuit that cuts off the supply of the oscillation stage current Iosc to the amplification element 11 when the oscillation enable signal en_osc is at the low level.

[0089] 1-3. Start-up sequence

[0090] In the present embodiment, the oscillation circuit 2 has a plurality of operation modes including a normal operation mode and a startup mode. The normal operation mode is an operation mode in which the oscillation circuit 10 oscillates in a state in which the absolute value of the negative resistance, i.e., the negative resistance value |nR|, becomes a first value |nR1| that is set in advance. Further, the startup mode is an operation mode from a state in which the oscillation of the oscillation circuit 10 is stopped to the normal operation mode. The startup mode is, for example, an operation mode from when the power supply to the oscillator 1 is turned on to the normal operation mode. Further, in a case where the oscillation circuit 2 has a standby mode in which the oscillation of the oscillation circuit 10 is stopped in a state in which the power supply to the oscillator 1 is turned on as an operation mode, an operation mode from the standby mode to the normal operation mode is also the startup mode.

[0091] In the present embodiment, the vibrator 3 is a quartz vibrator, and can resonate in a primary vibration or a secondary vibration. When the polarizations of the X-axis, Y-axis, and Z-axis of the vibration are illustrated, the Y-axis and Z-axis each become a cosine wave, and when the number of wave crests of each is set to p, q, and r, respectively, the vibration mode is expressed as (p.q.r). For example, in the case where the vibrator 3 is an AT-cut quartz vibrator, the primary vibration is a thickness primary vibration having a vibration mode of (1.0.0). This thickness primary vibration is a pure shear vibration of only the X-axis direction, and has a fixed polarization in the Z-axis direction. Further, for example, the secondary vibration is a thickness secondary vibration having a vibration mode of (3.1.0), (5.1.0), or (7.1.0). This thickness secondary vibration is a shear vibration of only the X-axis direction, but has an odd number of sine wave-like polarizations in the X-axis direction, and the signs of the polarities of the adjacent extreme values are opposite. Alternatively, the secondary vibration can also be a thickness secondary vibration having a vibration mode of (1.1.1) or (1.1.2). This thickness secondary vibration is a vibration close to the thickness primary vibration, and between the thickness primary vibration and the thickness secondary vibration having a vibration mode of (3.1.0), (5.1.0), or (7.1.0), and has one sine wave-like polarization in the X-axis direction, and one or two cosine wave-like polarizations in the Z-axis direction, and the signs of the polarities of the adjacent extreme values are opposite. Alternatively, the secondary vibration can also be a secondary vibration based on a high-order contour vibration having a vibration mode of (21.0.0). This secondary vibration based on a high-order contour vibration has an odd number of sine wave-like polarizations in the X-axis direction, and the signs of the polarities of the adjacent extreme values are opposite, and has a substantially fixed polarization in the Z-axis direction. Alternatively, the secondary vibration can also be a secondary vibration based on a high-order contour vibration having a vibration mode of (0.0.33). This secondary vibration based on a high-order contour vibration has an odd number of sine wave-like polarizations in the Z-axis direction, and the signs of the polarities of the adjacent extreme values are opposite, and has a substantially fixed polarization in the X-axis direction. Alternatively, the secondary vibration can also be a secondary vibration based on a high-order contour vibration having a vibration mode of (40.1.0), (42.1.0), or (12.1.0). This secondary vibration based on a high-order contour vibration has an odd number of sine wave-like polarizations in the X-axis direction, and the signs of the polarities of the adjacent extreme values are opposite.

[0092] The value R of the load-time series resistance when the vibrator 3 resonates in the primary vibration Lm The value R of the load-time series resistance when the vibrator 3 resonates in the secondary vibration Ls In other words, the vibration having the smallest value of the load-time series resistance is the primary vibration. In the normal operation mode, if the vibrator 3 resonates in the primary vibration, the oscillation circuit 10 normally oscillates, and the oscillation signal CK of the target frequency can be obtained, but if the vibrator 3 resonates in the secondary vibration, the oscillation circuit 10 abnormally oscillates, and the oscillation signal CK of the target frequency cannot be obtained. In the normal operation mode, in order to cause the oscillation circuit 10 to stably oscillate in the primary vibration, the negative resistance value |nR| is set to be much larger than RLm Specifically, the logic circuit 42 of the control circuit 40 supplies the current adjustment data triml[4:0] and the capacitance adjustment data trimCl[4:0], trimC2[4:0] transmitted from the nonvolatile memory 71 to the register 72 to the oscillation circuit 10, and controls so that the negative resistance value |nR| of the oscillation circuit 10 becomes the 1st value |nRl| determined by the current adjustment data triml[4:0] and the capacitance adjustment data trimCl[4:0], trimC2[4:0].

[0093] However, the 1st value |nRl| is much larger than R Lm , and thus the result is larger than R Ls . Thus, the 1st value |nRl| is larger than R Ls , and thus, when the negative resistance value |nR| is set to the 1st value |nRl| immediately from the state where the oscillation of the oscillation circuit 10 is stopped, the vibrator 3 can resonate with the sub vibration depending on the condition, and the oscillation circuit 10 can abnormally oscillate. Therefore, in the present embodiment, in order to reduce the possibility that the oscillation circuit 10 abnormally oscillates, the logic circuit 42 of the control circuit 40 controls so that the negative resistance value |nR| of the oscillation circuit 10 increases from the 2nd value |nR2| smaller than the 1st value |nRl| in the start-up mode.

[0094] Here, as described above, the 1st value |nRl| is a value larger than the value R Lm of the series resistance at the time of load when the vibrator 3 resonates with the main vibration, and is a value larger than the value R Ls of the series resistance at the time of load when the vibrator 3 resonates with the sub vibration. Further, the 2nd value |nR2| is a value at least smaller than the value R Ls of the series resistance at the time of load when the vibrator 3 resonates with the sub vibration, that is, a negative resistance value at which the vibrator 3 cannot resonate with the sub vibration. The 2nd value |nR2| can be smaller than the value R Lm of the series resistance at the time of load when the vibrator 3 resonates with the main vibration, or can be larger than the value R Lm . For example, the 2nd value |nR2| can be made smaller than R Lm so that the 2nd value |nR2| is reliably smaller than R Ls even if a deviation in characteristics of the vibrator 3 connected to the oscillation circuit 2 is considered.

[0095] Thus, in the present embodiment, the logic circuit 42 controls so that the negative resistance value |nR| of the oscillation circuit 10 increases from the 2nd value |nR2| at which the vibrator 3 cannot resonate with at least the sub vibration in the start-up mode. Thereby, there is a certain possibility that the negative resistance value |nR| is larger than R LmAnd less than R Ls In this state, oscillator 3 can resonate with the main vibration, but cannot resonate with the secondary vibration. Therefore, oscillator 3 resonates with the main vibration before resonating with the secondary vibration, and the oscillation circuit 10 oscillates normally based on the resonance in the main vibration.

[0096] Here, in Figure 5 In the oscillation circuit 10 shown, the transconductance of the amplifying element 11 is assumed to be g. m The capacitance value connected to the XI terminal is C. XI The capacitance value connected to the XO terminal is C. XO When the oscillation frequency of the oscillation circuit 10 is f=ω / 2π, the theoretical formula for the negative resistance value |nR| of the oscillation circuit 10 is as shown in formula (1).

[0097]

[0098] Furthermore, the mutual conductance g of amplifying element 11 m It is represented by equation (2). In equation (2), q is the charge of the electron, k is the Boltzmann constant, and T is the absolute temperature.

[0099]

[0100] According to equation (1), the mutual conductance g of amplifying element 11 m The larger the value of |nR|, the larger the negative resistance value. In equation (2), q, k, and T are constants. Therefore, the larger the oscillator current Iosc, the larger the mutual conductance g. m The larger the oscillator current Iosc, the larger the negative resistance value |nR|.

[0101] Therefore, in this embodiment, the logic circuit 42 of the control circuit 40 increases the value of the oscillation stage current Iosc in the startup mode, thereby increasing the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2|. Specifically, the logic circuit 42 performs suppression in the startup mode to change the value of the current adjustment data trimI[4:0] output to the oscillation circuit 10, thereby increasing the value of the oscillation stage current Iosc in a stepwise manner, thereby increasing the negative resistance value |nR| in a stepwise manner.

[0102] Figure 10 This is a waveform diagram illustrating an example of the sequence of transition from the oscillating circuit 2 to its normal operating mode after power is switched on. Figure 10In the example of FIG. 1, when the oscillator 1 is powered on, the reset period Tl starts, the power supply voltage Vdd rises from 0 V to a prescribed voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Then, the power-on reset signal POR changes from the high level to the low level, whereby the reset period Tl ends and the memory load period T2 starts.

[0103] In the memory load period T2, various information stored in the nonvolatile memory 71 is transferred to the register 72. After this transfer ends, the logic circuit 42 changes the oscillation enable signal en_osc from the low level to the high level, whereby the memory load period T2 ends and the start-up period T3 starts.

[0104] In the start-up period T3, the logic circuit 42 increases the current adjustment data triml[4:0] from a start value to an end value in stages by an arbitrary value, and in conjunction therewith, the value of the oscillation stage current Iosc increases in stages. The start value or the end value of the current adjustment data triml[4:0] can be set to an arbitrary value, for example, by being written in advance in the nonvolatile memory 71. In the example of FIG. 1, the logic circuit 42 increases the current adjustment data triml[4:0] from the start value 0 in stages by 1, and in conjunction therewith, the value of the oscillation stage current Iosc increases from I0 to I0+1, I0+2, I0+3, and I0+4 in stages. Figure 10 b In the example of FIG. 1, the logic circuit 42 increases the current adjustment data triml[4:0] from the start value 0 in stages by 1, and in conjunction therewith, the value of the oscillation stage current Iosc increases from I0 to I0+1, I0+2, I0+3, and I0+4 in stages. Lm Ls When the negative resistance value |nR| is greater than R Ls , but at this time, the oscillation of the oscillation circuit 10 due to the resonance in the main vibration of the vibrator 3 is sufficiently grown, so resonance in the sub-vibration of the vibrator 3 does not occur. When the current adjustment data triml[4:0] further increases to the end value 31, the value of the oscillation stage current Iosc becomes I b +31I0. Then, the logic circuit 42 changes the value of the current adjustment data triml[4:0] from the end value to a set value in the normal operation mode in stages by an arbitrary value. Figure 10 ​​In the example of Fig. 6, the logic circuit 42 causes the value of the current adjustment data triml[4:0] to be decreased in stages from the end value 31 by 1, and when the set value of the current adjustment data triml[4:0] in the normal operation mode reaches the value 20 transmitted to the register 72 during the memory load period T2, the value of the oscillation stage current Iosc becomes I b +20I0, and the negative resistance value |nR| becomes the 1st value |nRl|. Then, the logic circuit 42 causes the value of the current adjustment data triml[4:0] to be maintained at 20, and the output enable signal en_out is changed from the low level to the high level, whereby the start-up period T3 ends and the normal operation period T4 starts.

[0105] During the normal operation period T4, the output enable signal en_out is at the high level, and therefore the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0106] In addition, during the normal operation period T4, the logic circuit 42 causes the value of the current adjustment data triml[4:0] to be decreased in stages by 1 from the value 20, and when the set value of the current adjustment data triml[4:0] in the normal operation mode reaches the value 0, the value of the oscillation stage current Iosc becomes I Figure 10 In the example of Fig. 6, the operation mode during the start-up period T3 is the start-up mode, and the operation mode during the normal operation period T4 is the normal operation mode. Alternatively, the operation mode during the reset period Tl, the memory load period T2, and the start-up period T3 is the start-up mode.

[0107] In the example of Fig. 6, the operation mode during the start-up period T3 is the start-up mode, and the operation mode during the normal operation period T4 is the normal operation mode. Alternatively, the operation mode during the reset period Tl, the memory load period T2, and the start-up period T3 is the start-up mode. Figure 10 In the example of Fig. 6, the logic circuit 42 causes the value of the current adjustment data triml[4:0] to be decreased in stages from the end value 31 by 1, and when the set value of the current adjustment data triml[4:0] in the normal operation mode reaches the value 20 transmitted to the register 72 during the memory load period T2, the value of the oscillation stage current Iosc becomes I

[0108] Figure 11 is a waveform chart showing another example of the sequence of shifting to the normal operation mode after the power supply is turned on from the oscillation circuit 2. In the example of Fig. 7, during the start-up period T3, the logic circuit 42 causes the current adjustment data triml[4:0] to be increased in stages from the start value by an arbitrary value to the set value in the normal operation mode, and in conjunction therewith, the value of the oscillation stage current Iosc is increased in stages. The start value of the current adjustment data triml[4:0] can be set to an arbitrary value by being written in the nonvolatile memory 71 in advance, for example. In the example of Fig. 7, the logic circuit 42 causes the current adjustment data triml[4:0] to be increased in stages from the start value 0 by 1 to the set value 20 in the normal operation mode, and in conjunction therewith, the value of the oscillation stage current Iosc is increased from I Figure 11 Figure 11 b b ​​​+20I0. As a result, in the startup period T3, the negative resistance value |nR| of the oscillator circuit 10 is increased in steps from the second value |nR2| to the first value |nR1|. Then, the logic circuit 42 maintains the value of the current adjustment data triml[4:0] at 20, changes the output enable signal en_out from the low level to the high level, whereby the startup period T3 ends and the normal operation period T4 starts.

[0109] In Figure 11 the example, the logic circuit 42 does not need to increase the current adjustment data triml[4:0] from the start value to the end value, and therefore, the startup period T3 is shortened. In addition, in Figure 11 the example, the set value of the negative resistance value |nR| in the normal operation mode, i.e., the first value |nR1|, is larger than the maximum value of the negative resistance value |nR| in the startup period T3. That is, in the startup period T3, the negative resistance value |nR| is not larger than the first value |nR1|, and therefore, the negative resistance value |nR| becomes a value that is smaller than the value R Ls of the series resistance when the vibrator 3 resonates in the secondary vibration, and the time during which the negative resistance value |nR| becomes a value that is larger than the value R

[0110] In addition, in Figure 11 the example, the operation mode in the startup period T3 is the startup mode, and the operation mode in the normal operation period T4 is the normal operation mode. Alternatively, the operation mode in the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0111] 1-4. Control method of the oscillator circuit

[0112] Figure 12 is a flowchart showing an example of steps of the control method of the oscillator circuit 2. As shown in Figure 12 , when the oscillator 1 is turned on, first, the oscillator circuit 2 performs the reset step Sl. Specifically, in the reset step Sl, the power-on reset circuit 30 changes the power-on reset signal POR from the low level to the high level, and initializes the logic circuit 42. Then, the power-on reset circuit 30 changes the power-on reset signal POR from the high level to the low level, and the reset step Sl ends. The period of the reset step Sl corresponds to the reset period T1 of Figure 10 or Figure 11 .

[0113] Next, the oscillation circuit 2 performs the memory loading step S2. Specifically, in the memory loading step S2, the storage circuit 70 transfers various information stored in the non-volatile memory 71 to the register 72. Then, after the transfer is completed, the logic circuit 42 sets the oscillation enable signal en_osc to a high level, and the memory loading step S2 ends. The period of the memory loading step S2 is equivalent to... Figure 10 or Figure 11 During the memory loading period T2.

[0114] Next, the oscillation circuit 2 proceeds to startup step S3. Specifically, in startup step S3, logic circuit 42 sets the oscillation enable signal en_osc to a high level, controlling the increase of the negative resistance value |nR| of the oscillation circuit 10 from a second value |nR2|, which is smaller than the first value |nR1|. Then, logic circuit 42 changes the output enable signal en_out from a low level to a high level, and startup step S3 ends. The period of startup step S3 is equivalent to... Figure 10 or Figure 11 During startup, T3.

[0115] Finally, the oscillation circuit 2 performs normal operation step S4. Specifically, in normal operation step S4, the oscillation circuit 10 oscillates with the negative resistance value |nR| at the second value |nR2|, and the oscillation signal CKO output from the output circuit 60 is output from the external terminal OUT1 of the oscillator 1 via the OUT terminal. The period of normal operation step S4 is equivalent to Figure 10 or Figure 11 During the normal operation period T4.

[0116] Additionally, the operation mode in startup step S3 is startup mode, and the operation mode in normal operation step S4 is normal operation mode. Alternatively, the operation modes in reset step S1, memory loading step S2, and startup step S3 are startup mode.

[0117] Figure 13 This illustrates the first embodiment. Figure 12 A flowchart of an example of the startup step S3. Figure 13 The steps shown correspond to Figure 10 The actions of T3 during startup. For example... Figure 13 As shown, firstly, in step S31, logic circuit 42 sets the current adjustment data trimI[4:0] to the starting value. In Figure 10 In the example, the starting value is 0. By setting the current adjustment data trimI[4:0] to the starting value, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0118] Next, when a predetermined time elapses in step S32, in step S33, the logic circuit 42 determines whether the value of the current adjustment data triml[4:0] coincides with the end value. In Figure 10 In the example, the end value is 20.

[0119] In the case where the value of the current adjustment data triml[4:0] does not coincide with the end value in step S33, in step S34, the logic circuit 42 changes the value of the current adjustment data triml[4:0] so as to increase the oscillation stage current Iosc.

[0120] The steps S32, S33, S34 are repeated until the value of the current adjustment data triml[4:0] coincides with the end value, and when the value of the current adjustment data triml[4:0] coincides with the end value, in step S35, the logic circuit 42 changes the current adjustment data triml[4:0] to the set value in the normal operation mode.

[0121] Then, in step S36, the logic circuit 42 sets the output enable signal en_out to the high level, and the start of the step S3 is ended.

[0122] Figure 14 is a flowchart showing another example of the steps of the start step S3 in the first embodiment. Figure 12 is a flowchart showing another example of the steps of the start step S3 in the first embodiment. Figure 14 The steps shown in Figure 11 correspond to the operation during the start period T3 of Figure 14 As shown, first, in step S101, the logic circuit 42 sets the current adjustment data triml[4:0] to the start value. In Figure 11 In the example, the start value is 0. By setting the current adjustment data triml[4:0] to the start value, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0123] Next, when a predetermined time elapses in step S102, in step S103, the logic circuit 42 determines whether the value of the current adjustment data triml[4:0] coincides with the set value in the normal operation mode. The set value of the current adjustment data triml[4:0] in the normal operation mode is the value stored in the nonvolatile memory 71.

[0124] In the case where the value of the current adjustment data triml[4:0] does not coincide with the set value in the normal operation mode in step S103, in step S104, the logic circuit 42 changes the value of the current adjustment data triml[4:0] so as to increase the oscillation stage current Iosc.

[0125] Then, the steps S102, S103, S104 are repeated until the value of the current adjustment data triml[4:0] coincides with the set value in the normal operation mode, and when the value of the current adjustment data triml[4:0] coincides with the set value in the normal operation mode, the logic circuit 42 sets the output enable signal en_out to the high level in the step S105, and the start-up ends.

[0126] 1-5. Effects

[0127] In the oscillator 1 of the first embodiment described above, in the start-up mode in which the state is shifted from the state in which the oscillation circuit 10 stops oscillation to the normal operation mode in which the oscillation circuit 10 oscillates in the state in which the negative resistance value |nR| of the oscillation circuit 10 is the first value |nRl|, the negative resistance value |nR| of the oscillation circuit 10 is increased from the second value |nR2| smaller than the first value |nRl|. The value R Lm of the series resistance at the time of the load when the vibrator 3 resonates in the main vibration is smaller than the value R Ls of the series resistance at the time of the load when the vibrator 3 resonates in the sub vibration. Therefore, the negative resistance value |nR| of the oscillation circuit 10 is increased from the second value |nR2| to a value larger than R Lm and smaller than R Ls . Therefore, in the start-up mode, the oscillation based on the resonance in the main vibration of the vibrator 3 is grown first compared to the oscillation based on the resonance in the sub vibration of the vibrator 3. Therefore, according to the oscillator 1 of the first embodiment, even if there is a deviation in the characteristics of the vibrator 3, it is possible to reduce the possibility of abnormal oscillation.

[0128] In particular, in the oscillator 1 of the first embodiment, in the start-up mode, the value of the oscillation stage current Iosc is increased, and thereby, the negative resistance value |nR| of the oscillation circuit 10 is gradually increased in steps from the second value |nR2|, and therefore, the time in which the value is larger than R Lm and smaller than R Ls is longer. Therefore, the oscillation based on the resonance in the main vibration of the vibrator 3 is grown first compared to the oscillation based on the resonance in the sub vibration of the vibrator 3. Therefore, according to the oscillator 1 of the first embodiment, even if there is a deviation in the characteristics of the vibrator 3, it is possible to reduce the possibility of abnormal oscillation.

[0129] Further, according to the oscillator 1 of the first embodiment, in order to increase the negative resistance value |nR| of the oscillation circuit 10 in the start-up mode, the variable current source 12 for making the oscillation stage current Iosc the desired value corresponding to the resonance frequency of the vibrator 3 in the normal operation mode can be used.

[0130] 2. Second Embodiment

[0131] Hereinafter, regarding the oscillator 1 of the second embodiment, the same reference numerals will be used for structures that are the same as those in the first embodiment, and descriptions that are the same as those in the first embodiment will be omitted or simplified. The descriptions will mainly focus on the contents that are different from those in the first embodiment.

[0132] The structure of the oscillator 1 in the second embodiment is similar to... Figures 1-4 The structure is the same as that of the oscillation circuit 10 in the second embodiment, therefore its illustration and description are omitted. Furthermore, the structure of the oscillation circuit 10 in the second embodiment is the same as... Figure 5 Since they are the same, their illustrations and descriptions are omitted. The difference between the oscillator 1 of the second embodiment and the oscillator 1 of the first embodiment lies in the operation in the start-up mode.

[0133] According to equation (1), the capacitance value C XI C XO The smaller at least one of the values ​​is, the larger the negative resistance value |nR| is. Therefore, in the second embodiment, the logic circuit 42 of the control circuit 40 reduces at least one of the capacitance values ​​C1 and C2 of the variable capacitor circuits 14 and 15 in the startup mode, thereby increasing the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2|. Specifically, the logic circuit 42 controls in the startup mode to change the value of at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] output to the oscillation circuit 10, thereby increasing at least one of the capacitance values ​​C1 and C2 of the variable capacitor circuits 14 and 15 in a stepwise manner, thereby increasing the negative resistance value |nR| in a stepwise manner.

[0134] The other structures of the oscillator 1 in the second embodiment are the same as those in the first embodiment, therefore, its illustrations and descriptions are omitted.

[0135] Figure 15 This is a waveform diagram illustrating an example of the sequence of transition from the oscillation circuit 2 to the normal operating mode after power is turned on in the second embodiment. Figure 15 In the example, when oscillator 1 is powered on, the reset period T1 begins, the power supply voltage Vdd rises from 0V to the specified voltage value, the power-on reset signal POR changes from low to high, and the logic circuit 42 is initialized. Then, the power-on reset signal POR changes from high to low, thus ending the reset period T1, and the memory loading period T2 begins.

[0136] During memory loading period T2, various information stored in non-volatile memory 71 is transferred to register 72. After this transfer is completed, logic circuit 42 causes the oscillation enable signal en_osc to change from low level to high level, thereby ending memory loading period T2 and starting startup period T3.

[0137] During startup (T3), logic circuit 42 causes the capacitor adjustment data trimC1[4:0] and trimC2[4:0] to increase in stages from their starting values ​​to the set values ​​in the normal operating mode, in units of arbitrary values. Simultaneously, the values ​​of capacitors C1 and C2 increase in stages. The starting values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] can be set to arbitrary values, for example, by pre-writing them to the non-volatile memory 71. Figure 15 In the example, logic circuit 42 causes the capacitor adjustment data trimC1[4:0] and trimC2[4:0] to increase in steps of 1 from the initial value of 0, while the capacitor values ​​C1 and C2 decrease in steps of C0 from 31C0. As a result, during the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner from the second value |nR2|. When the negative resistance value |nR| is greater than R Lm And less than R Ls At this time, oscillator 3 begins to resonate with the main oscillation, and the amplitude of the current I_xtal output from oscillator 3 increases. Then, when the amplitude of current I_xtal exceeds the specified threshold, a pulse is generated in the oscillation signal CK. Then, the capacitor adjustment data trimC1[4:0] and trimC2[4:0] also increase, and the negative resistance value |nR| is greater than R. Ls However, at this moment, due to the resonance in the main vibration of oscillator 3, the oscillation of the oscillation circuit 10 has grown sufficiently, so the resonance in the secondary vibration of oscillator 3 will not occur. When the capacitor adjustment data trimC1[4:0] and trimC2[4:0] are further increased to reach the value 20 transferred to register 72 during memory loading period T2, the capacitor values ​​C1 and C2 become 11C0 respectively, and the negative resistance value |nR| becomes the first value |nR1|. Then, the logic circuit 42 keeps the values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] at 20, and changes the output enable signal en_out from low level to high level, thereby ending the startup period T3 and starting the normal operation period T4.

[0138] During normal operation T4, the output enable signal en_out is high, so the oscillation signal CK is buffered, and a pulse is generated in the oscillation signal CKO.

[0139] Additionally, during startup T3, both the capacitor adjustment data trimC1[4:0] and trimC2[4:0] are increased, thereby decreasing the capacitor values ​​C1 and C2. However, it is also possible to fix one of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] and increase the other, thereby fixing the capacitor values ​​C1 and C2 and decreasing the other.

[0140] In Figure 15 the example, the set value of the negative resistance value |nR| in the normal operation mode, i.e., the first value |nR1|, is larger than the maximum value of the negative resistance value |nR| in the startup period T3. That is, in the startup period T3, the negative resistance value |nR| is not larger than the first value |nR1|, and thus the negative resistance value |nR| becomes a value R Ls larger than the value of the load-time series resistance when the vibrator 3 resonates in the sub vibration, for a shorter time, and the resonance in the sub vibration of the vibrator 3 is less likely to occur.

[0141] In addition, in Figure 15 the example, the operation mode in the startup period T3 is the startup mode, and the operation mode in the normal operation period T4 is the normal operation mode. Alternatively, the operation mode in the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0142] Although the illustration of the sequence is omitted, in the startup period T3, the logic circuit 42 can also increase at least one of the capacitance adjustment data trimC1[4:0], trimC2[4:0] from the start value to the end value in stages by an arbitrary value as a unit, and then decrease to the set value in the normal operation mode in stages by an arbitrary value as a unit.

[0143] The flowchart showing the steps of the control method of the oscillation circuit 2 in the second embodiment is the same as Figure 12 , and thus the illustration and the description thereof are omitted. However, in the second embodiment, Figure 12 the steps of the startup step S3 are different from those of the first embodiment.

[0144] Figure 16 is a flowchart showing an example of the steps of the startup step S3 of Figure 12 in the second embodiment. Figure 16 The steps shown in Figure 15 correspond to the operation in the startup period T3 of Figure 16 . As shown in Figure 15 , first, in step S201, the logic circuit 42 sets the capacitance adjustment data trimC1[4:0], trimC2[4:0] to start values, respectively. In the example, the start values are both 0. By setting the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the start values, respectively, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0145] Next, when the prescribed time elapses in step S202, in step S203, the logic circuit 42 determines whether the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] coincide with the set values in the normal operation mode, respectively. The set values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] in the normal operation mode are the values stored in the nonvolatile memory 71.

[0146] In the case where the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] do not coincide with the set values in the normal operation mode in step S203, in step S204, the logic circuit 42 changes the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] so as to decrease the capacitance values Cl, C2.

[0147] Then, steps S202, S203, S204 are repeated until the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] coincide with the set values in the normal operation mode, and when the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] coincide with the set values in the normal operation mode, in step S205, the logic circuit 42 sets the output enable signal en_out to the high level, and the start-up ends.

[0148] In addition, the logic circuit 42 can fix the value of one of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] and change the value of the other, whereby one of the capacitance values Cl, C2 is fixed and the other is decreased.

[0149] In the oscillator 1 of the second embodiment described above, in the start-up mode, the capacitance values Cl, C2 of the variable capacitance circuits 14, 15 are decreased, whereby the negative resistance value |nR| of the oscillation circuit 10 is gradually increased in steps from the second value |nR2|, and thus, the time during which the value of the series resistance R Lm is greater than the value of the series resistance R Ls when the vibrator 3 resonates in the main vibration and is less than the value of the series resistance R when the vibrator 3 resonates in the sub vibration is longer. Therefore, the oscillation based on the resonance in the main vibration of the vibrator 3 grows first compared with the oscillation based on the resonance in the sub vibration of the vibrator 3. Therefore, according to the oscillator 1 of the second embodiment, even if there is a deviation in the characteristics of the vibrator 3, it is possible to reduce the possibility of abnormal oscillation.

[0150] Furthermore, according to the oscillator 1 of the second embodiment, in order to increase the negative resistance value |nR| of the oscillation circuit 10 in the start-up mode, the variable capacitor circuits 14 and 15 used in the normal operation mode to make the oscillation frequency of the oscillation circuit 10 a target frequency can also be used.

[0151] 3. Third Implementation Method

[0152] Hereinafter, regarding the oscillator 1 of the third embodiment, the same reference numerals will be used for structures that are the same as those in any of the above embodiments, and descriptions that are the same as those in any of the above embodiments will be omitted or simplified. The descriptions will mainly focus on the contents that are different from those in any of the above embodiments.

[0153] The structure of the oscillator 1 in the third embodiment is similar to... Figures 1-4 The structure is the same as that of the oscillation circuit 10 in the third embodiment, therefore its illustration and description are omitted. Furthermore, the structure of the oscillation circuit 10 in the third embodiment is the same as... Figure 5 Since they are the same, their illustrations and descriptions are omitted. The oscillator 1 of the third embodiment operates differently in the startup mode compared to the oscillators 1 of the above embodiments.

[0154] According to equation (1), the capacitance value C XI C XO The smaller at least one of the values ​​is, the larger the negative resistance value |nR| is. Therefore, in the third embodiment, the voltage control circuit 41 of the control circuit 40 reduces at least one of the capacitance values ​​C3 and C4 of the variable capacitor circuits 16 and 17 in the startup mode, thereby increasing the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2|. Specifically, the voltage control circuit 41 controls in the startup mode to change the value of at least one of the control voltages Vcnt1 and Vcnt2 output to the oscillation circuit 10, thereby continuously increasing at least one of the capacitance values ​​C3 and C4 of the variable capacitor circuits 16 and 17, thereby continuously increasing the negative resistance value |nR|.

[0155] Figure 17 This is a diagram illustrating an example of the structure of the voltage control circuit 41 in the third embodiment. (See diagram for example.) Figure 17 As shown, the voltage control circuit 41 includes a control voltage generation circuit 200, a filter circuit 210, a switching circuit 220, a filter circuit 230, a switching circuit 240, a resistor 250, and a resistor 260.

[0156] In normal operating mode, the control voltage generation circuit 200 generates control voltages Vcnt1X and Vcnt2X to change the oscillation frequency of the oscillation circuit 10 based on the voltage level of the frequency control signal supplied from the external terminal VC1 via the VC terminal. Furthermore, in startup mode, the control voltage generation circuit 200 outputs control voltages Vcnt1X and Vcnt2X corresponding to the control from the logic circuit 42. Control voltage Vcnt1X is input to the filter circuit 210, and control voltage Vcnt2X is input to the filter circuit 230.

[0157] The filter circuit 210 is a low-pass filter circuit that includes a resistor 211 and a capacitor 212, and outputs a control voltage Vcnt1f that makes the rise or fall of the control voltage Vcnt1 smooth.

[0158] According to the control from the logic circuit 42, the switching circuit 220 selects and outputs the control voltage Vcnt1X in the normal operating mode, and selects and outputs the control voltage Vcnt1f in the startup mode. The voltage output from the switching circuit 220 is supplied as the control voltage Vcnt1 via the resistor 250. Figure 5 16. Variable capacitor circuit.

[0159] The filter circuit 230 is a low-pass filter circuit that includes a resistor 231 and a capacitor 232, and outputs a control voltage Vcnt2f that makes the rise or fall of the control voltage Vcnt2 smooth.

[0160] According to the control from the logic circuit 42, the switching circuit 240 selects and outputs the control voltage Vcnt2X in the normal operating mode, and selects and outputs the control voltage Vcnt2f in the startup mode. The voltage output from the switching circuit 240 is supplied as the control voltage Vcnt2 via the resistor 260. Figure 5 17. Variable capacitor circuit.

[0161] The other structures of the oscillator 1 in the third embodiment are the same as those in the embodiments described above, therefore, its illustrations and descriptions are omitted.

[0162] Figure 18 This is a waveform diagram illustrating an example of the sequence of transition from the oscillation circuit 2 to the normal operating mode after power is turned on in the third embodiment. Figure 18 In the example, when oscillator 1 is powered on, the reset period T1 begins, the power supply voltage Vdd rises from 0V to the specified voltage value, the power-on reset signal POR changes from low to high, and the logic circuit 42 is initialized. Then, the power-on reset signal POR changes from high to low, thus ending the reset period T1, and the memory loading period T2 begins.

[0163] During the memory load period T2, the various information stored in the nonvolatile memory 71 is transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en osc from the low level to the high level, whereby the memory load period T2 ends and the start-up period T3 begins.

[0164] During the start-up period T3, under the control of the logic circuit 42, in the voltage control circuit 41, the control voltage generating circuit 200 causes the control voltages Vcntlx, Vcnt2x to increase from the start value V start to the end value V end The switching circuits 220, 240 select and output the control voltages Vcntlf, Vcnt2f output from the filter circuits 210, 230. As a result, the increase in the control voltages Vcntl, Vcnt2 becomes gradual, and the control voltages Vcntl, Vcnt2 increase continuously, accompanied by a continuous decrease in the capacitance values C3, C4, respectively. As a result, during the start-up period T3, the negative resistance value |nR| of the oscillation circuit 10 increases continuously from the second value |nR2|. When the negative resistance value |nR| becomes greater than R Lm and smaller than R Ls , the vibrator 3 starts to resonate in the main vibration, and the amplitude of the current I_xtal output from the vibrator 3 increases. Then, when the amplitude of the current I_xtal exceeds a prescribed threshold value, a pulse is generated in the oscillation signal CK. Then, the control voltages Vcntl, Vcnt2 also increase, and the negative resistance value |nR| becomes greater than R Ls However, at this time, the oscillation of the oscillation circuit 10 due to the resonance in the main vibration of the vibrator 3 is sufficiently grown, so resonance in the sub-vibration of the vibrator 3 does not occur. When the control voltages Vcntl, Vcnt2 further increase to reach the end value V end , the capacitance values C3, C4 become prescribed values, respectively, and the negative resistance value |nR| becomes the first value |nRl|. The end value V end may be the voltage value of the frequency control signal input from the VC terminal. Then, the logic circuit 42 changes the output enable signal en_out from the low level to the high level, whereby the start-up period T3 ends and the normal operation period T4 begins. The start value V start and the end value V end may be set to arbitrary values, for example, by being written in the nonvolatile memory 71 in advance.

[0165] During the normal operation period T4, the output enable signal en_out is at the high level, so the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0166] In addition, during the startup period T3, both control voltages Vcnt1 and Vcnt2 are increased, thereby decreasing the capacitance values ​​C3 and C4. However, one of the control voltages Vcnt1 and Vcnt2 can be fixed while the other is increased, thereby fixing one of the capacitance values ​​C3 and C4 while the other is decreased.

[0167] In addition, Figure 18 In the example, the operation mode during startup period T3 is startup mode, and the operation mode during normal operation period T4 is normal operation mode. Alternatively, the operation modes during reset period T1, memory load period T2, and startup period T3 are startup mode.

[0168] Although the sequence diagram is omitted, during startup T3, at least one of the control voltages Vcnt1 and Vcnt2 can be set from its initial value V. start It continuously increases until the final value V. end Then, make it from the ending value V end The voltage value of the frequency control signal input from the VC terminal changes continuously. For example, the minimum and maximum values ​​of the variable ranges of the control voltages Vcnt1 and Vcnt2 can be set as the starting value V. start and the final value V end .

[0169] A flowchart showing the steps of the control method for the oscillating circuit 2 in the third embodiment is provided. Figure 12 The embodiments are the same, therefore, their illustrations and descriptions are omitted. However, the third embodiment differs from the embodiments described above in that... Figure 12 The startup step S3.

[0170] Figure 19 This illustrates the third embodiment. Figure 12 A flowchart of an example of the startup step S3. Figure 19 The steps shown correspond to Figure 18 The actions of T3 during startup. For example... Figure 19 As shown, firstly, in step S301, the logic circuit 42 is set so that the switching circuits 220 and 240 of the voltage control circuit 41 select the output voltage of the filter circuits 210 and 230.

[0171] Next, in step S302, the logic circuit 42 performs control so that the control voltage generation circuit 200 of the voltage control circuit 41 causes the control voltages Vcnt1X and Vcnt2X to start from the initial value V start Change to the final value V end Therefore, the control voltages Vcnt1 and Vcnt2 change continuously from their initial values ​​to their final values.

[0172] Then, when the prescribed time elapses in step S303, in step S304, the logic circuit 42 sets the output enable signal en_out to the high level, and the start-up mode ends. The prescribed time is, for example, a time longer than the time for the control voltages Vcntl, Vcnt2 to change from the start values V start to the end values V end , and is appropriately determined in accordance with the time constants of the filter circuits 210, 230.

[0173] In addition, the logic circuit 42 can also fix the value of one of the control voltages Vcntlx, Vcnt2x and change the value of the other, thereby fixing one of the capacitance values Cl, C2 and reducing the other.

[0174] In the oscillator 1 of the 3rd embodiment described above, in the start-up mode, the capacitance values C3, C4 of the variable capacitance circuits 16, 17 are reduced, and thus the negative resistance value |nR| of the oscillation circuit 10 is continuously gradually increased from the 2nd value |nR2|, and thus the time becomes longer than the value of the series resistance R Lm when the load resonates with the main vibration of the vibrator 3 and shorter than the value of the series resistance R Ls when the load resonates with the sub vibration of the vibrator 3. Therefore, compared with the oscillation based on the resonance in the sub vibration of the vibrator 3, the oscillation based on the resonance in the main vibration of the vibrator 3 is grown first. Therefore, according to the oscillator 1 of the 3rd embodiment, even if there is a deviation in the characteristics of the vibrator 3, it is possible to reduce the possibility of abnormal oscillation.

[0175] Further, according to the oscillator 1 of the 3rd embodiment, in order to increase the negative resistance value |nR| of the oscillation circuit 10 in the start-up mode, it is possible to use the variable capacitance circuits 16, 17 for changing the oscillation frequency of the oscillation circuit 10 by the frequency control signal input from the external terminal VC1 in the normal operation mode.

[0176] 4. 4th Embodiment

[0177] Hereinafter, regarding the oscillator 1 of the 4th embodiment, the same reference numerals are attached to the same structures as those in any of the above embodiments, and the same explanation as that in any of the above embodiments is omitted or simplified, and the contents different from those in any of the above embodiments are mainly explained.

[0178] The structure of the oscillator 1 of the 4th embodiment is the same as that of the Figures 1-4 , and thus the illustration and explanation thereof are omitted. Further, the structure of the oscillation circuit 10 in the 4th embodiment is the same as that of the Figure 5 , and thus the illustration and explanation thereof are omitted. The oscillator 1 of the 4th embodiment is different from the oscillator 1 of each of the above embodiments in the operation in the start-up mode.

[0179] In the fourth embodiment, the logic circuit 42 of the control circuit 40 increases the value of the oscillation stage current Iosc in the startup mode and decreases at least one of the capacitance values Cl, C2 of the variable capacitance circuits 14, 15, thereby increasing the negative resistance value |nR| from the second value |nR2|. For example, the logic circuit 42 can also repeatedly perform the following control in the startup mode: without changing the capacitance values Cl, C2 of the variable capacitance circuits 14, 15, the value of the oscillation stage current Iosc is increased from the third value to a fourth value that is larger than the third value, and then at least one of the capacitance values Cl, C2 is decreased and the value of the oscillation stage current Iosc is changed to the third value. For example, the logic circuit 42 first performs control to keep the value of at least one of the capacitance adjustment data trimCl[4:0], trimC2[4:0] output to the oscillation circuit 10 at a start value, change the value of the current adjustment data triml[4:0] output to the oscillation circuit 10 from a start value to an end value, and increase the value of the oscillation stage current Iosc from the third value to the fourth value in steps, thereby increasing the negative resistance value |nR| in steps. Next, the logic circuit 42 performs control to change and keep the value of at least one of the capacitance adjustment data trimCl[4:0], trimC2[4:0] after changing the value of the current adjustment data triml[4:0] to the start value, thereby decreasing at least one of the capacitance values Cl, C2 by one stage, changing the value of the current adjustment data triml[4:0] from the start value to the end value, and increasing the value of the oscillation stage current Iosc from the third value to the fourth value in steps, thereby increasing the negative resistance value |nR| in steps. The logic circuit 42 repeatedly performs the same control while changing the value of at least one of the capacitance adjustment data trimCl[4:0], trimC2[4:0]. Finally, the logic circuit 42 performs control to change and keep the value of at least one of the capacitance adjustment data trimCl[4:0], trimC2[4:0] to an end value after changing the value of the current adjustment data triml[4:0] to the start value, thereby decreasing the capacitance values Cl, C2 by one stage, changing the value of the current adjustment data triml[4:0] from the start value to the end value, and increasing the value of the oscillation stage current Iosc from the third value to the fourth value in steps, thereby increasing the negative resistance value |nR| in steps.

[0180] The other structures of the oscillator 1 of the fourth embodiment are the same as those of the above-described embodiments, and thus the drawings and descriptions thereof are omitted.

[0181] Figure 20 is a waveform chart showing another example of the sequence of shifting to the normal operation mode after turning on the power supply from the oscillation circuit 2 in the fourth embodiment. In the fourth embodiment, the value of the oscillation stage current Iosc is increased from the third value to the fourth value in steps, and then at least one of the capacitance values Cl, C2 is decreased by one stage, the value of the oscillation stage current Iosc is changed from the third value to the fourth value in steps, and the negative resistance value |nR| is increased in steps.Figure 20 In the example, when oscillator 1 is powered on, the reset period T1 begins, the power supply voltage Vdd rises from 0V to the specified voltage value, the power-on reset signal POR changes from low to high, and logic circuit 42 is initialized. Then, the power-on reset signal POR changes from high to low, thus ending the reset period T1, and the memory loading period T2 begins.

[0182] During memory loading period T2, various information stored in non-volatile memory 71 is transferred to register 72. After this transfer is completed, logic circuit 42 causes the oscillation enable signal en_osc to change from low level to high level, thereby ending memory loading period T2 and starting startup period T3.

[0183] During startup (T3), logic circuit 42 first sets and holds the capacitor adjustment data trimC1[4:0] and trimC2[4:0] to their starting values, and then increases the current adjustment data trimI[4:0] in stages from the starting value to the ending value in arbitrary increments. Simultaneously, the value of the oscillation stage current Iosc increases in stages. The starting and ending values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0], and the current adjustment data trimI[4:0], can be set to arbitrary values, for example, by pre-writing them into the non-volatile memory 71. Figure 20 In the example, logic circuit 42 sets the capacitor adjustment data trimC1[4:0] and trimC2[4:0] to the starting value 0 and holds them, while the current adjustment data trimI[4:0] increases in stages from the starting value 0 in units of 1 to the ending value 31. As a result, with capacitor values ​​C1 and C2 at 31C0, the oscillation stage current Iosc increases from the third value I... b It increases in a stepwise manner to the 4th value I b +31I0, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner starting from the second value |nR2|.

[0184] Next, after changing the current adjustment data trimI[4:0] to the starting value 0, logic circuit 42 increases the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] by arbitrary values. Figure 20 In the example, the values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] are set to 1, which is obtained by increasing by 1 from 0, and are maintained. Then, the current adjustment data trimI[4:0] is increased in stages from the initial value of 0 in units of 1 to the final value of 31. As a result, when the capacitor values ​​C1 and C2 are reduced to 30C0, the oscillation stage current Iosc increases from the third value I...b increases to the fourth value I b +31 I0, the negative resistance value |nR| of the oscillation circuit 10 increases in steps. When the negative resistance value |nR| is greater than R

[0185] Next, the logic circuit 42 changes the capacitance adjustment data trimC1[4:0], trimC2[4:0] to the values obtained by increasing the values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] by 1, respectively, and holds the values. Then, the logic circuit 42 increases the current adjustment data trimI[4:0] from the start value 0 to the end value 31 in steps of 1. As a result, in the state where the capacitance values Cl, C2 are reduced to 29C0, respectively, the oscillation stage current Iosc increases from the third value I Figure 20 b increases to the fourth value I b +31 I0, the negative resistance value |nR| of the oscillation circuit 10 increases in steps. When the negative resistance value |nR| is greater than R Lm and smaller than R Ls , the resonator 3 starts to resonate in the main vibration, and the amplitude of the current I_xtal output from the resonator 3 increases. Then, when the amplitude of the current I_xtal exceeds a predetermined threshold value, a pulse is generated in the oscillation signal CK. Then, the capacitance adjustment data trimC1[4:0], trimC2[4:0] also increases, and the negative resistance value |nR| becomes greater than R Ls , but, at this time, the oscillation of the oscillation circuit 10 due to the resonance in the main vibration of the resonator 3 sufficiently grows, so that the resonance in the sub-vibration of the resonator 3 does not occur.

[0186] Then, when the values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] reach the end values 31, respectively, and the value of the current adjustment data trimI[4:0] reaches the end value 31, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] from the end value to the set value in the normal operation mode in steps of an arbitrary value. The end values of the capacitance adjustment data trimC1[4:0], trimC2[4:0] can be set to arbitrary values by being previously written in the nonvolatile memory 71, for example. Figure 20 ​In the example, logic circuit 42 causes the value of the current adjustment data trimI[4:0] to decrease in stages by 1 units starting from the end value 31. Then, when the value of the current adjustment data trimI[4:0] reaches the value 24 transferred to register 72 during memory load T2, logic circuit 42 maintains the value of the current adjustment data trimI[4:0] at 24, and the value of the oscillator current Iosc becomes I b +24I0. Furthermore, logic circuit 42 causes the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] to change in stages from the end value to the set value in the normal operating mode, in units of arbitrary values. In Figure 20 In the example, logic circuit 42 causes the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] to decrease in stages starting from the end value 31 in units of 1. Then, when the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] reach the values ​​26 transferred to register 72 during memory loading T2, logic circuit 42 keeps the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] at 26, and the capacitor values ​​C1 and C2 become 5C0. The value of the oscillation stage current Iosc becomes I b +24I0, and the capacitor values ​​C1 and C2 become 5C0 respectively, thus the negative resistance value |nR| becomes the first value |nR1|. Then, the logic circuit 42 causes the output enable signal en_out to change from low level to high level, thus ending the startup period T3 and starting the normal operation period T4.

[0187] During normal operation T4, the output enable signal en_out is high, so the oscillation signal CK is buffered, and a pulse is generated in the oscillation signal CKO.

[0188] Additionally, during startup T3, both the capacitor adjustment data trimC1[4:0] and trimC2[4:0] are increased, thereby decreasing the capacitor values ​​C1 and C2. However, it is also possible to fix one of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] and increase the other, thereby fixing the capacitor values ​​C1 and C2 and decreasing the other.

[0189] In addition, Figure 20 In the example, the operation mode during startup period T3 is startup mode, and the operation mode during normal operation period T4 is normal operation mode. Alternatively, the operation modes during reset period T1, memory load period T2, and startup period T3 are startup mode.

[0190] Although the illustration of the sequence is omitted, in order to shorten the startup period T3, the logic circuit 42 can also decrease the value of the current adjustment data triml [4:0] to the set value in the normal operation mode when the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] reach arbitrary end values set respectively, and the value of the current adjustment data triml [4:0] reaches the end value, and end the startup period T3. For example, the end values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] can also be the set values in the normal operation mode.

[0191] The flowchart showing the steps of the control method of the oscillation circuit 2 in the fourth embodiment is the same as Figure 12 , and therefore, the illustration and explanation thereof are omitted. However, in the fourth embodiment, Figure 12 the steps of the startup step S3 are different from those of the above-described embodiments.

[0192] Figure 21 is an example of the flowchart showing the steps of the startup step S3 in the fourth embodiment. Figure 12 Figure 21 The steps shown in Figure 20 correspond to the operation of the startup period T3 of Figure 21 . As shown in Figure 20 , first, in step S401, the logic circuit 42 sets the current adjustment data triml [4:0] and the capacitance adjustment data trimCl [4:0], trimC2 [4:0] to the start values. In the example of , the start value of the current adjustment data triml [4:0] is 0, and the start values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] are 0. By setting the current adjustment data triml [4:0] and the capacitance adjustment data trimCl [4:0], trimC2 [4:0] to the start values, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0193] Next, when a predetermined time elapses in step S402, in step S403, the logic circuit 42 determines whether the value of the current adjustment data triml [4:0] coincides with the end value. In the example of Figure 20 , the end value of the current adjustment data triml [4:0] is 31.

[0194] In the case where the value of the current adjustment data triml [4:0] does not coincide with the end value in step S403, in step S404, the logic circuit 42 changes the value of the current adjustment data triml [4:0] so as to increase the oscillation stage current Iosc.

[0195] Steps S402, S403, S404 are repeated until the value of the current adjustment data triml[4:0] coincides with the end value, and when the value of the current adjustment data triml[4:0] coincides with the end value, the logic circuit 42 determines in step S405 whether the values of the capacitance adjustment data trimCl[4:0], trimC2[4:0] coincide with the end values, respectively. In Figure 20 In the example, the end values of the capacitance adjustment data trimCl[4:0], trimC2[4:0] are both 31.

[0196] In the case where the values of the capacitance adjustment data trimCl[4:0], trimC2[4:0] do not coincide with the end values in step S405, the logic circuit 42 sets the current adjustment data triml[4:0] to the start value in step S406. Further, the logic circuit 42 changes the values of the capacitance adjustment data trimCl[4:0], trimC2[4:0] so that the capacitance values Cl, C2 are reduced, respectively, in step S407.

[0197] Steps S402, S403, S404, S405, S406, S407 are repeated until the values of the capacitance adjustment data trimCl[4:0], trimC2[4:0] coincide with the end values, and when the values of the capacitance adjustment data trimCl[4:0], trimC2[4:0] coincide with the end values, the logic circuit 42 changes the current adjustment data triml[4:0] to the set value in the normal operation mode in step S408. Further, the logic circuit 42 changes the capacitance adjustment data trimCl[4:0], trimC2[4:0] to the set values in the normal operation mode in step S409.

[0198] Then, the logic circuit 42 sets the output enable signal en_out to the high level in step S410, and the start-up of step S3 ends.

[0199] Further, the logic circuit 42 can fix the value of one of the capacitance adjustment data trimCl[4:0], trimC2[4:0] and change the value of the other, whereby one of the capacitance values Cl, C2 is fixed and the other is reduced.

[0200] In the oscillator 1 of the 4th embodiment described above, the value of the oscillation stage current Iosc is increased in the start-up mode, and the capacitance values Cl, C2 of the variable capacitance circuits 14, 15 are reduced, whereby the negative resistance value |nR| of the oscillation circuit 10 is gradually increased in steps from the 2nd value |nR2|, and thus becomes a value R Lmand less than the value of the series resistance R when the vibrator 3 resonates in the secondary vibration Ls the time of the value of the series resistance R when the vibrator 3 resonates in the secondary vibration. Therefore, compared with the oscillation based on the resonance in the secondary vibration of the vibrator 3, the oscillation based on the resonance in the primary vibration of the vibrator 3 grows first. Therefore, the oscillator 1 according to the fourth embodiment can reduce the possibility of abnormal oscillation even if there is a deviation in the characteristics of the vibrator 3.

[0201] In particular, in the oscillator 1 of the fourth embodiment, the logic circuit 42 repeatedly performs the control of increasing the value of the oscillation stage current Iosc from the third value to the fourth value while changing the capacitance values Cl, C2 of the variable capacitance circuits 14, 15. Therefore, the oscillator 1 according to the fourth embodiment can reduce the possibility that the capacitance values Cl, C2 of the variable capacitance circuits 14, 15 are too large or the value of the oscillation stage current Iosc is too small to cause the oscillation circuit 10 not to oscillate. Further, the logic circuit 42, after increasing the value of the oscillation stage current Iosc from the third value to the fourth value, changes the value of the oscillation stage current Iosc to the third value before decreasing the capacitance values Cl, C2, whereby the possibility that the negative resistance value |nR| sharply increases when the capacitance values Cl, C2 are decreased to cause the vibrator 3 to resonate in the secondary vibration can be reduced.

[0202] Further, the oscillator 1 according to the fourth embodiment can use the variable current source 12 for making the oscillation stage current Iosc a desired value corresponding to the resonance frequency of the vibrator 3 and the variable capacitance circuits 14, 15 for making the oscillation frequency of the oscillation circuit 10 a target frequency in the normal operation mode as well as in the startup mode to increase the negative resistance value |nR| of the oscillation circuit 10.

[0203] 5. Fifth Embodiment

[0204] Hereinafter, regarding the oscillator 1 of the fifth embodiment, the same reference numerals are assigned to the same structures as those in any of the above embodiments, and the same explanation as that in any of the above embodiments is omitted or simplified, and the explanation is mainly made on the contents different from those in any of the above embodiments.

[0205] The configuration of the oscillator 1 of the fifth embodiment is the same as that of the oscillator 1 of the fourth embodiment, and therefore, the illustration and explanation thereof are omitted. Figures 1-3

[0206] Figure 22 is a functional block diagram of the oscillator 1 of the fifth embodiment. As Figure 22 ​As shown, the oscillator 1 in the fifth embodiment, like the embodiments described above, includes an oscillation circuit 2 and an oscillator 3. The oscillation circuit 2, like the embodiments described above, includes an oscillation circuit 10, a power supply circuit 20, a power-on reset circuit 30, a control circuit 40, a reference voltage generation circuit 50, an output circuit 60, and a storage circuit 70. However, unlike the embodiments described above, it also includes an oscillation detection circuit 80. Furthermore, the oscillation circuit 2 may be configured by omitting or modifying some of these elements, or by adding other elements.

[0207] In startup mode, the oscillation detection circuit 80 detects when the signal output from the oscillator 3 exceeds a specified amplitude and outputs a detection signal DET.

[0208] The logic circuit 42 of the control circuit 40 sets the negative resistance value |nR| of the oscillation circuit 10 to the first value |nR1| according to the detection signal DET.

[0209] Figure 23 This is a diagram showing an example of the structure of the oscillation detection circuit 80. Figure 23 In the example, the oscillation detection circuit 80 includes a current source 300, three capacitor elements 301, 314, and 315, three variable resistors 302, 303, and 304, six N-channel MOS transistors 305, 306, 307, 308, 309, and 313, a comparator 310, and two CMOS inverters 311 and 312.

[0210] One end of the current source 300 is supplied with voltage Vreg, and the other end is connected to the drain of the N-channel MOS transistor 305.

[0211] The gate of N-channel MOS transistor 305 is connected to the gate of N-channel MOS transistor 307 and the gate of N-channel MOS transistor 309, and the sources of N-channel MOS transistors 305, 307 and 309 are grounded.

[0212] The drain of N-channel MOS transistor 307 is connected to the source of N-channel MOS transistor 306, and the drain of N-channel MOS transistor 309 is connected to the source of N-channel MOS transistor 308.

[0213] One end of variable resistor 304 is supplied with voltage Vreg, and the other end is connected to one end of variable resistor 303. The other end of variable resistor 303 is connected to one end of variable resistor 302, and the other end of variable resistor 302 is grounded.

[0214] One end of capacitor 301 is connected to terminal XI, and the other end is connected to the other end of variable resistor 303, one end of variable resistor 302, and the gate of N-channel MOS transistor 306. Terminal XI receives the signal output from oscillator 3.

[0215] The gate of the N-channel MOS transistor 308 is connected to the other end of the variable resistor 304 and one end of the variable resistor 303, and the drains of the N-channel MOS transistors 306, 308 are supplied with a voltage Vreg.

[0216] The inverting input terminal of the comparator 310 is connected to the source of the N-channel MOS transistor 308 and one end of the capacitor element 315, and the non-inverting input terminal is connected to the source of the N-channel MOS transistor 306 and one end of the capacitor element 314. The other end of the capacitor element 314 and the other end of the capacitor element 315 are grounded.

[0217] The output terminal of the comparator 310 is connected to the input terminal of the CMOS inverter 311 and the gate of the N-channel MOS transistor 313, and the output terminal of the CMOS inverter 311 is connected to the input terminal of the CMOS inverter 312. The source and the drain of the N-channel MOS transistor 313 are connected to one end and the other end of the variable resistor 303, respectively.

[0218] In the thus configured oscillation detection circuit 80, the gate of the N-channel MOS transistor 306 is input with a voltage V2 = Vreg x (Rl + R2) / (Rl + R2 + R3) obtained by dividing the voltage Vreg by the variable resistors 302, 303, 304. Rl, R2, R3 are the resistance values of the variable resistors 302, 303, 304, respectively. Further, the gate of the N-channel MOS transistor 306 is input with a voltage VI obtained by adding the voltage Vreg x Rl / (Rl + R2 + R3) obtained by dividing the voltage Vreg by the variable resistors 302, 303, 304 and the alternating component obtained by removing the direct component of the signal input from the XI terminal by the capacitor element 301. Therefore, the inverting input terminal of the comparator 310 is input with the voltage V2 - V gs2 , and the non-inverting input terminal of the comparator 310 is input with the voltage VI - V gs1 . V gs1 is the voltage between the gate and the source of the N-channel MOS transistor 306, and V gs2 is the voltage between the gate and the source of the N-channel MOS transistor 308.

[0219] The comparator 310 outputs a signal of low level when the voltage VI - V gs1 is lower than the voltage V2 - V gs2 , and outputs a signal of high level when the voltage VI - V gs1 is higher than the voltage V2 - V gs2The comparator 310 outputs a high-level signal. The output signal of comparator 310 is inverted by CMOS inverter 311, and then by CMOS inverter 312. The output signal of CMOS inverter 312 is then output as the detection signal DET to logic circuit 42. Therefore, the logic level of the detection signal DET is the same as the logic level of the output signal of comparator 310. Thus, the detection signal DET outputs a high-level signal at voltages V1-V2. gs1 Below voltage V2-V gs2 When it is low level, at voltage V1-V gs1 Higher than voltage V2-V gs2 The voltage is high at this time. At the start of the startup mode, the amplitude of the signal output from oscillator 3 and input from terminal XI is zero; therefore, the voltage V1-V... gs1 Below voltage V2-V gs2 Therefore, the detection signal DET is low. As the amplitude of the signal input from terminal XI increases, instantaneous voltage fluctuations are suppressed by capacitors 314 and 315, and the voltage V1-V gs1 The DC level rises. Then, at voltage V1-V gs1 Higher than voltage V2-V gs2 When the comparator 310 output signal changes to a high level, the detection signal DET also changes to a high level. When the detection signal DET changes from a low level to a high level, the logic circuit 42 sets the negative resistance value |nR| of the oscillation circuit 10 to the first value |nR1|. Furthermore, when the comparator 310 output signal becomes high, the drain-source of the N-channel MOS transistor 313 is turned on, the difference between voltage V1 and voltage V2 disappears, the comparator 310 output signal remains high, and the detection signal DET also remains high.

[0220] According to the oscillation detection circuit 80, the voltages V1 and V2 are not determined by the absolute values ​​of the variable resistors 302, 303, and 304, nor by the absolute values ​​of the resistance values ​​R1, R2, and R3, but by the ratio. Therefore, the error of the voltages V1 and V2 caused by the manufacturing error of the variable resistors 302, 303, and 304 is reduced, and the amplitude of the signal output from the oscillator 3 can be detected with high precision.

[0221] The other structures of the oscillator 1 in the fifth embodiment are the same as those in the embodiments described above, therefore, its illustrations and descriptions are omitted.

[0222] Figure 24 This is a waveform diagram illustrating another example of the sequence of transition from the oscillation circuit 2 to the normal operating mode after power is turned on in the fifth embodiment. Figure 24In the example, when oscillator 1 is powered on, the reset period T1 begins, the power supply voltage Vdd rises from 0V to the specified voltage value, the power-on reset signal POR changes from low to high, and logic circuit 42 is initialized. Then, the power-on reset signal POR changes from high to low, thus ending the reset period T1, and the memory loading period T2 begins.

[0223] During memory loading period T2, various information stored in non-volatile memory 71 is transferred to register 72. After this transfer is completed, logic circuit 42 causes the oscillation enable signal en_osc to change from low level to high level, thereby ending memory loading period T2 and starting startup period T3.

[0224] During startup (T3), logic circuit 42 first sets and holds the capacitor adjustment data trimC1[4:0] and trimC2[4:0] to their starting values, and then increases the current adjustment data trimI[4:0] in stages from the starting value to the ending value in arbitrary increments. Simultaneously, the value of the oscillation stage current Iosc increases in stages. The starting and ending values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0], and the current adjustment data trimI[4:0], can be set to arbitrary values, for example, by pre-writing them into the non-volatile memory 71. Figure 24 In the example, logic circuit 42 sets the capacitor adjustment data trimC1[4:0] and trimC2[4:0] to the starting value 0 and holds them, while the current adjustment data trimI[4:0] increases in stages from the starting value 0 in units of 1 to the ending value 31. As a result, with capacitor values ​​C1 and C2 at 31C0, the oscillation stage current Iosc increases from the third value I... b It increases in a stepwise manner to the 4th value I b +31I0, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner starting from the second value |nR2|.

[0225] Next, after changing the current adjustment data trimI[4:0] to the starting value 0, logic circuit 42 increases the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] by arbitrary values. Figure 24 In the example, the values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] are set to 1, which is obtained by increasing by 1 from 0, and are maintained. Then, the current adjustment data trimI[4:0] is increased in stages from the starting value of 0 in units of 1 to the ending value of 31. As a result, when the capacitor values ​​C1 and C2 are reduced to 30C0, the oscillation stage current Iosc increases from the 3rd value I... bIt increases in a stepwise manner to the 4th value I b +31I0, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner.

[0226] Next, after changing the current adjustment data trimI[4:0] to the starting value 0, logic circuit 42 increases the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] by arbitrary values. Figure 24 In the example, the values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] are set to 2, which is obtained by increasing 1 from 1, and held. Then, the current adjustment data trimI[4:0] is increased in stages from the starting value of 0 in units of 1 to the ending value of 31. As a result, when the capacitor values ​​C1 and C2 are reduced to 29C0, the oscillation stage current Iosc increases from the 3rd value I b It increases in a stepwise manner to the 4th value I b +31I0, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner. When the negative resistance value |nR| is greater than R... Lm And less than R Ls At this time, oscillator 3 begins to resonate with the main vibration, and the amplitude of the current I_xtal output from oscillator 3 increases. Then, when the amplitude of current I_xtal exceeds a specified threshold, a pulse is generated in the oscillation signal CK. In addition, when the amplitude of current I_xtal output from oscillator 3 reaches a specified value, for example, when the value of current adjustment data trimI[4:0] is 9 and the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] are both 2, the detection signal DET changes from low level to high level.

[0227] Next, in response to the detection signal DET becoming high, logic circuit 42 causes the value of the current adjustment data trimI[4:0] to change in stages, in arbitrary units, to the set value in the normal operating mode. Figure 24 In the example, when the detection signal DET becomes high, the value of the current adjustment data trimI[4:0] is 9. Therefore, the logic circuit 42 causes the value of the current adjustment data trimI[4:0] to increase in stages from 9 in units of 1. Then, when the value of the current adjustment data trimI[4:0] reaches the value 24 transferred to register 72 during memory load T2, the logic circuit 42 keeps the value of the current adjustment data trimI[4:0] at 24, and the value of the oscillator current Iosc becomes I b +24I0. Furthermore, logic circuit 42 causes the values ​​of capacitor adjustment data trimC1[4:0] and trimC2[4:0] to be changed in stages, in arbitrary units, to the set values ​​in the normal operating mode. Figure 24In the example, when the detection signal DET becomes high, the values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] are 2. Therefore, the logic circuit 42 increases the values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] in stages starting from 2, in increments of 1. Then, when the values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] reach the value 26 transferred to register 72 during memory loading T2, the logic circuit 42 keeps the values ​​of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] at 26, and the capacitor values ​​C1 and C2 become 5C0. The value of the oscillation stage current Iosc becomes I b +24I0, and the capacitance values ​​C1 and C2 both become 5C0. Therefore, the negative resistance value |nR| becomes the first value |nR1|. Before becoming the first value |nR1|, the negative resistance value |nR| is greater than R. Ls However, at this moment, the oscillation of the circuit 10 caused by the resonance in the main oscillation of the oscillator 3 has grown sufficiently, so the resonance in the secondary oscillation of the oscillator 3 will not occur. Then, the logic circuit 42 changes the output enable signal en_out from low level to high level, thereby ending the startup period T3 and starting the normal operation period T4.

[0228] During normal operation T4, the output enable signal en_out is high, so the oscillation signal CK is buffered, and a pulse is generated in the oscillation signal CKO.

[0229] Additionally, during startup T3, both the capacitor adjustment data trimC1[4:0] and trimC2[4:0] are increased, thereby decreasing the capacitor values ​​C1 and C2. However, it is also possible to fix one of the capacitor adjustment data trimC1[4:0] and trimC2[4:0] and increase the other, thereby fixing the capacitor values ​​C1 and C2 and decreasing the other.

[0230] In addition, Figure 24 In the example, the operation mode during startup period T3 is startup mode, and the operation mode during normal operation period T4 is normal operation mode. Alternatively, the operation modes during reset period T1, memory load period T2, and startup period T3 are startup mode.

[0231] A flowchart showing the steps of the control method for the oscillating circuit 2 in the fifth embodiment and Figure 12 The same applies, therefore, its illustrations and descriptions are omitted. However, in the fifth embodiment, Figure 12 The startup step S3 differs from the steps described in the above embodiments.

[0232] Figure 25 is a flowchart showing an example of the step of starting step S3 in the fifth embodiment. Figure 12 Figure 25 The steps shown correspond to the actions during the start T3 of Figure 24 As shown in Figure 25 , first, in step S501, the logic circuit 42 sets the current adjustment data triml[4:0] and the capacitance adjustment data trimCl[4:0], trimC2[4:0] to start values. In the example of Figure 24 , the start value of the current adjustment data triml[4:0] is 0, and the start values of the capacitance adjustment data trimCl[4:0], trimC2[4:0] are 0. By setting the current adjustment data triml[4:0] and the capacitance adjustment data trimCl[4:0], trimC2[4:0] to the start values, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0233] Next, in step S502, when a predetermined time elapses, in step S503, if the detection signal DET is at the low level, in step S504, the logic circuit 42 determines whether the value of the current adjustment data triml[4:0] is identical to the end value. In the example of Figure 24 , the end value of the current adjustment data triml[4:0] is 31.

[0234] In the case where the value of the current adjustment data triml[4:0] is not identical to the end value in step S504, in step S505, the logic circuit 42 changes the value of the current adjustment data triml[4:0] so that the oscillation stage current Iosc increases.

[0235] As long as the detection signal DET is at the low level in step S503, the steps S502, S504, S505 are repeated until the value of the current adjustment data triml[4:0] is identical to the end value, and when the value of the current adjustment data triml[4:0] is identical to the end value, in step S506, the logic circuit 42 determines whether the values of the capacitance adjustment data trimCl[4:0], trimC2[4:0] are respectively identical to the end values. In the example of Figure 24 , the end values of the capacitance adjustment data trimCl[4:0], trimC2[4:0] are both 31.

[0236] ​In the case where the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] do not coincide with the end values in step S506, the logic circuit 42 sets the current adjustment data triml [4:0] to the start value in step S507. Further, the logic circuit 42 changes the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] so that the capacitance values Cl, C2 are reduced, respectively, in step S508.

[0237] As long as the detection signal DET is at the low level in step S503, steps S502, S504, S505, S506, S507, and S508 are repeated until the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] coincide with the end values.

[0238] In the case where the detection signal DET is at the high level in step S503, or in the case where the values of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] coincide with the end values in step S506, the logic circuit 42 changes the current adjustment data triml [4:0] to the set value in the normal operation mode in step S509. Further, the logic circuit 42 changes the capacitance adjustment data trimCl [4:0], trimC2 [4:0] to the set values in the normal operation mode in step S510.

[0239] Then, the logic circuit 42 sets the output enable signal en_out to the high level in step S511, and the start-up of step S3 ends.

[0240] Further, the logic circuit 42 can fix the value of one of the capacitance adjustment data trimCl [4:0], trimC2 [4:0] and change the value of the other, thereby fixing one of the capacitance values Cl, C2 and reducing the other.

[0241] Further, Figure 24 and Figure 25 The sequence and flowchart corresponding to the case where the oscillation detection circuit 80 is added to the oscillator 1 of the 4th embodiment. Although the illustration of the sequence and flowchart is omitted, the oscillation detection circuit 80 can be added to the oscillators 1 of the 1st to 3rd embodiments.

[0242] In the oscillator 1 of the 5th embodiment described above, in the start-up mode, when the oscillation detection circuit 80 detects that the signal output from the vibrator 3 becomes a prescribed amplitude or more, the negative resistance value |nR| is set to the 1st value |nRl| and shifted to the normal operation mode, and thus it is possible to shorten the start-up time.

[0243] 6. 6th Embodiment

[0244] Hereinafter, regarding the oscillator 1 of the sixth embodiment, the same reference numerals will be used for structures that are the same as those in any of the above embodiments, and descriptions that are the same as those in any of the above embodiments will be omitted or simplified. The descriptions will mainly focus on the contents that are different from those in any of the above embodiments.

[0245] The structure of the oscillator 1 in the sixth embodiment is similar to Figures 1-4 The structure is the same as that of the oscillation circuit 10 in the fourth embodiment, therefore its illustration and description are omitted. Furthermore, the structure of the oscillation circuit 10 in the fourth embodiment is the same as... Figure 5 Since they are the same, their illustrations and descriptions are omitted.

[0246] In the above embodiments, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled according to the weighted multi-bit control data output from the control circuit 40.

[0247] For example, in the first or fourth embodiment, in the startup mode, the negative resistance value |nR| is controlled by the current adjustment data trimI[4:0], which has a higher weight for larger bits. For example, when the logic level of trimI[0] is reversed, the oscillator current Iosc increases or decreases by I0, and conversely, when the logic level of trimI[4] is reversed, the oscillator current Iosc increases or decreases by 16×I0. Therefore, for example, when the current adjustment data trimI[4:0] changes from 15 to 16, assuming that before trimI[0], trimI[1], trimI[2], and trimI[3] change from high to low levels respectively, and when trimI[4] changes from high to low levels, the oscillator current Iosc also increases instantaneously by 16×I0. Thus, when the negative resistance value |nR| is greater than the load when the oscillator 3 resonates with secondary vibration, the series resistance value R is increased. Ls At that time, the risk of abnormal oscillations caused by the resonance of oscillator 3 with secondary vibration increases.

[0248] Further, for example, in the second embodiment or the fourth embodiment, the negative resistance value |nR| is controlled by the control data, i.e., the capacitance adjustment data trimC1[4:0], trimC2[4:0], whose weight is larger as the bit is larger. For example, when the logic level of trimC1[0], trimC2[0] is inverted, the capacitance values C1, C2 are increased or decreased by CO, respectively, and, in contrast, when the logic level of trimC1[4], trimC2[4] is inverted, the capacitance values C1, C2 are increased or decreased by 16xCO, respectively. Therefore, for example, when the capacitance adjustment data trimC1[4:0], trimC2[4:0] is changed from 15 to 16, the capacitance value C1 is also temporarily increased by 16xCO, assuming that trimC1[4] is changed from high to low before trimC1[0], trimC1[1], trimC1[2], trimC1[3] are changed from high to low, respectively. Thus, when the negative resistance value |nR| is larger than the value of the series resistance R at the time when the oscillator 3 resonates with the sub vibration, the risk of abnormal oscillation of the oscillator 3 resonating with the sub vibration increases. The same can be said of the capacitance adjustment data trimC2[4:0]. Ls b b Therefore, in the sixth embodiment, in order to reduce the risk of abnormal oscillation, the control circuit 40 is configured so that the bit whose weight is smaller in the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 in the startup mode is changed in the logic level earlier.

[0250] Figure 26 is a diagram showing a configuration example of the control circuit 40 in the sixth embodiment. Figure 26 A configuration example of the control circuit 40 when the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 in the startup mode is the current adjustment data trimI[4:0] is shown. In the example of Figure 26 , the control circuit 40 includes the logic circuit 42 and ten delay circuits 411, 421, 422, 431, 432, 433, 441, 442, 443, 444. Also, as in each of the above embodiments, the control circuit 40 includes the voltage control circuit 41, but, in Figure 26 , the illustration is omitted.

[0251] ​The logic circuit 42 outputs current adjustment data trimIX[4:0]. trimIX[0] is output as trimI[0]. trimIX[1] is output as trimI[1] after being propagated in the delay circuit 411. trimIX[2] is output as trimI[2] after being propagated in the delay circuits 421, 422. trimIX[3] is output as trimI[3] after being propagated in the delay circuits 431, 432, 433. trimIX[4] is output as trimI[4] after being propagated in the delay circuits 441, 442, 443, 444.

[0252] For example, as shown in FIG. 4, the delay circuits 411, 421, 422, 431, 432, 433, 441, 442, 443, 444 are circuits in which four CMOS inverters 401, 402, 403, 404 are connected in series. Note that the number of CMOS inverters is not limited to four, but can be an even number. Figure 27

[0253] Figure 28 FIG. 6 is a diagram showing an example of waveforms of the bits of the current adjustment data trimIX[4:0], trimI[4:0]. In the example of FIG. 6, waveforms of the bits of the current adjustment data trimIX[4:0] when trimIX[4:0] changes from 15 to 16 are shown. Figure 28

[0254] In the example of FIG. 6, the logic levels of the bits of the current adjustment data trimIX[4:0] change simultaneously at time t1. Specifically, trimIX[0], trimIX[1], trimIX[2], trimIX[3] change from high levels to low levels, and trimIX[4] changes from a low level to a high level. Figure 28

[0255] ​​​The trimIX[0] is not propagated in the delay circuit and is output as the trimI[0], and thus, at the time t1, the trimI[0] changes from the high level to the low level. Further, after the time t1, the low level of the trimIX[1] is propagated in the delay circuit 411, and at the time t2, the trimI[1] changes from the high level to the low level. Further, after the time t1, the low level of the trimIX[2] is propagated in the delay circuits 421, 422, and at the time t3, the trimI[2] changes from the high level to the low level. Further, after the time t1, the low level of the trimIX[3] is propagated in the delay circuits 431, 432, 433, and at the time t4, the trimI[3] changes from the high level to the low level. Further, after the time t1, the high level of the trimIX[4] is propagated in the delay circuits 441, 442, 443, 444, and at the time t5, the trimI[4] changes from the low level to the high level.

[0256] Thus, the current adjustment data trimI[4:0] output to the oscillation circuit 10 changes in the logic level earlier in the order of the trimI[0], the trimI[1], the trimI[2], the trimI[3], the trimI[4] for the bit having a smaller weight.

[0257] Further, although not illustrated, in the start-up mode, the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 is the control circuit 40 in the case of the capacitance adjustment data trimC1[4:0], trimC2[4:0] is also configured similarly. Figure 26

[0258] The other structure of the oscillator 1 of the 6th embodiment is the same as that of each of the above embodiments, and thus, the illustration and the explanation thereof are omitted.

[0259] In the oscillator 1 of the 6th embodiment described above, in the start-up mode, the bit having a smaller weight of the current adjustment data trimI[4:0] or the capacitance adjustment data trimC1[4:0], trimC2[4:0] changes in the logic level earlier when the negative resistance value |nR| of the oscillation circuit 10 is increased. Thus, according to the oscillator 1 of the 6th embodiment, when the negative resistance value |nR| of the oscillation circuit 10 is increased, the negative resistance value |nR| does not increase abruptly in transition, and thus, the possibility of the abnormal oscillation due to the growth of the oscillation based on the resonance in the secondary vibration of the vibrator 3 is reduced.

[0260] 7. 7th Embodiment

[0261] ​Next, regarding the oscillator 1 of the seventh embodiment, the same reference numerals are assigned to the same structures as those in any of the above embodiments, and the same explanation as that in any of the above embodiments is omitted or simplified, and mainly the contents different from those in any of the above embodiments are explained.

[0262] The structure of the oscillator 1 of the seventh embodiment is the same as that of the Figures 1-4 sixth embodiment, and therefore, the illustration and explanation thereof are omitted.

[0263] In each of the above embodiments, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled in accordance with the weighted plurality of bits of the control data output from the control circuit 40. Therefore, as described above, except for the sixth embodiment, the risk of the resonator 3 resonating with the sub vibration to generate abnormal oscillation rises.

[0264] Therefore, in the seventh embodiment, in order to reduce the risk of generating abnormal oscillation, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled in accordance with the unweighted plurality of bits of the control data output from the control circuit 40. The unweighted plurality of bits of the control data can be data represented by a thermometer code.

[0265] For example, in the startup mode, the oscillation stage current Iosc output from the variable current source 12 of the oscillation circuit 10 is controlled in accordance with the unweighted 32 bits of the current adjustment data triml [31 :0], and thereby, the negative resistance value |nR| can also be controlled. Further, for example, in the startup mode, the capacitance values Cl, C2 of the variable capacitance circuits 14, 15 of the oscillation circuit 10 are controlled in accordance with the unweighted 32 bits of the capacitance adjustment data trimcl [31 :0], trimc2 [31 :0], and thereby, the negative resistance value |nR| can also be controlled.

[0266] Figure 29 is a diagram showing a structure example of the variable current source 12 controlled by the unweighted 32 bits of the current adjustment data triml [31 :0]. In Figure 29 the example of the variable current source 12, the variable current source 12 includes a current source 135, 32 current sources 136-0 to 136-31, 32 switching elements 137-0 to 137-31, and two P-channel MOS transistors 133, 134.

[0267] The gate and the drain of the P-channel MOS transistor 133 are connected, and the source is supplied with a voltage Vreg. The gate of the P-channel MOS transistor 134 is connected to the gate of the P-channel MOS transistor 133, the source is supplied with the voltage Vreg, and the drain is connected to the collector of the amplifying element 11 of the Figure 5

[0268] ​One end of the current source 135 is connected to the drain of the P-channel MOS transistor 133, and the other end is grounded, through which a fixed bias current I flows. b For each integer i above 0 and below 31, one end of current source 136-i is connected to the drain of P-channel MOS transistor 133 via switching element 137-i, and the other end is grounded. When switching element 137-i is in the on state, a fixed current I0 flows through it. For example, current sources 135, 136-0 to 136-31 can be configured using depletion-type N-channel MOS transistors, or they can be configured using a current mirror circuit.

[0269] For each integer i above 0 and below 31, the control terminal of switching element 137-i is adjusted by the data trimI[i] of bit i in the input current adjustment data trimI[31:0]. It is turned on when data trimI[i] is high and turned off when data trimI[i] is low. For example, switching elements 137-0 to 137-31 can be N-channel MOS transistors or transmission gates.

[0270] Figure 30 This shows the values ​​of each bit in the current adjustment data trimI[31:0] and from... Figure 29 The graph shows the relationship between the values ​​of the oscillation stage current Iosc output by the variable current source 12. Each bit 0 corresponds to a low level, and each bit 1 corresponds to a high level. For example, when bit 0 of the current adjustment data trimI[31:0] is 1 and bits 1 to 31 are 0, only the switching element 137-0 is turned on, resulting in an oscillation stage current Iosc = I... b +I0. Furthermore, for example, when bits 0 and 1 of the current adjustment data trimI[31:0] are 1 and bits 2 to 31 are 0, only two switching elements 137-0 and 137-1 are turned on, resulting in an oscillation stage current Iosc = I. b +2I0. Generally speaking, when the number of bits with a value of 1 in the 32 bits of the current adjustment data trimI[31:0] is set to N, and the number of bits with a value of 0 is set to 32-N, the oscillation stage current Iosc = I b +N×I0. Figure 30 The code shown is one in which bits 0 through 31 are all 0, or bits 0 through 31 are all 1, or for any integer j above 0 and below 30, bits 0 through j are all 1 and bits j+1 through 31 are all 0. This type of code is called a thermometer code.

[0271] In addition, although not illustrated, in the start-up mode, the variable capacitance circuits 14, 15 and the codes of the capacitance adjustment data trimC1[31:0], trimC2[31:0] in the case where the capacitance values Cl, C2 of the variable capacitance circuits 14, 15 are controlled in accordance with the 32-bit capacitance adjustment data trimC1[31:0], trimC2[31:0] that are not weighted are also the same as Figure 29 Figure 30 is also similarly configured.

[0272] The other structure of the oscillator 1 of the seventh embodiment is the same as that of each of the above-described embodiments, and thus, the illustration and description thereof are omitted.

[0273] In the oscillator 1 of the seventh embodiment described above, in the start-up mode, when the negative resistance value |nR| of the oscillation circuit 10 is increased, the current adjustment data trimI[31:0] and the capacitance adjustment data trimC1[31:0], trimC2[31:0] are data that are not weighted, for example, data represented by a thermometer code. Therefore, according to the oscillator 1 of the seventh embodiment, when the negative resistance value |nR| of the oscillation circuit 10 is increased, the negative resistance value |nR| does not abruptly increase transitionally, and thus, the possibility of abnormal oscillation due to the growth of oscillation based on resonance in the secondary vibration of the vibrator 3 is reduced.

[0274] 8. Modification

[0275] In the oscillator 1 of the first embodiment or the fourth embodiment described above, the logic circuit 42 controls, in the start-up mode, so that the value of the oscillation stage current Iosc is increased in steps, and thus, the negative resistance value |nR| is increased in steps, but can also control so that the value of the oscillation stage current Iosc is continuously increased, and thus, the negative resistance value |nR| is continuously increased.

[0276] In addition, in the oscillator 1 of the second embodiment or the fourth embodiment described above, the logic circuit 42 controls, in the start-up mode, so that at least one of the capacitance values Cl, C2 of the variable capacitance circuits 14, 15 is increased in steps, and thus, the negative resistance value |nR| is increased in steps, but can also control so that at least one of the capacitance values Cl, C2 of the variable capacitance circuits 14, 15 is continuously increased, and thus, the negative resistance value |nR| is continuously increased.

[0277] ​Further, the oscillator 1 of each of the above-described embodiments is an oscillator having a frequency control function such as a VCXO (Voltage Controlled Crystal Oscillator), but can also be an oscillator having a temperature compensation function such as a TCXO (Temperature Compensated Crystal Oscillator), an oscillator having both a temperature compensation function and a frequency control function such as a VC-TCXO (Voltage Controlled Temperature Compensated Crystal Oscillator), a simple oscillator having neither a temperature compensation function nor a frequency control function such as an SPXO (Simple Packaged Crystal Oscillator), an oscillator having a temperature control function such as an OCXO (Oven Controlled Crystal Oscillator), or the like. The VCXO is an abbreviation for Voltage Controlled Crystal Oscillator. The TCXO is an abbreviation for Temperature Compensated Crystal Oscillator. The VC-TCXO is an abbreviation for Voltage Controlled Temperature Compensated Crystal Oscillator. The SPXO is an abbreviation for Simple Packaged Crystal Oscillator. The OCXO is an abbreviation for Oven Controlled Crystal Oscillator. In a case where the oscillator 1 is an oscillator having a temperature compensation function or an oscillator having both a temperature compensation function and a frequency control function, in the start-up mode, the temperature compensation circuit can also cause the capacitance value of the variable capacitance circuit to decrease, thereby causing the negative resistance value to increase.

[0278] The present application is not limited to the present embodiments, and various modifications can be made within the scope of the gist of the present application.

[0279] The above-described embodiments and modified examples are one example, and are not limited thereto. For example, each of the embodiments and each of the modified examples can be appropriately combined.

[0280] The present application includes structures substantially the same as the structures described in the embodiments, for example, structures identical in function, method, and result, or structures identical in purpose and effect. In addition, the present application includes structures obtained by substituting non-essential parts of the structures described in the embodiments. Furthermore, the present application includes structures that exert the same effects as the structures described in the embodiments or structures that can achieve the same purpose. In addition, the present application includes structures obtained by adding known techniques to the structures described in the embodiments.

[0281] According to the above-described embodiments and modifications, the following is derived.

[0282] One embodiment of an oscillation circuit includes an oscillation circuit connected to a vibrator, and a control circuit that controls the oscillation circuit, the oscillation circuit having a normal operation mode in which the oscillation circuit oscillates in a state where a negative resistance value becomes a first value, and a startup mode in which a state in which the oscillation circuit stops oscillating is shifted to the normal operation mode, the control circuit controlling in the startup mode in such a manner that the negative resistance value increases from a second value smaller than the first value.

[0283] In the oscillation circuit, in the startup mode in which a state in which the oscillation circuit stops oscillating is shifted to the normal operation mode in which the oscillation circuit oscillates in a state where a negative resistance value becomes a first value, the negative resistance value of the oscillation circuit increases from a second value smaller than the first value. The value R Lm of a series resistance when the vibrator 3 resonates in a sub vibration is smaller than the value R Ls Therefore, the negative resistance value of the oscillation circuit increases from the second value and becomes a value larger than R Lm and smaller than R Ls Therefore, in the startup mode, oscillation based on resonance in a main vibration of the vibrator grows first compared to oscillation based on resonance in a sub vibration of the vibrator. Therefore, according to the oscillation circuit, even if there is a deviation in characteristics of the connected vibrator, it is possible to reduce the possibility of abnormal oscillation.

[0284] In one embodiment of the oscillation circuit, the control circuit can control in the startup mode in such a manner that the negative resistance value increases in steps.

[0285] In the oscillation circuit, in the startup mode, the negative resistance value of the oscillation circuit increases from the second value in steps, and therefore, becomes a value larger than R Lm and smaller than R LsThe value of the time is longer. Therefore, the oscillation based on the resonance in the primary vibration of the oscillator grows earlier than the oscillation based on the resonance in the secondary vibration of the oscillator. Therefore, according to this oscillation circuit, even if there are deviations in the characteristics of the connected oscillator, the possibility of abnormal oscillations can be reduced.

[0286] In one embodiment of the oscillation circuit, the control circuit may control the operation in the startup mode by continuously increasing the negative resistance value.

[0287] In this oscillation circuit, during startup mode, the negative resistance value of the oscillation circuit continuously increases from the second value onwards, thus becoming greater than R. Lm And less than R Ls The value of the time is longer. Therefore, the oscillation based on the resonance in the primary vibration of the oscillator grows earlier than the oscillation based on the resonance in the secondary vibration of the oscillator. Therefore, according to this oscillation circuit, even if there are deviations in the characteristics of the connected oscillator, the possibility of abnormal oscillations can be reduced.

[0288] In one embodiment of the oscillation circuit, the first value may be greater than or equal to the maximum value of the negative resistance value in the startup mode.

[0289] According to this oscillation circuit, in the startup mode, the negative resistance value of the oscillation circuit is no greater than the first value. Therefore, the negative resistance value of the oscillation circuit becomes the value of the series resistance R when the oscillator resonates with the load during secondary vibration. Ls Larger values ​​have shorter durations, making it less likely for resonance to occur in the secondary oscillations of the oscillator.

[0290] In one embodiment of the oscillation circuit, the oscillation circuit may include an amplifying element and a variable current source that supplies current to the amplifying element, and the control circuit increases the value of the current in the startup mode, thereby increasing the value of the negative resistance.

[0291] According to this oscillation circuit, for example, in order to increase the negative resistance value of the oscillation circuit in the startup mode, a variable current source that is used in the normal operating mode to make the current supplied to the amplification element become a desired value corresponding to the resonant frequency of the oscillator can also be used.

[0292] In one embodiment of the oscillation circuit, the oscillation circuit may include a variable capacitor circuit connected to a node connected to the oscillator, wherein the control circuit reduces the capacitance of the variable capacitor circuit in the startup mode, thereby increasing the negative resistance value.

[0293] According to the oscillation circuit, for example, in order to increase the negative resistance value of the oscillation circuit in the startup mode, the variable capacitance circuit for making the oscillation frequency of the oscillation circuit a target frequency in the normal operation mode can be used.

[0294] In one embodiment of the oscillation circuit, the oscillation circuit can include an amplification element, a variable current source that supplies a current to the amplification element, and a variable capacitance circuit connected to a node connected to the vibrator, and the control circuit can increase the value of the current and decrease the capacitance value of the variable capacitance circuit in the startup mode, thereby increasing the negative resistance value.

[0295] According to the oscillation circuit, for example, in order to increase the negative resistance value of the oscillation circuit in the startup mode, the variable capacitance circuit for making the oscillation frequency of the oscillation circuit a target frequency in the normal operation mode can be used.

[0296] In one embodiment of the oscillation circuit, the control circuit can repeatedly perform control in which the value of the current is increased from a third value to a fourth value that is larger than the third value without changing the capacitance value, and then the capacitance value is decreased and the value of the current is changed to the third value in the startup mode.

[0297] According to the oscillation circuit, in the startup mode, the value of the current supplied to the amplification element is repeatedly increased from a third value to an upper limit value while the capacitance value of the variable capacitance circuit is changed, and thus it is possible to reduce the possibility that the capacitance value of the variable capacitance circuit is too large or the value of the current supplied to the amplification element is too small, and the oscillation circuit does not oscillate. Furthermore, in the oscillation circuit, the control circuit changes the value of the current supplied to the amplification element to the third value before decreasing the capacitance value of the variable capacitance circuit after increasing the value of the current supplied to the amplification element from the third value to a fourth value, and thus it is possible to reduce the possibility that the negative resistance value sharply increases when the capacitance value of the variable capacitance circuit is decreased, and the vibrator resonates in a side vibration.

[0298] One embodiment of the oscillation circuit can include an oscillation detection circuit that detects a case where a signal output from the vibrator becomes a prescribed amplitude or more in the startup mode and outputs a detection signal, and the control circuit can set the negative resistance value to the first value based on the detection signal.

[0299] According to the oscillation circuit, when the oscillation circuit is caused to oscillate in the startup mode, the negative resistance value is set to the first value and shifted to the normal operation mode, and thus it is possible to shorten the startup time.

[0300] In one mode of the oscillation circuit, the negative resistance value can be controlled in accordance with control data of a plurality of bits that are weighted, and the bit whose weight is smaller in the control data is the bit whose logic level changes earlier.

[0301] According to the oscillation circuit, when the negative resistance value of the oscillation circuit is increased, the negative resistance value does not increase abruptly in transition, and thus the possibility of abnormal oscillation due to growth of oscillation based on resonance in the secondary vibration of the vibrator is reduced.

[0302] In one mode of the oscillation circuit, the negative resistance value can be controlled in accordance with control data of a plurality of bits that are not weighted.

[0303] According to the oscillation circuit, when the negative resistance value of the oscillation circuit is increased, the negative resistance value does not increase abruptly in transition, and thus the possibility of abnormal oscillation due to growth of oscillation based on resonance in the secondary vibration of the vibrator is reduced.

[0304] In one mode of the oscillation circuit, the control data can be data represented by a thermometer code.

[0305] One mode of an oscillator has one mode of the oscillation circuit and the vibrator.

[0306] In the oscillator, in the startup mode in which the negative resistance value of the oscillation circuit is increased from a second value smaller than the first value to a value larger than R Lm and smaller than R Ls , until the normal operation mode in which the oscillation circuit is caused to oscillate with the negative resistance value being the first value, the vibrator resonates with the main vibration when the value of the series resistance R Lm when the vibrator 3 resonates with the secondary vibration. Ls Thus, the negative resistance value of the oscillation circuit is increased from the second value to a value larger than R Lm and smaller than R Ls . Thus, in the startup mode, oscillation based on resonance in the main vibration of the vibrator grows first compared to oscillation based on resonance in the secondary vibration of the vibrator. Thus, according to the oscillator, even if there is a deviation in the characteristics of the vibrator, it is possible to reduce the possibility of abnormal oscillation.

[0307] In one embodiment of the control method for an oscillating circuit, the oscillating circuit has an oscillation circuit connected to an oscillator, the oscillating circuit having a normal operating mode in which the oscillating circuit oscillates when the negative resistance value is a first value, and a start-up mode from which the oscillating circuit stops oscillating and transitions to the normal operating mode, wherein, in the start-up mode, the control is performed by increasing the negative resistance value from a second value smaller than the first value.

[0308] In the control method of this oscillation circuit, during the start-up mode, from the state where the oscillation circuit stops oscillating to the normal operating mode where oscillation occurs when the negative resistance value of the oscillation circuit reaches its first value, the negative resistance value of the oscillation circuit increases from a second value, which is smaller than the first value. The value R of the series resistance when the oscillator resonates with the main vibration under load. Lm The value of the series resistance R when the load is smaller than that of the oscillator 3 when it resonates with the secondary vibration is less than the value of the series resistance R. Ls Therefore, the negative resistance value of the oscillation circuit increases from the second value to become greater than R. Lm And less than R Ls The value of . Therefore, in the startup mode, the oscillation based on the resonance in the main vibration of the oscillator grows first compared to the oscillation based on the resonance in the secondary vibration of the oscillator. Therefore, according to the control method of this oscillation circuit, even if there is a deviation in the characteristics of the connected oscillator, the possibility of abnormal oscillation can be reduced.

Claims

1. An oscillation circuit, comprising: an oscillation circuit connected to an oscillator; and a control circuit that controls the oscillation circuit, the oscillation circuit having a normal operation mode in which the oscillation circuit operates with a negative resistance value being a first value, and a startup mode that is an operation mode from when power is turned on until the normal operation mode is shifted to, or an operation mode from when a standby mode is shifted to until the normal operation mode is shifted to, the oscillation circuit including an amplification element, a variable current source that supplies a current to the amplification element, and a variable capacitance circuit connected to a node connected to the oscillator, the control circuit repeatedly performing, in the startup mode, control that increases the value of the current from a third value to a fourth value that is larger than the third value without changing the capacitance value of the variable capacitance circuit, then decreases the capacitance value, and changes the value of the current to the third value, thereby controlling in such a manner that the negative resistance value increases from a second value that is smaller than the first value.

2. The oscillation circuit according to claim 1, wherein the control circuit controls in the startup mode in such a manner that the negative resistance value increases in steps.

3. The oscillation circuit according to claim 1, wherein the control circuit controls in the startup mode in such a manner that the negative resistance value continuously increases.

4. The oscillation circuit according to any one of claims 1 to 3, wherein the first value is larger than or equal to a maximum value of the negative resistance value in the startup mode.

5. The oscillation circuit according to any one of claims 1 to 3, wherein the oscillation circuit has an oscillation detection circuit that detects a case where a signal output from the oscillator becomes a prescribed amplitude or more in the startup mode and outputs a detection signal, and the control circuit sets the negative resistance value to the first value based on the detection signal.

6. The oscillation circuit according to any one of claims 1 to 3, wherein the negative resistance value is controlled based on control data of a plurality of bits that are weighted, and the bit whose weight is smaller changes its logic level earlier.

7. The oscillation circuit according to any one of claims 1 to 3, wherein the negative resistance value is controlled based on control data of a plurality of bits that are not weighted.

8. The oscillation circuit according to claim 7, wherein the control data is data represented by a thermometer code.

9. An oscillator, comprising: the oscillation circuit according to any one of claims 1 to 8; and the oscillator. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 10. A control method of an oscillation circuit having an oscillation circuit connected to an oscillator, the oscillation circuit including an amplifying element, a variable current source that supplies a current to the amplifying element, and a variable capacitance circuit connected to a node connected to the oscillator, the oscillation circuit having a normal operation mode in which the oscillation circuit oscillates in a state where a negative resistance value is a first value, and a startup mode, the startup mode being an operation mode from when power is turned on until the normal operation mode is shifted or an operation mode from when a standby mode is shifted until the normal operation mode is shifted, wherein in the startup mode, the following control is repeatedly performed: the value of the current is increased from a third value to a fourth value that is larger than the third value without changing a capacitance value of the variable capacitance circuit, then the capacitance value is decreased, and the value of the current is changed to the third value, whereby the control is performed in such a manner that the negative resistance value is increased from a second value that is smaller than the first value. ​

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