A high-precision capacitor-to-voltage converter based on hold error correction technology

Abstract

The invention discloses a high-precision capacitor-to-voltage converter based on a hold error correction technology, comprising: a voltage excitation source, an external capacitor sensor, a common-mode charge controller, a differential charge amplifier, a gain error corrector, and a hold error corrector; the voltage excitation source is used to generate an excitation signal to excite the external capacitor sensor to generate a charge signal; the common-mode charge controller is used to absorb the common-mode component in the charge signal to suppress the common-mode charge interference; the differential charge amplifier is used to convert the differential component of the charge signal into a voltage signal; the gain error corrector is used to correct the gain error generated by the differential charge amplifier; and the hold error corrector is used to correct the hold error in the gain error corrector. The invention can suppress the output voltage loss caused by the hold error and improve the gain accuracy.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a high-precision capacitor-to-voltage converter based on a hold error correction technology. Background Art

[0002] As semiconductor technology continues to advance and device size continues to shrink, the accuracy requirements for MEMS (Micro-Electro-Mechanical System) capacitive sensor interface circuits are becoming increasingly higher. However, modern high-efficiency amplifiers such as Inverter-based amplifiers (IBA) and Dynamic amplifiers (DA) cannot be used in high-precision MEMS capacitive sensor interface circuits due to their low open-loop gain.

[0003] Specifically, due to parasitic capacitance, the closed-loop feedback coefficient of the front-end amplifier of the interface circuit is very low (e.g. -40dB), which requires the amplifier to have a high gain (e.g. 80dB) to achieve low gain error (e.g. <1%) and low gain drift. However, the open-loop gain of high-efficiency amplifiers such as IBA is usually very low (e.g. around 30dB), and therefore cannot meet the gain error requirements. Even if the traditional MEMS capacitive sensor capacitance-to-voltage conversion circuit uses a gain error corrector to increase the equivalent gain, due to the retention error in the gain error corrector, it can actually only increase the equivalent gain by 2 orders (i.e. 30dB to 60dB), which still cannot meet the gain error requirements. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-precision capacitor-to-voltage converter based on a hold error correction technology. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] A high-precision capacitor-to-voltage converter based on a hold error correction technology, the converter comprising: a voltage excitation source, an external capacitor sensor, a common-mode charge controller, a differential charge amplifier, a gain error corrector, and a hold error corrector; wherein the voltage excitation source is connected to the external capacitor sensor and is used to generate an excitation signal to stimulate the external capacitor sensor to generate a charge signal; the common-mode charge controller is connected to the external capacitor sensor and is used to absorb the common-mode component in the charge signal to suppress common-mode charge interference; the differential charge amplifier is connected to the common-mode charge controller and is used to convert the differential component of the charge signal into a voltage signal; the gain error corrector is connected to the differential charge amplifier and is used to correct the gain error generated by the differential charge amplifier; the hold error corrector is connected to the gain error corrector and the differential charge amplifier and is used to correct the hold error in the gain error corrector.

[0006] In one embodiment of the present invention, the external capacitive sensor includes a first sensing capacitor and a second sensing capacitor; wherein one plate of the first sensing capacitor and one plate of the second sensing capacitor are connected to form a common electrode of the sensing unit; another plate of the first sensing capacitor and another plate of the second sensing capacitor respectively form a first differential electrode and a second differential electrode of the sensing unit, wherein the first differential electrode and the second differential electrode are connected to the input end of the differential charge amplifier to form a fully differential capacitor voltage structure.

[0007] In one embodiment of the present invention, the common-mode charge controller includes a common-mode amplifier and a common-mode feedback capacitor; the input end of the common-mode amplifier is connected across the first differential electrode and the second differential electrode; and the two differential feedback capacitors are connected across the output end of the common-mode amplifier, the first differential electrode and the second differential electrode.

[0008] Beneficial effects of the present invention:

[0009] The present invention can suppress the output voltage loss caused by the holding error and improve the gain accuracy.

[0010] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural schematic diagram of a high-precision capacitor-to-voltage converter based on a hold error correction technology provided by an embodiment of the present invention;

[0012] Figure 2 It is a schematic diagram of the charge-to-voltage conversion network circuit in a traditional capacitor-to-voltage converter;

[0013] Figure 3 It is a schematic diagram of a charge-to-voltage conversion network circuit in a capacitor-to-voltage conversion circuit based on a hold error correction technology provided by an embodiment of the present invention;

[0014] Figure 4 is a schematic diagram of a circuit structure of a hold error correction technology provided by an embodiment of the present invention;

[0015] Figure 5 The present invention provides a circuit diagram of the internal connection relationship of a capacitor-to-voltage converter using a two-stage holding error corrector.

[0016] Description of reference numerals:

[0017] 101-capacitance sensor; 102-voltage excitation source; 103-common mode charge controller; 104-differential charge amplifier; 105-hold error corrector; 106-gain error corrector; 201-hold error sampling network; 202-hold error correction network; 203-differential amplifier. DETAILED DESCRIPTION

[0018] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0019] See also Figure 2 , Figure 2 It is a schematic diagram of the charge-to-voltage conversion network circuit in a traditional capacitor-to-voltage converter.

[0020] The circuit architecture includes: a differential charge amplifier 104 and a gain error corrector 106, wherein the differential charge amplifier 104 is composed of an integral capacitor C I and differential amplifier A 0 The gain error corrector 106 is composed of a holding capacitor C H0 and calibration capacitor C C0 The interface circuit has two working phases Φ1 and Φ2. In the Φ1 phase of the first cycle, all capacitors including the sensing capacitor are set, and the output voltage is in a holding state under the action of the holding capacitor; in the Φ2 phase of the first cycle, the sensing capacitor in the capacitance sensor 101 is stepped by the opposite phase step voltage signal V through the differential port. R The charge signal representing the capacitance difference is transmitted to the differential charge amplifier. Ideally, the charge is integrated by the integral capacitor C I All are absorbed and converted into output voltage signals. The output voltage expression is:

[0021]

[0022] Where ΔC is the capacitance change of the sensing capacitor in the capacitive sensor under the stimulation of the physical signal, V R is the amplitude of the step voltage signal generated by the excitation source.

[0023] In actual situations, since the actual op amp gain is not infinite, gain error will occur, resulting in the output voltage value expression becoming:

[0024]

[0025] Among them, σ d is the deterioration factor, and its expression is:

[0026]

[0027] In the Φ1 phase of the second cycle, the capacitor C H0 and capacitor C C0 connected and form a feedback loop with the amplifier, so that the capacitor C H0The output voltage is sampled as the gain error and stored in the calibration capacitor C C0 As the operation cycle gradually increases, the error term is gradually absorbed, and the output gradually climbs to the ideal value, and its expression is:

[0028]

[0029] However, the actual response of the traditional capacitor-voltage conversion circuit still has a holding error phenomenon, that is, when switching from the Φ2 stage to the Φ1 stage, the holding capacitor C H0 The voltage jump occurs on the left plate of the output voltage, causing an unexpected level drop in the output voltage, so the output voltage value expression becomes:

[0030]

[0031] The percentage error of its gain accuracy is calculated as:

[0032]

[0033] It can be seen from formula (6) that the capacitance-voltage conversion circuit of the MEMS capacitive sensor has limited ability to improve the gain accuracy. Due to the existence of the hold error, the equivalent gain of the amplifier can only be increased by 2 orders, which cannot meet the gain error requirement.

[0034] In order to solve the problem that the capacitance-to-voltage conversion circuit of the traditional MEMS capacitive sensor has limited ability to improve gain accuracy, the present invention proposes a hold error correction technology to further improve gain accuracy by eliminating the hold error generated by the gain error corrector.

[0035] Example

[0036] See also Figure 1 , Figure 1 1 is a schematic diagram of a high-precision capacitor-to-voltage converter based on a hold error correction technology provided by an embodiment of the present invention, wherein the converter comprises:

[0037] Voltage excitation source 102 , external capacitance sensor 101 , common-mode charge controller 103 , differential charge amplifier 104 , gain error corrector 106 , hold error corrector 105 .

[0038] The voltage excitation source 102 is connected to the external capacitive sensor 101 and is used to generate an excitation signal to stimulate the external capacitive sensor to generate a charge signal.

[0039] It should be noted that the voltage excitation source generates a step voltage of a certain amplitude to excite the capacitive sensor, mainly a rectangular excitation.

[0040] The common-mode charge controller 103 is connected to the external capacitance sensor 101 and is used to absorb the common-mode component in the charge signal to suppress the common-mode charge interference.

[0041] The differential charge amplifier 104 is connected to the common-mode charge controller 103 and is used to convert the differential component of the charge signal into a voltage signal.

[0042] It should be noted that converting the differential component of the charge signal into a voltage signal can realize differential signal readout.

[0043] The gain error corrector 106 is connected to the differential charge amplifier 104 and is used to correct the gain error generated by the differential charge amplifier.

[0044] Specifically, the gain error of the differential charge amplifier is absorbed to improve the gain accuracy.

[0045] The hold error corrector 105 is connected to the gain error corrector 106 and the differential charge amplifier 104 and is used to correct the hold error in the gain error corrector.

[0046] Specifically, the holding error generated by the gain error corrector is absorbed to further improve the gain accuracy.

[0047] Optionally, the external capacitive sensor includes a first sensing capacitor and a second sensing capacitor.

[0048] One electrode plate of the first sensing capacitor is connected to one electrode plate of the second sensing capacitor to form a common electrode of the sensing unit.

[0049] The other plate of the first sensing capacitor and the other plate of the second sensing capacitor respectively form a first differential electrode and a second differential electrode of the sensing unit, wherein the first differential electrode and the second differential electrode are connected to the input end of the differential charge amplifier to form a fully differential capacitance-voltage structure, i.e., a fully differential CVC (Capacitance-to-voltage converter) structure.

[0050] Optionally, the common-mode charge controller includes a common-mode amplifier and a common-mode feedback capacitor.

[0051] An input terminal of the common mode amplifier is connected across the first differential electrode and the second differential electrode.

[0052] It should be noted that the common-mode charge controller is connected to two differential electrodes of the external capacitive sensor to read out the common-mode component in the charge signal and convert it into a common-mode voltage, thereby suppressing common-mode charge interference.

[0053] Two differential feedback capacitors are connected across the common-mode amplifier output, the first differential electrode, and the second differential electrode.

[0054] Optionally, the differential charge amplifier includes a charge-to-voltage conversion network and a differential amplifier.

[0055] The charge-to-voltage conversion network consists of an integral capacitor C I constitute.

[0056] The differential amplifier consists of a differential op amp A 0 constitute.

[0057] Optionally, the gain error corrector includes a holding capacitor C H0 and calibration capacitor C C0 .

[0058] Optionally, the hold error corrector includes two unit gain buffers and a sampling capacitor C H1 .

[0059] Optionally, the input and output ends of the hold error corrector are connected to the left plate of the hold capacitor of the differential charge amplifier.

[0060] Optionally, the common-mode charge controller is connected to an external capacitive sensor and includes:

[0061] The common mode charge controller is connected to the first differential electrode and the second differential electrode of the sensing unit of the external capacitive sensor.

[0062] See also Figure 3 , Figure 3 It is a schematic diagram of a charge-to-voltage conversion network circuit in a capacitor-to-voltage conversion circuit based on a hold error correction technology provided by an embodiment of the present invention.

[0063] The improved charge-to-voltage conversion network provided by the present invention is mainly composed of three parts: a differential charge amplifier 104, a gain error corrector 106 and a hold error corrector 105. A first-stage hold error corrector 105 is added to the internal structure of the traditional charge-to-voltage conversion network to eliminate the hold error in the gain error corrector to further improve the gain accuracy. The hold error corrector 105 consists of a unit gain amplifier and a hold capacitor C H1 The input and output ports are connected to the holding capacitor C H0 The left plate of the , through the clock signal and the switch to complete the error correction. Figure 1 In the conventional MEMS capacitive sensor capacitance-voltage conversion circuit structure shown in FIG, in the Φ2 stage, the capacitor C is maintained H0 The left plate is grounded, so the voltage value of the left plate is zero. At this time, the differential op amp input terminal, that is, the left plate of the Φ1 stage holding capacitor C H0The voltage value at the access position is not zero, so at the moment of switching between the Φ2 stage and the Φ1 stage, a voltage jump will occur on the left plate of the holding capacitor, resulting in voltage loss at the input port of the differential amplifier, and then the output voltage value will also be lost. This phenomenon is the holding error. H0 The left plate adds a hold error corrector. In the Φ1 stage, the input voltage value of the differential amplifier A0 is sampled to the hold error sampling capacitor C. H1 In the Φ2 phase, the sampled voltage is transferred to the holding capacitor C H0 The left plate keeps the capacitance C H0 The left plate voltage value is the same as the differential op amp input voltage value, which can avoid voltage jumps at the moment of transition between the Φ2 stage and the Φ1 stage, reduce output voltage loss, and improve gain accuracy.

[0064] See also Figure 4 , Figure 4 It is a schematic diagram of a circuit structure of a holding error correction technology provided by an embodiment of the present invention. Figure 4 This is an implementation scheme of the holding error corrector 105 proposed by the present invention, but the circuit implementation is not limited to this. The specific circuit of the holding error corrector 105 in this embodiment adopts the following Figure 4 The differential charge amplifier structure shown in the figure is composed of a holding error sampling network 201, a gain error correction network 202 and a differential amplifier 203. G The port is connected to the holding capacitor C in the main differential charge amplifier H0 The left plate of the circuit, in the Φ1 stage, switch Φ1 is closed, Φ2 is open, and the error sampling capacitor C is maintained. SH1 is charged to achieve error sampling; in the Φ2 stage, switch Φ2 is closed, Φ1 is disconnected, and the sampled voltage is output through the gain error corrector 202 and the differential amplifier 203, thereby raising the holding capacitor C H0 The left plate voltage is used to suppress the output voltage loss caused by the holding error.

[0065] Theoretically, the percentage error of gain accuracy after using a first-stage hold error corrector becomes:

[0066]

[0067] That is, theoretically, the equivalent gain of the amplifier can be increased by 4 orders after using a first-order hold error corrector.

[0068] Further, see Figure 5 , Figure 5 1 is a circuit diagram of the internal connection relationship of a capacitor voltage converter using a two-stage holding error corrector provided by an embodiment of the present invention. The two-stage error corrector 105 has the same internal structure, and the input port V G2Connect the holding capacitor C in the first stage H1 The left plate. Since the hold error corrector 105 itself also has a hold error, when the gain accuracy still cannot meet the requirements after using a first-stage hold error corrector 105, in order to further eliminate the hold error of the hold error corrector, a higher gain can be achieved by increasing the number of stages of the hold error corrector 105. Theoretically, the hold error can be infinitely reduced by nesting an infinite number of stages of hold error correctors 105, so that the gain accuracy percentage error infinitely approaches zero. Similarly, the input port V GN Connect to the holding capacitor C of the previous stage H(N-1) on the left side plate.

[0069] The capacitor voltage conversion circuit proposed in the present invention introduces a holding error corrector, which is used to hold the capacitor C H0 The left plate voltage rises to V O / A 1 , to suppress the output voltage loss caused by the holding error, thereby improving the gain accuracy. Specifically, the present invention can increase the equivalent gain by 4 orders (i.e., from 30dB to 120dB), making it possible to apply the high-efficiency amplifier to the high-precision MEMS capacitive sensor interface circuit.

[0070] In summary, the present invention is based on the hold error correction technology and introduces a hold error corrector, which can further improve the gain accuracy by correcting the hold error. Furthermore, by increasing the number of nested hold error correctors to achieve higher gain accuracy, in theory, nesting an infinite number of hold error correctors can infinitely reduce the hold error, so that the gain accuracy percentage error infinitely approaches zero.

[0071] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0072] In the present invention, unless otherwise clearly specified and limited, the term "connection" and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0073] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-precision capacitor-to-voltage converter based on a hold error correction technique, characterized in that: The converter comprises: voltage excitation source, external capacitance sensor, common mode charge controller, differential charge amplifier, gain error corrector, hold error corrector; wherein, The voltage excitation source is connected to the external capacitive sensor and is used to generate an excitation signal to stimulate the external capacitive sensor to generate a charge signal; The common-mode charge controller is connected to an external capacitive sensor to absorb the common-mode component in the charge signal to suppress common-mode charge interference; The differential charge amplifier is connected to the common-mode charge controller and is used for converting the differential component of the charge signal into a voltage signal; The gain error corrector is connected to the differential charge amplifier and is used to correct the gain error generated by the differential charge amplifier; The hold error corrector is connected to the gain error corrector and the differential charge amplifier, and is used to correct the hold error in the gain error corrector; wherein: The differential charge amplifier consists of an integrating capacitor C I , a differential amplifier A0, two first switches Φ1 and one second switch Φ2; The first ends of the two first switches Φ1 are both grounded, and the second ends are connected to the integral capacitors C I The first end and the second end are connected; The non-inverting input terminal of the differential amplifier A0 is grounded; the inverting input terminal of the differential amplifier A0 is connected to the gain error corrector; the output terminal of the differential amplifier A0 is connected to the second terminal of the second switch Φ2; The first end of the second switch Φ2 is connected to the integral capacitor C I A first end is connected; The hold error corrector is composed of a hold error sampling network, a gain error correction network and a differential amplifier; wherein: The holding error sampling network includes: a first switch Φ1 and a holding error sampling capacitor C SH1 The first end of the first switch Φ1 in the holding error sampling network is grounded, and the second end is connected to the holding error sampling capacitor C SH1 The first end of The error sampling capacitor C SH1 The second terminal is connected to V G Port connection; The gain error correction network includes: a first switch Φ1, two second switches Φ2, a capacitor C C1 and holding capacitor C H1 ; The capacitor C C1 The first end of the capacitor C is connected to the holding error sampling network; C1 The second end of is connected to the second end of the first switch Φ1 of the gain error correction network; A first end of the first switch Φ1 of the gain error correction network is connected to a second end of one of the two second switches Φ2; A first terminal of one of the two second switches Φ2 is grounded; The holding capacitor C H1 The first end of the holding capacitor C is connected to the first end of the first switch Φ1 of the gain error correction network; H1 The second end of is connected to the second end of the other second switch Φ2 of the two second switches Φ2; A first end of another second switch Φ2 of the two second switches Φ2 is connected to the holding error corrector; The differential amplifier comprises a differential amplifier A1, wherein the non-inverting input terminal of the differential amplifier A1 is grounded, the reverse input terminal is connected to the gain error correction network, and the output terminal is connected to the gain error correction network; The gain error corrector comprises: a holding capacitor C H0 , calibration capacitor C C0 and a first switch Φ1; The holding capacitor C H0 The first end of the capacitor C is connected to the differential charge amplifier. H0 The second end of the first switch Φ1 is connected to the second end of the first switch Φ1; The first end of the first switch Φ1 is connected to the calibration capacitor C C0 The second end of the first switch Φ1 is connected to the input voltage; In the Φ1 stage, the first switch Φ1 is closed and the second switch Φ2 is open, maintaining the error sampling capacitor C SH1 is charged to achieve error sampling; in the Φ2 stage, the second switch Φ2 is closed, the first switch Φ1 is opened, and the sampling voltage is output through the gain error corrector and the differential amplifier, thereby raising the holding capacitor C H0 The left plate voltage is used to suppress the output voltage loss caused by the holding error.

2. The converter according to claim 1, characterized in that The external capacitance sensor includes a first sensing capacitor and a second sensing capacitor; wherein, One electrode plate of the first sensing capacitor is connected to one electrode plate of the second sensing capacitor to form a common electrode of the sensing unit; Another plate of the first sensing capacitor and another plate of the second sensing capacitor respectively form a first differential electrode and a second differential electrode of the sensing unit, wherein the first differential electrode and the second differential electrode are connected to the input end of the differential charge amplifier to form a fully differential capacitor voltage structure.

3. The converter according to claim 2, characterized in that The common-mode charge controller includes a common-mode amplifier and a common-mode feedback capacitor; An input terminal of the common mode amplifier is connected across the first differential electrode and the second differential electrode; Two differential feedback capacitors are connected across the common-mode amplifier output, the first differential electrode, and the second differential electrode.

4. The converter according to claim 1, characterized in that The differential charge amplifier comprises a charge-to-voltage conversion network and a differential amplifier; wherein, The charge-to-voltage conversion network consists of an integrating capacitor C I constitute; The differential amplifier is composed of differential operational amplifier A0.

5. The converter according to claim 1, characterized in that The hold error corrector consists of two unity gain buffers and a sampling capacitor C H1 .

6. The converter according to claim 1, characterized in that The input and output ends of the holding error corrector are connected to the left plate of the holding capacitor of the differential charge amplifier.

7. The converter according to claim 1, characterized in that The common-mode charge controller is connected to an external capacitive sensor and comprises: The common mode charge controller is connected to the first differential electrode and the second differential electrode of the sensing unit of the external capacitive sensor.

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