Transposed convolution using systolic arrays

Abstract

In one example, a neural network accelerator can execute a set of instructions to: load a first weight data element from a memory into a systolic array, the first weight data element having a first coordinate; extract, from the instructions, information indicating a first subset of input data elements to be obtained from the memory, the first subset based on a stride of a transpose convolution operation and a second coordinate of the first weight data element in a rotated array of weight data elements; obtain the first subset of input data elements from the memory based on the information; load the first subset of input data elements into the systolic array; and control the systolic array to perform a first computation based on the first weight data element and the first subset of input data elements to produce an output data element of an array of output data elements.

Description

Technical Field Background Art

[0001] Artificial neural networks are computing systems with an architecture based on biological neural networks. They can be trained using training data to learn how to perform a computational task for an application.

[0002] Hardware accelerators such as neural network processors can be programmed to implement artificial neural networks to perform computational tasks. A common computational task is the convolution operation between a weight matrix and an input data matrix. In a convolution operation, the weight matrix can be traversed over the input data matrix in multiple strides and superimposed with the input data matrix until the entire input data matrix has been traversed. For each stride, the sum of the multiplications between the weight matrix and the superimposed portion of the input data matrix can be generated as the output of the convolution operation, and multiple outputs of the convolution operation can be generated at multiple strides. The convolution operation has many applications, such as extracting features from images, performing image recognition, etc.

[0003] There are various types of convolution operations that are used for other applications. One example is a transposed convolution, which can be based on a normal convolution operation between a rotated weight matrix and a dilated input data matrix. The transposed convolution operation has various applications. For example, the transposed convolution operation can be part of an upsampling operation, where the elements of the original input data matrix can be interpolated based on the rotated weight matrix to form an output data matrix. As another example, the transposed convolution can be part of a backpropagation operation during the training process for training the weights of the weight matrix. Summary of the Invention BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Various embodiments will be described according to the present disclosure with reference to the accompanying drawings, in which:

[0005] Figure 1 An example of a classifier apparatus for processing data using the techniques disclosed herein is presented;

[0006] Figures 2A-2F is a simplified block diagram illustrating predictive models and calculations using the techniques disclosed herein, according to certain aspects of the present disclosure;

[0007] Figure 3 shows an example implementation of the transposed convolution operation;

[0008] Figures 4A-4C An example neural network processor and its operation according to certain aspects of the present disclosure are presented;

[0009] Figures 5A-5D Demonstrates a method for normal convolution operations according to certain aspects of the present disclosure. Figures 4A-4C Operations at an example neural network processor;

[0010] Figures 6A-6G Demonstrates methods for transposed convolution operations according to certain aspects of the present disclosure. Figures 4A-4C Operations at an example neural network processor;

[0011] Figure 7A and Figure 7B Contains methods for supporting transposed convolution operations according to certain aspects of the present disclosure Figures 4A-4C a block diagram of additional features of an example neural network processor;

[0012] Figure 8 A block diagram illustrating an example of a host system according to certain aspects of the present disclosure is shown;

[0013] Figure 9 An example method for performing a dilated convolution operation at a neural network processor according to certain aspects of the present disclosure is presented;

[0014] Figure 10 An example method for generating instructions for a neural network processor to perform a transposed convolution operation according to certain aspects of the present disclosure is presented; and

[0015] Figure 11 Contains a diagram of an example network. DETAILED DESCRIPTION

[0016] Examples of the present disclosure relate to neural network processing, and more particularly, to performing transposed convolution operations at a neural network processor and hardware and / or software systems to support transposed convolution operations at the neural network processor.

[0017] Hardware accelerators such as neural network processors can be programmed to implement artificial neural networks to perform computational tasks. A common computational task is a convolution operation between a weight matrix configured as a filter and an input data matrix. The input data matrix can correspond to pixels of an image, and the filter can include an array of filter elements configured to, for example, extract target features from the image. As part of the convolution operation, the filter can traverse different positions of the image in multiple strides. At each stride position, the sum of the products between each filter coefficient and the overlapping pixels of the image can be generated as the convolution output for the stride position. The convolution output can indicate, for example, whether the image contains the target feature, the image position of the target feature, etc.

[0018] There are various types of convolution operations for other applications. One example is a transposed convolution, which can be based on a normal convolution operation between a rotated weight matrix and a dilated input data matrix. The transposed convolution operation has various applications. For example, the transposed convolution operation can be part of an upsampling operation. As part of the upsampling operation, the dilated input data matrix can be convolved with the rotated weight matrix to interpolate elements of the original input data matrix based on the rotated weight matrix to form new elements. The new elements can be included in the output data matrix to expand its size and number of elements relative to the original input data matrix. The transposed convolution operation can be performed in a neural network, where the weight coefficients can be trained to improve the interpolation operation. As another example, the transposed convolution can be part of a backpropagation operation in a neural network during training to train the weight matrix.

[0019] Despite its practicality, the transposed convolution operation may require a large number of memory operations, which may reduce the efficiency of the operation in the neural network processor. For example, to generate an expanded input data matrix, the elements of the original input data matrix may be copied from one set of locations in memory to another set of locations in memory, where zeros are inserted between the elements of the input data matrix at the new locations to form the expanded input data matrix. As another example, the elements of the weight matrix may be copied from one set of locations in memory to another set of locations in memory to perform a rotation. In these cases, the copying of the elements of the input data array, the insertion of zeros, and the copying of the weight matrix elements may require a large number of memory operations, which may reduce the performance of the neural network processor.

[0020] Examples of the present disclosure relate to neural network processing, and more specifically, to performing a transposed convolution operation at a neural network processor and hardware and / or software systems to support the transposed convolution operation at the neural network processor. The transposed convolution operation can be based on a normal convolution operation between a rotated weight data array and an expanded input data array. The rotated weight data array can be a 180-degree rotated version of the original weight data array, and the expanded input data array can be obtained by padding a plurality of zeros between adjacent input data elements of the original input data array. The number of zeros can be based on the stride of the transposed convolution operation. For example, in the case where the stride of the transposed convolution operation is two, each input data element can be surrounded by a zero (stride minus one) to expand the original input data array, and the convolution output can be generated by traversing the expanded output data array with the rotated weight data array having a stride of one in the normal convolution operation. The present disclosure relates to configuring a neural network processor to perform a normal convolution operation between the original weight data array and the original input data array to produce an output data array of the transposed convolution.

[0021] In some instances, the neural network processor includes a memory, a systolic array, a summing buffer, and a controller. The memory can store the input data elements of the original input data array and the weight data elements of the original weight data array. Both the input data array and the weight data array can be multidimensional. For example, the input data array can include one or more two-dimensional input data matrices, wherein each input data matrix corresponds to an input channel. In addition, the weight data array can include one or more two-dimensional weight data matrices, wherein each weight data matrix corresponds to an input channel and an output channel. The input data elements can be stored at addresses in the memory based on their coordinates in the original input data array, and the weight data elements can be stored at addresses in the memory based on their coordinates in the original weight data array.

[0022] To perform a transposed convolution operation, the controller may obtain a first weight data element from a memory based on a first coordinate of a first weight data element in the original weight data array and load the first weight data element into a systolic array. The first coordinate may be converted to a second coordinate by mapping a 180-degree rotation operation of a weight matrix representing the array of weight data elements. The controller may also select a first subset of input data elements of the original input data array based on an instruction and load the first subset of input data elements into the systolic array to calculate a first partial sum between the first weight data element and the first subset of input data elements. The selection may be based on the stride of the transposed convolution operation, the second coordinate obtained from the mapping, and size information of a summing buffer. Specifically, the first subset of input data elements loaded into the systolic array may represent input data elements of a dilated input array that overlap with the first weight data element when the rotated weight data array is at a different stride position relative to the dilated input data array, and a plurality of first partial sums generated from the first subset of input data elements may fit into the summing buffer. The first subset of input data elements were adjacent to each other in the original input data array before dilation. In addition, the first partial sum can be stored at a location within the summing buffer based on the second coordinate and the stride. The controller can control the systolic array to load other weight data elements and other subsets of the input data elements for other weight data elements to generate other partial sums. The partial sums can be accumulated and / or superimposed in the summing buffer to generate output data elements of an output data array, which can also be multidimensional and can include multiple two-dimensional output data matrices corresponding to multiple output channels.

[0023] As described above, each subset of input data elements can be selected based on the following: the input data elements that overlap with the weight data elements in the transposed convolution operation ("overlapping input data elements") are determined based on the second coordinates of the weight data elements in the rotated array of the stride and the weight data elements. In addition, the position of the summing buffer for receiving the partial sums is also based on the stride and the second coordinate. The determination of the overlapping input data elements and the target for the partial sums in the summing buffer for the weight data elements can be performed by a compiler, which can encode the overlapping input data elements and the target information in the calculation instructions for the weight data elements. The controller can then execute the calculation instructions for the weight data elements.

[0024] In some instances, the neural network processor further includes a mechanism configured to generate zero output data elements when the stride of the transposed convolution operation is greater than the size of the weight data array, such that the dilated output data array is generated by inserting a plurality of zeros between input data elements that are greater than the size of the weight data array. For example, when the stride of the transposed convolution operation is two and zeros are padded between adjacent input data elements to form the dilated input data array, and the weight array including a single weight data element traverses the dilated input data array with a stride of one, the zero output data elements are generated at the stride position where the single weight data element overlaps with the padded zeros. To improve computational efficiency, the controller can control the summing buffer to output zeros for the zero output data elements without requiring the systolic array to calculate zero partial sums of the zero output data elements based on various techniques. For example, the controller can initialize the summing buffer to zero before computation of the output tile begins, so that the destinations of the summing buffer that do not receive partial sums from the systolic array during computation can output zeros. As another example, the summing buffer can include a register for each destination and a multiplexer controlled by the output of the register. The register may store an indication of whether the target received a partial sum (e.g., a write operation) during computation of the output tile. The register may be reset prior to the start of computation of the output tile. At the end of computation, when the summing buffer receives a read operation from the target, the summing buffer may reference the register of the target, and the multiplexer may be controlled to output the contents of the target or zero based on whether the register indicates that the target has received a partial sum (or write operation) during computation.

[0025] The determination of overlapping input data elements and the target of the partial sum can be based on a stride pattern, which can define a set of pattern coordinates where adjacent pattern coordinates are separated by a distance corresponding to the stride. For example, for a stride of two, adjacent pattern coordinates can be separated by a distance of one. For the first weight data element, the compiler can shift the stride pattern based on an offset according to the second coordinate (the rotated coordinate of the first weight data element) to determine the first area in the output data array corresponding to the target of the partial sum in the summing buffer. The size of the summing buffer (e.g., the number of columns and rows) can define the output tiles of the output data elements of the first area in the output data array. The compiler can shift the stride pattern relative to a reference position based on an offset based on the second coordinate. The reference position can be located at the first output data element of the output tile of the target mapped to the summing buffer, or at an imaginary position of the output data array with north fill and west fill mapped to the target of the summing buffer. The size of the summing buffer (e.g., the number of columns and rows) can also define a series of coordinates of the output data elements of the output tile. The compiler can compare the shifted pattern coordinates with the series of coordinates to determine a set of overlapping coordinates. The overlap coordinates may provide a target (e.g., an address) for a summing buffer to receive the first partial sum. The target may define a first region, and the count of targets may define a count of adjacent input data elements included in the first subset of input data elements. The compiler may encode first information indicating the target in the computation instruction. The first information may include, for example, a target address corresponding to a first overlap coordinate of the overlap coordinates of the output data element, a stride parameter based on a stride indicating a distance between adjacent targets, and the count of overlap coordinates.

[0026] The compiler can then determine the overlapping input data elements based on a projection operation from the first region back to the second region in the input data array. The compiler can calculate the third coordinate of the first input data element in the input data element in the expanded input data array based on the second coordinate of the first weight data element in the rotated weight data array, wherein the first input data element overlaps with the first weight data element when the rotated weight data array is located at the first stride position relative to the expanded input data array. As part of the projection operation, the compiler can scale the third coordinate by the inverse of the stride to determine the fourth coordinate of the first input data element of the original input data array, and the count of the target can provide a count of adjacent input data elements selected for the first subset starting from the fourth coordinate. The fourth coordinate and the count of the input data elements can define the second region. The compiler can encode second information indicating the fourth coordinate and the count of the input data elements in the calculation instruction. The second information can include, for example, a source address corresponding to the fourth coordinate and a count of adjacent input data elements selected from the original input data array.

[0027] Examples of the present disclosure can improve the efficiency of performing transposed convolution operations on a neural network processor by reducing memory operations. For example, the disclosed techniques can avoid additional memory operations involving copying elements of the original input data matrix in memory to generate a dilated input data matrix / array. In addition, the disclosed techniques can also avoid additional memory operations involving copying elements of the original weight data matrix in memory to generate a rotated weight data matrix / array. These can reduce the number of memory operations, which can reduce memory access latency and increase the speed of transposed convolution operations.

[0028] In the following description, various examples will be described. For purposes of explanation, specific configurations and details are set forth to provide a thorough understanding of the examples. However, it will be apparent to those skilled in the art that the examples can be practiced without these specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the embodiments being described.

[0029] Figure 1 An example classifier device 100 for processing data using the techniques disclosed herein is shown. The classifier device 100 can be, for example, a computing device that operates a software application 102 and a prediction model 103 to predict information contained in a data sequence and performs a predetermined function based on the prediction. For example, the classifier device 100 can be part of an image recognition service that is provided for identifying certain objects (e.g., text, people, etc.) from an image. It should be understood that the image recognition service is provided only as an illustrative example, and the techniques disclosed herein can be used for other data processing applications, including, for example, text-based data processing (e.g., processing of search queries), audio data processing, etc. In addition, the classifier device 100 can operate many different prediction models to process different input data in parallel or at different times.

[0030] In some instances, image recognition services can be provided in a multi-tenant computing service system. A multi-tenant computing service system can typically include multiple servers that can host data and be used by multiple clients or organizations to run instances, such as virtual machine instances or bare metal instances (e.g., operating systems running directly on server hardware). In most instances, such as bare metal or virtual machine instances, the multi-tenant computing service system can be allocated to a client when the client needs it and taken out of use when the client no longer needs it, so that resources can be reallocated to other clients. In this disclosure, the terms "tenant," "client," and "customer" are used interchangeably, but such terms do not necessarily imply the existence of any particular business arrangement. The term "instance" can refer to an instance that executes, for example, directly on server hardware or as a virtual machine. Different types of instances typically correspond to different hardware capabilities and / or hardware arrangements (e.g., different amounts of available memory and / or processing hardware). In Figure 1 In an example, the multi-tenant computing service system can provide image recognition services when a client needs them, and stop using them when the client no longer needs them, so that resources supporting the image recognition services (e.g., access to the software application 102 and the underlying hardware resources used to process the software application 102) can be reallocated to other clients. Different clients (or a single client) can require the application 102 to process different input data using the same or different prediction models, including the prediction model 103.

[0031] exist Figure 1 In an example, software application 102 may receive pixel data of image 104 from a user. Image 104 may include an array of pixels. Software application 102 may perform analysis on the pixel data and predict one or more objects 106 depicted in image 104. The analysis may include, for example, comparing the pixel data to a set of predetermined feature data. The predetermined feature data may include data associated with a set of predetermined visual image features, such as, for example, a nose object, a mouth object, etc. The predetermined feature data may also include data associated with non-visual image features or a combination of visual image features and non-visual image features. As will be discussed in more detail below, software application 102 may employ prediction model 103 to calculate a set of scores based on the pixel data of image 104. The set of scores may represent, for example, the likelihood that image 104 contains the image features represented by the feature data. Software application 102 may then determine other information about the content of image 104 based on the scores. For example, based on the scores, software application 102 may determine that image 104 is, for example, an image of a panda, a cat, or another object.

[0032] The prediction model 103 may be in the form of an artificial neural network. The artificial neural network may include a plurality of processing nodes, wherein each processing node is configured to process a portion of the input pixel data, or is configured to further process intermediate outputs from other processing nodes. Figure 1 An example of a predictive model 103 using the techniques disclosed herein is shown. Figure 1 In the example, the prediction model 103 may be a multi-layer neural network such as a deep neural network (DNN), a convolutional neural network (CNN), etc. The prediction model 103 may include an input layer 207, a set of intermediate layers including intermediate layers 209 and 211, and an output layer ( Figure 2A (not shown in FIG. 1 ). It should be understood that the prediction model 103 may also include other different types of neural networks, including, for example, long short-term memory (LSTM), multi-layer perceptron (MTP), multi-scale dense network (MSDNET), etc.

[0033] Layer 207 may process pixel data representing different portions of image 104. For example, Figure 2AIn the example of , layer 207 can process pixel data of image 204. Each processing node of layer 207 is assigned to receive a pixel value (e.g., x0, x1, x2, ... x) corresponding to a predetermined pixel within image 104. n ), and transmit one or more weights with the received pixel values ​​to layer 209. In the case where the prediction model 203 is a DNN, a set of weights defined based on the matrix W1 can be assigned to each processing node of layer 207. Each processing node of layer 207 can send the received pixel value and the assigned weight to each processing node of layer 209. In the case where the prediction model 103 is a CNN, the groups of processing nodes of layer 207 can share a set of weights, and each group can send the set of weights and the pixel values ​​received by the group of processing nodes to a single processing node of layer 209. Different neural network models can include different topologies (e.g., including a different number of layers, different connections between layers, etc.) and / or each layer can include a different set of weights.

[0034] Layer 209 may process the scaled outputs from layer 207 to produce a set of intermediate outputs. For example, assuming that processing node 210a of layer 209 is connected to n processing nodes in layer 207, processing node 210a may produce the sum of the scaled outputs received from layer 207 based on the following equation:

[0035]

[0036] Here, sum 210a W1 represents the intermediate output generated by processing node 210a. i ×x i represents the scaling of a particular pixel value (e.g., x0) by a processing node of layer 207 with an associated weight (e.g., W10). In the case where the prediction model 103 is a DNN, each processing node of layer 209 may generate a sum based on the scaling of the pixel values ​​from each processing node of layer 207, and then generate a sum (e.g., Sum) by summing the scaled pixel values. 210a ). The sum can also represent the dot product between an input vector comprising many elements (e.g., pixel values) and a weight vector (e.g., W1). In some instances, a bias can also be added to the scaled output to produce an intermediate output.

[0037] In the case where the prediction model 103 is a CNN, each processing node of the layer 209 may generate an intermediate output based on scaling pixel values ​​from a set of processing nodes of the layer 207. The intermediate output may represent a convolution result between a set of pixel values ​​and a filter including weight values. Figure 2B shows an example of a convolution operation that layer 209 can perform. Figure 2B, filter 230 may include a two-dimensional array of weights. The weights in filter 230 may represent the spatial distribution of pixels of certain features to be detected from the image. The two-dimensional array may be R rows high and S columns wide, and may typically be smaller than the input image, which is H pixels high and W pixels wide. Each weight may be mapped to a pixel in a rectangular block of pixel values ​​having the same R rows and S columns. A processing node of layer 209 (e.g., processing node 210a) may receive a group 240 of pixel values ​​corresponding to a first rectangular block of pixels from the input image corresponding to the first step position of filter 230 from a group of processing nodes of input layer 207, and generate a convolution output 242 based on the sum of the multiplication results between each weight of filter 230 and each corresponding pixel in group 240 according to Equation 1, thereby generating a dot product between the matrix represented by filter 230 and the matrix represented by group 240. Another processing node of layer 209 may also receive a group 244 of pixel values ​​corresponding to a second rectangular block of pixels from the input image corresponding to a second stride position of filter 230 from another group of processing nodes of input layer 207 and generate a convolution output 246 based on summing the multiplication results between each weight of filter 230 and each corresponding pixel in group 244 according to Equation 1, thereby generating a dot product between the matrix of filter 230 and the matrix represented by group 240. In some examples, Figure 2B Each convolution output (e.g., convolution output 242, convolution output 346, etc.) in layer 209 may correspond to an output of a processing node of layer 209. In some examples, pixel data in an input image may be referred to as an input feature map indicating that the pixel is processed by the same filter (or the same filter bank) corresponding to one or more features. A convolution output may be referred to as an output feature map indicating that the output is the result of processing the input feature map with the filter.

[0038] like Figure 2B As shown in , the convolution operations can be arranged in a sliding window so that the second rectangular block overlaps or is otherwise adjacent to the first rectangular block in the input image. Figure 2B In the example of , D can be the stride distance (in pixels) of the sliding window of each convolution operation, so that the pixel block corresponding to group 244 can be located at a distance D (in pixels) from the pixel block corresponding to group 240, and the next pixel block can also be located at the same distance D from group 244. Other processing nodes of layer 209 can also receive pixel groups corresponding to other rectangular blocks and generate other intermediate outputs. The convolution output can be part of the convolution output array. The convolution output array can have a smaller height and a smaller width than the input image. The rectangular blocks of convolution outputs can be further grouped, and a convolution operation can be performed at layer 211 between the convolution output group and another set of filter weights to generate another set of convolution outputs.

[0039] In some instances, a convolution operation may be performed between multiple images and multiple filters. For example, referring to Figure 2C , a set of C filters 260 may correspond to a plurality of (C) images 270, and a convolution operation may be performed between each filter in the set of filters 260 and a pixel block on a corresponding image of the image 270. Each image in the image 270 may correspond to an input channel. The convolution results of each filter-image pair may be summed to produce the following convolution output:

[0040]

[0041] Here, the convolution operation involves an image (or pixel array). c eD+r,fD+s may refer to the value of a pixel at index c within the plurality of (C) images 270 with row coordinates eD+r and column coordinates fD+s. For the remainder of this disclosure, the element X c eD+r,fD+s The coordinates of can be expressed in the form of (eD+r, fD+s). The index c can represent a specific input channel. D is the sliding window stride distance, and e and f correspond to the position of the data element in the convolution output array, which can also correspond to a specific sliding window. In addition, r and s correspond to specific positions within the sliding window. The pixel at the (r, s) position and the pixel of the image with index c can also correspond to the weight W in the corresponding filter with the same index c at the same (r, s) position. c r,s Equation 2 indicates that in order to calculate the convolution output O e,f , each pixel in the sliding window (indexed by (e, f)) can be multiplied by the corresponding weight W c r,s The partial sum of the multiplied products within each sliding window in each image within the image group may be calculated, and then the sum of the partial sums for all images of the image group may be calculated.

[0042] Furthermore, in some instances, a convolution operation can be performed on a set of images using multiple sets of filters to generate a set of convolution output arrays, each convolution output array corresponding to a set of filters. Each set of filters can correspond to an output channel. For example, multiple sets of filters can correspond to multiple features to be detected from the set of images, and each convolution output array can correspond to a detection result for each feature from the set of images. For example, where M sets of filters are applied to C images to generate M convolution output arrays, Equation 2 can be updated as follows:

[0043]

[0044] Here, the convolution output Oe,f m and weight W c,m r,s has an index m corresponding to one of the M sets of filters. The index m may represent a specific output channel.

[0045] Figure 2D An example of a C set of input data sets (where C = 3) to be convolved with M sets of filters (where M = 2) is shown. Each set of input data corresponds to an entry in a pixel array. Each set of filters in the M sets of filters contains a set of C filters corresponding to the C set of input pixel arrays. The convolution operation produces M sets of output data elements, where each set of output data elements corresponds to a convolution output array. Each convolution output array corresponds to convolving a set of filters (in the M sets) with the input pixel array. For example, O can be generated by the sum of the dot products between a set of pixels 282 and the filter array 284, the dot products between a set of pixels 286 and the filter array 288, and the dot products between a set of pixels 289 and the filter array 292. 0,0 0 .

[0046] Return Reference Figure 2A , a processing node of layer 209 can be configured to generate a convolution output element of a convolution output array, and the group M of processing nodes of layer 209 can correspond to the group M of convolution output array. The processing node of layer 209 can also process each convolution output with an activation function to generate an activation output. The activation function can convert the convolution output into a decision of whether to forward the convolution output to the intermediate layer 211 to influence the classifier decision (similar to triggering a biological neuron). An example of an activation function can be a rectified linear unit (ReLU) defined according to the following equation:

[0047]

[0048] In addition to ReLU, other forms of activation functions can also be used, including, for example, the softplus function (which can be a smooth approximation of the ReLU function), the hyperbolic tangent function (tanh), the inverse tangent function (arctan), the sigmoid function, the Gaussian function, etc.

[0049] A processing node of layer 209 (e.g., processing node 210a) may process the sum with a ReLU function to generate a first output of layer 209 based on the following equation:

[0050] first_output 210a =ReLU(Sum 210a )(Equation 5)

[0051] Layer 211 may further process the scaled intermediate output from layer 209 by, for example, performing additional convolution operations based on different sets of filters. The output from each processing node of layer 211 may be forwarded to other higher intermediate layers, or to the output layer ( Figure 2A (not shown). The output layer can form an output vector representing, for example, the probability that certain features are included in image 104 and / or the probability that image 204 contains an image of a panda. For example, the output vector can be compared with a reference vector associated with a panda's nose object or a reference vector associated with pandas. A decision as to whether image 104 is an image of a panda can be made based on the comparison results.

[0052] Figure 2B-2D The convolution operation can be used to support various types of convolution operations for various applications, such as transposed convolution operations. Figure 2E and Figure 2F shows an example of transposed convolution operation. Figure 2E and Figure 2F As shown, the transposed convolution operation can be based on a normal convolution operation between a rotated weight matrix, such as the rotated filter 260, and a dilated input data matrix, such as the dilated image 270. The rotated weight matrix can be formed by performing a 180-degree rotation of the original weight matrix (e.g., the original filter 260), which involves transposing the weight matrix along the vertical dimension (e.g., Figure 2E The R dimension in the ) flips the element and then moves it along the horizontal dimension (e.g. Figure 2E The mapping of the (r, s) coordinates of the original filter 260 having (r, s) coordinates between (0, 0) and (R-1, S-1) and the rotated filter 260 may be based on the following equation:

[0053] r rotate =R-1-r original (Equation 6)

[0054] s rotate =S-1-s original (Equation 7)

[0055] In Equation 6, r original represents the r coordinate of the filter element in the original filter 260, and r rotate represents the r coordinate of the filter element in the rotated filter 260. In addition, s original represents the s coordinate of the filter element in the original filter 260, and s rotate represents the s-coordinate of the filter element in the rotated filter 260. For example, Figure 2E As shown in FIG, the weight data element W in the original filter 260 0,0has coordinates (0, 0), but in the rotated filter 260, the same weight data element W 0,0 Has coordinates (2, 2).

[0056] Additionally, the expanded image 270 may be formed by inserting a number of zeros between each input data element of the original image 270. The number of zeros may be based on the stride of the transposed convolution operation. Figure 2E As shown, for a transposed convolution operation with a stride of 2, a zero (stride minus one) is inserted between each input data element of the original image 270 to form the dilated image 270, so that the first row (e.g., X 0,0 、X 0,1 A row of zeros is inserted along the H dimension between adjacent rows of input data elements above (north of) the original image 270 and below the last row of input data elements of the original image 270. In addition, a row of zeros is inserted along the H dimension between adjacent rows of input data elements above (north of) the original image 270 and below the last row of input data elements of the original image 270. 0,0 、X 1,0 A column of zeros is inserted between adjacent columns of input data elements and to the right of the last column of input data elements of the original image 270. Figure 2F As shown in , for a transposed convolution operation with a stride of 4, three zeros are inserted between each input data element of the original image 270 to form the dilated image 270.

[0057] A normal convolution operation may then be performed between the rotated filter 260 and the dilated image 270 to produce a convolution output array 280. A normal convolution operation may be performed by multiplying the image by 1 with a stride of Figure 2B D) is performed on the rotated filer 260 across the dilated image 270. One output data element can be formed by the sum of the products between the rotated filter 260 and the overlapping input data elements (including padded zeros) of the dilated image 270. In the case where the stride of the transposed convolution operation is larger than the size of the rotated filter 260, as in Figure 2F As shown in , the convolution output array 280 will contain zero output data elements.

[0058] Figure 3 An example sequence 300 of implementing a transposed convolution operation in a computing environment is shown. Figure 3As shown in , the filter elements of the original filter 260 can be stored in memory 302. The address of each filter element in memory 302 can be based on the (r, s) coordinates of the filter element. In some examples, a processor 304 (e.g., a host device) can perform a read operation 306 on memory 302 to obtain the filter elements of the original filter 260, and perform a rotation operation 308 to calculate the rotated (r, s) coordinates of each filter element based on Equations 6 and 7. In some examples, the filter elements of the original filter 260 can be stored in memory 302 in a rotated form (based on Equations 6 and 7), and the rotation operation 308 can be skipped. The hardware processor 304 can perform a write operation 310 to store the filter elements at the addresses based on the rotated (r, s) coordinates back to memory 302. In addition, the input data elements of the original image 270 can also be stored in memory 302. The address of each input data element can be based on the coordinates of the input data element in the original dilated image 270. The processor 304 may perform a read operation 316 at the memory 302 to obtain the input data elements of the original image 270 and a write operation 318 at the memory 302 to store the input data elements at addresses / coordinates corresponding to the dilated image 270. A convolution operation 320 may then be performed between the rotated filter 260 and the dilated image 270 from the memory 302 for a transposed convolution operation.

[0059] Sequence 300 may involve a large number of memory read and write operations. For example, a large number of read operations 306 and write operations 310 may be performed for a large number and / or multi-dimensional filter 360 (e.g., having multiple input and output channels, such as Figure 2D In addition, a large number of read operations 316 and write operations 318 may be performed for the expansion of a large number and / or multi-dimensional image 270. All of these additional memory read and write operations increase latency and increase the time required to complete the transposed convolution operation in the computing environment.

[0060] Figure 4A 4 illustrates an example of an integrated circuit device that can be configured to perform various types of convolution operations, including normal convolution operations and transposed convolution operations. The example of FIG4 illustrates an accelerator 402. In various examples, for a set of input data (e.g., input data 450), the accelerator 402 can use a processing engine array 410, an activation engine 416, and / or a pooling engine 418 to perform calculations. In some examples, the example accelerator 402 can be an integrated circuit component of a processor, such as a neural network processor. The processor can have other integrated circuit components, including additional accelerator engines. The accelerator 402 can include a controller 422 to control the operation of the processing engine array 410, the activation engine 416, and / or the pooling engine 418.

[0061] In various embodiments, memory subsystem 404 may include multiple memory banks 414. In these embodiments, each memory bank 414 may be independently accessible, meaning that reading from one memory bank is not dependent on reading from another. Similarly, writing to one memory bank does not affect or restrict writing to a different memory bank. In some cases, each memory bank can be read from and written to simultaneously. Various techniques can be used to provide independently accessible memory banks 414. For example, each memory bank can be a physically separate memory component with an address space that is separate and independent of the address space of each other memory bank. In this example, each memory bank can have at least one read channel and at least one separate write channel that can be used simultaneously. In these examples, memory subsystem 404 can allow simultaneous access to the read or write channels of multiple memory banks. As another example, memory subsystem 404 can include arbitration logic so that, for example, arbitration between the outputs of multiple memory banks 414 allows the output of more than one memory bank to be used. In these and other examples, while globally managed by memory subsystem 404, each memory bank can operate independently of any other memory bank.

[0062] Making memory banks 414 independently accessible can improve the efficiency of accelerator 402. For example, multiple values ​​can be read simultaneously and provided to each row of processing engine array 410, allowing the entire processing engine array 410 to be used within a single clock cycle. As another example, a memory bank 414 can be read while a result computed by processing engine array 410 is being written to memory subsystem 404. In contrast, a single memory may only be able to service one read or write at a time. In the case of a single memory, multiple clock cycles may be required before processing engine array 410 can be started, for example, to read input data for each row of processing engine array 410.

[0063] In various embodiments, memory subsystem 404 can be configured to simultaneously serve multiple clients, including processing engine array 410, activation engine 416, pooling engine 418, and any external clients accessing memory subsystem 404 via communication fabric 420. In some embodiments, being able to serve multiple clients can mean that memory subsystem 404 has at least as many memory banks as clients. In some cases, each row of processing engine array 410 can be counted as a separate client. In some cases, each column of processing engine array 410 can output a result, such that each column can be counted as a separate write client. In some cases, the output from processing engine array 410 can be written to memory bank 414, which can then subsequently provide input data for processing engine array 410. As another example, activation engine 416 and pooling engine 418 can include multiple execution channels, each of which can be a separate memory client. For example, memory bank 414 can be implemented using static random access memory (SRAM).

[0064] In various embodiments, memory subsystem 404 may include control logic. The control logic may, for example, track the address space of each of memory banks 414, identify the memory bank 414 to read from or write to, and / or move data between memory banks 414. In some embodiments, memory banks 414 may be hardwired to specific clients. For example, a group of memory banks 414 may be hardwired to provide values ​​to rows of processing engine array 410, with one memory bank servicing one row. As another example, a group of memory banks may be hardwired to receive values ​​from columns of processing engine array 410, with one memory bank receiving data for each column.

[0065] Processing engine array 410 is a computational matrix of example accelerator 402. Processing engine array 410 can, for example, perform parallel integration, convolution, correlation, and / or matrix multiplication. Processing engine array 410 includes a plurality of processing engines 411 arranged in rows and columns so that a result output by one processing engine 411 can be directly input to another processing engine 411. Thus, processing engines 411 not located on the outer edges of processing engine array 410 can receive data for operation from other processing engines 411 rather than from memory subsystem 404.

[0066] In various examples, processing engine array 410 uses systolic execution, in which data arrives at each processing engine 411 at regular intervals from different directions. In some examples, input data can flow into processing engine array 410 from the left and weight values ​​can be loaded at the top. In some examples, weights and input data can flow from the left, and partial sums can flow from top to bottom. In these and other examples, multiplication and accumulation operations move through processing engine array 410 in a diagonal wavefront, with data moving right and down across the array. Control signals can be input to the left at the same time as weights and can flow through and down with the computation.

[0067] In various embodiments, the number of columns in processing engine array 410 determines the computational power of processing engine array 410, and the number of rows determines the memory bandwidth required to achieve maximum utilization of processing engine array 410. Processing engine array 410 may, for example, have 64 columns and 428 rows, or some other number of columns and rows.

[0068] An example of a processing engine 411 is illustrated in FIG4 . As illustrated in this example, the processing engine 411 may include a multiplier-accumulator circuit. Inputs from the left may include, for example, input data i and weight values ​​w, where the input data is a value obtained from a set of input data or a set of intermediate results, and the weight values ​​are from a set of weight values ​​that connect one layer of the neural network to the next layer. The set of input data may be, for example, an image submitted for identification or object recognition, an audio clip provided for speech recognition, a text string for natural language processing or machine translation, or the current state of a game that needs to be analyzed to determine the next move. In some examples, the input data and weight values ​​are output to the right for input to the next processing engine 411.

[0069] In the example shown, the input from above may include a partial sum p_in, which is provided by another processing engine 411 or by a previous round of calculation in the processing engine array 410. When starting calculations on a new set of input data, the top row of the processing engine array 410 may receive a fixed value for p_in, such as zero. As shown in this example, i and w are multiplied, and the result is summed with p_in to produce a new partial sum p_out, which can be input to another processing engine 411. Various other implementations of the processing engine 411 are possible.

[0070] The output from the last row in processing engine array 410 may be temporarily stored in summing buffer 412. The result may be an intermediate result that may be written to memory bank 414 to be provided to processing engine array 410 for further computation. Alternatively, the result may be a final result that, once written to memory bank 414, may be read from memory subsystem 404 via communication fabric 420, the final result being output by the system.

[0071] In some embodiments, accelerator 402 includes an activation engine 416. In these embodiments, activation engine 416 can combine the results from processing engine array 410 into one or more output activations. For example, for a convolutional neural network, the convolutions from multiple channels can be summed to produce an output activation for a single channel. In other instances, it may be necessary to accumulate the results from one or more columns in processing engine array 410 to produce an output activation for a single node in the neural network. In some instances, activation engine 416 can be bypassed.

[0072] In various examples, activation engine 416 can include multiple separate execution channels. In these examples, an execution channel can correspond to a column of processing engine array 410 and can perform operations on the output of the column, the results of which can be stored in memory subsystem 404. In these examples, activation engine 416 can be capable of performing between 1 and n parallel calculations, where n is equal to the number of columns in processing engine array 410. In some cases, one or more of the calculations can be performed simultaneously. Examples of calculations that each execution channel can perform include exponential, square, square root, identity, binary step, bipolar step, sigmoid, and ramp, among others.

[0073] In some embodiments, accelerator 402 may include pooling engine 418. Pooling is the combination of the outputs of the columns of processing engine array 410. The combination may include, for example, calculating maximum, minimum, average, median, summation, multiplication, or another logical or mathematical combination. In various instances, pooling engine 418 may include multiple execution paths that operate on the values ​​of the corresponding columns of processing engine array 410. In these instances, pooling engine 418 may be able to perform parallel computations between 1 and n times, where n equals the number of columns in processing engine array 410. In various instances, the execution paths of pooling engine 418 may operate in parallel and / or simultaneously. In some instances, pooling engine 418 may be bypassed.

[0074] Activation engine 416 and pooling engine 418 may be collectively referred to herein as an execution engine. Processing engine array 410 is another example of an execution engine. Another example of an execution engine is a direct memory access (DMA) engine that may be located outside of accelerator 402.

[0075] Input data 450 can arrive through communication structure 420. Communication structure 420 can connect accelerator 402 to other components of the processor, such as a DMA engine that can obtain input data 450 from input / output (I / O) devices, storage drives, or network interfaces. Input data 450 can be one-dimensional data, such as a string or a sequence of numbers, or two-dimensional data, such as an array of pixel values ​​of an image or the frequency and amplitude values ​​of an audio signal over time. In some instances, input data 450 can be three-dimensional, such as for contextual information or virtual reality data used by self-driving cars. In some embodiments, memory subsystem 404 can include a separate buffer for input data 450. In some embodiments, when accelerator 402 receives input data 450, input data 450 can be stored in memory bank 414.

[0076] In some examples, accelerator 402 may implement a neural network processing engine. In these examples, accelerator 402 may execute a neural network to perform a task for which the neural network has been trained, given a set of input data 450. Executing a neural network on a set of input data may be referred to as inference or performing inference.

[0077] The weights of the neural network can be stored in the memory subsystem 404 along with the input data 450 that the neural network will operate on. The addresses of the weights and input data 450 in the memory subsystem 404 can be based on or mapped to the coordinates of the weights and input data 450 in the weight data array and input data array, respectively, allowing the weights and input data to be retrieved based on addresses derived from their coordinates. The neural network can also include instructions executable by the controller 422 to control the processing engine array 410 to perform various calculations on the weights and input data. These instructions can be generated by a compiler and can also be stored in the memory subsystem 404, the storage bank 414, or a separate instruction buffer. The processing engine array 410 can output intermediate results representing the outputs of various layers of the neural network. In some cases, the activation engine 416 and / or the pooling engine 418 can be enabled to perform calculations required by certain layers of the neural network. The accelerator 402 can store the intermediate results in the memory subsystem 404 for input to the processing engine array 410 to calculate the results of the next layer of the neural network. The processing engine array 410 can further output the final results from the last layer of the neural network. The final result may be stored in the memory subsystem 404 and subsequently copied to the host processor memory or to another location.

[0078] Figure 4B and Figure 4C An example of the operation of the accelerator 402 is shown. Figure 4BAs shown in FIG, the memory subsystem 404 can be organized into multiple rows, such as memory rows 425, 426, etc. Each memory row can store input data elements for a specific input channel. Memory access circuitry (e.g., memory access circuitry 427) can be controlled to sequentially fetch input data elements to the processing engine array 410 based on a set of memory fetch parameters 430 comprising a starting address, a stride, and a number of elements. The starting address parameter can define the location of the first input data element to be read from the memory row, the stride parameter can define the number of input data elements to be skipped between fetched input data elements, and the number of fetched elements parameter can define the total number of input data elements to be fetched. Since the input data elements are stored in a spreading space, the access circuitry 427 can determine the address of the fetched input data element and update a counter based on the stride. For example, the access circuitry 427 can begin fetching the first input data element from the starting address, add an address offset based on the stride to the starting address to fetch the next input data element while skipping multiple input data elements, and repeat until the number of fetched elements is reached. As will be described in more detail below, memory fetch parameters 430 may be included in an instruction for computing a set of partial sums. The instruction may be generated by a compiler and parsed by the controller 422 to extract the memory fetch parameters 430. The controller 422 may then control the fetching of input data elements from the memory subsystem 400 based on the fetched memory fetch parameters 430. As will be described in more detail below, the starting address, stride, and number of element parameters may be configured to support different types of convolution operations, such as normal convolution operations, dilated convolution operations, and the like.

[0079] The processing engines 411 of the processing engine array 410 can be organized into rows such as row 431 and columns such as column 432. Each row of processing engines 411 is mapped to an input channel and can sequentially receive input data elements from the memory row of the memory system 404 mapped to the input channel, while each column of processing engines 411 can be mapped to an output channel. The input data elements are stored in a continuous address space and follow an order based on their coordinates in the input data array. Each processing engine 411 can store weight data elements for the input channel and the output channel to which the processing engine is mapped. Each column of processing engine 411. Reference Figure 4A and Figure 4B , the processing engine 411 within the engine can receive input data elements of the input channel (e.g., Figure 4A The input data i), which is compared with the stored weights (e.g., Figure 4AThe weight data w) is multiplied to generate a product, the product is added to the input partial sum p_in to generate a new partial sum p_out, and the new partial sum p_out is passed to the processing engine 411 under the same column. The bottom processing engine 411 of the column can generate a partial sum representing the sum of the products between the weight data elements stored in the column of the processing engine 411 and the input data elements of the different input channels received from the memory sub-station 404.

[0080] Where the memory fetch parameters 430 indicate a starting address at the rightmost input data element of each row, a stride of one (which may indicate a skip in this example), and a certain number of input data elements are fetched, a first partial sum may be generated in the first iteration column 432 of the processing engine 411 based on the stored weight data elements and the input data elements provided by the memory subsystem 404 as follows:

[0081] The first part and = X 0 0,0 ×W 0,0 0,0 +X 0 0,0 ×W 1,0 0,0 +...+X C 0,0 ×W C,0 0,0 (Equation 8)

[0082] In a second iteration, column 432 of processing engine 411 may generate a second partial sum based on the stored weight data elements and input data elements provided by memory subsystem 404 as follows:

[0083] The second part and = X 0 0,1 ×W 0,0 0,0 +X 0 0,1 ×W 1,0 0,0 +...+X C 0,1 ×W C,0 0,0 (Equation 9)

[0084] Each column of the processing engine 411 can provide the partial sums generated in the iteration to a column summation buffer, such as column summation buffers 442, 443, etc., both of which are part of the summation buffer 412. The partial sums are generated based on weight data elements at the same coordinates of different filter arrays associated with different input channels and output channels, and the partial sums correspond to different output data elements. Figure 4C, each column summation buffer in the column summation buffers 442 and 443 contains a plurality of entries, such as E 0,0 、E 0,1 、E 0,2 Each entry may have coordinates that map to coordinates of an output tile, which may represent a region of the output array. Each entry may have an adder (in Figure 4C ). The entries may then store the accumulated partial sums. The operations at the column summing buffers 442 and 443 may be controlled by a set of buffer write parameters 452 comprising a target offset, a step size, and the number of write elements. The destination offset parameter may indicate the entry to which the first partial sum (of the first iteration) is to be added. The step size parameter may indicate the number of entries to be skipped between adjacent entries receiving the partial sum. The step size parameter may correspond to gaps between non-zero input data elements that overlap with the weight data elements when the weight data array is in different step positions. In addition, the number of write elements indicates the number of partial sums to be added to the entries of the summing buffer starting from the starting address, wherein adjacent entries are separated based on the step size parameter as described above.

[0085] As an illustrative example, where the target offset is 2 and the stride is also 2, the first partial sum from column 432 may be stored in entry E 0,2 At, the second part and can be stored in E 0,4 (where entry E is skipped 0,3 ), the third part and can be stored in E 0,6 (where entry E is skipped 0,5 ) and so on until a number of partial sums specified by the number of write elements are stored. As will be described in more detail below, buffer write parameters 452 can be included in the instruction for calculating a set of partial sums. The instruction can be parsed by the controller 422 to extract the buffer write parameters 452. The controller 422 can then control the operation of the summing buffer based on the extracted buffer write parameters 452. As will be described below, the buffer write parameters 452 can be configured to support convolution operations.

[0086] After calculating the partial sum based on the first set of weight data elements (whose coordinates in the corresponding filter array are the same but the input channel and the output channel are different), the processing engine array 410 can load a new set of weight data elements from different coordinates and repeat the partial sum calculation. The new partial sum can be added to the partial sum calculated from the first set of weight data elements stored in the summing buffer 412. The calculation and accumulation of the partial sums of the remaining weight data elements can continue to generate the data elements of the output tile. After generating the data elements of the output tile, the summing buffer 412 can provide the data elements of the output tile to the activation engine 416 and / or the pooling engine 418 for post-processing, and the post-processed output data elements can be stored in the memory subsystem 404. The post-processed output data can be sent from the memory subsystem 404 to the communication structure 420 and / or obtained to the processing engine array 410 as input data for subsequent neural network layer processing.

[0087] Figures 5A-5D An example configuration of accelerator 402 for performing normal convolution operations is shown. Figure 5A shows the overlap between the different weight data elements of the 3×3 filter array 504 and the input data elements of the input data array 502, the filter array may be Figure 3 The original filter 260, the input data element may be the original image 270. Figure 5A , the input data array 502 may be padded with a row 506 of zeros at the top and a column 508 of zeros on the left. The number of zero-padded rows may be specified by the pad_north parameter, where pad_north equal to one indicates that a row of zeros is padded at the top (north) of the input data array 502. Additionally, the number of zero-padded columns may be specified by the pad_west parameter, where pad_west equal to one indicates that a column of zeros is padded at the left (west) of the input data array 502. A normal convolution operation may be performed between the zero-padded input data array 502 and the filter array 504 with a stride of 2. Some of the input data elements / padded zeros that overlap with a particular weight data element at different stride positions are shaded. As Figure 5AAs shown in , some of the padded zeros and the input data element at coordinate (1, 1) can overlap with the weight data element (0, 0) at different stride positions. In addition, the input data elements (0, 0), (0, 2) and (2, 2) can overlap with the weight data element (1, 1) at different stride positions. Further, the input data elements (1, 1), (1, 3) and (3, 3) can overlap with the weight data element (2, 2) at different stride positions. In each case, there is a gap between each input data element that overlaps with the weight data element. The gap can be defined based on the stride distance of the convolution operation. When the stride distance is two, the gap includes one input data element.

[0088] Return Reference Figure 4B and Figure 4C , in order to execute Figure 5A For a normal convolution operation, the controller 422 may be provided with memory acquisition parameters 430 that define a set of overlapping non-zero input data elements for the weight data elements loaded into the processor engine 411. The set of overlapping non-zero input data elements may be defined based on the starting address, step size, and number of acquisition element parameters. The starting address may be the address of the first overlapping non-zero input data element in the memory subsystem 404. The address may be determined based on a mapping between the memory subsystem 404 address and the coordinates of the input data elements stored in the memory subsystem 404. In addition, the step size may correspond to the above-mentioned gap and may be based on the stride distance. Further, the number of acquisition elements may be based on the size of the output tile for the convolution operation, which in turn may be based on the size of the summing buffer, as will be described below. Based on the memory acquisition parameters 430 for each weight data element, the controller 422 may acquire the correct subset of input data elements to the processing engine array 410 to be multiplied with the weight data element to produce a partial sum.

[0089] Additionally, the controller 422 may be provided with a buffer write parameter 452 to store non-zero partial sums for different stride positions at entries of a column summing buffer (e.g., column summing buffer 442) corresponding to the stride position. Figure 4C , the partial sum of the stride position (0, 0) can be found in entry E 0,0 The partial sum at stride position (0, 1) can be found in entry E 0,1 The target offset of the buffer write parameter 452 may also be based on a set of overlapping non-zero input data elements for the weight data element. Specifically, the target offset may be provided to the column summation buffer to skip a number of entries corresponding to zero partial sums (which corresponds to the number of padding zeros that overlap with the weight data element) until an entry corresponding to a stride position where the weight data element overlaps with the input data element. Figure 5A In the example of , the weight data element (0, 0) overlaps with padding zeros at the first few stride positions until it overlaps with the input data element at (1, 1). The target offset of the buffer write parameter 452 can be configured to ensure that the partial sum generated from the input data element at (1, 1) is stored at the entry that reflects the stride position of the filter array 504 when the weight data element (0, 0) overlaps with the input data element (1, 1).

[0090] Figure 5B Example operations for determining overlapping input data elements for a particular weight data element, which may be performed by a compiler, are shown. Figure 5B Based on the size of the column sum buffer (e.g., the number of rows and columns of entries), the compiler can determine the size of the output tile and the total number of entries in the column sum buffer. As described above, the output tile includes the output data elements of the region 520 in the output data array, and the output tile can be defined by the coordinate range of the first region in the output data array.

[0091] In operation 522, the compiler may perform a projection operation from the region 520 represented by the output tile to determine a region 530 in the input data array 502 that may provide input data elements to be convolved with the weight data elements to produce the output tile. The projection operation may take into account the size of the first region and the stride distance of the convolution operation. As described above, the stride distance may define a gap between each overlapping input data element, where a stride distance of two produces a gap between the input data elements. The size of the region 530 may be determined based on the size of the region 520 and the gap. For example, referring to Figure 5B , based on an output tile having 10 output data elements per row and having three rows (30 entries total), the size of region 530 can be determined by scaling the size of region 520 by a factor of two so that region 520 has 20 input data elements per row and has six rows. With such an arrangement, since one input data element is skipped between two input data elements, the total number of input data elements (and the resulting partial sum) can be equal to the total number of output data elements in the output tile and the number of entries of the column sum buffer.

[0092] After determining the size of region 520, the compiler can align region 530 with the padded input data array 502. The alignment can be based on the coordinates of the weight data elements and the pad_north parameter and the pad_west parameter. The coordinates of the upper left corner of region 530 relative to the original input data array 502 can be based on the following equation:

[0093] Start_coordinates region530=(weight_r–pad_west,weight_s–pad_north) (Equation 10)

[0094] In Equation 10, start_coordinates region530 refers to the coordinate of the upper left corner of area 530, weight_r refers to the row coordinate of the weight data element, weight_s refers to the column coordinate of the weight data element, pad_west refers to the number of columns of zeros added to the left side of the input data array 502, and pad_north refers to the number of rows of zeros added to the top of the input data array 502.

[0095] like Figure 5A As shown, for the weight data element (0, 0), the upper left corner of the region 530 can be aligned with the upper left corner of the zero-filled input data array 502. Through such alignment, the weight data element (0, 0) overlaps with the upper left corner element of the region 530 when the filter array 504 is at the stride position (0, 0), and the upper left corner element represents the first input data element to be multiplied by the weight data element and is located at coordinates (-1, -1) relative to the original input data array 502. Based on the alignment operation, the compiler can determine the target coordinate range of the region 520 relative to the original input data array 502. Figure 5B , the target coordinate range of region 530 may be (-1, -1) and (4, 18) relative to the upper left corner of the original input data array 502, which has coordinates (0, 0).

[0096] In operation 540, after determining the target coordinates for region 530, the compiler may overlay stride pattern 550 on region 530. Stride pattern 550 may define the gaps between overlapping input data elements based on a stride distance. Each dark box in stride pattern 550 may represent an overlapping input data element. As described above, when the stride distance is two, the gaps contain input data elements. When stride pattern 550 is overlaid on region 530, the upper left corner of stride pattern 550 is aligned with the upper left corner of region 530. Based on the alignment and the gaps in stride pattern 550, the compiler may calculate the coordinates of stride pattern 550 relative to original input data array 502 based on the coordinates (-1, -1) of the upper leftmost element of region 530 and the gap information. For example, the first element of the stride pattern overlaps the upper leftmost element of region 530 and has coordinates (-1, -1), the second element of the stride pattern, which is in the same row as the first element, has a gap of 1 from the first element and may have coordinates (-1, 1), and so on. Based on the coordinates of the stride pattern and the size of the original input data array 502, which can define a series of coordinates of input data elements contained in the original input data array 502, the compiler can identify a first subset of coordinates that are within the zero-filled region and a second subset of coordinates that are within the original input data array 502. The first subset of coordinates is within the zero-filled region and can represent zero input data elements that produce a zero partial sum (due to multiplication by zero), while the second subset of coordinates can represent non-zero input data elements that produce a non-zero partial sum. The non-zero input data elements represented by the second subset of coordinates can be overlapping input data elements with the weight data element (0, 0) in the original input data array 502.

[0097] The compiler may determine the starting address, stride, and number of fetch elements parameters of the memory fetch parameter 430 based on the first subset of coordinates in the zero-filled region and the second subset of coordinates in the original input data array 502. Specifically, the starting address parameter of the memory fetch parameter 430 may correspond to the first coordinate in the second subset of coordinates. Figure 5B In the example of , the starting address may correspond to coordinate (1, 1) of the input data array 502, which may be converted to an address in the memory subsystem 404. Furthermore, the stride is based on the stride distance described above. The number of get element parameters may be based on the size of the second subset of coordinates. Figure 5B In the example of , the size of the second subset of coordinates may be 18, since there are 18 non-zero input data elements that may overlap with the weight data element (0, 0) in the original input data array 502. Therefore, the number of get elements parameter may also be set to 18.

[0098] The compiler can also determine the target offset, stride, and number of write element parameters of the buffer write parameters 452 based on the first subset of coordinates in the zero-filled area and the second subset of coordinates in the original input data array 502. Specifically, based on the first subset of coordinates, the compiler can determine that the first 11 input data elements are zero, which means that the first 11 entries of the column summation buffer need to be skipped, and the target offset parameter can be set to 11. In addition, since 18 input data elements are to be obtained, 18 partial sums will be generated, and the number of write element parameters can be set to 18. In addition, the non-zero input data elements that overlap with the weight data elements are separated by stride, which means that when the weight data array is located at different stride positions in the input data array, there is no gap between the overlapping non-zero input data elements. Therefore, the stride parameter of the buffer write parameters 452 can be set to one.

[0099] Referring back to operation 522 and Equation 10, the compiler may adjust the alignment of region 530 relative to the populated input data array 502 based on the coordinates of the weight data elements by adding offsets along both the row and column dimensions. Figure 5C , for weight data element (1, 1), the compiler can use equation 8 to calculate the coordinates of the upper left corner of region 530 and obtain (0, 0). That is, compared with weight data element (0, 0), region 530 is shifted one unit to the right and bottom from the upper left corner of the filled input data array 502. The coordinates of the upper left corner of region 530 can become (0, 0), and the coordinate range of region 530 can become (0, 0) to (5, 19). By such alignment, the upper leftmost element of region 530 representing the first input data element to be multiplied with weight data element (1, 1) overlaps with the weight data element when filter array 504 is at stride position (0, 0). For weight data element (1, 1), region 530 and stride pattern 550 overlap with original input data array 502, but do not overlap with zero padding. The first input data element starts from coordinate (0, 0), and a total of 30 input data elements can be obtained. Furthermore, since there are no zero input data elements, there are no entries to the skip column sum buffer.

[0100] In addition, for weight data element (2, 2), the compiler can use equation 10 to calculate the coordinates of the upper left corner of region 530 and obtain (1, 1). That is, the compiler can shift region 530 two units to the right and bottom from the upper left corner of the padded input data array 502. The coordinate range of region 530 becomes (1, 1) to (6, 20). By this type of alignment, the upper leftmost element of region 530 representing the first input data element to be multiplied with weight data element (2, 2) overlaps with the weight data element when filter array 504 is at stride position (0, 0). For weight data element (2, 2), region 530 and stride pattern 550 overlap with original input data array 502, but do not overlap with zero padding. The first input data element starts from coordinate (1, 1), and a total of 27 input data elements can be obtained. In addition, since there is no zero input data element, there is no entry for skipping column summation buffers.

[0101] Figure 5D Shown for the above Figure 5A – Figure 5C Examples of memory fetch parameters 430 and buffer write parameters 452 for weight data elements (0,0), (1,1), and (2,2) for a convolution operation are shown.

[0102] Figures 6A-6F An example configuration of the accelerator 402 for performing an example transposed convolution operation is shown. Figure 6A As shown, the accelerator 402 can be configured based on the memory fetch parameters 430 and the buffer write parameters 452 to perform a transposed convolution operation between the original input data array 502 and the original filter array 504 to produce the same transposed convolution output array 280, which is obtained by Figure 3 The convolution operation 320 between the dilated input data array 502 and the rotated filter array 504 produces Figure 6A – Figure 6F In the example, the stride of the example transposed convolution operation is two.

[0103] To perform the transposed convolution operation, the controller 422 of the accelerator 402 may obtain the first weight data element from the memory system 404 based on the first coordinate of the first weight data element in the original filter array 504 and load the first weight data element into the systolic array. However, the memory fetch parameters 430 and the buffer write parameters 452 may be based on the second coordinate of the first weight data element in the rotated filter array 504, wherein the memory fetch parameters include a starting address and a number of fetch elements to indicate a subset of input data elements to be loaded into the processing engine array 410 for the first weight data element, and the buffer write parameters include a target offset and a number of write elements of the buffer write parameters to indicate an entry of the summing buffer 412 to receive the partial sum from the processing engine array 410. The compiler may convert the first coordinate to the second coordinate and generate the memory fetch parameters 430 and the buffer write parameters 452 based on the second coordinate and the rate of the transposed convolution.

[0104] Figure 6B A coordinate generation operation 600 that can be performed by a compiler is shown. The coordinate generation operation 600 can convert the original coordinates 604 of the weight data elements in the original filter array 504 into rotated coordinates 606 of the weight data elements in the rotated filter array 504. The conversion can be performed by a coordinate mapping module 602 (which can include circuitry for performing operations based on, for example, equations 6 and 7 above) and size information 608, which can define the maximum r and s coordinates of the original file filer array 504 (e.g., R and S in equations 6 and 7). The compiler can then determine the memory fetch parameters 430 and the buffer write parameters 452 based on the rotated coordinates 606. The compiler can generate calculation instructions that control the controller 422 to load weight data elements from the memory subsystem 404 and / or from the external memory based on the address obtained from the original coordinates 604, and at the same time include memory acquisition parameters 430 and buffer write parameters 452 based on the rotated coordinates 606 in the same calculation instructions to enable the controller 422 to select input data elements based on the rotated coordinates 606 to calculate the partial sum with the weight data elements, and store the partial sum at the entry of the summation buffer 412 based on the rotated coordinates 606.

[0105] Figures 6C to 6E The operations for determining entries of the summing buffer 412 to receive partial sums for weight data elements from the processing engine array 410 are shown, which may also be performed by the compiler. The operations for determining entries of the column summing buffer may be similar to Figure 5BOperations 522 and 540 may be based on shifting a stride pattern (e.g., stride pattern 550) by an offset based on the coordinates of the weight data elements, but the alignment of the stride pattern is relative to the column summation buffer to account for gaps between entries caused by zero padding of the dilated input data array 502, as described below. Figures 6C to 6E In the example shown, the column sum buffer 442 may have 18 columns and 4 rows of entries and may store output tiles.

[0106] refer to Figure 6C , as part of a transposed convolution operation with a stride of 2, the rotated filter array 504 may traverse the dilated input data array 502 with a stride of 1. The weight data element at (0, 0) of the rotated filter array 504 overlaps with the input data elements (represented by the grey squares) of the original input data array 502 at stride positions (1, 1), (1, 3), etc., where the overlapping input data elements overlap at Figure 6C The stride position may correspond to the entry E of the column summing buffer 442. 1,1 、E 1,3 etc. (represented by the shaded squares) to receive partial sums from the multiplication of the weight data element and the overlapping input data element at column 432 of the processing engine array 410. In addition, for other stride positions where the weight data element overlaps the padding zeros of the dilated input data array 502, the corresponding entries of the column summation buffer 442 (e.g., E 0,0 ) will not receive partial sums from the processing engine array 410. Figure 6C As shown, adjacent entries of the received partial sum are separated by a gap of one entry, which corresponds to the gap between the non-zero input data elements of the dilated input data array 502 and the stride of the transposed convolution (one zero). Figure 6C It is also shown that the entries of the column summation buffer 442 that receive the partial sums of the weight data elements at (1, 1) and (2, 2) of the rotated filter array 504 have a gap of one between adjacent entries, which also corresponds to the stride of the transposed convolution.

[0107] The compiler can determine entries of the column sum buffer to receive partial sums based on aligning the stride pattern 550 (or other stride pattern that matches the stride of the transposed convolution) with a region representing a portion of the transposed convolution output array 280, and the region can be shifted based on a second coordinate of the first weight data element relative to a reference position of the column sum buffer. The operation can be similar to Figure 5B and Figure 5C Specifically, refer to Figure 6DAs part of operation 622, based on the dimensions of the column sum buffer 442 (e.g., the number of rows and columns of entries), and the padding of the output data array, the compiler can determine a region 630 that contains a portion of the transposed convolution output array 280 produced by the transposed convolution operation. Region 630 contains the maximum size of an output tile that can be stored in the column sum buffer 442, a zero-padded region that includes a north pad region 636 above the output tile and a west pad region 638 to the left of the output tile. The north pad region 636 can contain one or more rows of zeros based on a parameter pad_north, and the west pad region 638 can contain one or more columns of zeros based on a parameter pad_west.

[0108] The compiler can then align region 630 relative to a reference position. The reference position can be an imaginary position outside of column summing buffer 442, taking into account the north padding region and the west padding region. The alignment can be based on the coordinates of the weight data element and the pad_north parameter and the pad_west parameter. The coordinates of the upper left corner of region 630 can be based on the following equation:

[0109] Start_coordinates region_630 =(rotate_weight_r–pad_west,rotate_weight_s–pad_north)

[0110] (Equation 11)

[0111] In Equation 11, start_coordinates region_630 refers to the coordinates of the upper left corner of region 630 relative to the padding area at the top and left of the column summing buffer 442, rotate_weight_r refers to the row coordinates of the weight data elements in the rotated filter array 504, rotate_weight_s refers to the column coordinates of the weight data elements in the rotated filter array 504, pad_west refers to the number of columns of zeros added to the left side of the output tile, and pad_north refers to the number of rows of zeros added to the top of the output tile.

[0112] like Figure 6D As shown, for the weight data element at (0, 0) of the rotated filter array 504, the upper left corner of region 630 can be aligned with the upper left corner of the zero-filled region including region 636 and region 638, which can be located at coordinates (-1, -1) relative to column summation buffer 442. With such alignment, the weight data element W at (0, 0) of the rotated filter array 504 when the rotated filter array 504 is at stride position (0, 0) is 2,2Overlapping with the upper leftmost element of region 630, this may represent the first output data element of the output tile generated between the product of the weight data element and the first input data element of the expanded input data array 502. The first output data element may be located at coordinates (-1, -1) relative to the column sum buffer 442. Based on the alignment operation, the compiler may determine an output coordinate range for region 630 within the column sum buffer 442 that corresponds to an output tile that may fit within the weight data element of the column sum buffer 442. Figure 6D , using a column summing buffer 442 having 4 rows and 18 columns, the output coordinates of region 630 within the column summing buffer 442 may range from (0, 0) to (3, 17).

[0113] In operation 640, after determining the output coordinate range of region 630, the compiler can overlay stride pattern 550 on region 630. Stride pattern 550 can define the gap between adjacent entries of the received partial sum. In the case where the stride of the transposed convolution is two, the gap between adjacent entries is one. Return to reference Figure 6C , which reflects the number of padding zeros between the non-zero input data elements of the dilated input data array 502. When the stride pattern 550 is superimposed on the region 630, the upper left corner of the stride pattern 550 is aligned with the upper left corner of the region 630. Based on the alignment and the gap in the stride pattern 550, the compiler can calculate the coordinates of the stride pattern 550 relative to the original input data array 502 based on the coordinates (-1, -1) of the upper left element of the region 630 and the gap information. For example, the first element of the stride pattern overlaps with the upper left element of the region 630 and has coordinates (-1, -1), the second element of the stride pattern that is in the same row as the first element has a gap of 1 from the first element and can have coordinates (-1, 1), and so on. Based on the coordinates of the stride pattern and the output coordinate range of the region 630 within the column summation buffer 442, the compiler can determine the entry (and associated coordinates) of the column summation buffer 442 that receives the non-zero partial sum. For example, the first entry of the column summation buffer 442 for receiving the partial sum is E at coordinates (1, 1). 1,1 , and the first 19 entries (the 18 entries in the first row, plus entry E 0,1 ) do not receive a partial sum and will be skipped, which results in a target offset of 19 in buffer write parameters 452. Additionally, 18 entries will receive a partial sum, which results in a number of write elements in buffer write parameters 452 of 18. Further, adjacent entries receiving partial sums are separated by a gap of 1, which results in a step size of 2 in buffer write parameters 452.

[0114] Figure 6EThe alignment of the zero-filled output tiles of region 630 relative to the other weight data elements is shown. Figure 5C In the case of , the compiler may adjust the alignment of region 630 relative to the zero-fill region including regions 636 and 638 based on the coordinates of the weight data elements in the rotated filter array 504. The adjustment may be based on adding an offset along both the row and column dimensions. For example, referring to Figure 6E , for the weight data element W at (1, 1) of the rotated filter array 504 1,1 , the compiler can calculate the coordinates of the upper left corner of region 630 using equation 11 above and obtain (0, 0). That is, region 630 is shifted one unit to the right and bottom from the upper left corner of the zero-filled output tile. The coordinates of the upper left corner of region 630 can become (0, 0) and the output coordinate range of region 630 within column sum buffer 442 is from (0, 0) to (3, 17). The first output data element starts at coordinate (0, 0), and a total of 18 partial sums will be stored in column sum buffer 442, with a gap of 1 between adjacent entries. The compiler can determine in buffer write parameters 452 that the target offset is 0, the number of elements to be written is 18, and the stride is 2.

[0115] Furthermore, for the weight data element W at (2, 2) of the rotated filter array 504 0,0 , the compiler can calculate the coordinates of the upper left corner of region 630 using equation 11 above and obtain (1, 1). That is, region 630 is shifted two units to the right and bottom from the upper left corner of the zero-filled region including regions 636 and 638. The coordinates of the upper left corner of region 630 can become (1, 1) and the output coordinate range of region 630 in column sum buffer 442 is from (0, 0) to (3, 17). The first output data element starts at coordinate (1, 1), and a total of 18 partial sums will be stored in column sum buffer 442, with a gap of 1 between adjacent entries. The compiler can determine the target offset as 19, the number of elements to be written as 18, and the stride as 2 in buffer write parameters 452.

[0116] The compiler may then determine overlapping input data elements based on a projection operation that projects a portion of region 630 within column sum buffer 442 into a region of raw input data array 502 to identify input data elements to be loaded into processing engine array 410 . Figure 6F The projection operation is shown. Figure 6F As shown, the region 632 corresponding to the output coordinate range of region 630 within column summing buffer 442 can be projected to region 645 within original input data array 502. The projection operation is similar to Figure 5BOperation 522 is performed as described above, but the size of region 645 is reduced by a factor equal to the stride of the transposed convolution to take into account that the original input data array 502 is expanded by the same stride factor, thereby obtaining the expanded input data array 502. In the case where region 630 has dimensions of 4 rows and 18 columns, the projected region 645 in the original input data array 502 can have 2 rows and 9 columns and contain 18 consecutive input data elements without skipping in between. The compiler can determine that the number of fetch elements is 18 and the stride is 1 for the memory fetch parameter 430.

[0117] The compiler can also calculate an offset 650 that indicates the first input data element in region 630. Offset 650 can be relative to the upper left corner of the original input data array 502. The compiler can determine offset 650 based on the coordinates of the first input data element in the dilated input data array 502, which overlaps with the weight data element when the rotated filter array 504 and the dilated input data array 502 are in the first stride position, and scale down the coordinates (by performing integer division) based on the rate of the transposed convolution. The compiler can determine the starting address of the memory fetch parameter 430 based on offset 650.

[0118] The coordinates of the first overlapping input data element in the dilated input data array 502 may be determined based on the rotated coordinates of the weight data element in the dilated input data array 502. For example, referring back to Figure 6C , for the weight data element W at (0, 0) of the rotated filter array 504 2,2 , the coordinates of the first input data element in the dilated input data array are (1, 1). The offset 650 can be determined by scaling (1, 1) by a factor of 2 (the stride of the transposed convolution) to obtain the coordinates of the first input data element in the original input data array 502 as (0, 0). Based on the same technique, the compiler can 1,1 and W 0,0 The coordinates of the first input data element in the original input data array 502 are determined to be (0, 0) and (1, 1), respectively.

[0119] Figure 6G Shown for the above Figure 6A – Figure 6F The weight data element W of the transposed convolution operation shown 0,0 、W 1,1 and W 2,2 The controller 422 may retrieve the weight data element W based on its coordinate in the original filter array 504. 0,0 、W 1,1 and W2,2 , but the parameters in memory fetch parameters 430 and buffer write parameters 452 are determined based on their rotated coordinates in rotated filter array 504 as described above.

[0120] As mentioned above, the transposed convolution operation can produce zero output data elements. Figure 2F As shown, this occurs when a dilated output data array is generated by inserting multiple zeros between input data elements that are larger than the size of the weight data array. Figure 2F , the stride of the transposed convolution operation is four and three zeros are padded between adjacent input data elements to form the dilated image 270, while the size of the rotated filter 260 is 3×3 and a zero output data element may be produced when the rotated filter 260 completely overlaps with the padded zeros.

[0121] To improve computational efficiency, controller 422 may control column sum buffers (eg, column sum buffer 442 ) to output zeros from entries to represent zero output data elements without passing zero input data elements to processing engine array 410 to compute zero partial sums. Figure 7A and Figure 7B An example technique that can be used in accelerator 402 to output zero output data elements is shown. Figure 7A As shown, the controller 422 can reset the column summation buffer (and the entire summation buffer 412) before performing the first calculation for the transposed convolution. The controller 422 can perform the reset based on the calculation instructions generated by the compiler. In such an example, the controller can execute the reset calculation instruction to initialize the contents of the column summation buffer (and the entire summation buffer 412) to zero, and then execute the calculation instruction to calculate the partial sum of each weight data element. Entries that do not receive any partial sums during the calculation can output zero as an output data element.

[0122] Figure 7B shows another technique for outputting zero output data elements. Figure 7B As shown, the summing buffer 412 includes access circuitry 702 for performing read / write operations on column summing buffers (e.g., column summing buffer 442). The access circuitry 702 can receive read / write requests including addresses and perform read / write operations on entries of the column summing buffer based on the addresses. For example, a write request can include an address based on a target offset parameter of the buffer write parameter 452. As another example, a read request can include the address of each entry to read out an output data element of an output tile and provide the output data element to, for example, the activation engine 416, the pooling engine 418, etc. for further processing.

[0123] In some instances, such as Figure 7BAs shown, summing buffer 412 may include a set of write status registers 704 and a multiplexer 706. Write status register 704 may store a flag for each entry to indicate whether the entry has received a write operation from access circuit 702 based on the address included in the write request. When access circuit 702 receives a write request including the address of an entry, access circuit 702 may assert a flag associated with the entry in write status register 704 based on the address. When access circuit 702 receives a read request including the address of the entry, write status register 704 may provide the asserted flag based on the address to multiplexer 706, which may output the contents stored in the entry. On the other hand, if the entry did not receive a write operation prior to the read request, the flag for the entry will remain deasserted, and write status register 704 may provide a deasserted flag to multiplexer 706, which may output a zero based on the deasserted flag. In some examples, the write status register 704 can be reset by the controller 422 before executing the first computation instruction for the transposed convolution operation, and the resetting of the write status register 704 does not require the controller to execute an additional reset instruction.

[0124] Figure 8 A block diagram illustrating an example of a host system 800 on which a compiler 830 as described herein may run is included. The illustrated host system 800 is an example of a computing device and includes a processor 802, processor memory 804, at least one storage device 806, various input / output (I / O) devices 808, and at least one network interface 810. Figure 8 In the example, the host system 800 further includes an acceleration engine 812, which may include Figures 4A-4C accelerator 402. In various examples, host system 800 can be implemented as a data center, a desktop computer, a laptop computer, a tablet computer, or a smartphone, among other examples, as a server. In some examples, operations or components discussed below as being executed or included in host system 800 can be executed or included in other computer devices. For example, compiler 830 can be executed on host system 800 when acceleration engine 812 is located at a different host system.

[0125] The processor 802 is an integrated circuit device that can execute program code in the form of instructions. The program code can be used in various software applications or tools, such as an operating system 820 or a compiler 830 shown. When the processor 802 is executing a program, the program's instructions can be stored in the processor memory 804. The instructions can also be stored elsewhere, such as on a storage device 806, and can be loaded into the processor memory 804 when needed by the processor 802. The processor 802 can also use the processor memory 804 for temporary storage of other data that the processor 802 operates on. In various examples, alternatively or additionally, although a non-volatile memory type can be used for the processor memory 804, the processor memory 804 is a volatile memory type, such as a random access memory type.

[0126] Storage device 806 is an example of a device that can include non-volatile memory. For example, storage device 806 can be a magnetic disk drive, a solid-state drive, or an optical drive, among other examples. Storage device 806 can further be non-transitory, such that when storage device 806 is not powered, program code and other data stored on storage device 806 still exists.

[0127] Storage device 806 is an example of a peripheral device, which is a component that can be coupled to host system 800 to add functionality to host system 800. Other examples of peripheral devices include input / output devices 808 and network interface 810. Input / output devices 808 can include user input and output devices such as a keyboard, mouse, touch screen, microphone, display, speakers, printer, and scanner, among other examples. Network interface 810, which can be implemented using a network interface card, can provide access to one or more networks. Network interface 810 can include, for example, a physical port for connecting a network cable and / or a wireless antenna to communicate with Wi-Fi and / or cellular networks. Network interface 810 can also be described as an I / O device.

[0128] Acceleration engine 812 is another type of peripheral device or I / O device. Acceleration engine 812 is a device specifically designed to perform certain operations that can be performed by processor 802, but can be performed faster by acceleration engine 812. For example, acceleration engine 812 can be a neural network accelerator and, as such, can perform massively parallel computations of neural networks more efficiently than when the computations are performed by processor 802. As another example, acceleration engine 812 can be a graphics processing unit (GPU) and can be optimized to perform the computations required for graphics rendering. Other examples of devices that can be implemented by acceleration engine 812 include cryptographic accelerators, compression and decompression accelerators, 3-D accelerators, regular expression accelerators, security accelerators, and the like.

[0129] In various examples, the acceleration engine 812 can implement program code to perform certain operations. For example, when the acceleration engine 812 is a neural network accelerator, the acceleration engine 812 can be programmed to execute a specific neural network, such as a neural network that performs image recognition or a neural network that performs machine translation. As another example, to support the execution of the neural network, the acceleration engine 812 can be programmed to perform operations such as copying data for the neural network from the processor memory 804 (for example) to the acceleration engine 812, copying input data for the neural network from the processor memory 804 to the acceleration engine 812, and / or copying results from the acceleration engine 812 to the processor memory 804, among other examples.

[0130] To generate program code for the acceleration engine 812, in various instances, the host system 800 may execute a compiler 830. Generally, a compiler is a software program that translates program code written in a human-readable language into a format (e.g., machine instructions) that can be read and processed by an integrated circuit device. Figure 8 In the example of , acceleration engine 812 is a neural network accelerator, and compiler 830 is used to compile the neural network description into instructions to be executed by acceleration engine 812. When acceleration engine 812 implements a different type of accelerator, another compiler can be used.

[0131] For example, the compiler 830 may be activated when the operating system 820 receives keyboard, mouse, touch screen, voice command, or other input from the input / output device 708. The input may further include parameters for the compiler 830, such as input code 842 for compilation and configuration options for the compilation process. Once the compiler 830 is activated, the processor 802 may load the instructions of the compiler 830 into the processor memory 804 and may execute the instructions.

[0132] exist Figure 8 In the example of FIG, compiler 830 includes a first stage 832, a second stage 836, and a third stage 840, each of which performs different operations to produce compiled code 844. In other examples, compiler 830 may combine the operations of first stage 832, second stage 836, and / or third stage 840 into fewer stages, or may divide the operations of one of the stages into multiple stages.

[0133] The first stage 832 can receive and process input code 842. The input code 842 can describe a program in a high-level programming language, such as Java, C++, or TensorFlow, among many other examples. The input code 842 can describe, for example, the steps for performing image recognition, speech recognition, machine translation, or other operations. The input code 842 can be obtained, for example, from the storage device 806. Alternatively, although not shown here, the input code 842 can be located in the processor memory 804 or can be obtained from a network location using the network interface 810. Processing of the input code 842 can include classifying the operations described in the input code 842 into layers, where the output of one layer provides the input to the next layer. Processing can also include identifying steps to be performed by the processor 802 rather than the acceleration engine 812. For example, by executing the driver 822, the processor 802 may need to perform steps such as configuring direct memory access (DMA) descriptors to move data to or from the acceleration engine 812, among other examples.

[0134] The output 834 of the first stage 832 can be organized, for example, into layers, nodes, and connections between nodes of a neural network. The second stage 836 can perform intermediate processing on this output 834. For example, the operations performed in any one layer or at any one node in a layer may be too many for the acceleration engine 812 to perform simultaneously. The acceleration engine 812 may, for example, have a limited amount of local storage space for the data required for the calculation, or the calculation may be more than the acceleration engine 812 can perform at one time. In this example, the first stage 832 can break down the operations of the layer or node into smaller operations that can fit into the local memory of the acceleration engine and / or can fit into the computing power of the acceleration engine 812. The processing performed on the output 834 of the first stage 832 can include other steps, such as scheduling or determining the order in which the acceleration engine 812 and / or processor 802 will perform the operations, as well as other examples.

[0135] In various examples, the output 838 of the second stage 836 includes various steps to be performed by the components of the acceleration engine 812 in the order in which the steps are to be performed. The output 838 can be represented as, for example, a data flow graph, where the nodes in the graph represent memory operations, calculations, and other operations, and the edges or connections between the nodes represent dependencies between the nodes, such as data dependencies, memory dependencies, or operation dependencies, among other examples.

[0136] The third stage 840 may operate on the output 838 of the second stage 836 and perform various steps before generating instructions to be executed by the acceleration engine 812. These steps may include, for example, removing redundant dependencies, resolving or handling dependencies between nodes by inserting synchronization instructions into the code, identifying possible optimizations in memory usage or memory bandwidth usage, and other operations.

[0137] In some instances, the third stage 840 may include a data scheduler 850 to schedule the movement of data, such as input data and weight data, in the acceleration engine 812 to support various operations, such as convolution operations and dilated convolutions as described above. For example, the data scheduler 850 may obtain instructions (e.g., from a data flow graph) to perform a convolution operation (e.g., normal convolution, dilated convolution, etc.) between the input data array and the filter array to produce a convolution output array. Based on the size of the summing buffer at the acceleration engine 812, the data scheduler 850 may determine the output tiles that are suitable for the summing buffer, and may determine an instruction sequence to initiate the convolution operation to produce one output tile at a time. For each instruction, the data scheduler 850 may determine the sequence in which to load the weight data elements of the filter array into the processing engine array 410, and based on the above in Figures 5A-6G For each weight data element, a subset of input data to be loaded into the processing engine 410 is determined using the techniques described in

[15] for various types of convolution operations, such as normal convolution operations, transposed convolution operations, etc. For example, the data scheduler 850 may perform a transformation of the coordinates of the weight data element into rotated coordinates, such as Figure 6B The data scheduler 850 may then determine a first region (e.g., Figure 6F 632), such as Figures 6C-6E and then projecting the first region back into the input data array to obtain the second region (e.g., Figure 6F 645), the second region containing input data elements to be selected for multiplication with the weight data elements, such as Figure 6F As described. The projection can be based on the stride of the transposed convolution operation, where the size of the second region is based on the first region scaled by the stride of the transposed convolution operation. Based on the projection operation, the data scheduler 850 can also determine a set of buffer write parameters 452, which include a target offset and a number of write elements. The data scheduler 850 can then generate instructions to control the acceleration engine 812 to load the corresponding subset of weight data elements and input data elements to perform the transposed convolution operation.

[0138] The output of the third stage 840 is compiled code 844, which may include machine instructions in binary format. In some instances, the compiled code 844 may be stored in the processor memory 804. Alternatively or in addition, the compiled code 844 may be copied to the storage device 806 or to a network location. As described above, the acceleration engine 812 may be located at a different host system, in which case the compiled code 844 may be sent to another host system via the network interface 810.

[0139] exist Figure 8 In the example of FIG. 8 , the host system 800 may execute a driver 822, which may also be referred to as a device driver or runtime driver, to manage the acceleration engine 812. The driver 822 may provide an interface between an application executing on the host system 800 (or on another host system) and the acceleration engine 812. For example, the driver 822 may provide an application program interface (API) that defines functions for feeding input data to the acceleration engine 812 and defining operations to be performed on the input data. In this and other examples, the driver 822 may configure the acceleration engine 812 to perform operations. For example, the driver 822 may identify a neural network for the acceleration engine 812 to execute and the location of compiled code 844 for the neural network in the processor memory 804 or on the storage device 806. The driver 822 may further load the acceleration engine 812 or cause the acceleration engine 812 to load the compiled code 844, may load or cause the acceleration engine 812 to load the input data on which the neural network is to operate, and / or may cause the acceleration engine 812 to execute the input data. Once the acceleration engine 812 has completed, the acceleration engine 812 may notify the driver 822, and the driver 822 may deliver the results back to the application that requested the results.

[0140] Figure 9 A flow chart of an example method 900 for performing a transposed convolution operation is shown. The method 900 may be performed by, for example, various components of the accelerator 402, including the memory subsystem 404, the processing engine array 410, the summing buffer 412, and the controller 422.

[0141] Method 900 begins at step 902, where a controller (e.g., controller 422) can obtain a first weight data element of an array of weight data elements from a memory (e.g., memory subsystem 404) based on a first coordinate of the first weight data element in the array of weight data elements. The weight data elements can be stored at addresses in the memory subsystem 404 that reflect the coordinates of the weight data elements in the array of weight data elements. The controller 422 can be provided with the address of the first weight data element in a first calculation instruction and can obtain the first weight data element based on the address from the memory subsystem 404 after executing the first calculation instruction.

[0142] In step 904, the controller may load the first weight data element into a systolic array (e.g., processing engine array 410). As described above, each processing engine 411 may store a weight data element, and the controller may send the first weight data element to the processing engine 411 for storage.

[0143] In step 906, the controller can select a first subset of the input data elements of the array of input data elements based on the second coordinates of the first weight data element in the 180-degree rotated form of the array of weight data elements and the stride of the transposed convolution operation. The first subset of input data elements will be multiplied with the first weight data element at the processing engine 411 to produce a first partial sum, which can be forwarded to the column summation buffer (e.g., column summation buffer 442) of the summing buffer 412. The first subset can be selected based on a first calculation instruction comprising a first group of memory acquisition parameters 430, which can include the starting address, stride, and number of elements. When the 180-degree rotated array of weight data elements is located at a different stride position in the expanded array of the input data elements in the transposed convolution operation, the starting address and number of elements can reflect the input data elements that overlap with the first weight data element. Determining the first subset of input data elements may include shifting a stride pattern relative to a reference position of column sum buffer 442 based on a second coordinate to determine a first region representing an output tile that can fit into column sum buffer 442, and projecting the first region back into a second region within the array of input data elements to determine a count of input data elements included in the first subset. The stride pattern may include a set of pattern addresses, wherein the spacing between the pattern addresses reflects the stride of the transposed convolution operation. The size of the second region that determines the count of input data elements included in the first subset may be determined based on the first region (which reflects the size of column sum buffer 442) and scaled down by the inverse of the stride of the transposed convolution operation. The starting address of the first subset may be determined based on the coordinates of non-zero input data elements in the dilated array of input data elements, scaled down by the inverse of the stride of the transposed convolution operation, the non-zero input data elements overlapping the first weight data element when the 180-degree rotated array of weight data elements is located at the first stride position within the dilated array of input data elements.

[0144] In step 908, the controller may stream each input data element of the first subset starting from the first address from the memory into the systolic array to be multiplied by the first weight data element to calculate the first partial sum. The input data elements may be sent sequentially to the processing engine 411, which stores the first weight data element in step 904. The processing engine 411 may multiply each input data element by the first weight data element to produce the first partial sum. The first address may be the starting address of the first subset described above. The first partial sum may be sent to the first target address in the column summation buffer based on a first calculation instruction including a first set of buffer write parameters 452, which may include a target offset, a stride, and a number of write elements. The first partial sum may be added to the data stored at the first destination address. The first set of buffer write parameters 452 may be based on a shifted stride pattern as described above in step 906.

[0145] In step 910, the controller may obtain a second weight data element of the array of weight data elements from the memory based on the third coordinate of the second weight data element of the array of weight data elements. As described above, the weight data elements may be stored at addresses in the memory subsystem 404 that reflect the coordinates of the weight data elements in the array of weight data elements. The controller 422 may be provided with the address of the second weight data element in the second calculation instruction and may obtain the second weight data element based on the address from the memory subsystem 404 after executing the second calculation instruction.

[0146] In step 912 , the controller may load the second weight data element into the systolic array. The second weight data element may replace the first weight data element stored in the processing engine 411 in step 904 .

[0147] In step 914, the controller can select a second subset of input data elements of the array of input data elements based on the fourth coordinate of the second weight data element in the 180-degree rotated form of the array of weight data elements and the stride of the transposed convolution operation. The second subset of input data elements will be multiplied with the second weight data element at the processing engine 411 to produce a second partial sum, which can be forwarded to the column summing buffer. The second subset can be selected based on a second calculation instruction including a second set of memory acquisition parameters 430. When the 180-degree rotated array of weight data elements is located at a different stride position within the expanded array of input data elements in the transposed convolution operation, the second subset can be input data elements that overlap with the second weight data element. Determination of the second subset of input data elements can include shifting the stride pattern relative to the reference position of the column summing buffer 442 based on the fourth coordinate to determine the output tile, and projecting the output tile back to the array of input data elements to determine the count of input data elements included in the second subset. The starting address of the second subset can be determined based on the coordinates of the non-zero input data elements in the expanded array of input data elements, and when the 180-degree rotated array of weight data elements is located at the first step position relative to the expanded array of input data elements, the non-zero input data elements overlap with the second weight data elements.

[0148] In step 916, the controller may stream each input data element of the second subset starting from the second address from the memory into the systolic array to be multiplied by the second weight data element to calculate the second partial sum. The input data elements may be sent sequentially to the processing engine 411, which stores the second weight data elements in step 912. The processing engine 411 may multiply each input data element by the second weight data element to produce the second partial sum. The second address may be the starting address of the second subset described above. The second partial sum may be sent to a second target address in the column summation buffer based on a second calculation instruction including a second set of buffer write parameters 452. The second partial sum may be added to the data stored at the second target address, some or all of which may overlap with the first target address. The second set of buffer write parameters 452 may be based on the shifted stride pattern as described above in step 914.

[0149] In step 918, the controller may generate an output data array of the transposed convolution operation based on the first partial sum and the second partial sum. As described above, some of the first target addresses and the second target addresses may overlap, and some output data elements of the output data array may include the sum of the first partial sum and the second partial sum. Other output data elements of the output data array may be formed by superimposing the first partial sum and the second partial sum.

[0150] Figure 10 A flow chart of an example method 1000 for generating instructions for a neural network processor to perform a transposed convolution operation is shown. The method 1000 may be performed by Figure 8 The compiler 830 and other compilers in the program are executed.

[0151] Method 1000 begins at step 1002, where a compiler may receive first information indicating a stride of a transposed convolution operation to be performed by a systolic array (e.g., processing engine array 410) based on a weight data array and an input data array to generate an output data array. For example, the first information may be received from input code 842, which may indicate an application (an upsampling operation, a backward propagation operation, etc.) using a result of the transposed convolution operation.

[0152] In step 1004, the compiler may receive second information indicating the size of a summation buffer, such as column summation buffer 442. The summation buffer accumulates and stores partial sums from the systolic array for use in the transposed convolution operation. The second information may also be received from, for example, input code 842. As described above, the size information may be used to determine the output tile and, through a projection operation, may be used to determine a subset of the input data elements of the input data array for each weight data element of the weight data array.

[0153] In step 1006, the compiler may obtain a coordinate mapping between the weight data array and the 180-degree rotated version of the weight data array. The mapping may be performed, for example, by a coordinate mapping module 602, which may convert the original coordinates 604 of each weight data element in the weight data array into the rotated coordinates 606 of the weight data element in the 180-degree rotated version of the weight data array.

[0154] In step 1008, the compiler may determine a target address of a summing buffer for each weight data element of the weight data array to receive a partial sum. The partial sum is derived from a transposed convolution operation involving each weight data element. The determination may be based on the stride of the transposed convolution, the size information of the summing buffer, the coordinates of each weight data element in the weight data array, and the mapping of the coordinates. Specifically, return to reference Figure 6B, the compiler can convert the coordinates of each weight data element in the array of weight data into the rotated coordinates of the weight data element in the rotated weight data array. The compiler can determine a first area in the output data array corresponding to the target of the partial sum in the summing buffer based on the shifted stride pattern according to the rotated coordinates. The stride pattern can define a set of pattern coordinates, wherein adjacent pattern coordinates are separated by a distance corresponding to the stride of the transposed convolution operation. The size of the summing buffer (e.g., the number of columns and rows) can define the output tile of the output data elements of the first area in the output data array. The compiler can shift the stride pattern relative to a reference position with an offset based on the second coordinate. The reference position can be located at the first output data element of the output tile of the target mapped to the summing buffer, or at an imaginary position of the output data array with north padding and west padding mapped to the target of the summing buffer. The size of the summing buffer (e.g., the number of columns and rows) can also define a series of coordinates of the output data elements of the output tile. The compiler can compare the shifted pattern coordinates with the series of coordinates to determine a set of overlapping coordinates. The overlapping coordinates can provide the target address of the summing buffer to receive the first partial sum.

[0155] In step 1010, the compiler may determine, for each weight data element of the weight data array, a subset of input data elements of the input data array to be multiplied with each weight data element to calculate a partial sum. The subset of input data elements is determined based on a projection operation from the target address, the coordinates of each weight data element in the array of weight data, and a mapping of the coordinates. Return to Reference Figure 6F , the compiler may determine a first region including output tiles to be stored at a target address of the summing buffer, and project the first region back to a second region of the input data array to determine the number of input data elements to be included in the subset. The projection operation may be based on shrinking the first region by the inverse of the stride of the transposed convolution. The compiler may also calculate a third coordinate of a first input data element among the input data elements in the dilated input data array based on the second coordinate of the first weight data element in the rotated weight data array, the first input data element overlapping the first weight data element when the rotated weight data array is located at the first stride position relative to the dilated input data array. As part of the projection operation, the compiler may scale the third coordinate by the inverse of the stride to determine a fourth coordinate of the first input data element in the original input data array.

[0156] In step 1012, the compiler may generate a calculation instruction for each weight data element of the weight data array to include information indicating a target address and a subset of input data elements. The information may include, for example, a starting source address and a count of input data elements based on the projection operation in step 1010. The information may also include, for example, a starting target address, a step size indicating a gap between adjacent target addresses, and a count of target addresses based on the operation in step 1012. The calculation instruction may also include an address of each weight data element in a memory based on the coordinates of each weight data element in the weight data array.

[0157] Embodiments of the present disclosure may also be described in terms of the following:

[0158] 1. A non-transitory computer-readable medium storing instructions that, when executed by one or more hardware processors, cause the one or more hardware processors to:

[0159] loading a first weight data element of an array of weight data elements from a memory into a systolic array, the first weight data element having a first coordinate in the array of weight data elements;

[0160] extracting, from the instruction, information indicating a first subset of input data elements to be obtained from the memory, the first subset being based on a stride of a transposed convolution operation and a second coordinate of a first weight data element in the rotated array of weight data elements;

[0161] obtaining the first subset of input data elements from the memory based on the information;

[0162] loading the first subset of input data elements into the systolic array; and

[0163] The systolic array is controlled to perform a first calculation based on the first weight data element and the first subset of input data elements to produce an output data element of an array of output data elements.

[0164] 2. The non-transitory computer-readable medium of clause 1, wherein the instructions comprise:

[0165] a weight address of the first weight data element in the memory based on the first coordinate; and

[0166] source addresses of said first subset of input data elements in said memory based on said second coordinate,

[0167] Wherein execution of the instructions causes the one or more hardware processors to obtain the first weight data element from the memory based on the first address and to obtain the first subset of input data elements from the memory based on the second address.

[0168] 3. The non-transitory computer-readable medium of clause 2, wherein the input data elements are stored in a contiguous address space within the memory.

[0169] 4. The non-transitory computer-readable medium of clause 3, wherein the source address is a first source address associated with a first portion of the contiguous address space storing the first subset of input data elements;

[0170] The instructions include:

[0171] the first source address;

[0172] a first count of input data elements in said first subset of input data elements;

[0173] a second source address associated with a second portion of the contiguous address space storing a second subset of input data elements; and

[0174] a second count of input data elements in said second subset of input data elements;

[0175] wherein the instructions, when executed by the one or more hardware processors, further cause the one or more hardware processors to:

[0176] obtaining the first subset of the input data elements from the memory based on the first source address and the first count;

[0177] controlling the systolic array to perform the first calculation between the first subset of input data elements and the first weight data elements to produce a first partial sum;

[0178] obtaining the second subset of the input data elements from the memory based on the second source address and the second count;

[0179] obtaining a second weight data element from said memory; and

[0180] controlling the systolic array to perform a second calculation between the second subset of the input data elements and the second weight data elements to produce a second partial sum; and

[0181] wherein the output data element is generated from the first partial sum and the second partial sum.

[0182] 5. The non-transitory computer-readable medium of clause 4, wherein the instructions include a first target address of a summing buffer for receiving the first partial sum and a second target address of the summing buffer for receiving the second partial sum;

[0183] wherein the first target address is based on a stride pattern shifted from a reference position by a first offset, the first offset being based on the first coordinate;

[0184] wherein the second target address is based on the stride pattern shifted from the reference position by a second offset, the second offset being based on the second coordinate; and

[0185] Wherein the stride pattern is based on the stride of the transposed convolution operation.

[0186] 6. The non-transitory computer-readable medium of clause 5, wherein the reference position is based on a size of a north fill and a size of a west fill of the array of output data elements.

[0187] 7. The non-transitory computer-readable medium of clause 5 or 6, wherein:

[0188] The target address of the summing buffer is mapped to a series of coordinates of output data elements in the array of output data elements;

[0189] The stride pattern defines pattern coordinates;

[0190] The gap between adjacent pattern coordinates of the stride pattern is based on the stride;

[0191] The shifting of the stride pattern comprises a shifting of the pattern coordinates; and

[0192] The first and second target addresses include first and second pattern coordinates, respectively, of a shifted stride pattern within the range of coordinates that map to the output data element of the target address of the summing buffer.

[0193] 8. The non-transitory computer-readable medium of clause 7, wherein the instructions, when executed by the one or more hardware processors, cause the one or more hardware processors to cause the summing buffer to:

[0194] adding the first partial sum to the data stored at the first target address; and

[0195] The second partial sum is added to the data stored at the second target address.

[0196] 9. The non-transitory computer-readable medium of clause 7 or 8, wherein:

[0197] said rotated array of weight data elements being based on a 180 degree rotation of said array of weight data elements;

[0198] the transposed convolution operation comprising a convolution operation between the rotated array of weight data elements and a dilated array of input data elements, the dilated array of input data elements being dilated based on padding a number of zeros between input data elements of the array of input data elements according to the stride;

[0199] the first source address being based on a first position of a first input element in the dilated array of input data, the first input element overlapping the first weight data element of the rotated array of weight data elements when the rotated array of weight data elements is located at a starting stride position relative to the dilated array of input data elements;

[0200] the first count of input data elements in the first subset of the input data elements being based on a count of the first target address;

[0201] the second source address is based on a second position of a second input element in the dilated array of input data elements, the second input element overlapping the second weight data element of the rotated array of weight data elements when the rotated array of weight data elements is located at the starting stride position relative to the dilated array of input data; and

[0202] The second count of input data elements in the second subset of the input data elements is based on the count of the second target address.

[0203] 10. The non-transitory computer-readable medium of any of clauses 5 to 9, wherein the instructions, when executed by the one or more hardware processors, cause the one or more hardware processors to: initialize the summing buffer to zero.

[0204] 11. The non-transitory computer-readable medium of any one of clauses 5 to 10, wherein the instructions, when executed by the one or more hardware processors, cause the one or more hardware processors to:

[0205] The summing buffer is controlled to output zeros for output data elements at a third target address based on an indication that the third target address has not received a write operation since the transposed convolution operation began.

[0206] 12. A device comprising:

[0207] a memory storing a set of instructions; and

[0208] One or more hardware processors configured to execute the set of instructions to:

[0209] receiving first information indicating a stride of a transposed convolution operation to be performed by the systolic array based on the weight data array and the input data array to produce an output data array;

[0210] receiving second information indicating a size of the summing buffer;

[0211] Obtaining a mapping of coordinates between the weight data array and a 180-degree rotated version of the weight data array;

[0212] determining, for each weight data element of the weight data array, a target address of the summing buffer to receive a partial sum from the transposed convolution operation involving the each weight data element, the target address being determined based on the stride of the transposed convolution, the size information of the summing buffer, the coordinates of the each weight data element in the weight data array, and the mapping of coordinates;

[0213] determining, for each weight data element of the weight data array, a subset of input data elements of the input data array to be multiplied by each weight data element to produce the partial sum, the subset of input data elements being determined based on a projection operation from the target address, the coordinates of each weight data element in the weight data array, and the mapping of coordinates; and

[0214] A calculation instruction for each weight data element of the weight data array is generated to include third information indicative of the target address and the subset of input data elements.

[0215] 13. The apparatus of clause 12, wherein the one or more hardware processors are configured to execute the set of instructions to, for each weight data element:

[0216] determining rotated coordinates of the weight data in the 180 degree rotated version of the weight data array based on the mapping and coordinates of the coordinates of each weight data element in the weight data array;

[0217] determining an offset based on the rotated coordinates;

[0218] shifting the stride pattern relative to a reference position based on the offset; and

[0219] The target address of the summing buffer is determined based on the size of the summing buffer and a shifted stride pattern to receive partial sums from the systolic array.

[0220] 14. The apparatus of clause 13, wherein the transposed convolution operation comprises a convolution operation between the 180-degree rotated version of the weight data array and a dilated input data array, the dilated input data array being dilated based on padding a number of zeros between input data elements of the input data array according to the stride;

[0221] The one or more hardware processors are configured to execute the set of instructions to perform the projection operation, the projection operation comprising, for each weight data element:

[0222] determining a first position of a first input element in the dilated input data array, the first input element overlapping each of the weight data elements when the 180-degree rotated weight data array is at a starting stride position relative to the dilated input data array;

[0223] determining a second position of the first input element in the input data array based on scaling the first position by the inverse of the stride; and

[0224] A count of input data elements included in the subset of input data elements starting with the first input element is determined based on the count of the target addresses.

[0225] 15. Apparatus according to any of clauses 13 or 14, wherein the reference position is based on a size of a north fill and a size of a west fill of the output data array.

[0226] 16. A method for performing a transposed convolution operation in a neural network accelerator, the method comprising:

[0227] obtaining a first weight data element of an array of weight data elements from a memory, wherein said obtaining is based on a first coordinate of said first weight data element in said array of weight data elements;

[0228] loading the first weight data element into a systolic array of the neural network accelerator;

[0229] receiving a selection of a first subset of input data elements of an array of input data elements to be multiplied with the first weight data element, the first subset being selected based on second coordinates of the first weight data elements in a 180 degree rotated version of the array of weight data elements and a stride of the transposed convolution operation;

[0230] streaming each input data element of the first subset starting from a first source address from the memory into the systolic array to compute a first partial sum;

[0231] obtaining, from the memory, a second weight data element of the array of weight data elements, wherein the obtaining is based on a third coordinate of the second weight data element of the array of weight data elements;

[0232] loading the second weight data element into the systolic array;

[0233] receiving a selection of a second subset of input data elements of the array of input data elements to be multiplied with the second weight data element, the second subset being selected based on fourth coordinates of the second weight data elements in the 180 degree rotated version of the array of weight data elements and the stride of the transposed convolution operation;

[0234] streaming each input data element of the second subset starting from a second address from the memory into the systolic array to compute a second partial sum; and

[0235] An output data array of the transposed convolution operation is generated based on the first partial sum and the second partial sum.

[0236] 17. The method of clause 16, further comprising:

[0237] adding the first partial sum to a partial sum stored at a first target address in a summing buffer, the first target address being based on a second coordinate of the first weight data element in the 180 degree rotated version of the array of the stride and weight data elements; and

[0238] adding the second partial sum to a partial sum stored at a second target address in the summing buffer, the second target address being based on a fourth coordinate of the second weight data element in the 180 degree rotated version of the array of stride and weight data elements;

[0239] Wherein a size of the first subset of input data elements is selected based on a size of the summation buffer and the stride of the transposed convolution.

[0240] 18. The method of clause 17, wherein the first target address in the summing buffer is based on a stride pattern that is shifted from a reference location by a first offset based on the second coordinate;

[0241] wherein the second target address in the summing buffer is based on the stride pattern shifted from the reference location by a second offset based on the fourth coordinate; and

[0242] Wherein each element of the stride pattern is separated by a gap based on the stride.

[0243] 19. The method of clause 18, wherein the transposed convolution operation comprises a convolution operation between a first array comprising the 180-degree rotated version of the array of weight data elements and a second array comprising a dilated version of the array of input data elements, the dilated version of the array being created by padding a plurality of zeros between adjacent input data elements of the array of input data elements, the number of zeros being based on the stride;

[0244] wherein the first source address is based on a fifth coordinate of a first input data element of the second array scaled by the inverse of the stride, the first input data element overlapping the first weight data element of the first array when the first array is at a starting stride position relative to the second array; and

[0245] wherein the second source address is based on a sixth coordinate of a second input data element of the second array scaled by the inverse of the stride, the second input data element overlapping with the second weight data element of the first array when the first array is located at the starting stride position relative to the second array.

[0246] 20. The method of any one of clauses 16 to 19, further comprising:

[0247] The summing buffer is reset before calculating the first partial sum and the second partial sum.

[0248] 21. The method of any one of clauses 16 to 20, further comprising:

[0249] storing, at each register associated with each target address, a flag indicating whether the each target address has received a partial sum from the systolic array; and

[0250] The summing buffer is controlled to output zeros for a third target address based on the flag stored in the register associated with the third target address, the flag indicating that the third target address has not received a partial sum from the systolic array.

[0251] Figure 11 A diagram of an example network 1100 is included, which may include one or more host systems, such as Figure 8 For example, Figure 11 The example network 1100 includes a plurality of nodes 1102a-1102h, wherein one or more of the plurality of nodes may be Figure 8The host system shown. Other nodes in nodes 1102a-1102h may be other computing devices, each of which includes at least a memory for storing program instructions, a processor for executing the instructions, and a network interface for connecting to network 1100.

[0252] In various instances, network 1100 can be used to process data. For example, input data can be received at one of nodes 1102a-1102h or received from other networks 1108 with which network 1100 can communicate. In this instance, the input data can be directed to a node in the network 1100 that comprises an acceleration engine, for the acceleration engine to run and produce a result. The result can then be transferred to a node or other network that receives the input data. In various instances, the input data can be accumulated from various sources, comprising one or more nodes in nodes 1102a-1102h and / or a computing device positioned in other networks 1108, and the accumulated input data can be directed to one or more host systems in network 1100. The result from the host system can then be distributed back to the source that collects the input data.

[0253] In various instances, one or more of nodes 1102a-1102h can be responsible for operations such as accumulating input data for host system operations, tracking which host systems are busy and which host systems can accept more work, determining whether the host systems are operating correctly and / or most efficiently, monitoring network security and / or other management operations.

[0254] exist Figure 11 In the example of FIG, nodes 1102a-1102h are connected to each other using a switching fabric with point-to-point links. The switching fabric includes multiple switches 1104a-1104d, which can be arranged in a multi-layer network such as a Clos network. A network device that filters and forwards data packets between local area network (LAN) segments can be referred to as a switch. Switches typically operate at the data link layer (layer 2) of the Open Systems Interconnection (OSI) reference model and sometimes at the network layer (layer 3) and can support several data packet protocols. Figure 11 The switches 1104a-1104d may be connected to the nodes 1102a-1102h and provide multiple paths between any two nodes.

[0255] The network 1100 may also include one or more network devices for connecting to other networks 1108, such as routers 1106. Routers use headers and forwarding tables to determine the best path to forward packets, and use protocols such as the Internet Control Message Protocol (ICMP) to communicate with each other and configure the best route between any two devices. Figure 11The router 1106 can be used to connect to other networks 1108, such as a subnet, a LAN, a wide area network (WAN), and / or the Internet.

[0256] In some examples, the network 1100 can include any one or combination of many different types of networks, such as a wired network, the Internet, a wireless network, a cellular network, and other private and / or public networks. If present, the interconnected switches 1104a-1104d and routers 1106 can be referred to as a switching fabric 1110, a fabric, a network fabric, or simply a network. In the context of computer networks, the terms "fabric" and "network" are used interchangeably herein.

[0257] Nodes 1102a-1102h may be any combination of host systems, processor nodes, storage subsystems, and I / O chassis representing user equipment, service provider computers, or third-party computers.

[0258] The user device may include a computing device for accessing applications 1132 (e.g., a web browser or mobile device application). In some aspects, applications 1132 may be hosted, managed, and / or provided by a computing resource service or service provider. Applications 1132 may allow a user to interact with a service provider computer, for example, to access network content (e.g., web pages, music, videos, etc.). The user device may be a computing device such as, for example, a mobile phone, a smartphone, a personal digital assistant (PDA), a laptop computer, a netbook, a desktop computer, a thin terminal device, a tablet computer, an e-book reader, a game console, etc. In some examples, the user device may communicate with the service provider computer via other networks 1108. In addition, the user device may be part of a distributed system that is managed, controlled, or otherwise part of a service provider computer (e.g., a console device integrated with the service provider computer).

[0259] Figure 11The nodes may also represent one or more service provider computers. One or more service provider computers may provide local applications configured to run on user devices, with which users can interact. In some instances, the service provider computers may provide computing resources such as, but not limited to, client entities, low-latency data storage, persistent data storage, data access, management, virtualization, cloud-based software solutions, and electronic content performance management. The service provider computers may also be operable to provide users with web hosting, databases, computer application development and / or implementation platforms, or combinations thereof. In some instances, the service provider computers may be provided as one or more virtual machines implemented in a hosted computing environment. A hosted computing environment may include one or more computing resources that are rapidly provisioned and released. These computing resources may include computing, network, and / or storage devices. A hosted computing environment may also be referred to as a cloud computing environment. The service provider computers may include one or more servers, which may be arranged in a cluster, as a server farm, or as independent individual servers, and may host applications 1132 and / or cloud-based software services. These servers may be configured as part of an integrated distributed computing environment. In some aspects, additionally or alternatively, the service provider computer may comprise a computing device such as, for example, a mobile phone, a smartphone, a personal digital assistant (PDA), a laptop computer, a desktop computer, a netbook, a server computer, a thin terminal device, a tablet computer, a gaming console, etc. In some cases, the service provider computer may communicate with one or more third-party computers.

[0260] In one example configuration, nodes 1102a-1102h may include at least one memory 1118 and one or more processing units (or processors 1120). Processor 1120 may be implemented in hardware, computer-executable instructions, firmware, or a combination thereof. The computer-executable instructions or firmware implementation of processor 1120 may include computer-executable instructions or machine-executable instructions written in any suitable programming language for performing the various functions described.

[0261] In some cases, the hardware processor 1120 can be a single-core processor or a multi-core processor. A multi-core processor can include multiple processing units within the same processor. In some instances, the multi-core processors can share certain resources, such as a bus and a second-level cache or a third-level cache. In some cases, each core in a single-core processor or a multi-core processor can also include multiple execution logical processors (or execution threads). Among such cores (e.g., a core with multiple logical processors), several stages of the execution pipeline and lower-level caches can also be shared.

[0262] The memory 1118 can store program instructions that can be loaded and executed on the processor 1120, as well as data generated during the execution of these programs. Depending on the configuration and type of the nodes 1102a-1102h, the memory 1118 can be volatile (such as RAM) and / or non-volatile (such as ROM, flash memory, etc.). The memory 1118 can contain an operating system 1128, one or more data storage areas 1130, one or more application programs 1132, one or more drivers 1134, and / or services for implementing the features disclosed herein.

[0263] Operating system 1128 can support basic functions of nodes 1102a-1102h, such as scheduling tasks, executing applications, and / or controlling peripheral devices. In some embodiments, the service provider computer can host one or more virtual machines. In these embodiments, each virtual machine can be configured to execute its own operating system. Examples of operating systems include Unix, Linux, Windows, Mac OS, iOS, Android, etc. Operating system 1128 can also be a proprietary operating system.

[0264] Data storage area 1130 may contain permanent or temporary data used and / or operated by operating system 1128, application programs 1132, or driver programs 1134. Examples of such data include web pages, video data, audio data, images, user data, and the like. In some embodiments, the information in data storage area 1130 may be provided to a user device via network 1108. In some cases, additionally or alternatively, data storage area 1130 may contain stored application programs and / or driver programs. Additionally or alternatively, data storage area 1130 may store standard and / or proprietary software libraries, and / or standard and / or proprietary application user interface (API) libraries. The information stored in data storage area 1130 may be machine-readable object code, source code, interpreted code, or intermediate code.

[0265] Driver 1134 comprises the program that can provide communication between the component in node.For example, some drivers 1134 can provide the communication between operating system 1128 and other storage device 1122, network device 1124 and / or I / O device 1126.Alternatively or in addition, some drivers 1134 can provide the communication between application program 1132 and operating system 1128, and / or the communication between application program 1132 and the peripheral device that service provider computer can access.In many cases, driver 1134 can comprise the driver (for example, printer driver, display driver, hard disk driver and solid state device driver) that provides the function that is easy to understand.In other cases, driver 1134 can provide proprietary or special function.

[0266] The service provider computer or server may also include additional storage devices 1122, which may include removable storage devices and / or non-removable storage devices. Additional storage devices 1122 may include magnetic storage, optical disks, solid-state disks, flash memory, and / or tape storage devices. Additional storage devices 1122 may be housed in the same rack as nodes 1102a-1102h or may be located in an external hard drive enclosure. Memory 1118 and / or additional storage devices 1122 and their associated computer-readable media may provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for the computing device. In some embodiments, memory 1118 may include multiple different types of memory, such as SRAM, DRAM, or ROM.

[0267] Removable and non-removable memory 1118 and additional storage devices 1122 are examples of computer-readable storage media. For example, computer-readable storage media may include volatile or non-volatile, removable or non-removable media implemented in a method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Memory 1118 and additional storage devices 1122 are examples of computer storage media. Other types of computer storage media that may be present in nodes 1102a-1102h may include, but are not limited to, PRAM, SRAM, DRAM, RAM, ROM, EEPROM, flash memory or other storage technologies, CD-ROM, DVD or other optical storage devices, magnetic cassettes, magnetic tape, magnetic disk storage devices or other magnetic storage devices, solid-state drives, or other media that can be used to store the desired information and that can be accessed by nodes 1102a-1102h. Computer-readable media also includes combinations of any of the above media types, including multiple elements of a single media type.

[0268] Alternatively or additionally, computer-readable communication media may include computer-readable instructions, program modules, or other data transmitted within a data signal, such as a carrier wave or other transmission. However, as used herein, computer-readable storage media does not include computer-readable communication media.

[0269] Nodes 1102a-1102h may also include I / O devices 1126, such as a keyboard, mouse, pen, voice input device, touch input device, display, speaker, printer, etc. Nodes 1102a-1102h may also include one or more communication channels 1136. Communication channels 1136 may provide a medium through which the various components of nodes 1102a-1102h can communicate. One or more communication channels 1136 may take the form of a bus, ring, switch fabric, or network.

[0270] The nodes 1102a - 1102h may also contain a network device 1124 that allows the nodes 1102a - 1102h to communicate with a stored database, another computing device or server, a user terminal, and / or other devices on the network 1100 .

[0271] In some embodiments, the network device 1124 is a peripheral device, such as a PCI-based device. In these embodiments, the network device 1124 includes a PCI interface for communicating with a host device. The term "PCI" or "PCI-based" can be used to describe any protocol in the PCI bus protocol family, including the original PCI standard, PCI-X, Accelerated Graphics Port (AGP) and PCI-Express (PCIe) or any other improvement or derivative protocol based on the PCI protocol discussed herein. A PCI-based protocol is a standard bus protocol for connecting devices such as local peripheral devices to a host device. A standard bus protocol is a data transmission protocol whose specifications have been defined and adopted by various manufacturers. Manufacturers ensure that compatible devices are compatible with computing systems that implement the bus protocol, and vice versa. As used herein, a PCI-based device also includes a device that communicates using fast non-volatile memory (NVMe). NVMe is a device interface specification for accessing non-volatile storage media connected to a computing system using PCIe. For example, the bus interface module may implement NVMe and the network device 1124 may connect to the computing system using a PCIe interface.

[0272] The modules described herein may be software modules, hardware modules, or a suitable combination thereof. If the modules are software modules, the modules may be embodied on a non-transitory computer-readable medium and processed by a processor of any of the computer systems described herein. It should be noted that the described processes and architectures may be executed in real time or in an asynchronous mode prior to any user interaction. The modules may be configured in the manner suggested in the aforementioned figures, and / or the functionality described herein may be provided by one or more modules existing as separate modules, and / or the module functionality described herein may be distributed across multiple modules.

[0273] Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the claims.

[0274] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrative examples thereof are shown in the drawings and have been described in detail above. However, it should be understood that there is no intention to limit the present disclosure to the specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0275] Unless otherwise indicated herein or clearly contradicted by context, the terms "a / an" and "the" and similar referents used in the context of describing the disclosed examples (especially in the context of the following claims) should be interpreted to cover both the singular and the plural. The terms "comprising," "having," "including," and "containing" should be interpreted as open-ended terms (i.e., meaning "including, but not limited to") unless otherwise indicated herein or clearly contradicted by context. The term "connected" should be interpreted as partially or completely contained within, attached to, or joined together, even in the presence of intervening substances. Unless otherwise indicated herein, the recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. Unless otherwise stated, the use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illustrate examples of the present disclosure and does not limit the scope of the present disclosure. No language in this specification should be construed as indicating any non-claimed element as essential to the practice of the present disclosure.

[0276] Unless expressly stated otherwise, disjunctive language such as the phrase "at least one of X, Y, or Z" is intended to be understood in the context of being generally used to express that an item, term, etc. can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that certain instances require that at least one of X, at least one of Y, or at least one of Z each be present.

[0277] Various examples of the present disclosure are described herein, including the best modes for implementing the present disclosure known to the inventors. After reading the above description, variations of these examples will become apparent to those of ordinary skill in the art. The inventors anticipate that technicians may adopt such variations when appropriate, and the inventors intend that the present disclosure be practiced in other ways different from those specifically described herein. Therefore, where permitted by applicable law, the present disclosure includes all modifications and equivalents of the subject matter recited in the appended claims. In addition, unless otherwise indicated herein or clearly contradicted by the context, the present disclosure encompasses any combination of the above-mentioned elements in all their possible variations.

Claims

1. A non-transitory computer-readable medium storing instructions that, when executed by one or more hardware processors, cause the one or more hardware processors to: loading a first weight data element of an array of weight data elements from a memory into a systolic array, the first weight data element having a first coordinate in the array of weight data elements; extracting, from the instruction, information indicating a first subset of input data elements to be obtained from the memory, the first subset of input data elements being based on a stride of a transposed convolution operation and second coordinates of first weight data elements in a 180 degree rotated version of the array of weight data elements; obtaining the first subset of input data elements from the memory based on the information; loading the first subset of input data elements into the systolic array; and The systolic array is controlled to perform a first calculation based on the first weight data element and the first subset of input data elements to produce an output data element of an array of output data elements.

2. The non-transitory computer-readable medium of claim 1 , wherein the instructions comprise: a weight address of the first weight data element in the memory based on the first coordinate of the first weight data element in the array of weight data elements; and source addresses of the first subset of input data elements in the memory based on the second coordinates of the first weight data element in a 180 degree rotated version of the array of weight data elements, Wherein execution of the instructions causes the one or more hardware processors to obtain the first weight data element from the memory based on the weight address and to obtain the first subset of input data elements from the memory based on the source address. 3 . The non-transitory computer-readable medium of claim 2 , wherein the input data elements are stored in a contiguous address space within the memory.

4. The non-transitory computer-readable medium of claim 3, wherein the source address is a first source address associated with a first portion of the contiguous address space storing the first subset of input data elements; The instructions include: the first source address; a first count of input data elements in said first subset of input data elements; a second source address associated with a second portion of the contiguous address space storing a second subset of input data elements; as well as a second count of input data elements in said second subset of input data elements; wherein the instructions, when executed by the one or more hardware processors, further cause the one or more hardware processors to: obtaining the first subset of the input data elements from the memory based on the first source address and the first count; controlling the systolic array to perform the first calculation between the first subset of input data elements and the first weight data elements to produce a first partial sum; obtaining the second subset of the input data elements from the memory based on the second source address and the second count; obtaining a second weight data element from the memory; and controlling the systolic array to perform a second calculation between the second subset of the input data elements and the second weight data elements to produce a second partial sum; and wherein the output data element is generated from the first partial sum and the second partial sum.

5. The non-transitory computer-readable medium of claim 4, wherein the instructions include a first target address of a summing buffer for receiving the first partial sum and a second target address of the summing buffer for receiving the second partial sum; wherein the first target address is based on a stride pattern shifted from a reference position by a first offset, the first offset being based on the first coordinate; wherein the second target address is based on the stride pattern shifted from the reference position by a second offset, the second offset being based on the second coordinate; and Wherein the stride pattern is based on the stride of the transposed convolution operation. 6 . The non-transitory computer-readable medium of claim 5 , wherein the reference position is based on a size of a north fill and a size of a west fill of the array of output data elements.

7. The non-transitory computer-readable medium according to claim 5 or 6, wherein: The target address of the summing buffer is mapped to a series of coordinates of output data elements in the array of output data elements; The stride pattern defines pattern coordinates; The gap between adjacent pattern coordinates of the stride pattern is based on the stride; The shifting of the stride pattern comprises a shifting of the pattern coordinates; and The first and second target addresses include first and second pattern coordinates, respectively, of a shifted stride pattern within the range of coordinates that map to the output data element of the target address of the summing buffer.

8. The non-transitory computer-readable medium of claim 7, wherein the instructions, when executed by the one or more hardware processors, cause the one or more hardware processors to cause the summing buffer to: adding the first partial sum to the data stored at the first target address; and The second partial sum is added to the data stored at the second target address.

9. The non-transitory computer-readable medium of claim 7, wherein: the transposed convolution operation comprising a convolution operation between a 180-degree rotated version of the array of weight data elements and a dilated array of input data elements, the dilated array of input data elements being dilated based on padding a number of zeros between input data elements of the array of input data elements according to the stride; the first source address being based on a first position of a first input element in the dilated array of input data, the first input element overlapping the first weight data element of the 180-degree rotated version of the array of weight data elements when the 180-degree rotated version of the array of weight data elements is located at a starting stride position relative to the dilated array of input data elements; the first count of input data elements in the first subset of the input data elements being based on a count of the first target address; the second source address is based on a second position of a second input element in the dilated array of input data elements, the second input element overlapping the second weight data element of the 180-degree rotated version of the array of weight data elements when the 180-degree rotated version of the array of weight data elements is located at the starting stride position relative to the dilated array of input data; and The second count of input data elements in the second subset of the input data elements is based on the count of the second target address.

10. The non-transitory computer-readable medium of claim 5 or 6, wherein the instructions, when executed by the one or more hardware processors, cause the one or more hardware processors to: initialize the summing buffer to zero.

11. The non-transitory computer-readable medium of claim 5 or 6, wherein the instructions, when executed by the one or more hardware processors, cause the one or more hardware processors to: The summing buffer is controlled to output zeros for output data elements at a third target address based on an indication that the third target address has not received a write operation since the transposed convolution operation began.

12. A device comprising: a memory storing a set of instructions; as well as One or more hardware processors configured to execute the set of instructions to: receiving first information indicating a stride of a transposed convolution operation to be performed by the systolic array based on the weight data array and the input data array to produce an output data array; receiving second information indicating a size of the summing buffer; Obtaining a mapping of coordinates between the weight data array and a 180-degree rotated version of the weight data array; determining, for each weight data element of the weight data array, a target address of the summing buffer to receive a partial sum from the transposed convolution operation involving the each weight data element, the target address being determined based on the stride of the transposed convolution, the size information of the summing buffer, the coordinates of the each weight data element in the weight data array, and the mapping of coordinates; determining, for each weight data element of the weight data array, a subset of input data elements of the input data array to be multiplied by each weight data element to produce the partial sum, the subset of input data elements being determined based on a projection operation from the target address, the coordinates of each weight data element in the weight data array, and the mapping of coordinates; and A calculation instruction for each weight data element of the weight data array is generated to include third information indicative of the target address and the subset of input data elements.

13. The apparatus of claim 12 , wherein the one or more hardware processors are configured to execute the set of instructions to, for each weight data element: determining rotated coordinates of the weight data in the 180 degree rotated version of the weight data array based on the mapping and coordinates of the coordinates of the each weight data element in the weight data array; determining an offset based on the rotated coordinates; shifting the stride pattern relative to a reference position based on the offset; and The target address of the summing buffer is determined based on the size of the summing buffer and a shifted stride pattern to receive partial sums from the systolic array.

14. The apparatus of claim 13 , wherein the transposed convolution operation comprises a convolution operation between the 180-degree rotated version of the weight data array and a dilated input data array, the dilated input data array being dilated based on padding a number of zeros between input data elements of the input data array according to the stride; The one or more hardware processors are configured to execute the set of instructions to perform the projection operation, the projection operation comprising, for each weight data element: determining a first position of a first input element in the dilated input data array when the 180-degree rotated weight data array is at a starting stride position relative to the dilated input data array, The first input element overlaps with each of the weight data elements; determining a second position of the first input element in the input data array based on scaling the first position by the inverse of the stride; and A count of input data elements included in the subset of input data elements starting with the first input element is determined based on the count of the target addresses.

15. Apparatus according to any one of claims 13 or 14, wherein the reference position is based on a size of a north padding and a size of a west padding of the output data array.

Images