Bandgap reference voltage source

Abstract

The present invention provides a bandgap reference voltage source, and the voltage source includes: a bandgap reference main circuit and a bandgap reference start-up transient enhancement circuit. The bandgap reference start-up transient enhancement circuit includes a voltage replication module, a negative feedback loop module, a logic flip-flop module, and a switched current source module. The voltage replication module is configured to obtain a bandgap reference driving voltage according to the mirrored current output from the first output terminal of the bandgap reference main circuit. The negative feedback loop module is configured to regulate the voltage of the bandgap reference driving voltage. The switched current source module is configured to be turned on or off according to the logic control signal, so as to control the charging state of the second output terminal of the bandgap reference main circuit, solving the problem in the prior art that the load capacitance at the output terminal affects the turn-on speed of the bandgap reference voltage source, realizing the transient enhancement of the turn-on of the output voltage of the bandgap reference voltage source, and being able to greatly reduce the time for the output voltage to reach the stable value.

Description

Technical Field

[0001] The present invention relates to the field of electronic technologies, and particularly to a bandgap reference voltage source. Background Art

[0002] The bandgap reference voltage source is an important module in modern power management and hybrid integrated circuit systems. It can be widely applied to various electronic devices such as analog-to-digital and digital-to-analog converters, data collectors, etc. Its main feature is that it can output a DC voltage that is independent of the power supply and the process and has certain temperature characteristics.

[0003] For the bandgap reference voltage source, the magnitude of the output voltage can be changed through various circuit structures to meet the requirements of different voltage magnitudes of the modules powered. Since power needs to be supplied to each module, a large load capacitance often generates at the output end, thereby affecting the transient turn-on speed of the bandgap reference output end. Therefore, how to weaken or eliminate this kind of influence has become the key to improving the important transient performance of the bandgap reference. Summary of the Invention

[0004] Aiming at the deficiencies existing in the prior art, the bandgap reference voltage source provided by the present invention solves the problem that the load capacitance at the output end in the prior art affects the turn-on speed of the bandgap reference voltage source, realizes the transient enhancement of the turn-on of the output voltage of the bandgap reference voltage source, and can greatly reduce the time for the output voltage to reach the stable value.

[0005] The present invention provides a bandgap reference voltage source, which includes: a bandgap reference main circuit and a bandgap reference start transient enhancement circuit. The bandgap reference start transient enhancement circuit includes a voltage replication module, a negative feedback loop module, a logic flip-flop module, and a switched current source module; the bandgap reference main circuit is used to provide a reference voltage for the subsequent load; the input end of the voltage replication module is connected to the first output end of the bandgap reference main circuit, and is used to obtain a bandgap reference drive voltage according to the mirror current output from the first output end of the bandgap reference main circuit; the input end of the negative feedback loop module is connected to the output end of the voltage replication module, and is used to regulate the voltage of the bandgap reference drive voltage; the first input end of the logic flip-flop module is connected to the output end of the negative feedback loop module, and the second input end of the logic flip-flop module is connected to the second output end of the bandgap reference main circuit, and is used to output a corresponding logic control signal according to the current voltage value output from the second output end of the bandgap reference main circuit; the input end of the switched current source module is connected to the output end of the logic flip-flop module, and the output end of the switched current source module is connected to the second output end of the bandgap reference main circuit, and is used to conduct or cut off according to the logic control signal, thereby controlling the charging state of the second output end of the bandgap reference main circuit.

[0006] Optionally, the negative feedback loop module includes: a first NMOS transistor, a second NMOS transistor, a first resistor, and a second resistor; the gate of the first NMOS transistor is connected to the output terminal of the voltage replication module, the drain of the first NMOS transistor is connected to the power output terminal, the source of the first NMOS transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; the gate of the second NMOS transistor is connected to the second end of the first resistor, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor; wherein, the source of the first NMOS transistor is the output terminal of the negative feedback loop module.

[0007] Optionally, the logic flip module includes: a first PMOS transistor and a third NMOS transistor; the gate of the first PMOS transistor is connected to the second output terminal of the bandgap reference main circuit, the source of the first PMOS transistor is connected to the output terminal of the negative feedback loop module, and the drain of the first PMOS transistor is the output terminal of the logic flip module; the gate of the third NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor, and the source of the third NMOS transistor is grounded.

[0008] Optionally, the voltage replication module includes: a second PMOS transistor and a third resistor; the gate of the second PMOS transistor is connected to the first output terminal of the bandgap reference main circuit, the source of the second PMOS transistor is connected to the power output terminal, the drain of the second PMOS transistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded.

[0009] Optionally, the switched current source module includes: a fourth NMOS transistor and a mirror current source; the gate of the fourth NMOS transistor is connected to the output terminal of the logic flip circuit, the drain of the fourth NMOS transistor is connected to the output terminal of the mirror current source, and the source of the fourth NMOS transistor is the output terminal of the switched current source module.

[0010] Optionally, the mirror current source includes: a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a current source; the gates of the third PMOS transistor and the fourth PMOS transistor are connected; the sources of the third PMOS transistor and the fourth PMOS transistor are respectively connected to the power output terminal; the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor; the drain of the fourth PMOS transistor is connected to the gate of the fourth PMOS transistor; the gates of the fifth NMOS transistor and the sixth NMOS transistor are connected; the drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor; the sources of the fifth NMOS transistor and the sixth NMOS transistor are respectively grounded; the drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor; the drain of the sixth NMOS transistor is further connected to the output terminal of the current source; the input terminal of the current source is connected to the power output terminal.

[0011] Optionally, the bandgap reference main circuit includes: a fifth PMOS transistor, a sixth PMOS transistor, a seventh MOS transistor, an operational amplifier, a first triode, a second triode, a fourth resistor, and a fifth resistor; the drain of the fifth PMOS transistor is connected to the inverting input terminal of the operational amplifier; the gates of the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor are respectively connected to the output terminal of the operational amplifier; the sources of the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor are respectively connected to the power output terminal; the emitter of the first triode is connected to the inverting input terminal of the operational amplifier; the bases and collectors of the first triode, the bases and collectors of the second triode are respectively grounded; the emitter of the second triode is connected to the first end of the fourth resistor; the second end of the fourth resistor is connected to the non-inverting input terminal of the operational amplifier; the non-inverting input terminal of the operational amplifier is further connected to the drain of the sixth PMOS transistor; the drain of the seventh PMOS transistor is grounded through the fifth resistor; wherein, the gate of the seventh PMOS transistor is the first output terminal of the bandgap reference main circuit; the drain of the seventh PMOS transistor is the second output terminal of the bandgap reference main circuit.

[0012] Optionally, the bandgap reference main circuit further includes: a sixth resistor and a seventh resistor; the first end of the sixth resistor is connected to the inverting input terminal of the operational amplifier; the first end of the seventh resistor is connected to the non-inverting input terminal of the operational amplifier; the second ends of the sixth resistor and the seventh resistor are respectively grounded.

[0013] Optionally, the mirror current source includes: a voltage follower, an eighth PMOS transistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first capacitor, and a second capacitor; the positive input terminal of the voltage follower is connected to the power supply output terminal, the negative input terminal of the voltage follower is connected to the first terminal of the eighth resistor, and the second terminal of the eighth resistor is grounded; the gate of the eighth PMOS transistor is connected to the output terminal of the voltage follower, the source of the eighth PMOS transistor is connected to the first terminal of the ninth resistor, the drain of the eighth PMOS transistor is connected to the first terminal of the tenth resistor, the second terminal of the tenth resistor is connected to the voltage supply terminal, and the second terminal of the ninth resistor is connected to the first terminal of the eighth resistor; the first terminal of the eleventh resistor is connected to the power supply output terminal, the second terminal of the eleventh resistor is respectively connected to the first terminal of the twelfth resistor, the first terminal of the first capacitor, and the positive input terminal of the voltage follower, the second terminals of the twelfth resistor and the first capacitor are respectively grounded, the first terminal of the second capacitor is respectively connected to the voltage supply terminal and the power supply terminal of the voltage follower, and the second terminal of the second capacitor is grounded.

[0014] Optionally, the bandgap reference start-up transient enhancement circuit further includes: a start-up module, the input terminal of the start-up module is connected to the feedback terminal of the negative feedback loop module, and the output terminal of the start-up module is connected to the first output terminal of the bandgap reference main circuit; the start-up module includes: a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the gate of the seventh NMOS transistor is connected to the gate of the second NMOS transistor, the drain of the seventh NMOS transistor is connected to the gate of the eighth NMOS transistor, the sources of the seventh NMOS transistor and the eighth NMOS transistor are respectively grounded, and the drain of the eighth NMOS transistor is the output terminal of the start-up module; the source of the ninth PMOS transistor is connected to the drain of the first NMOS transistor, the gate and the drain of the ninth PMOS transistor are respectively connected to the source of the tenth PMOS transistor, and the gate and the drain of the tenth PMOS transistor are respectively connected to the gate of the eighth NMOS transistor.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] In the present invention, the mirror current of the bandgap reference main circuit is led out through a voltage replication module to obtain another required driving voltage for the bandgap reference. In the actual process, it can be known that due to the influence of the load capacitance, the driving voltage of the bandgap reference will reach the stable value earlier than the output voltage of the bandgap reference main circuit during the transient turn-on process; after the driving voltage of the bandgap reference is further stabilized through the negative feedback loop module, this driving voltage of the bandgap reference is used as the power supply voltage of the logic flip-flop module, and at the same time, the output logic signal of the logic flip-flop module is controlled through the voltage at the second output terminal of the bandgap reference main circuit, so as to control the conduction and cut-off of the switching current source module, and further control the charging state of the second output terminal of the bandgap reference main circuit, realizing the transient enhancement of the turn-on of the output voltage of the bandgap reference voltage source, and can greatly reduce the time for the output voltage to reach the stable value. Brief Description of the Drawings

[0017] The drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 Shown is a schematic structural diagram of a bandgap reference voltage source provided by an embodiment of the present invention;

[0020] Figure 2 Shown is a schematic circuit diagram of a bandgap reference voltage source provided by an embodiment of the present invention;

[0021] Figure 3 Shown is a comparison diagram of the transient response curves of the output voltages of a bandgap reference voltage source with a bandgap reference start-up transient enhancement circuit and a traditional bandgap reference voltage source at turn-on provided by an embodiment of the present invention;

[0022] Figure 4 Shown is a schematic circuit diagram of a mirror current source provided by an embodiment of the present invention;

[0023] Figure 5 Shown is another schematic structural diagram of a bandgap reference voltage source provided by an embodiment of the present invention;

[0024] Figure 6 Shown is another schematic circuit diagram of a bandgap reference voltage source provided by an embodiment of the present invention. Detailed Description of the Embodiments

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts belong to the scope of protection of this application. In the examples of this invention, functional units with the same reference numerals have the same and similar structures and functions.

[0026] Embodiment 1

[0027] Figure 1 The following shows a schematic structural diagram of a bandgap reference voltage source provided by an embodiment of the present invention. As Figure 1 shown, the bandgap reference voltage source 100 specifically includes:

[0028] A bandgap reference main circuit 110 and a bandgap reference start-up transient enhancement circuit 120. The bandgap reference start-up transient enhancement circuit 120 includes a voltage replication module 121, a negative feedback loop module 122, a logic inversion module 123, and a switched current source module 124;

[0029] The bandgap reference main circuit 110 is used to provide a reference voltage for the subsequent load 200;

[0030] The input end of the voltage replication module 121 is connected to the first output end of the bandgap reference main circuit 122, and is used to obtain a bandgap reference drive voltage according to the mirror current output from the first output end of the bandgap reference main circuit 122;

[0031] The input end of the negative feedback loop module 122 is connected to the output end of the voltage replication module 121, and is used to regulate the voltage of the bandgap reference drive voltage;

[0032] The first input end of the logic inversion module 123 is connected to the output end of the negative feedback loop module 122, and the second input end of the logic inversion module 123 is connected to the second output end of the bandgap reference main circuit 122. The logic inversion module 123 is used to output a corresponding logic control signal according to the current voltage value output from the second output end of the bandgap reference main circuit 122;

[0033] The input end of the switched current source module 124 is connected to the output end of the logic inversion module 123, and the output end of the switched current source module 124 is connected to the second output end of the bandgap reference main circuit 122. The switched current source module 124 is used to conduct or cut off according to the logic control signal, so as to control the charging state of the second output end of the bandgap reference main circuit 122.

[0034] Among them, the second output terminal of the bandgap reference main circuit 122 is also connected to the subsequent-stage load 200, and the subsequent-stage load 200 includes a load capacitor Cload. The second output terminal of the bandgap reference main circuit 122 is also grounded through the load capacitor Cload.

[0035] It should be noted that in this embodiment, the voltage replication module 121 is used to replicate the current of the bandgap reference circuit 122, so as to generate a bandgap reference driving voltage value, and the bandgap reference driving voltage value needs to be greater than the voltage value output by the second output terminal of the bandgap reference circuit 122; the negative feedback loop module 122 stabilizes the bandgap reference driving voltage output by the voltage replication module 121 and conducts voltage transfer; the power supply voltage and the input terminal of the logic flip-flop module 123 are respectively provided by the output voltage of the negative feedback loop module 122 and the output voltage of the bandgap reference circuit 122. This circuit uses the characteristic of its own flip threshold voltage to cause a change in the output logic signal through the change of the input; the switch current source module 124 is turned on or off through the logic control signal output by the logic flip-flop module 123, so as to charge the second output terminal of the bandgap reference circuit 122 in the on state and stop charging the second output terminal of the bandgap reference circuit 122 in the off state.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] The present invention extracts the mirror current of the bandgap reference main circuit through the voltage replication module to obtain another required bandgap reference driving voltage. In the actual process, it can be known that due to the influence of the load capacitor, the bandgap reference driving voltage will reach the stable value earlier than the output voltage of the bandgap reference main circuit during the transient turn-on process; after the bandgap reference driving voltage is further stabilized by the negative feedback loop module, the bandgap reference driving voltage is used as the power supply voltage of the logic flip-flop module, and at the same time, the output logic signal of the logic flip-flop module is controlled through the voltage of the second output terminal of the bandgap reference main circuit, so as to control the on and off of the switch current source module, and further control the charging state of the second output terminal of the bandgap reference main circuit, realizing the transient enhancement of the turn-on of the output voltage of the bandgap reference voltage source, and can greatly reduce the time for the output voltage to reach the stable value.

[0038] Embodiment 2

[0039] Figure 2 The following shows a circuit schematic diagram of a bandgap reference voltage source provided by an embodiment of the present invention; as Figure 2 shown, the negative feedback loop module 132 includes:

[0040] The first NMOS transistor MN1, the second NMOS transistor MN2, the first resistor R1, and the second resistor R2; the gate of the first NMOS transistor MN1 is connected to the output terminal of the voltage replication module 131, the drain of the first NMOS transistor MN1 is connected to the power output terminal, the source of the first NMOS transistor MN1 is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is grounded; the gate of the second NMOS transistor MN2 is connected to the second terminal of the first resistor R1, the source of the second NMOS transistor MN2 is grounded, and the drain of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1; wherein, the source of the first NMOS transistor MN1 is the output terminal of the negative feedback loop module 132.

[0041] In this embodiment, the logic flip module 133 includes: a first PMOS transistor MP1 and a third NMOS transistor MN3; the gate of the first PMOS transistor MP1 is connected to the second output terminal of the bandgap reference main circuit 120, the source of the first PMOS transistor MP1 is connected to the output terminal of the negative feedback loop module 132, and the drain of the first PMOS transistor MP1 is the output terminal of the logic flip module 133; the gate of the third NMOS transistor MN3 is connected to the gate of the first PMOS transistor MP1, the drain of the third NMOS transistor MN3 is connected to the drain of the first PMOS transistor MP1, and the source of the third NMOS transistor MN3 is grounded.

[0042] In this embodiment, the voltage replication module 131 includes: a second PMOS transistor MP2 and a third resistor R3; the gate of the second PMOS transistor MP2 is connected to the first output terminal of the bandgap reference main circuit 120, the source of the second PMOS transistor MP2 is connected to the power output terminal, the drain of the second PMOS transistor MP2 is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is grounded.

[0043] In this embodiment, the switched current source module 134 includes: a fourth NMOS transistor MN4 and a mirror current source 1341; the gate of the fourth NMOS transistor MN4 is connected to the output terminal of the logic flip circuit, the drain of the fourth NMOS transistor MN4 is connected to the output terminal of the mirror current source 1341, and the source of the fourth NMOS transistor MN4 is the output terminal of the switched current source module 134.

[0044] Further, the mirror current source 1341 includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a current source IA; the gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4, the sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are respectively connected to the power output terminal, the drain of the third PMOS transistor MP3 is connected to the drain of the fourth NMOS transistor MN4, and the drain of the fourth PMOS transistor MP4 is connected to the gate of the fourth PMOS transistor MP4; the gate of the fifth NMOS transistor MN5 is connected to the gate of the sixth NMOS transistor MN6, the drain of the fifth NMOS transistor MN5 is connected to the drain of the fourth PMOS transistor MP4, the sources of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are respectively grounded, the drain of the sixth NMOS transistor MN6 is connected to the gate of the sixth NMOS transistor MN6, the drain of the sixth NMOS transistor MN6 is further connected to the output terminal of the current source, and the input terminal of the current source IA is connected to the power output terminal.

[0045] It should be noted that in this embodiment, the voltage replication module 131 composed of the second PMOS transistor MP2 and the third resistor R3 replicates the mirror current output by the bandgap reference main circuit 120, and through the voltage division of the third resistor R3, the bandgap reference driving voltage is obtained.

[0046] Optionally, a negative feedback loop module 132 for transmitting and stabilizing the driving voltage is constituted by the first NMOS transistor MN1, the second NMOS transistor MN2, the first resistor R1, and the second resistor R2, which is used to ensure that the replicated bandgap reference driving voltage at the front end can be kept relatively stable, reduce its influence by the load, and at the same time output a relatively stable voltage to the rear logic flip - flop module 133 to provide its power supply voltage.

[0047] In this embodiment, the logic flip - flop module 133 composed of the first PMOS transistor MP1 and the third NMOS transistor MN3 judges the logic signal of the output voltage of the bandgap reference main circuit 120 and outputs the corresponding logic level, and controls the conduction and cut - off of the rear - end switched current source module 134 through this level.

[0048] Optionally, a switch current source module 134 formed by a fourth NMOS transistor MN4, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a current source is controlled by the output of a front-end logic flip module 133, thereby controlling the opening or closing of the current path. Through the mirror current bias of the current source, the second output terminal of the bandgap reference main circuit 120 is charged, thereby reducing the time for the output voltage of the bandgap reference main circuit 120 to reach a stable value and achieving the purpose of transient startup.

[0049] In this embodiment, the bandgap reference main circuit includes:

[0050] A fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh MOS transistor, an operational amplifier A0, a first triode Q1, a second triode Q2, a fourth resistor R4, and a fifth resistor R5; the drain of the fifth PMOS transistor MP5 is connected to the inverting input terminal of the operational amplifier A0, the gates of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are respectively connected to the output terminal of the operational amplifier A0, and the sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are respectively connected to the power output terminal; the emitter of the first triode Q1 is connected to the inverting input terminal of the operational amplifier A0, the base, the collector of the first triode Q1, the base, and the collector of the second triode Q2 are respectively grounded, the emitter of the second triode Q2 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the non-inverting input terminal of the operational amplifier A0, the non-inverting input terminal of the operational amplifier A0 is further connected to the drain of the sixth PMOS transistor MP6, and the drain of the seventh PMOS transistor MP7 is grounded through the fifth resistor R5; wherein, the gate of the seventh PMOS transistor MP7 is the first output terminal of the bandgap reference main circuit, and the drain of the seventh PMOS transistor MP7 is the second output terminal of the bandgap reference main circuit.

[0051] In this embodiment, the bandgap reference main circuit further includes: a sixth resistor R6 and a seventh resistor R7; the first end of the sixth resistor R6 is connected to the inverting input terminal of the operational amplifier A0, the first end of the seventh resistor R7 is connected to the non-inverting input terminal of the operational amplifier A0, and the second ends of the sixth resistor R6 and the seventh resistor R7 are respectively grounded.

[0052] It should be noted that in this embodiment, the bandgap reference main circuit is composed of P-type transistors MP5, MP6, MP7, triodes Q1, Q2, resistors R4, R5, R6, R7, an operational amplifier, and an enabling circuit. Among them, R6 is equal to R7, the currents flowing through P-type transistors MP5 and MP6 are equal, the current ratio of P-type transistor MP7 to MP5 (or MP6) is K1, the current ratio of P-type transistor MP2 to MP5 (or MP6) is K2, the number ratio of triodes Q2 and Q1 is N:1, and the voltage difference between triodes Q1 and Q2 across resistor R4 is:

[0053]

[0054] This voltage value is proportional to temperature (i.e., PTAT voltage), where q is the electric charge quantity, q = 1.6 * 10^-19 C; K is the Boltzmann constant, K = 1.38 * 10^-23 J / K; T is the absolute temperature.

[0055] Therefore, the PTAT current flowing through resistor R4 is:

[0056]

[0057] where R4 is the resistance value of the fourth resistor R4;

[0058] The current flowing through resistor R7 is:

[0059]

[0060] This current is inversely proportional to temperature (i.e., CTAT current), where R7 is the resistance value of the seventh resistor R7;

[0061] Therefore, the current flowing through MP5 (or MP6) is:

[0062] I MP5 / MP6 = I PTAT + I CTAT

[0063] The current flowing through transistor MP7 is:

[0064] I MP7 = (I PTAT + I CTAT ) × K1

[0065] The current flowing through transistor MP2 is:

[0066] I MP2 = (I PTAT + I CTAT ) × K2

[0067] The reference voltage Vref output by the bandgap reference main circuit is:

[0068]

[0069] The driving voltage generated after passing through the bandgap reference output voltage replication circuit is:

[0070]

[0071] To ensure the normal operation of the source follower transistor MN1, the highest power supply voltage of the output logic flip module is:

[0072]

[0073] Where V TH1 is the threshold voltage of the transistor MN1.

[0074] It should be further noted that by selecting the sizes of the relevant transistors inside the logic flip module, the magnitude of the flip threshold voltage can be controlled, so that it can be applied to different output voltage values of the bandgap reference main circuit.

[0075] In the actual application process of the bandgap reference, there is a situation where the load capacitance at the output end is relatively large, that is, a relatively large load capacitance is formed between the output end of the bandgap reference main circuit and the subsequent load. This capacitance affects the voltage stabilization time at the output end when the bandgap reference main circuit starts up, making the output voltage start up more slowly. In view of this characteristic, the present invention generates another replicated voltage through a current mirror. Since there is no excessive capacitance affecting the transient of this voltage, it has a faster power-on speed compared to the output voltage of the bandgap reference main circuit. In view of this, by reusing this replicated voltage, after stabilization through a negative feedback loop, this voltage is used as the power supply voltage of the logic flip module. At the same time, the output end of the bandgap reference main circuit is connected to the input end of the logic flip module. Since the power supply voltage of the logic flip module stabilizes prior to the input signal, the P-type transistor inside the logic flip module conducts in the initial stage, outputting a high level to turn on the subsequent switching transistor, and giving a charging current to the output end of the bandgap reference main circuit to enhance the rapid stabilization of the output voltage.

[0076] When the input signal is greater than the flip threshold voltage of the logic flip module, by virtue of the inherent logic level characteristic of the logic flip module, the output will immediately become low level to turn off the switching transistor and end the charging of the output end of the bandgap reference main circuit. At this point, the overall circuit of the bandgap reference voltage source is turned off, and the startup transient enhancement of the bandgap reference output voltage is completed.

[0077] Figure 3 The figure shows a comparison diagram of the transient response curves of the output voltage at startup between a bandgap reference voltage source with a bandgap reference startup transient enhancement circuit provided by an embodiment of the present invention and a traditional bandgap reference voltage source; as Figure 3As shown in the figure, it can be clearly seen that with the assistance of the start-up transient enhancement circuit of the bandgap reference, the output transient stabilization time of the bandgap reference in this embodiment is shortened by nearly 63 μs, greatly reducing the problem of slow transient response at the output end of the bandgap reference caused by a large load capacitance.

[0078] Embodiment 3

[0079] Figure 4 The following is a schematic circuit diagram of a mirror current source provided by an embodiment of the present invention. The mirror current source includes:

[0080] A voltage follower U1, an eighth PMOS transistor MP8, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10; the non-inverting input terminal of the voltage follower U1 is connected to the power supply output terminal, the inverting input terminal of the voltage follower U1 is connected to the first terminal of the eighth resistor R8, and the second terminal of the eighth resistor R8 is grounded; the gate of the eighth PMOS transistor MP8 is connected to the output terminal of the voltage follower, the source of the eighth PMOS transistor MP8 is connected to the first terminal of the ninth resistor R9, the drain of the eighth PMOS transistor MP8 is connected to the first terminal of the tenth resistor R10, the second terminal of the tenth resistor R10 is connected to the voltage supply terminal VDD, and the second terminal of the ninth resistor R9 is connected to the first terminal of the eighth resistor R8.

[0081] In this embodiment, the mirror current source further includes: an eleventh resistor R11, a twelfth resistor R12, and a first capacitor C1; the first terminal of the eleventh resistor R11 is connected to the power supply output terminal, the second terminal of the eleventh resistor R11 is respectively connected to the first terminal of the twelfth resistor R12, the first terminal of the first capacitor C1, and the non-inverting input terminal of the voltage follower U1, and the second terminals of the twelfth resistor R12 and the first capacitor C1 are respectively grounded.

[0082] In this embodiment, the mirror current source further includes: a second capacitor C2, the first terminal of the second capacitor C2 is respectively connected to the voltage supply terminal VDD and the power supply terminal of the voltage follower U1, and the second terminal of the second capacitor C2 is grounded.

[0083] Embodiment 4

[0084] Figure 5 The following is a schematic structural diagram of another bandgap reference voltage source provided by an embodiment of the present invention. As Figure 5 shown, the start-up transient enhancement circuit of the bandgap reference further includes: a start-up module 125, the input terminal of the start-up module 125 is connected to the feedback terminal of the negative feedback loop module 122, and the output terminal of the start-up module 125 is connected to the first output terminal of the bandgap reference main circuit 110.

[0085] As shown Figure 6 in the figure, the startup module 125 includes: a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8; the gate of the seventh NMOS transistor MN7 is connected to the gate of the second NMOS transistor MN2, the drain of the seventh NMOS transistor MN7 is connected to the gate of the eighth NMOS transistor MN8, the sources of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are grounded respectively, and the drain of the eighth NMOS transistor MN8 is the output terminal of the startup module 125; the source of the ninth PMOS transistor MP9 is connected to the drain of the first NMOS transistor MN1, the gate and the drain of the ninth PMOS transistor MP9 are connected to the source of the tenth PMOS transistor MP10 respectively, and the gate and the drain of the tenth PMOS transistor MP10 are connected to the gate of the eighth NMOS transistor MN8 respectively.

[0086] It should be noted that before the power is applied and when the bandgap reference main circuit is working properly, there is no current flowing through the startup module at this time, and the gate terminals of the MP9 and MP10 transistors are both at low level. When the power is instantaneously applied, the MP9 and MP10 transistors will conduct and play a pulling-up role (since the current in the resistor R2 in the negative feedback loop module is 0 and the MN7 is in the cut-off state), making the gate terminal of the MN8 at high level. The MN8 conducts at this time and then pulls down the first output terminal of the bandgap reference voltage source main circuit to low level. At this time, the bandgap reference voltage source main circuit starts.

[0087] After the bandgap reference voltage source main circuit starts, due to the existence of current, a current flows through the resistor R2 in the negative feedback loop module, and then the MN7 conducts, pulling down the gate terminal of the MN8. Due to the diode connection method of the MP9 and MP10, there is a voltage drop from the power supply to the drain of the MN7. Thus, the gate voltage of the MN8 can be controlled and it enters the cut-off state. At this point, the startup module stops working, the bandgap reference voltage source main circuit outputs normally, and at the same time, the rear part (voltage replication module, negative feedback loop module, logic flip module, and switched current source module) outputs a transient enhancement circuit to work normally, accelerating the stabilization of the transient output voltage of the bandgap reference main circuit.

[0088] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0089] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A bandgap reference voltage source, characterized in that, The voltage source includes: a bandgap reference main circuit and a bandgap reference start-up transient enhancement circuit, where the bandgap reference start-up transient enhancement circuit includes a voltage replication module, a negative feedback loop module, a logic inversion module, and a switched current source module; The bandgap reference main circuit is used to provide a reference voltage for a subsequent load; The input end of the voltage replication module is connected to the first output end of the bandgap reference main circuit, and is used to obtain a bandgap reference driving voltage according to the mirror current output from the first output end of the bandgap reference main circuit; The input end of the negative feedback loop module is connected to the output end of the voltage replication module, and is used to regulate the voltage of the bandgap reference driving voltage; The first input end of the logic inversion module is connected to the output end of the negative feedback loop module, and the second input end of the logic inversion module is connected to the second output end of the bandgap reference main circuit, and is used to output a corresponding logic control signal according to the current voltage value output from the second output end of the bandgap reference main circuit; The input end of the switched current source module is connected to the output end of the logic inversion module, and the output end of the switched current source module is connected to the second output end of the bandgap reference main circuit, and is used to conduct or cut off according to the logic control signal, so as to control the charging state of the second output end of the bandgap reference main circuit.

2. The bandgap reference voltage source according to claim 1, wherein The negative feedback loop module includes: a first NMOS transistor, a second NMOS transistor, a first resistor, and a second resistor; The gate of the first NMOS transistor is connected to the output end of the voltage replication module, the drain of the first NMOS transistor is connected to the power supply output end, the source of the first NMOS transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; The gate of the second NMOS transistor is connected to the second end of the first resistor, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor; Wherein, the source of the first NMOS transistor is the output end of the negative feedback loop module.

3. The bandgap reference voltage source according to claim 1, characterized in that, The logic inversion module includes: a first PMOS transistor and a third NMOS transistor; The gate of the first PMOS transistor is connected to the second output end of the bandgap reference main circuit, the source of the first PMOS transistor is connected to the output end of the negative feedback loop module, and the drain of the first PMOS transistor is the output end of the logic inversion module; The gate of the third NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor, and the source of the third NMOS transistor is grounded.

4. The bandgap reference voltage source according to claim 1, characterized in that, The voltage replication module includes: a second PMOS transistor and a third resistor; The gate of the second PMOS transistor is connected to the first output end of the bandgap reference main circuit, the source of the second PMOS transistor is connected to the power supply output end, the drain of the second PMOS transistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded.

5. The bandgap reference voltage source according to any one of claims 1-4, characterized in that The switched current source module includes: The fourth NMOS transistor and the mirror current source; the gate of the fourth NMOS transistor is connected to the output terminal of the logic inversion module, the drain of the fourth NMOS transistor is connected to the output terminal of the mirror current source, and the source of the fourth NMOS transistor is the output terminal of the switching current source module.

6. The bandgap reference voltage source according to claim 5, characterized in that, The mirror current source includes: a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a current source; The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, the sources of the third PMOS transistor and the fourth PMOS transistor are respectively connected to the power output terminal, the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the fourth PMOS transistor is connected to the gate of the fourth PMOS transistor; The gate of the fifth NMOS transistor is connected to the gate of the sixth NMOS transistor, the drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor, the sources of the fifth NMOS transistor and the sixth NMOS transistor are respectively grounded, the drain of the sixth NMOS transistor is connected to the gate of the sixth NMOS transistor, the drain of the sixth NMOS transistor is further connected to the output terminal of the current source, and the input terminal of the current source is connected to the power output terminal.

7. The bandgap reference voltage source according to claim 1, wherein The bandgap reference main circuit includes: A fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an operational amplifier, a first triode, a second triode, a fourth resistor, and a fifth resistor; The drain of the fifth PMOS transistor is connected to the inverting input terminal of the operational amplifier, the gates of the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor are respectively connected to the output terminal of the operational amplifier, and the sources of the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor are respectively connected to the power output terminal; The emitter of the first triode is connected to the inverting input terminal of the operational amplifier, the bases of the first triode, the collector of the first triode, the base of the second triode, and the collector of the second triode are respectively grounded, the emitter of the second triode is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the non-inverting input terminal of the operational amplifier, the non-inverting input terminal of the operational amplifier is further connected to the drain of the sixth PMOS transistor, and the drain of the seventh PMOS transistor is grounded through the fifth resistor; Wherein, the gate of the seventh PMOS transistor is the first output terminal of the bandgap reference main circuit, and the drain of the seventh PMOS transistor is the second output terminal of the bandgap reference main circuit.

8. The bandgap reference voltage source according to claim 7, wherein The bandgap reference main circuit further includes: A sixth resistor and a seventh resistor; The first end of the sixth resistor is connected to the inverting input terminal of the operational amplifier, the first end of the seventh resistor is connected to the non-inverting input terminal of the operational amplifier, and the second ends of the sixth resistor and the seventh resistor are respectively grounded.

9. The bandgap reference voltage source according to claim 5, wherein The mirror current source includes: A voltage follower, an eighth PMOS transistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first capacitor and a second capacitor; The non-inverting input terminal of the voltage follower is connected to the power supply output terminal, the inverting input terminal of the voltage follower is connected to the first end of the eighth resistor, and the second end of the eighth resistor is grounded; The gate of the eighth PMOS transistor is connected to the output terminal of the voltage follower, the source of the eighth PMOS transistor is connected to the first end of the ninth resistor, the drain of the eighth PMOS transistor is connected to the first end of the tenth resistor, the second end of the tenth resistor is connected to the voltage supply terminal, and the second end of the ninth resistor is connected to the first end of the eighth resistor; The first end of the eleventh resistor is connected to the power supply output terminal, the second end of the eleventh resistor is respectively connected to the first end of the twelfth resistor, the first end of the first capacitor and the non-inverting input terminal of the voltage follower, the second ends of the twelfth resistor and the first capacitor are respectively grounded, the first end of the second capacitor is respectively connected to the voltage supply terminal and the power supply terminal of the voltage follower, and the second end of the second capacitor is grounded.

10. The bandgap reference voltage source according to claim 2, characterized in that, The bandgap reference start-up transient enhancement circuit further includes: a start-up module, the input terminal of the start-up module is connected to the feedback terminal of the negative feedback loop module, and the output terminal of the start-up module is connected to the first output terminal of the bandgap reference main circuit; The start-up module includes: a ninth PMOS transistor, a tenth PMOS transistor, a seventh NMOS transistor and an eighth NMOS transistor; The gate of the seventh NMOS transistor is connected to the gate of the second NMOS transistor, the drain of the seventh NMOS transistor is connected to the gate of the eighth NMOS transistor, the sources of the seventh NMOS transistor and the eighth NMOS transistor are respectively grounded, and the drain of the eighth NMOS transistor is the output terminal of the start-up module; The source of the ninth PMOS transistor is connected to the drain of the first NMOS transistor, the gate and the drain of the ninth PMOS transistor are respectively connected to the source of the tenth PMOS transistor, and the gate and the drain of the tenth PMOS transistor are respectively connected to the gate of the eighth NMOS transistor.

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