Computing chips and computing boards

Abstract

The present disclosure relates to a computing chip and a computing power board. The computing chip includes a plurality of operation stages arranged in a pipeline structure, each operation stage includes: a first combinational logic circuit, the first combinational logic circuit occupies a plurality of first cell points adjacent to each other, at least a portion of the first cell points are located in a first incomplete column; one or more second combinational logic circuits, each second combinational logic circuit occupies one or more second cell points, at least a portion of the second cell points are located in a second incomplete column; and a plurality of registers, each register occupies a plurality of third cell points, at least a portion of the third cell points are located in a first incomplete column or a second incomplete column; wherein the first cell point, the second cell point and the third cell point occupy the same area on the computing chip.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and more particularly, to a computing chip and a computing power board. Background Art

[0002] Generally, a computing chip can be designed based on a pipeline structure according to the characteristics of an algorithm. Specifically, the arithmetic logic can be divided into several arithmetic levels arranged in a pipeline structure, and each arithmetic level can have a similar functional design and arithmetic structure.

[0003] Currently, various circuits or devices in an arithmetic level are usually designed to occupy a rectangular area in a computing chip. The rectangular area is composed of a number of cell points in rows and columns. Here, a cell point refers to the smallest unit in chip design. However, due to the characteristics of the circuits or devices themselves, the space in some rectangular areas may not be fully utilized, that is, some cell points may not be used for any circuits or devices. Therefore, the layout of existing computing chips is not compact enough, which will cause the computing chip or other devices containing the computing chip to occupy a large space. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a computing chip and a computing power board.

[0005] According to a first aspect of the present disclosure, there is provided a computing chip, the computing chip including a plurality of arithmetic levels arranged in a pipeline structure, and each arithmetic level includes:

[0006] A first combinational logic circuit, the first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a part of the first cell points being located in a first non-complete column, in the first non-complete column, the number of first cell points being less than a first preset number N1, where the first preset number N1 is the maximum number of cell points that can be accommodated in each column of the computing chip;

[0007] One or more second combinational logic circuits, each second combinational logic circuit occupying one or more second cell points, at least a part of the second cell points being located in a second non-complete column, in the second non-complete column, the number of second cell points being less than or equal to a second preset number N2, where N2 = N1 / 2; and a plurality of registers, each register occupying a plurality of third cell points, at least a part of the third cell points being located in the first non-complete column or the second non-complete column;

[0008] Wherein, the first cell points, the second cell points and the third cell points occupy the same area on the computing chip.

[0009] In some embodiments, at least another part of the first cell points is located in the first complete column, and in the first complete column, the number of the first cell points is equal to the first preset number N1.

[0010] In some embodiments, in the first incomplete column, the number of the first cell points is greater than or equal to the second preset number N2.

[0011] In some embodiments, in the same first combinational logic circuit, the number of the first incomplete columns is equal to one.

[0012] In some embodiments, in the data flow direction in the computing chip, the input end of the first combinational logic circuit is directly connected to the register, and the output end of the first combinational logic circuit is directly connected to the register.

[0013] In some embodiments, in the data flow direction in the computing chip, the input end of the first combinational logic circuit is directly connected to the second combinational logic circuit, or the output end of the first combinational logic circuit is directly connected to the second combinational logic circuit.

[0014] In some embodiments, the first combinational logic circuit includes an adder.

[0015] In some embodiments, when the number of the second cell points occupied by the same second combinational logic circuit is greater than the second preset number N2, the second cell points exceeding the second preset number N2 are located on the middle one or two rows of the computing chip.

[0016] In some embodiments, at least one second combinational logic circuit occupies the third preset number N3 of second cell points located in the same second complete column, where N3 = N1 - 2.

[0017] In some embodiments, in the data flow direction in the computing chip, the input end of the first second combinational logic circuit is directly connected to the register, and the output end of the last second combinational logic circuit is directly connected to the register.

[0018] In some embodiments, in the data flow direction in the computing chip, the input end of at least one second combinational logic circuit is directly connected to the first combinational logic circuit, or the output end of at least one second combinational logic circuit is directly connected to the first combinational logic circuit.

[0019] In some embodiments, each register includes a low-bit sub-register and a high-bit sub-register having an equal fourth number of bits N0, where N0 = (N1 - 2) / 2.

[0020] In some embodiments, the low-bit sub-register includes N0 first storage units and a first clock unit;

[0021] The high-bit sub-register includes N0 second storage units and a second clock unit;

[0022] Wherein, the first clock unit and the second clock unit are commonly connected to the same clock signal source.

[0023] In some embodiments, the first clock unit and the second clock unit are located on the middle two rows of the computing chip.

[0024] In some embodiments, the first number of bits of the first combinational logic circuit is 2N0 or 2N0 - 1;

[0025] The second number of bits of the second combinational logic circuit is less than or equal to 2NO; and

[0026] The third number of bits of the register is 2N0.

[0027] According to a second aspect of the present disclosure, there is also provided a computing power board, which includes one or more computing chips as described above.

[0028] Other features and advantages of the present disclosure will become clearer through the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0030] With reference to the accompanying drawings, the present disclosure can be more clearly understood according to the following detailed description, wherein:

[0031] Figure 1 is a schematic structural diagram of a computing chip;

[0032] Figure 2 is a schematic structural diagram of another computing chip;

[0033] Figure 3 is a schematic structural diagram of a computing chip according to an exemplary embodiment of the present disclosure;

[0034] Figure 4 is a schematic structural diagram of yet another computing chip;

[0035] Figure 5 is a schematic structural diagram of a computing chip according to another exemplary embodiment of the present disclosure.

[0036] Note that in the embodiments described below, in some cases, the same reference numerals are used commonly between different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In some cases, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it is not necessary to discuss it further in subsequent drawings.

[0037] For ease of understanding, the positions, sizes, ranges, etc. of the structures shown in the drawings and the like sometimes do not represent the actual positions, sizes, ranges, etc. Therefore, the present disclosure is not limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. Detailed implementation manners

[0038] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. It should be noted that: Unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0039] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way limits the present disclosure, its application, or its use. That is to say, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. Those skilled in the art should understand that these examples are merely illustrative of the embodiments of the present disclosure and not in an exhaustive manner. In addition, the drawings do not have to be drawn to scale, and some features may be enlarged to show the details of some specific components.

[0040] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be regarded as part of the specification.

[0041] In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not restrictive. Therefore, other examples of the exemplary embodiments may have different values.

[0042] According to a first aspect of the present disclosure, a computing chip is proposed. By changing the layout of the circuits or devices therein, the computing chip is made more compact to reduce the space it occupies.

[0043] As Figures 1 to 5 shown, the computing chip may include a plurality of operation levels arranged in a pipeline structure (shown as the (M - 1)th level, the Mth level, and the (M + 1)th level in the figure, and the schematic structure of the Mth level is specifically shown). In Figures 1 to 5In the computing chip, data generally flows in the direction from left to right. That is to say, the data output from the (M - 1)-th stage flows to the M-th stage. After being processed by the M-th stage, the data continues to flow to the (M + 1)-th stage for further processing. In the computing chip, different computing stages can have similar functional designs and computing structures to implement corresponding algorithms.

[0044] As Figures 1 to 5 shown, for each computing stage in the computing chip, it can include a sequential logic circuit and a combinational logic circuit. In the sequential logic circuit, the output at any moment depends not only on the input signal at that time but also on the original state of the sequential logic circuit; while in the combinational logic circuit, the output at any moment depends only on the input at that moment and has nothing to do with the original state of the combinational logic circuit. The bit widths of the sequential logic circuit and the combinational logic circuit correspond to each other to facilitate the execution of algorithms. For example, the bit width of the combinational logic circuit can be less than or equal to the bit width of the sequential logic circuit.

[0045] As described above, in the computing chip, the smallest unit of chip design can be called a cell point. It can be understood that each sequential logic circuit or combinational logic circuit can occupy an integer number of cell points in the computing chip. In addition, in some computing chips, for the convenience of layout, a number of cell points arranged in a rectangular array are allocated to each sequential logic circuit or combinational logic circuit. That is, for each sequential logic circuit or combinational logic circuit, it can occupy a rectangular area in the computing chip.

[0046] Taking Figures 1 to 5 the computing chip shown as an example, the sequential logic circuit therein can include a register 300, the combinational logic circuit can include a first combinational logic circuit 100 and a second combinational logic circuit 200. The first combinational logic circuit 100 can include an adder, and the second combinational logic circuit 200 can include other conventional logic circuits except for performing addition operations. Among them, the first combinational logic circuit 100 can occupy a plurality of adjacent first cell points, the second combinational logic circuit 200 can occupy one or more second cell points, and the register 300 can occupy a plurality of third cell points. It should be noted that the first cell points, the second cell points, and the third cell points here are intended to distinguish the cell points belonging to different circuits or devices, but the areas occupied by the first cell points, the second cell points, and the third cell points on the computing chip are the same.

[0047] In the computing chip, the register 300 can be used to store the data output by the previous combinational logic circuit and, under the control of the clock signal, transfer the stored data to the subsequent combinational logic circuit at an appropriate moment for further processing.

[0048] In some embodiments, the register 300 can be a multi-bit register, which can include multiple storage units and at least one clock unit, and each storage unit or clock unit can respectively occupy multiple third cell points and be arranged in the same column in the computing chip.

[0049] Further, in order to facilitate more flexible setting of the space in the computing chip, the register 300 can be composed of several sub-registers with lower bit numbers. In Figures 1 to 5 the example shown, the register 300 can include a low-bit sub-register 310 and a high-bit sub-register 320 with equal fourth bit numbers N0, so as to achieve a balanced space layout. It can be understood that when the fourth bit numbers of both the low-bit sub-register 310 and the high-bit sub-register 320 are N0, the third bit number of the register 300 composed of them is 2N0. In a specific example, N0 can be 4, 8, 16, or 32, etc.

[0050] Among them, the low-bit sub-register 310 can include N0 first storage units and a first clock unit, and the high-bit sub-register 320 can include N0 second storage units and a second clock unit, and the first clock unit and the second clock unit can be commonly connected to the same clock signal source to synchronize all the clocks in the same register 300.

[0051] Further, in order to simplify the connection of the first clock unit and the second clock unit, the first clock unit and the second clock unit can be arranged on the middle two rows of the computing chip, while the first storage units and the second storage units are respectively arranged towards both sides of the computing chip.

[0052] In Figures 1 to 5 the example shown, the maximum number of cell points that can be accommodated in each column in the computing chip, that is, the first preset number N1, can be determined according to the number of rows occupied by the register 300. Here, N1 = 2N0 + 2. Specifically, in a register 300, multiple first storage units can be respectively located in the 1st row to the N0th row from top to bottom (from low bit to high bit) in the computing chip, the first clock unit can be located in the (N0 + 1)th row, the second clock unit can be located in the (N0 + 2)th row, and multiple second storage units are respectively located in the (N0 + 3)th row to the (2N0 + 2)th row.

[0053] For convenience of description, the number of second cell points occupied by each second combinational logic circuit 200 described in the present disclosure is less than or equal to a first preset number N1. However, it can be understood that other ways can also be adopted to define the second combinational logic circuit 200 such that the number of second cell points it occupies is greater than the first preset number N1. In this case, those skilled in the art can still adjust the layout of the second combinational logic circuit 200 or other circuits or devices in the computing chip according to the technical solutions described in the present disclosure to make full use of the originally vacant cell points and make the computing chip more compact.

[0054] As Figures 1 to 5 shown, one or more second combinational logic circuits 200 can be continuously arranged in the data flow direction in the computing chip. In some embodiments, the input end of the first second combinational logic circuit 200 can be directly connected to the register 300, and the output end of the last second combinational logic circuit 200 can be directly connected to another register 300 different from the aforementioned register.

[0055] Of course, in some other embodiments, the input end and / or output end of at least one second combinational logic circuit can also be directly connected to the first combinational logic circuit. In a specific example, the input end of a corresponding second combinational logic circuit can be directly connected to the first combinational logic circuit in the previous operation stage, or the output end of a corresponding second combinational logic circuit can be directly connected to the first combinational logic circuit in the next operation stage.

[0056] According to different algorithms, the operations performed by the second combinational logic circuit 200 can be diversified. Correspondingly, the number of second cell points required to be occupied by each second combinational logic circuit 200 may be different, and in some cases, the second cell points in the same second combinational logic circuit 200 may be discontinuously distributed. Therefore, the layout of the computing chip can be adjusted according to the second combinational logic circuit 200 to make full use of the space.

[0057] In some cases, similar to the aforementioned register 300, a second combinational logic circuit 200 can be composed of several second combinational logic sub - circuits with lower bit widths. In Figures 1 to 5In the illustrated example, the second combinational logic circuit 200 may include a low-bit second combinational logic sub-circuit 210 and a high-bit second combinational logic sub-circuit 220. Since the second combinational logic circuit 200 does not include a clock unit, its second number is generally less than or equal to 2N0, and in the area on the computing chip for arranging the second combinational logic circuit 200, the cell points in the middle two rows of the computing chip can be left vacant. In particular, in some cases, at least one second combinational logic circuit 200 occupies a third preset number N3 of second cell points in the same second complete column, where N3 = N1 - 2.

[0058] As Figures 1 to 5 shown, in the data flow direction in the computing chip, a first combinational logic circuit 100 is also provided. In some embodiments, the input end of the first combinational logic circuit 100 can be directly connected to the register 300, and the output end of the first combinational logic circuit 100 can be directly connected to another register 300 different from the aforementioned register to implement corresponding processing of the data. Related to the third number 2N0 of the register 300, the first number of the first combinational logic circuit 100 can be 2N0 or 2N0 - 1.

[0059] Of course, in some other embodiments, the input end and / or the output end of the first combinational logic circuit can also be directly connected to the second combinational logic circuit to implement corresponding operations.

[0060] When the first combinational logic circuit 100 is an adder, due to functional requirements, the multiple first cell points corresponding to the first combinational logic circuit 100 are usually adjacent to each other. When adjusting the layout of various circuits or devices in order to make full use of the space on the computing chip, the above-mentioned limiting conditions need to be considered.

[0061] As Figure 1 shown, in a relatively ideal case, the first combinational logic circuit 100, the second combinational logic circuit 200, and the register 300 respectively completely or substantially completely occupy all the cell points in the corresponding rectangular regions. Of course, in the second combinational logic circuit 200, there may be one or two vacant rows between the low-bit second combinational logic sub-circuit 210 and the high-bit second combinational logic sub-circuit 220, but this has little impact on the overall space utilization rate of the computing chip.

[0062] In some cases, if the number of second cell points required to be occupied by a second combinational logic circuit is very small, then this second combinational logic circuit can be arranged in the originally vacant middle one or two rows, so that this second combinational logic circuit no longer needs to occupy a separate column in the computing chip, thus helping to reduce the total number of columns of cell points and thereby reducing the area of the required computing chip.

[0063] As Figure 2 shown, in some cases, if the number of second cell points required to be occupied by a second combinational logic circuit 200 is less than or equal to a second preset number N2 (N2 = N1 / 2), and one or two originally empty rows of cell points in the computing chip are not enough to arrange this second combinational logic circuit 200, then it will occupy a new column of cell points, resulting in waste of space in the computing chip. In Figure 2 a specific example of, the middle second combinational logic circuit 200 only occupies half or less than half of the cell points in a column.

[0064] In this case, as Figure 3 shown, the second combinational logic sub-units and / or sub-registers on the right side of the originally empty cell points can be moved to the left one by one. When moving to the first combinational logic circuit 100, some of the first cell points in the first combinational logic circuit 100 can be arranged to share the same column with the second combinational logic sub-units or sub-registers, so as to make full use of the space in the computing chip. In other words, in the first combinational logic circuit 100, at least some of the first cell points are located in a first non-complete column, in which the number of first cell points is less than the first preset number N1; at the same time, in the second combinational logic circuit 200, at least some of the second cell points are located in a second non-complete column, in which the number of second cell points is less than or equal to the second preset number N2; and in the register 300, at least some of the third cell points are located in the first non-complete column or the second non-complete column, that is, at least two of the first combinational logic circuit 100, the second combinational logic circuit 200 and the register 300 can share the cell points on the same column in the computing chip.

[0065] In some embodiments, the number of first cell points occupied by the first combinational logic circuit 100 is relatively large, so at least some other first cell points are located in a first complete column, in which the number of first cell points is equal to the first preset number N1. At this time, the first combinational logic circuit 100 including both the first complete column and the first non-complete column will occupy an L-shaped area.

[0066] Since the re-layout of the second combinational logic circuit 200 and the register 300 is carried out in units of the second combinational logic sub-circuit or sub-register, and the number of bits of each second combinational logic sub-circuit or each sub-register is usually half of the number of bits of the second combinational logic circuit 200 and the register 300 respectively (in some cases, the number of bits of the second combinational logic sub-circuit is less than half of the number of bits of the second combinational logic circuit 200), the number of cell points that may be vacant in a column is usually greater than or equal to N2. Correspondingly, in the first non-complete column, the number of the first cell points can be greater than or equal to the second preset number N2.

[0067] Furthermore, in order to minimize the number of cell points in the computing chip as much as possible, in the same first combinational logic circuit 100, the number of the first non-complete columns can be equal to one, so as to avoid an excessive number of first non-complete columns from increasing the total number of columns of cell points in the computing chip.

[0068] In some other cases, as Figure 4 shown, the number of the second cell points occupied by the same second combinational logic circuit 200 may be greater than the second preset number N2, that is, it occupies more than half of the cell points in the same column.

[0069] In this case, as Figure 5 shown, the second cell points exceeding the second preset number N2 can be arranged on the middle one or two rows of the computing chip, so as to vacate at least half of the cell points in a column, thereby facilitating the sequential leftward movement of the second combinational logic sub-circuits and / or sub-registers originally on the right without having to split the second combinational logic sub-circuits and / or sub-registers anymore, which helps to ensure the integrity of the circuit or device. When moving to the first combinational logic circuit 100, some of the first cell points in the first combinational logic circuit 100 can be arranged to share the same column with the second combinational logic sub-units or sub-registers, so as to make full use of the space in the computing chip.

[0070] In the solution of the present disclosure, by utilizing the non-integrity of the number of bits of the second combinational logic circuit 200 and changing the layout of the cell points occupied by the first combinational logic circuit 100, the second combinational logic circuit 200 and / or the register 300, specifically, not limited to allocating corresponding rectangular areas for each first combinational logic circuit 100, second combinational logic circuit 200 or register 300, but arranging at least two types of cell points belonging to different circuits or devices among the first cell points, the second cell points and the third cell points in the same column of the computing chip, the full utilization of the area in the computing chip is realized, and the overall utilization rate is improved.

[0071] According to a second aspect of the present disclosure, a computing board is also proposed, and the computing chips as described above can be included in the computing board. Specifically, the computing board can include one or more computing chips. The multiple computing chips can perform computing tasks in parallel.

[0072] As used herein, words such as "front", "rear", "top", "bottom", "above", "below", etc., if any, are used for descriptive purposes and not necessarily to describe an invariant relative position. It should be understood that such words are interchangeable under appropriate circumstances, such that the embodiments of the present disclosure described herein, for example, can operate in other orientations different from those shown or otherwise described herein.

[0073] As used herein, the word "exemplary" means "serving as an example, instance, or illustration", rather than as a "model" to be precisely replicated. Any implementation described herein exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory expressed or implied in the above technical field, background art, summary of the invention, or detailed description.

[0074] As used herein, the word "substantially" means including any minor variations caused by design or manufacturing defects, tolerances of devices or components, environmental effects, and / or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0075] In addition, the previous description may have referred to elements or nodes or features that are "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element / node / feature is connected (or communicates) with another element / node / feature electrically, mechanically, logically, or otherwise. Similarly, unless otherwise explicitly stated, "coupled" means that one element / node / feature can be connected to another element / node / feature directly or indirectly, mechanically, electrically, logically, or otherwise to allow interaction, even if the two features may not be directly connected. That is, "coupled" is intended to include both direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0076] In addition, for reference purposes only, terms such as "first", "second", etc. may also be used herein and are thus not intended to be limiting. For example, unless the context clearly indicates otherwise, words such as "first", "second", and other such numerical words referring to structures or elements do not imply an order or sequence.

[0077] It should also be noted that, as used herein, the words "comprises", "comprising", "has" and any other variants specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0078] In the present disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" the object, etc.

[0079] Those skilled in the art should also realize that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations and substitutions are also possible. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

[0080] Although some specific embodiments of the present disclosure have been described in detail by way of example, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of the present disclosure. The embodiments disclosed herein can be combined with each other arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that the above embodiments can be modified without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A computing chip, characterized in that: The computing chip includes a plurality of computing stages arranged in a pipeline structure, each computing stage including: a first combinational logic circuit, wherein the first combinational logic circuit occupies a plurality of first cell points adjacent to each other, at least a portion of the first cell points are located in a first incomplete column, and in the first incomplete column, the number of first cell points is less than a first preset number N1, wherein the first preset number N1 is a maximum number of cell points that can be accommodated in each column of the computing chip; One or more second combinational logic circuits, each of which occupies one or more second unit cells, at least part of which is located in a second incomplete column, and the number of second unit cells in the second incomplete column is less than or equal to a second preset number N2, where N2=N1 / 2; and a plurality of registers, each register occupying a plurality of third unit cell points, at least some of the third unit cell points being located in the first incomplete column or the second incomplete column; The first unit cell point, the second unit cell point and the third unit cell point occupy the same area on the computing chip.

2. The computing chip according to claim 1, characterized in that: At least another part of the first cell points is located in a first complete column, and in the first complete column, the number of the first cell points is equal to the first preset number N1.

3. The computing chip according to claim 1, characterized in that: In the first incomplete column, the number of first cell points is greater than or equal to the second preset number N2.

4. The computing chip according to claim 1, characterized in that: In the same first combinatorial logic circuit, the number of first incomplete columns is equal to one.

5. The computing chip according to claim 1, characterized in that: In the data flow direction in the computing chip, the input end of the first combinational logic circuit is directly connected to the register, or the output end of the first combinational logic circuit is directly connected to the register.

6. The computing chip according to claim 1, characterized in that: In the data flow direction in the computing chip, the input end of the first combinational logic circuit is directly connected to the second combinational logic circuit, or the output end of the first combinational logic circuit is directly connected to the second combinational logic circuit.

7. The computing chip according to claim 1, characterized in that: The first combinatorial logic circuit includes an adder.

8. The computing chip according to claim 1, characterized in that: When the number of second unit cell points occupied by the same second combinational logic circuit is greater than the second preset number N2, the second unit cell points exceeding the second preset number N2 are located on one or two middle rows of the computing chip.

9. The computing chip according to claim 1, characterized in that: At least one second combinational logic circuit occupies a third preset number N3 of second cell sites located in the same second complete column, where N3=N1-2.

10. The computing chip according to claim 1, characterized in that: In the data flow direction in the computing chip, the input end of the first second combinational logic circuit is directly connected to the register, and the output end of the last second combinational logic circuit is directly connected to the register.

11. The computing chip according to claim 1, characterized in that: In the data flow direction in the computing chip, an input end of at least one second combinational logic circuit is directly connected to the first combinational logic circuit, or an output end of at least one second combinational logic circuit is directly connected to the first combinational logic circuit.

12. The computing chip according to claim 1, characterized in that: Each register includes a low-bit sub-register and a high-bit sub-register having an equal fourth bit number N0, wherein N0=(N1-2) / 2.

13. The computing chip according to claim 12, characterized in that: The low bit sub-register includes N0 first storage units and a first clock unit; The high bit position sub-register includes N0 second storage units and a second clock unit; The first clock unit and the second clock unit are connected to the same clock signal source.

14. The computing chip according to claim 13, characterized in that: The first clock unit and the second clock unit are located on the middle two rows of the computing chip.

15. The computing chip according to claim 12, characterized in that: The first bit number of the first combinational logic circuit is 2N0 or 2N0-1; The second bit number of the second combinatorial logic circuit is less than or equal to 2N0; and The third bit of the register is 2N0.

16. A hashing board, characterized in that: The computing board comprises one or more computing chips according to any one of claims 1 to 15.

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