A circuit for mutual monitoring between a CPU and an FPGA

Abstract

The present invention provides a circuit for mutual monitoring between a CPU and an FPGA. The circuit includes a first AND gate, a LOCAL bus module, a second AND gate, and a third AND gate. The first AND gate is used to implement the monitoring of the CPU by the FPGA. The LOCAL bus module is located within the CPU. One end of the LOCAL bus module is electrically connected to the GPIO module, and the other end is bidirectionally electrically connected to the FPGA. Moreover, the output ends of both the GPIO module and the CPU are electrically connected to the input end of the second AND gate. The LOCAL bus module and the second AND gate are used to implement the monitoring of the FPGA by the CPU. The output ends of the first AND gate and the second AND gate are electrically connected to the third AND gate, and the third AND gate is used to output a channel valid CHV signal or a channel invalid CHV signal. The circuit designed by the present invention has the advantages of simple and reliable structure, and has been successfully applied to a certain type of unmanned aerial vehicle, being stable and reliable during use.

Description

Technical Field

[0001] The present invention belongs to the field of airborne computers, relates to circuit design technology, and specifically relates to a circuit for mutual monitoring between a CPU and an FPGA. Background Art

[0002] The aircraft electromechanical system is the general term for the subsystems that perform flight support functions in an aircraft. It is a necessary and basic condition for ensuring the various functions of the aircraft. Its reliability and technological advancement directly affect the overall performance of the aircraft and have an important impact on the safety of the aircraft. Compared with the mission system, the electromechanical system places high requirements on the safety of the airborne computer. The airborne computer should be able to accurately judge its own state during operation. When it is working normally, it receives instructions from the superior controller and performs corresponding acquisition and output actions; when it is working abnormally, it should remain silent to prevent false output from causing the spread of faults.

[0003] Currently, during the operation of the airborne computer, there is no strong correlation between the CPU and the FPGA in the self-state monitoring, and it is impossible to accurately sense whether the other is working properly. Therefore, when any one of the CPU and the FPGA fails, the airborne computer can still execute the corresponding acquisition and output actions according to the original instructions, resulting in false output and the spread of faults, and there is a problem of affecting the safety of the system. Summary of the Invention

[0004] In order to achieve the purpose of improving the safety of the airborne computer, the present invention provides a circuit for mutual monitoring between a CPU and an FPGA. Through the mutual monitoring between the CPU and the FPGA, when any one of the CPU and the FPGA appears abnormal, the airborne computer should remain silent and output the corresponding safety state according to the system requirements, avoiding the problem of the spread of faults caused by false output.

[0005] The technical solution for achieving the invention purpose is as follows: A circuit for mutual monitoring between a CPU and an FPGA, the circuit includes a first AND gate, a LOCAL bus module, a second AND gate, and a third AND gate.

[0006] Among them, the first AND gate is located in the FPGA, and the input terminals of the first AND gate are electrically connected to the GPIO module located in the CPU. The first AND gate receives the power supply valid signal PSV and the processor valid signal CPUV output by the GPIO module, and outputs the CPUERROR signal to realize the monitoring of the CPU by the FPGA.

[0007] Among them, the LOCAL bus module is located inside the CPU. One end of the LOCAL bus module is electrically connected to the GPIO module, and the other end is bidirectionally electrically connected to the FPGA. The output ends of the GPIO module and the FPGA are both electrically connected to the input end of the second AND gate. The second AND gate is used to receive the logic valid signal LGCV output by the GPIO module and the DONE signal output by the FPGA. The LOCAL bus module and the second AND gate are used to realize the monitoring of the FPGA by the CPU.

[0008] Among them, the output ends of the first AND gate and the second AND gate are electrically connected to the third AND gate. The third AND gate is used to output a channel valid CHV signal or a channel invalid CHV signal.

[0009] By designing the circuit for mutual monitoring between the CPU and the FPGA, the present invention can associate the CPU and the FPGA. When both the CPU and the FPGA are normal, a channel valid CHV signal is output to determine that the channel status is valid. When any one of the CPU and the FPGA has an abnormality, a channel invalid CHV signal is output to determine that the channel is invalid. At this time, the airborne computer should remain silent and output the corresponding safety status according to the system requirements, so as to avoid the problem of fault spread caused by the misoutput of the airborne computer.

[0010] In an embodiment of the present invention, a logic watchdog is further provided in the above FPGA, and the logic watchdog is located between the GPIO module and the first AND gate.

[0011] The GPIO module performs a dog feeding operation on the logic watchdog. The logic watchdog outputs a dog feeding signal WDV to the first AND gate according to whether there is a dog feeding operation. The first AND gate outputs a CPU ERROR signal according to the dog feeding signal WDV, the power valid signal PSV, and the processor valid signal CPUV to realize the monitoring of the CPU.

[0012] In another embodiment of the present invention, the above LOCAL bus module is used to perform read and write tests on the FPGA, and the LOCAL bus module outputs a logic valid signal LGCV to the second AND gate through the GPIO module to realize the monitoring of the FPGA.

[0013] Furthermore, the method for the LOCAL bus module to monitor the FPGA includes the following steps:

[0014] The LOCAL bus module accesses the FPGA and writes test data into the FPGA;

[0015] The FPGA performs an inversion operation on the test data to generate inverted test data;

[0016] The LOCAL bus module receives the inverted test data and compares the inverted test data with the test data;

[0017] If the test data is consistent with the inverted test data, it is determined that the FPGA is working properly, and the logical valid signal LGCV is output as "1";

[0018] If the test data is inconsistent with the inverted test data, it is determined that the FPGA is working abnormally, and the logical valid signal LGCV is output as "0".

[0019] In an embodiment of the present invention, the output end of the above third AND gate is further connected to a NOT gate, and the output end of the NOT gate is electrically connected to the output control bus driver. The NOT gate is used to invert the channel valid CHV signal to enable the output control bus driver to be in an enabled state or a safe state.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] 1. By designing a circuit for mutual monitoring between the CPU and the FPGA, the CPU and the FPGA can be associated. When both the CPU and the FPGA are normal, the channel valid CHV signal is output to determine that the channel status is valid. When any one of the CPU and the FPGA is abnormal, the channel invalid CHV signal is output to determine that the channel is invalid. At this time, the airborne computer should remain silent and output the corresponding safe state according to the system requirements, thereby avoiding the problem of fault spread caused by the misoutput of the airborne computer.

[0022] 2. By electrically connecting the output point of the third AND gate to the output control bus driver through a NOT gate, when any one of the CPU and the FPGA is abnormal and the channel invalid CHV signal is output to determine that the channel is invalid, the NOT gate can invert the channel invalid CHV signal to enable the output control bus driver to control the product to be in an enabled state or a safe state. For example, when the third AND gate outputs the channel valid CHV signal, after being inverted by the NOT gate, the control bus driver is in an enabled state; when the third AND gate outputs the channel invalid CHV signal, after being inverted by the NOT gate, the control bus driver is in a non-enabled state, making the product unable to output. By configuring the pull-up and pull-down resistors at the output end of the bus driver, the output interface of the product is in the safe state required by the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only for the present invention to more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is the circuit design diagram for mutual monitoring between the CPU and the FPGA in the specific implementation manner. Specific implementation manner

[0025] The present invention will be further described below in conjunction with specific embodiments, and the advantages and features of the present invention will become clearer as the description progresses. However, these embodiments are exemplary only and do not constitute any limitation to the scope of the present invention. Those skilled in the art should understand that without departing from the spirit and scope of the present invention, modifications or substitutions can be made to the details and forms of the technical solutions of the present invention, but such modifications and substitutions all fall within the protection scope of the present invention.

[0026] In the description of this embodiment, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present invention.

[0027] In addition, terms such as "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "plurality" is two or more.

[0028] This specific implementation manner provides a circuit for mutual monitoring between a CPU and an FPGA. The circuit includes a first AND gate, a LOCAL bus module, a second AND gate, and a third AND gate.

[0029] Among them, as Figure 1 shown, the first AND gate is located inside the FPGA. The input terminals of the first AND gate are electrically connected to the GPIO module located inside the CPU. The first AND gate receives the power supply valid signal PSV and the processor valid signal CPUV output by the GPIO module, and outputs a CPU ERROR signal to implement the monitoring of the CPU by the FPGA.

[0030] Specifically, the power supply valid signal PSV is that the CPU monitors the secondary power supply voltage through the built-in AD. The 5V digital voltage and the 15V analog voltage are divided by resistors to a reasonable range and then connected to the built-in AD of the CPU for voltage acquisition. If the CPU acquires the secondary power supply voltage normally, the power supply valid signal PSV outputs "1"; if the CPU acquires the secondary power supply voltage outside the normal range, the power supply valid signal PSV outputs "0". The processor valid signal CPUV is the BIT of the CPU itself. The CPU realizes the test and monitoring of its own internal resources through its own logical operations, arithmetic operations, memory tests, etc. When the test of the CPU's own internal resources is normal, the processor valid signal CPUV outputs "1"; if the test is abnormal, the processor valid signal CPUV outputs "0". When the first AND gate monitors the CPU, when both the power supply valid signal PSV and the processor valid signal CPUV output 1, it means the CPU is normal, and at this time, the CPU ERROR signal output by the first AND gate is 1. When any one of the power supply valid signal PSV and the processor valid signal CPUV outputs 0, it means the CPU is abnormal, and at this time, the CPU ERROR signal output by the first AND gate is 0.

[0031] In an embodiment of this specific implementation manner, in order to improve the accuracy of the FPGA's monitoring of the CPU, as Figure 1 shown, a logic watchdog is further provided in the above FPGA. The logic watchdog is located between the GPIO module and the first AND gate. Among them, the GPIO module performs a dog feeding operation on the logic watchdog, and the logic watchdog outputs a dog feeding signal WDV to the first AND gate according to whether there is a dog feeding operation. Specifically, the CPU periodically performs a dog feeding operation on the FPGA through the WDI signal of the GPIO module. When the dog feeding operation is normal, it indicates that the CPU is working normally, and the dog feeding signal WDV output by the logic watchdog is "1"; when the dog feeding operation is abnormal, it indicates that there is an abnormality in the CPU software, that is, the dog feeding operation fails to be performed within the specified time, and the output dog feeding signal WDV is "0". At this time, the first AND gate outputs a CPU ERROR signal according to the dog feeding signal WDV, the power supply valid signal PSV, and the processor valid signal CPUV. That is, when the dog feeding signal WDV, the power supply valid signal PSV, and the processor valid signal CPUV are all "1", it means the CPU is normal, and the CPU ERROR signal output by the first AND gate is "1"; when any one or more of the dog feeding signal WDV, the power supply valid signal PSV, and the processor valid signal CPUV are "0", it means the CPU is abnormal, and the CPU ERROR signal output by the first AND gate is "0".

[0032] Among them, as Figure 1As shown, the LOCAL bus module is located within the CPU. One end of the LOCAL bus module is electrically connected to the GPIO module, and the other end is bidirectionally electrically connected to the FPGA. The output end of the GPIO module is electrically connected to the input end of the second AND gate, and the second AND gate is used to receive the logically valid signal LGCV output by the GPIO module. In an embodiment of the above LOCAL bus module, the LOCAL bus module is used to perform read and write tests on the FPGA, and the LOCAL bus module outputs the logically valid signal LGCV to the second AND gate via the GPIO module to achieve monitoring of the FPGA. The method for the LOCAL bus module to monitor the FPGA includes the following steps: The LOCAL bus module accesses the FPGA and writes test data into the FPGA; the FPGA performs an inversion operation on the test data to generate inverted test data; the LOCAL bus module receives the inverted test data and compares the inverted test data with the test data; if the test data is consistent with the inverted test data, it is determined that the FPGA is working properly, and the logically valid signal LGCV is output as "1"; if the test data is inconsistent with the inverted test data, it is determined that the FPGA is working abnormally, and the logically valid signal LGCV is output as "0".

[0033] The input end of the second AND gate is also electrically connected to the output end of the FPGA. The FPGA outputs a DONE signal according to its own loading situation; wherein, the DONE signal output when the FPGA loading is completed is "1", and the DONE signal output when the FPGA is working abnormally or the FPGA loading fails is "0".

[0034] When both the output DONE signal and the logically valid signal LGCV are 1, it indicates that the FPGA is in a normal working state at this time, and the second AND gate outputs "1"; when any one of the output DONE signal and the logically valid signal LGCV is 0, it indicates that the FPGA is in an abnormal working state at this time, and the second AND gate outputs "0". The LOCAL bus module and the second AND gate are used to achieve the monitoring of the FPGA by the CPU.

[0035] In the above monitoring of the FPGA by the CPU and the monitoring of the CPU by the FPGA, when the CPU is normal, the second AND gate outputs "1" at this time; when the CPU is abnormal, the second AND gate outputs "0" at this time; when the FPGA is normal, the CPUERROR signal output by the first AND gate is "1"; when the FPGA is abnormal, the CPU ERROR signal output by the first AND gate is "0". As Figure 1 shown, the output ends of the first AND gate and the second AND gate are electrically connected to the third AND gate, and the third AND gate is used to output a channel valid CHV signal or a channel invalid CHV signal.

[0036] Specifically, when both the CPU and the FPGA are normal, the first AND gate and the second AND gate both output "1" to the third AND gate. At this time, the third AND gate outputs a channel valid CHV signal, which is "1", indicating that the channel is normal, and the airborne computer still executes the corresponding acquisition and output actions according to the original instructions. When either the CPU or the FPGA is abnormal, the first AND gate and the second AND gate output one or two "0"s to the third AND gate. At this time, the third AND gate outputs a channel invalid CHV signal, which is "0", indicating that the channel is abnormal, meaning that the internal operation of the airborne computer is abnormal. The airborne computer should remain silent and output the corresponding safety state according to the system requirements.

[0037] In another embodiment of this specific implementation manner, in order to ensure that when the channel is abnormal, the airborne computer should remain silent and output the corresponding safety state according to the system requirements, as Figure 1 shown, a NOT gate is also connected to the output end of the third AND gate, and the output end of the NOT gate is electrically connected to the output control bus driver. The NOT gate is used to invert the channel valid CHV signal to enable the output control bus driver to be in the enabled state or the safety state. For example, when the output of the third AND gate is "0", the channel is invalid. After the NOT gate inverts the output of the third AND gate, it becomes "1". At this time, the output control bus driver is in the disabled state, and the product cannot output. By configuring the pull-up and pull-down resistors at the output end of the bus driver, the output interface of the product is in the safety state required by the system, ensuring that the product does not malfunction when the channel fails. When the output of the third AND gate is "1", the channel is valid, and at this time, the output control bus driver is in the enabled state, and the product executes the output according to the original control instructions of the airborne computer.

[0038] The circuit designed in this specific implementation manner for mutual monitoring between the CPU and the FPGA can associate the CPU and the FPGA. When both the CPU and the FPGA are normal, it outputs a channel valid CHV signal to determine that the channel status is valid. When any one of the CPU and the FPGA is abnormal, it outputs a channel invalid CHV signal to determine that the channel is invalid. At this time, the airborne computer should remain silent and output the corresponding safety state according to the system requirements, thus avoiding the problem of fault spread caused by incorrect output of the airborne computer.

[0039] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

[0040] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A circuit for mutual monitoring between a CPU and an FPGA, characterized in that: The circuit includes a first AND gate, a LOCAL bus module, a second AND gate, and a third AND gate; The first AND gate is located within the FPGA, and the input terminals of the first AND gate are electrically connected to the GPIO module located within the CPU. The first AND gate receives the power supply valid signal PSV and the processor valid signal CPUV output by the GPIO module, and outputs a CPU ERROR signal to implement the monitoring of the CPU by the FPGA; The LOCAL bus module is located within the CPU. One end of the LOCAL bus module is electrically connected to the GPIO module, and the other end is bidirectionally electrically connected to the FPGA; the output terminals of the GPIO module and the FPGA are both electrically connected to the input terminals of the second AND gate. The second AND gate is used to receive the logic valid signal LGCV output by the GPIO module and receive the DONE signal output by the FPGA. The LOCAL bus module and the second AND gate are used to implement the monitoring of the FPGA by the CPU; The output terminals of the first AND gate and the second AND gate are electrically connected to the third AND gate. The third AND gate is used to output a channel valid CHV signal or a channel invalid CHV signal. The output terminal of the third AND gate is also connected to a NOT gate, and the output terminal of the NOT gate is electrically connected to an output control bus driver. The NOT gate is used to invert the channel valid CHV signal, so that the output control bus driver controls the product to be in an enabled state or a safe state; A logic watchdog is further provided within the FPGA, and the logic watchdog is located between the GPIO module and the first AND gate; The GPIO module performs a dog feeding operation on the logic watchdog, and the logic watchdog outputs a dog feeding signal WDV to the first AND gate according to whether there is a dog feeding operation; the first AND gate outputs a CPU ERROR signal through the dog feeding signal WDV, the power supply valid signal PSV, and the processor valid signal CPUV to implement the monitoring of the CPU.

2. The circuit for mutual monitoring between the CPU and the FPGA according to claim 1, characterized in that: The LOCAL bus module is used to perform read and write tests on the FPGA, and the LOCAL bus module outputs the logic valid signal LGCV to the second AND gate through the GPIO module to implement the monitoring of the FPGA.

3. The circuit for mutual monitoring between the CPU and the FPGA according to claim 1, characterized in that: The method for the LOCAL bus module to monitor the FPGA includes the following steps: The LOCAL bus module accesses the FPGA and writes test data into the FPGA; The FPGA performs an inversion operation on the test data to generate inverted test data; The LOCAL bus module receives the inverted test data and compares the inverted test data with the test data; If the test data is consistent with the inverted test data, it is determined that the FPGA is working properly, and the logic valid signal LGCV is output as "1"; If the test data is inconsistent with the inverted test data, it is determined that the FPGA is working abnormally, and the logic valid signal LGCV is output as "0".

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