Techniques for mirroring command / address or interpreting command / address logic in a memory device

Abstract

Examples include techniques for mirroring command / address or interpreting command / address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command / address signal and mirroring the command / address or interpreting command / address logic indicated in the command / address signal based on one or more shorted pins of the memory device.

Description

[0001] Related Cases

[0002] This application claims priority under 35 USC §365(c) to U.S. Patent No. 15 / 266,991, filed on September 15, 2016, entitled “Techniques for Mirroring Commands / Addresses or Interpreting Command / Address Logic in a Memory Device,” which in turn claims the benefit of priority to U.S. Provisional Application No. 62 / 304,212, filed on March 5, 2016, entitled “Techniques for Mirroring Commands / Addresses or Interpreting Command / Address Logic in a Memory Device.” The entire disclosures of these documents are incorporated herein by reference for all purposes. Technical Field

[0003] The examples described herein generally involve memory devices on dual in-line memory modules (DIMMs). Background Art

[0004] Memory modules coupled to computing platforms or systems, such as those configured as servers, may include dual in-line memory modules (DIMMs). DIMMs may include various types of memory, including volatile or non-volatile types of memory. As memory technology has advanced to include memory cells with increasingly higher densities, the memory capacity of DIMMs has also increased considerably. Moreover, advances in data rates for accessing data to be written to or read from memory included in a DIMM have enabled large amounts of data to flow between a requestor requiring access and a memory device included in the DIMM. Higher data rates may result in an increased frequency of signals transmitted to / from the memory included in the DIMM. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example system is shown.

[0006] Figure 2 An example first portion of a dual in-line memory module (DIMM) is shown.

[0007] Figure 3 An example second portion of a DIMM is shown.

[0008] Figure 4 An example pinout diagram is shown.

[0009] Figure 5 Example memory device logic is shown.

[0010] Figure 6 An example device is shown.

[0011] Figure 7 An example first logic flow is shown.

[0012] Figure 8 An example first logic flow is shown.

[0013] Fig. 9 Example storage media are shown.

[0014] Fig.10 An example computing platform is shown. DETAILED DESCRIPTION

[0015] As contemplated by the present disclosure, higher data rates for accessing data to be written to or read from a memory or memory device on a DIMM may result in an increased frequency of signals transmitted to / from the memory device on the DIMM. Techniques for improving signal integrity and saving power may be implemented to include command / address signal mirroring or inversion.

[0016] In some examples, a memory bus that transmits data via an increased frequency can perform best when the interconnect stubs between memory devices on opposite sides of a DIMM are minimized or made as short as possible. Some existing DIMMs may use special "mirror" packages or tolerate long stubs and associated suboptimal signal routing. Other DIMMs may handle this by not using packages with different mirrors. Instead, these other DIMMs may perform command / address mirroring for the pins of the memory devices, which may be swapped without changing functionality. For example, pins that may be used purely for address bits. For example, pins for command bits may not be swapped. The same situation may occur for this type of swapping for inversion of command / address signals. This can significantly limit the number of pins that can be used for mirroring.

[0017] Also, in some examples of how current computing systems implement inversion through memory devices in DIMMs, a memory controller may use multiple command cycles during initialization. The first cycle may be issued normally, and the second cycle may issue a copy of the same command with the logic inverted. This may impose very complex requirements on the host memory controller to flip or invert the bits.

[0018] Figure 1 A system 100 is shown. Figure 1 As shown in , in some examples, system 100 includes a host 110 coupled to DIMMs 120-1 to 120-n, where "n" is any positive integer having a value greater than 2. For these examples, DIMMs 120-1 to 120-n may be coupled to host 110 via one or more channels 140-1 to 140-n. Figure 1As shown in , host 110 may include an operating system (OS) 114, one or more applications ((one or more) Apps) 116, and circuitry 112. Circuitry 112 may include one or more processing elements 111 (e.g., processors or processor cores) coupled to a memory controller 113. Host 110 may include, but is not limited to, a personal computer, a desktop computer, a laptop computer, a tablet computer, a server, a server array or server farm, a web server, a network server, an Internet server, a workstation, a minicomputer, a mainframe computer, a supercomputer, a network device, a web device, a distributed computing system, a multiprocessor system, a processor-based system, or a combination thereof.

[0019] In some examples, such as Figure 1 As shown in , DIMMs 120-1 to 120-n may include corresponding memory dies or devices 120-1 to 120-n. Memory devices 120-1 to 120-n may include various types of volatile and / or non-volatile memory. Volatile memory may include, but is not limited to, random access memory (RAM), dynamic RAM (D-RAM), double data rate synchronous dynamic RAM (DDR SDRAM), static random access memory (SRAM), thyristor RAM (T-RAM), or zero capacitor RAM (Z-RAM). Non-volatile memory may include, but is not limited to, non-volatile types of memory (such as byte or block addressable 3-dimensional (3-D) cross point memory). These block-addressable or byte-addressable non-volatile types of memory of the memory devices 120-1 to 120-n may include, but are not limited to, memory using chalcogenide phase change materials (e.g., chalcogenide glass), multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory combined with memristor technology, or spin-transfer torque MRAM (STT-MRAM), or any combination of the above, or other non-volatile memory types.

[0020] According to some examples, the memory devices 122-1 to 122-n, which include volatile and / or non-volatile types of memory, may operate according to a variety of memory technologies, such as new technologies associated with DIMMs being developed, including but not limited to DDR5 (DDR version 5, currently being discussed by JEDEC), LPDDR5 (LPDDR version 5, currently being discussed by JEDEC), HBM2 (HBM version 2, currently being discussed by JEDEC), and / or other new technologies based on derivatives or extensions of such specifications. The memory devices 122-1 to 122-n may also operate according to other memory technologies such as, but not limited to, DDR4 (Double Data Rate (DDR) Version 4, initial specification published by JEDEC in September 2012), LPDDR4 (Low Power Double Data Rate (LPDDR) Version 4, JESD209-4, initially published by JEDEC in August 2014), WIO2 (Wide I / O 2 (WideIO2), JESD229-2, initially published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235, initially published by JEDEC in October 2013), and / or other technologies based on derivatives or extensions of these specifications.

[0021] According to some examples, the DIMMs 120-1 to 120-n may be designed to function as registered DIMMs (RDIMMs), load reduced DIMMs (LRDIMMs), low power DIMMs (LPDIMMs), fully buffered DIMMs (FB-DIMMs), unbuffered DIMMs (UDIMMs), or small outline (SODIMMs). Examples are not limited to only these DIMM designs.

[0022] In some examples, the memory devices 122-1 to 122-n in the DIMMs 120-1 to 120-n may include all or a combination of types of volatile or non-volatile memory. For example, the memory device 122-1 in the DIMM 120-1 may include volatile memory (e.g., DRAM) on the front side or first side, and may include non-volatile memory (e.g., 3D cross point memory) on the back side or second side. In other examples, a hybrid DIMM may include a combination of non-volatile and volatile types of memory for the memory devices 122-1 on either side of the DIMM 120-1. In other examples, all memory devices 122-1 may be either volatile type of memory or non-volatile type of memory. In some examples, multiple channels may be coupled to the memory devices maintained on the DIMM, and in some examples, separate channels may be routed to different non-volatile / volatile types and / or groups of memory devices. For example, a first channel to a memory device including non-volatile memory and a second channel to a memory device including volatile memory. In other examples, a first channel may be routed to memory devices on a first side of the DIMM and a second channel is routed to memory devices on a second side of the DIMM.Examples are not limited to the above examples of how multiple channels may be routed to memory devices included on a single DIMM.

[0023] Figure 2 An example DIMM section 200 is shown. In some examples, DIMM section 200 shows how a bilateral memory module assembly can have memory devices or dies 201 and 202 on opposite sides of a printed circuit board (PCB) 203 and share a common address bus for command / address buses A and B. For these examples, pins 212 and 214 on memory device 201 become mirror images of pins 222 and 224 on memory device 202 for the common command / address buses A and B.

[0024] In some examples, connections between mirrored or identical pins on either side of PCT 203 result in branching lines (by Figure 2 ), which may consume PCB routing resources and may affect bus frequency scaling. As described more below, techniques for implementing mirroring can reduce the length of this branch line. However, DIMM portion 200 shows an example when mirroring is not implemented.

[0025] Figure 3An example DIMM portion 300 is shown. In some examples, command / address signals can be exchanged at the target memory device so that the command / address signals can be consistent between memory devices on opposite sides of PCB 303. Thus, common vias through PCB 303 can be shared, such as Figure 3 . Now, a command / address signal such as command / address A may be connected to pin 322 of memory device 320, and may also be connected to pin 312 of memory device 310 to form a shortest path or branch line (which is routed through PCB 303) between these memory devices. As described more below, a strap pin may be utilized on a given memory device to indicate that a given command / address pin has been mirrored. For example, a first command / address to memory device 320 indicated in a command / address signal received via command / address A at pin 322 may be a mirror image of a second command / address to memory device 310 at pin 312, or vice versa.

[0026] According to some examples, the DIMM may use circuits or logic in a register buffer (not shown) to generate additional copies of the command / address bus to reduce bus load. For these examples, the logic and / or circuits in the register buffer may cause the command / address signal to be propagated from the register buffer to multiple bus segments of the memory device on the DIMM. The propagated command / address signal may indicate corresponding command / address logic with logic levels inverted relative to each other. The inversion of the logic levels indicated in these propagated command / address signals may improve power efficiency and signal integrity. However, the circuits and / or logic in the memory device and / or in the register buffer need to know that the command / address logic indicated in the command / address signal has been inverted. In some examples, another shorting pin or bit may be utilized so that the memory device and / or logic in the register buffer may un-invert the command / address logic indicated in the command / address signal for correct command / address logic interpretation.

[0027] Figure 4 An example pin diagram 400 is shown. In some examples, the pin diagram 400 can be used for a memory device having DRAM included on a DIMM. For these examples, the shorted pins indicated in the pin diagram 400 in boxes F2 (Mirror) and G2 (CAI) can indicate whether the memory device should mirror the command / address indicated in the command / address signal and / or interpret the command / address logic indicated in the received command / address signal as inverted.

[0028] According to some examples, a MIRROR pin (F2) of a target memory device designed according to pinout 400 may be connected to a power pin, such as an output storage drain power voltage (VDDQ) pin (e.g., H1). For these examples, the target memory device may internally swap an even-numbered command / address (CA) with the next higher corresponding odd-numbered CA to mirror a given CA to the target memory device. Example swap pairs for mirroring a given CA according to pinout 400 may include swapping CA2 with CA3 (not CA1), swapping CA4 with CA5 (not CA3), swapping CA6 with CA7 (not CA5), etc. In some examples, the MIRROR pin may be tied or connected to a ground pin, such as a VSSQ pin (e.g., G1) if CA swapping is not required or desired.

[0029] In some examples, a memory device designed to use a pinout such as pinout 400 may internally invert the command / address logic level indicated in a received command / address signal (e.g., routed from a register buffer) where the CAI (command address inversion) pin is connected to VDDQ (e.g., H1). According to some examples, if the command / address logic is not to be interpreted as inverted, the CAI pin may be connected or tied to a ground pin such as the VSSQ pin (e.g., H1).

[0030] Two independent shorting pins for MIRROR and CAI can allow four different combinations, which may include [no mirror, no inversion], [no mirror, inversion], [mirror, no inversion] or [mirror, inversion].

[0031] Figure 5 An example memory device logic 500 is shown. In some examples, such as Figure 5 As shown in , the circuits of the memory device logic 500 can be activated based on whether one or both of the shorting pin 501 of MIRROR or the shorting pin 502 of CAI has been connected to the power / VDDQ pin (generating a 1) or to the ground / VSSQ pin (generating a 0). Figure 5 As shown in FIG, if a logic 1 is generated from the short pin 501, the memory device including the memory device logic 500 can flip the command / address signal received through the CMD / ADD pin 510 (of command / address CA0 to CA13) by using the multiplexer 530. Also, if a logic 1 is generated from the short pin 502, the memory device including the memory device logic 500 can invert the command / address logic indicated in the command / address signal received through the CMD / ADD pin 510 (of command / address CA0 to CA13) by using the XOR gate 520.

[0032] Figure 6 An example block diagram of device 600 is shown. Figure 6 The device 600 is shown in FIG. 6 as having a limited number of elements in a certain topology, but it can be appreciated that the device 600 can include more or fewer elements in alternative topologies as desired for a given implementation.

[0033] The device 600 may be supported by circuitry 620 maintained at or located at a memory device on a DIMM coupled to a host via one or more channels. The circuitry 620 may be arranged to execute one or more software or firmware implemented components or logic 622-a. Notably, "a" and "b" and "c" and similar designators as used herein are intended to be variables representing any positive integer. Thus, for example, if an implementation sets a value of a=3, a complete set of software or firmware for component or logic 622-a may include component or logic 622-1 or 622-2. The examples presented are not limited to this context and different variables used throughout may represent the same or different integer values. Moreover, these 'components' or "logic" may be software / firmware stored in a computer-readable medium, and although in Figure 6 Components are shown as discrete blocks in the , but this does not limit these components to storage in different computer-readable media components (eg, separate memories, etc.).

[0034] According to some examples, the circuit 620 may include a processor or processor circuit. The processor or processor circuit may be any of a variety of commercially available processors, including but not limited to AMD® Athlon®, Duron®, and Opteron® processors; ARM® application, embedded, and security processors; IBM® and Motorola® DragonBall® and PowerPC® processors; IBM and Sony® Cell processors; Intel® Atom®, Celeron®, Core (2) Duo®, Core i3, Core i5, Core i7, Itanium®, Pentium®, Xeon®, Xeon Phi®, and XScale® processors; and similar processors. According to some examples, the circuit 620 may also be an application specific integrated circuit (ASIC), and at least some components or logic 622-a may be implemented as hardware elements of the ASIC.

[0035] According to some examples, the device 600 may include mirror logic 622-1. The mirror logic 622-1 may be executed by the circuit 620 to receive a first command / address signal indicating a first command / address to a target memory device, which may include the device 600. The target memory device may be located on a first side of a DIMM. The command / address signal may be included in the CMD / ADD to be mirrored 605. The mirror logic 622-1 may then mirror the first command / address so that the first command / address indicated in the command / address signal is a mirror of a second command / address to a memory device on a second side of the DIMM. The mirrored command / address may be included in the mirrored CMD / ADD 630.

[0036] In some examples, the device 600 may also include inversion logic 622-2. The inversion logic 622-2 may be executed by the circuit 620 to receive a command / address signal at a memory device including the device 600. The inversion logic 622-2 may determine whether the command / address logic indicated by the command / address signal has been inverted based on the short pins of the memory device and then interpret the command / address logic indicated by the command / address signal based on the determination. The inverted command / address logic may be included in the CMD / ADD signal 610, and the interpreted command / address logic may be included in the interpreted CMD / ADD logic 635.

[0037] Figure 7 An example logic flow 700 is shown. Figure 7 As shown in , the first logic flow includes logic flow 700. Logic flow 700 may represent some or all operations performed by one or more logics, features, or devices described herein (such as device 700). More specifically, logic flow 700 may be implemented by mirror logic 622-1.

[0038] According to some examples, the logic flow 700 may receive a command / address signal indicating a first command / address to a target memory device on a first side of a DIMM at block 702. For these examples, the mirror logic 622-1 may receive the command / address signal.

[0039] In some examples, the logic flow 700 may determine a first command / address indicated in the command / address signal to be mirrored based on the shorted pins of the target memory device at block 704. For these examples, the mirror logic 622-2 may make this determination.

[0040] According to some examples, at block 706, the logic flow 700 can mirror the first command / address to the target memory device such that the first command / address indicated in the command / address signal is a mirror of a second command / address to the non-target memory device on the second side of the DIMM. For these examples, the mirroring logic 622-1 can mirror the first command / address to the target memory device.

[0041] Figure 8 An example logic flow 800 is shown. Figure 8 As shown in , the first logic flow includes logic flow 800. Logic flow 800 may represent some or all operations performed by one or more logics, features, or devices described herein (such as device 800). More specifically, logic flow 800 may be implemented by inversion logic 622-1.

[0042] According to some examples, logic flow 800 may receive a command / address signal at a memory device on a DIMM at block 802. For these examples, inversion logic 622-1 may receive the command / address signal.

[0043] In some examples, logic flow 800 may determine whether command / address logic indicated by the command / address signal has been inverted based on the shorted pins of the memory device at block 804. For these examples, inversion logic 822-2 may determine whether command / address logic has been inverted.

[0044] According to some examples, at block 806, the logic flow 800 can interpret the command / address logic indicated by the command / address signal based on a determination that the command / address logic indicated in the command / address signal has been inverted. For these examples, the inversion logic 822-2 can interpret the command / address logic based on the determination.

[0045] Fig. 9 An example storage medium 900 is shown. Fig. 9As shown in , the first storage medium includes storage medium 900. Storage medium 900 may include an article of manufacture. In some examples, storage medium 900 may include any non-transitory computer-readable medium or machine-readable medium, such as an optical, magnetic or semiconductor storage device. Storage medium 900 may store various types of computer-executable instructions, such as instructions for implementing logic flow 700 or 800. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and the like. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like. Examples are not limited to this context.

[0046] Fig.10 An example computing platform 1000 is shown. In some examples, such as Fig.10 As shown in , computing platform 1000 may include memory system 1030, processing component 1040, other platform components 1050, or communication interface 1060. According to some examples, computing platform 1000 may be implemented in a computing device.

[0047] According to some examples, memory system 1030 may include controller 1032 and one or more memory devices 1034. For these examples, logic and / or features residing or located at controller 1032 may perform at least some processing operations or logic of device 600 and may include storage media (which includes storage media 1000). In addition, one or more memory devices 1034 may include similar types of volatile or non-volatile memory (not shown) as described above for Figure 1-3 1040 ). In some examples, the controller 1032 can be part of the same die as the one or more memory devices 1034. In other examples, the controller 1032 and the one or more memory devices 1034 can be located on the same die or integrated circuit as the processor (e.g., included in the processing component 1040). In still other examples, the controller 1032 can be in a separate die or integrated circuit coupled to or on the one or more memory devices 1034.

[0048] According to some examples, the processing component 1040 may include various hardware elements, software elements, or a combination of the two. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices (PLDs), digital signal processors (DSPs), FPGAs / programmable logic, memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software elements may include software components, programs, applications, computer programs, applications, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, APIs, instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination thereof. As desired for a given example, determining whether to implement an example using hardware elements and / or software elements can vary depending on any number of factors, such as desired computational rate, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints.

[0049] In some examples, other platform components 1050 may include common computing elements such as one or more processors, multi-core processors, coprocessors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia I / O components (e.g., digital displays), power supplies, etc. Examples of memory units associated with other platform components 1050 or storage system 1030 may include, but are not limited to, various types of computer-readable and machine-readable storage media in the form of one or more higher-speed memory units, such as read-only memory (ROM), RAM, DRAM, DDR DRAM, synchronous DRAM (SDRAM), DDR SDRAM, SRAM, programmable ROM (PROM), EPROM, EEPROM, flash memory, ferroelectric memory, SONOS memory, polymer memory (e.g., ferroelectric polymer memory), nanowires, FeTRAM or FeRAM, Osborn memory, phase change memory, memristor, STT-MRAM, magnetic or optical cards, and any other type of storage medium suitable for storing information.

[0050] In some examples, the communication interface 1060 may include logic and / or features for supporting a communication interface. For these examples, the communication interface 1060 may include one or more communication interfaces that operate according to various communication protocols or standards to communicate through a direct or network communication link. Direct communication may occur through a direct interface using a communication protocol or standard described in one or more industry standards (including descendants and variants) (such as standards associated with the SMBus specification, PCIe specification, NVMe specification, SATA specification, SAS specification, or USB specification). Network communication may occur through a network interface using a communication protocol or standard (such as those described in one or more Ethernet standards published by IEEE). For example, one such Ethernet standard may include IEEE 802.3-2012, "Carrier sense Multiple access with Collision Detection (CSMA / CD) Access Method and Physical Layer Specifications" (hereinafter referred to as "IEEE 802.3"), published in December 2012.

[0051] The computing platform 1000 may be part of a computing device, which may be, for example, a user device, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a smart phone, an embedded electronic device, a game console, a server, a server array or server farm, a web server, a network server, an Internet server, a workstation, a minicomputer, a mainframe computer, a supercomputer, a network equipment, a web equipment, a distributed computing system, a multiprocessor system, a processor-based system, or a combination thereof. Accordingly, the functionality and / or specific configurations of the computing platform 1000 described herein may be included or omitted in various embodiments of the computing platform 1000 as appropriately desired.

[0052] The components and features of computing platform 1000 may be implemented using any combination of discrete circuits, ASICs, logic gates, and / or single-chip architectures. In addition, the features of computing platform 1000 may be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any combination of the foregoing, where appropriate. Note that hardware, firmware, and / or software elements may be collectively or individually referred to herein as "logic," "circuit," or "circuitry."

[0053] One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium, which represent various logic within a processor, which, when read by a machine, computing device, or system, causes the machine, computing device, or system to fabricate logic to perform the techniques described herein. Such representations may be stored on tangible machine-readable media and supplied to various customers or fabrication facilities to be loaded into fabrication machines that actually fabricate the logic or processor.

[0054] Various examples can be realized using hardware elements, software elements or a combination of the two. In some examples, hardware elements can include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements can include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, APIs, instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols or any combination thereof. As desired for a given example, determining whether to use hardware elements and / or software elements to realize an example can vary according to any number of factors, such as desired computing rate, power level, heat resistance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed and other design or performance constraints.

[0055] Some examples may include an article of manufacture or at least one computer-readable medium. A computer-readable medium may include a non-transitory storage medium for storing logic. In some examples, a non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and the like. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, applications, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, APIs, instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0056] According to some examples, a computer-readable medium may include a non-transitory storage medium for storing or maintaining instructions, which, when executed by a machine, a computing device, or a system, causes the machine, the computing device, or the system to perform methods and / or operations according to the described examples. Instructions may include any suitable type of code (such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc.). Instructions may be implemented according to a predefined computer language, manner, or syntax to instruct a machine, a computing device, or a system to perform a certain function. Instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0057] Some examples may be described using the expression "in one example" or "example" along with its derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase "in one example" in various places in the specification are not necessarily all referring to the same example.

[0058] The expressions "coupled" and "connected" along with their derivatives may be used to describe some examples. These terms are not necessarily intended to be synonyms for each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0059] The following examples relate to additional examples of the techniques disclosed herein.

[0060] Example 1. An example apparatus may include: circuitry for a memory device on a first side of a DIMM. The circuitry may include logic, at least a portion of which is hardware, that may receive a command / address signal indicating a first command / address to the target memory device. The logic may also determine to mirror the first command / address indicated in the command / address signal based on a shorting pin of the memory device. The logic may also mirror the first command / address to the memory device such that the first command / address indicated in the command / address signal is a mirror of a second command / address to the memory device on a second side of the DIMM.

[0061] Example 2. As an apparatus as described in Example 1, the logic for mirroring the first command / address to the target memory device may include logic for swapping corresponding even-numbered commands / addresses to the target memory device with corresponding next higher odd-numbered commands / addresses to the target memory device.

[0062] Example 3. As an apparatus of Example 1, the logic for determining that the first command / address indicated in the command / address signal is the mirror of the second command / address based on the shorting pin includes logic for determining that the shorting pin is connected to a power pin of the target memory device.

[0063] Example 4. The device of Example 3, wherein the power pin comprises a VDDQ pin.

[0064] Example 5. In the apparatus of Example 1, the DIMM may be an RDIMM, an LPDIMM, an LRDIMM, an FB-DIMM, an UDIMM, or a SODIMM.

[0065] Example 6. In the apparatus of Example 1, the memory device may include a non-volatile memory or a volatile memory.

[0066] Example 7. In the device of Example 6, the volatile memory may be DRAM.

[0067] Example 8. In the device of Example 6, the non-volatile memory may be a three-dimensional cross-point memory, a memory using a chalcogenide phase change material, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level PCM, a resistive memory, an Austrian memory, a nanowire memory, a FeTRAM, an MRAM memory combined with a memristor technology, or an STT-MRAM.

[0068] Example 9. An example method may include receiving, by circuitry at a target memory device on a first side of a DIMM, a command / address signal indicating a first command / address to the target memory device. The method may also include determining to mirror the first command / address indicated in the command / address signal based on a shorting pin of the target memory device. The method may also include mirroring the first command / address to the target memory device such that the first command / address indicated in the command / address signal is a mirror of a second command / address to a non-target memory device on a second side of the DIMM.

[0069] Example 10. The method of Example 9, mirroring the first command / address to the target memory device may include swapping a corresponding even-numbered command / address to the target memory device with a corresponding next higher odd-numbered command / address to the target memory device.

[0070] Example 11. As the method of Example 9, determining based on the shorting pin that the first command / address indicated in the command / address signal is the mirror image of the second command / address may include the shorting pin being connected to a power pin of the target memory device.

[0071] Example 12. The method of Example 11, wherein the power pin may be a VDDQ pin.

[0072] Example 13. The method of Example 9, wherein the DIMM can be an RDIMM, an LPDIMM, an LRDIMM, an FB-DIMM, a UDIMM, or a SODIMM.

[0073] Example 14. As the method of Example 9, the memory device may include a non-volatile memory or a volatile memory.

[0074] Example 15. In the method of Example 14, the volatile memory may be a DRAM.

[0075] Example 16. As described in Example 14, the non-volatile memory can be a three-dimensional cross-point memory, a memory using a chalcogenide phase change material, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level PCM, a resistive memory, an Austrian memory, a nanowire memory, FeTRAM, an MRAM memory combined with a memristor technology, or an STT-MRAM.

[0076] Example 17. Example at least one machine-readable medium may include a plurality of instructions, which in response to being executed by a system may cause the system to perform the method according to any one of Examples 9 to 16.

[0077] Example 18. An example device may include components for performing the method of any one of Examples 9 to 16.

[0078] Example 19. An example apparatus may include circuitry of a memory device on a first side of a DIMM, the circuitry including logic, at least a portion of which may be hardware, the logic may receive a command / address signal. The logic may also determine, based on shorting pins of the memory device, whether a command / address logic indicated by the command / address signal has been inverted. The logic may also interpret the command / address logic indicated by the command / address signal based on the determination.

[0079] Example 20. The apparatus of Example 19, the logic may determine that the command / address signal indicates that the command / address logic has been inverted based on the shorting pin being connected to a power pin of the target memory device.

[0080] Example 21. In the device of Example 20, the power pin may be a VDDQ pin.

[0081] Example 22. The device of Example 19, wherein the command / address logic indicated by the command / address signal can be inverted by circuitry of a register buffer of the DIMM.

[0082] Example 23. The apparatus of Example 19, wherein the DIMM can be an RDIMM, an LPDIMM, an LRDIMM, an FB-DIMM, a UDIMM, or a SODIMM.

[0083] Example 24. In the apparatus of Example 19, the memory device may include a non-volatile memory or a volatile memory.

[0084] Example 25. In the device of Example 24, the volatile memory may be DRAM.

[0085] Example 26. In the device of Example 24, the non-volatile memory may be a three-dimensional cross-point memory, a memory using a chalcogenide phase change material, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level PCM, a resistive memory, an Austrian memory, a nanowire memory, a FeTRAM, an MRAM memory combined with a memristor technology, or an STT-MRAM.

[0086] Example 27. An example method may include receiving a command / address signal by a target memory device on a DIMM. The method may also include determining whether a command / address logic indicated by the command / address signal has been inverted based on shorting pins of the memory device. The method may also include interpreting the command / address logic indicated by the command / address signal based on the determination.

[0087] Example 28. The method of Example 27 may further include determining that the command / address signal indicates that the command / address logic has been inverted based on the shorting pin being connected to a power pin of the target memory device.

[0088] Example 29. The method of Example 28, wherein the power pin may be a VDDQ pin.

[0089] Example 30. As the method of Example 27, the command / address logic indicated by the command / address signal may have been inverted by circuitry of a register buffer of the DIMM.

[0090] Example 31. The method of Example 27, wherein the DIMM can be an RDIMM, an LPDIMM, an LRDIMM, an FB-DIMM, a UDIMM, or a SODIMM.

[0091] Example 32. As the method of Example 27, the memory device may include a non-volatile memory or a volatile memory.

[0092] Example 33. As described in Example 32, the volatile memory can be DRAM.

[0093] Example 34. As described in the method of Example 32, the non-volatile memory can be a three-dimensional cross-point memory, a memory using a chalcogenide phase change material, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level PCM, a resistive memory, an Austrian memory, a nanowire memory, FeTRAM, an MRAM memory combined with a memristor technology, or an STT-MRAM.

[0094] Example 35. Example at least one machine-readable medium may include a plurality of instructions, which in response to being executed by a system may cause the system to perform a method according to any one of Examples 27 to 34.

[0095] Example 36. An example device may include components for performing the method of any one of Examples 27 to 34.

[0096] Example 37. An example system may include a DIMM including one or more first memory devices on a first side and one or more second memory devices on a second side. The system may also include a memory device from among the one or more first memory devices, the memory device having a first shorting pin and including logic, at least a portion of which may be hardware. For these examples, the logic may receive a first command / address signal indicating a first command / address targeted to the memory device. The logic may also determine whether the first shorting pin is connected to a power pin. The logic may also mirror the first command / address targeted to the memory device based on the determination, such that the first command / address indicated in the first command / address signal is a mirror of a second command / address to a memory device from among the one or more second memory devices on the second side of the DIMM.

[0097] Example 38. As described in Example 37, the logic for mirroring the first command / address to the memory device from the first one or more memory devices may include logic for swapping corresponding even-numbered commands / addresses to the memory device from the first one or more memory devices with corresponding next higher odd-numbered commands / addresses to the memory device from the first one or more memory devices.

[0098] Example 39. In the system of Example 37, the power pin may be a VDDQ pin.

[0099] Example 40. In the system of Example 37, the memory device from among the one or more first memory devices can have a second shorting pin. For these examples, the memory device can also include logic that can receive a second command / address signal and interpret the command / address logic indicated by the second command / address signal based on the second shorting pin being connected to a power pin that is the same as or different from the power pin to which the first shorting pin is connected, such that the command / address logic indicated by the second command / address signal is interpreted as being inverted.

[0100] Example 41. As the system of Example 40, the power pin that is the same as or different from the power pin to which the first shorting pin is connected may be the same as or different from the VDDQ pin.

[0101] Example 42. As in the system of Example 40, the command / address logic indicated by the second command / address signal may have been inverted by circuitry of a register buffer of the DIMM.

[0102] Example 43. The system of Example 37, wherein the DIMM can be an RDIMM, an LPDIMM, an LRDIMM, an FB-DIMM, a UDIMM, or a SODIMM.

[0103] Example 44. In the system of Example 37, the memory device may include a non-volatile memory or a volatile memory.

[0104] Example 45. In the system of Example 44, the volatile memory may be DRAM.

[0105] Example 46. In the system of Example 44, the non-volatile memory may be a three-dimensional cross-point memory, a memory using a chalcogenide phase change material, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level PCM, a resistive memory, an Austrian memory, a nanowire memory, a FeTRAM, an MRAM memory combined with a memristor technology, or an STT-MRAM.

[0106] It is emphasized that the abstract of the present disclosure is provided to comply with 37 CFR section 1.72 (b), which requires an abstract that will allow the reader to quickly determine the nature of the technical disclosure. It is advocated with the following understanding: it will not be used to interpret or limit the scope or meaning of the example. In addition, in the above detailed description, it can be seen that various features are gathered together in a single example for the purpose of simplifying the present disclosure. This method disclosed should not be interpreted as reflecting the intention that the claimed example requires more features than the features explicitly described in each example. Instead, as reflected in the accompanying examples, the subject matter of the invention lies in less than all the features of a single disclosed example. Therefore, the following examples are thus combined in the detailed description, wherein each example is independently used as a separate example. In the accompanying examples, the terms "including" and "wherein" are used as common English synonyms of the corresponding terms "including" and "wherein", respectively. In addition, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0107] Although the subject matter is described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the accompanying examples is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A memory device, comprising: Short the pins; Power pin; as well as A circuit for: receiving a command / address signal indicative of a first command / address directed to the memory device; determining to mirror the first command / address indicated in the command / address signal based on the shorting pin connected to the power pin; as well as The first command / address is mirrored such that the first command / address indicated in the command / address signal is a mirror image of a second command / address directed to a second memory device.

2. The memory device of claim 1, the circuitry for mirroring the first commands / addresses comprising circuitry for swapping even-numbered commands / addresses directed to the memory device with corresponding next higher odd-numbered commands / addresses directed to the second memory device.

3. The memory device of claim 1, the power pin comprising an output storage drain power voltage (VDDQ) pin.

4. The memory device of claim 1, comprising the memory device located on a first side of a dual in-line memory module (DIMM) and the second memory device located on a second side of the DIMM.

5. The memory device of claim 4, the DIMM comprising a registered DIMM (RDIMM), a low power DIMM (LPDIMM), a load reduced DIMM (LRDIMM), a fully buffered DIMM (FB-DIMM), an unbuffered DIMM (UDIMM), or a small form factor DIMM (SODIMM).

6. The memory device of claim 1, including the memory device, the memory device will include non-volatile memory or volatile memory.

7. The memory device of claim 6, the volatile memory comprising dynamic random access memory (DRAM).

8. The memory device of claim 6, wherein the non-volatile memory comprises a three-dimensional cross-point memory, a memory using a chalcogenide phase change material, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level phase change memory (PCM), a resistive memory, an Austrian memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), a magnetoresistive random access memory (MRAM) memory combined with a memristor technology, or a spin-transfer torque MRAM (STT-MRAM).

9. A memory device on a dual in-line memory module (DIMM), the memory device comprising: Short the pins; Power pin; as well as A circuit for: Receive command / address signal; determining, based on the shorting pin being connected to the power pin, that a command / address logic level indicated by the command / address signal has been inverted; and The command / address logic level indicated by the command / address signal is interpreted based on the determination.

10. The memory device of claim 9, the power pin comprising an output storage drain power voltage (VDDQ) pin.

11. The memory device of claim 9, the shorting pin comprising a command & address inversion (CAI) pin.

12. The memory device of claim 9, including the command / address logic level indicated by the command / address signal being inverted by circuitry of a register buffer of the DIMM.

13. The memory device of claim 9, the DIMM comprising a registered DIMM (RDIMM), a low power DIMM (LPDIMM), a load reduced DIMM (LRDIMM), a fully buffered DIMM (FB-DIMM), an unbuffered DIMM (UDIMM), or a small form factor DIMM (SODIMM).

14. The memory device of claim 9, comprising the memory device, the memory device will include a non-volatile memory or a volatile memory, the volatile memory includes a dynamic random access memory (DRAM), the non-volatile memory includes a three-dimensional cross-point memory, a memory using a chalcogenide phase change material, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level phase change memory (PCM), a resistive memory, an Austrian memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), a magnetoresistive random access memory (MRAM) memory combined with a memristor technology, or a spin-transfer torque MRAM (STT-MRAM).

15. A system for operating a memory device, comprising: a dual in-line memory module (DIMM) comprising one or more first memory devices on a first side and one or more second memory devices on a second side; as well as a memory device from among the one or more first memory devices, the memory device having a first shorting pin and a power pin, the memory device comprising a circuit for: receiving a first command / address signal indicating a first command / address directed to the memory device; determining to mirror the first command / address indicated in the first command / address signal based on the first shorting pin connected to the power pin; as well as mirroring the first command / address targeted to the memory device such that the first command / address indicated in the first command / address signal is a mirror of a second command / address to a second memory device from among the one or more second memory devices on the second side of the DIMM, wherein the circuitry for mirroring the first command / address includes circuitry for swapping a corresponding even-numbered command / address to the memory device with a corresponding next higher odd-numbered command / address to the second memory device, Also included is a memory device having a second shorting pin, the circuit being configured to: receiving a second command / address signal; and The command / address logic level indicated by the second command / address signal is interpreted based on the second shorting pin being connected to a power pin that is the same as or different from a power pin of the memory device to which the first shorting pin is connected, so that the command / address logic level indicated by the second command / address signal is interpreted as being inverted.

16. The system for operating a memory device of claim 15, the power pin comprising an output storage drain power voltage (VDDQ) pin.

17. The system for operating a memory device of claim 15, the power pin that is the same as or different from the power pin to which the first shorting pin is connected comprises a same as or different output storage drain power voltage (VDDQ) pin of the memory device.

18. The system for operating a memory device of claim 15, comprising the command / address logic level indicated by the second command / address signal being inverted by circuitry of a register buffer of the DIMM.

19. The system for operating a memory device of claim 15, wherein the DIMM comprises a registered DIMM (RDIMM), a low power DIMM (LPDIMM), a load reduced DIMM (LRDIMM), a fully buffered DIMM (FB-DIMM), an unbuffered DIMM (UDIMM), or a small form factor DIMM (SODIMM).

20. The system for operating a memory device as described in claim 15, including the memory device, the memory device will include non-volatile memory or volatile memory, the volatile memory includes dynamic random access memory (DRAM), the non-volatile memory includes three-dimensional cross-point memory, memory using chalcogenide phase change material, multi-threshold level NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, Austrian memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory combined with memristor technology, or spin transfer torque MRAM (STT-MRAM).

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