Electroluminescent display device

Abstract

An electroluminescent display device includes: a display panel including a display area and a non-display area surrounding the display area, the display area including a plurality of pixel arrangement areas and a plurality of scanning circuit areas between the plurality of pixel arrangement areas; a scanning drive circuit formed in the plurality of scanning circuit areas; and a clock signal line for transmitting a clock signal and a first voltage line and a second voltage line located on both sides of the clock signal line, the clock signal line and the first voltage line and the second voltage line being located in the scanning circuit area, wherein the first voltage line transmits a low potential driving voltage, and the low potential driving voltage is provided to a cathode corresponding to the display area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0136733 filed in Korea on October 21, 2020, the entire contents of which are hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] The present disclosure relates to an electroluminescent display device. Background Art

[0004] With the advent of the information society, the demand for various types of display devices has increased. Recently, various flat display devices such as electroluminescent display devices, including organic light emitting diode (OLED) display devices, quantum dot light emitting diode (QLED) display devices, and micro light emitting diode (micro LED) display devices have been used.

[0005] Electroluminescent display devices are widely used because they have advantages of small size, light weight, thin profile, and low power driving.

[0006] Recently, an electroluminescent display device uses a gate in panel (GIP) type, and a gate driving circuit is formed at both sides of a display area.

[0007] In this case, the width of the bezel of the display device increases. Summary of the invention

[0008] Accordingly, the present disclosure is directed to an electroluminescent display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0009] One advantage of the present disclosure is to provide an electroluminescent display device capable of reducing the width of a frame and achieving a narrow frame.

[0010] Other features and advantages of the present disclosure will be described in the following description, and part will become obvious from the description, or can be learned through the practice of the present disclosure. These and other advantages of the present disclosure will be realized and obtained through the structures particularly pointed out in the present disclosure.

[0011] To achieve these and other advantages and in accordance with the purposes of the present disclosure, as implemented and broadly described herein, an electroluminescent display device includes: a display panel, which includes a display area and a non-display area surrounding the display area, the display area including a plurality of pixel arrangement areas and a plurality of scanning circuit areas between the plurality of pixel arrangement areas; a scanning drive circuit, which is formed in the plurality of scanning circuit areas; and a clock signal line for transmitting a clock signal and a first voltage line and a second voltage line located on both sides of the clock signal line, the clock signal line and the first voltage line and the second voltage line being located in the scanning circuit area, wherein the first voltage line transmits a low potential driving voltage, which is provided to a cathode corresponding to the display area.

[0012] On the other hand, an electroluminescent display device includes: a display panel, which includes a display area and a non-display area surrounding the display area, the display area includes a plurality of pixel arrangement areas and a plurality of scanning circuit areas between the plurality of pixel arrangement areas; a scanning drive circuit, which is formed in the plurality of scanning circuit areas; and a clock signal line for transmitting a clock signal and a first voltage line and a second voltage line located on both sides of the clock signal line, the clock signal line and the first voltage line and the second voltage line being located in the scanning circuit area, wherein the first voltage line and the second voltage line transmit voltages of different direct current (DC) waveforms.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0015] Figure 1 is a view showing an electroluminescent display device according to an embodiment of the present disclosure;

[0016] Figure 2 is a view showing a conceptual configuration of a gate signal generating circuit of a scan driving circuit according to an embodiment of the present disclosure;

[0017] Figure 3 is a view showing a conceptual configuration of an emission signal generating circuit of a scan driving circuit according to an embodiment of the present disclosure;

[0018] Figure 4 is a view schematically showing an example of the arrangement of a gate signal generating circuit and an emission signal generating circuit of a scan driving circuit according to an embodiment of the present disclosure;

[0019] Figure 5 is a view schematically showing a configuration of a pixel block according to an embodiment of the present disclosure;

[0020] Figure 6 is a view schematically showing a signal line formed along a scanning circuit region where a gate signal generating circuit is located according to an embodiment of the present disclosure;

[0021] Figure 7 is a view schematically showing a signal line formed along a scanning circuit region where a transmission signal generating circuit is located according to an embodiment of the present disclosure;

[0022] Figure 8 is a view schematically showing an example of a cathode of a display panel and a line transmitting a low potential driving voltage according to an embodiment of the present disclosure;

[0023] Fig. 9 is a view showing an example of the structure of pixels and a common control circuit block in a pixel block according to an embodiment of the present disclosure;

[0024] Fig.10 Yes Drive Fig. 9 Waveform diagrams of signals of pixels and common control circuit blocks;

[0025] Fig.11 is a view schematically showing an example of the arrangement of a gate signal generating circuit of a scan driving circuit according to another embodiment of the present disclosure;

[0026] Fig.12 is a view schematically showing an example of the arrangement of an emission signal generating circuit of a scan driving circuit according to another embodiment of the present disclosure; and

[0027] Fig.13 is a view schematically showing a display panel of an electroluminescent display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The same reference numerals may be used throughout the drawings to refer to the same or like parts.

[0029] Figure 1 is a view showing an electroluminescent display device according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The electroluminescent display device 10 may include a display panel 100 in which a plurality of pixels are arranged in a matrix form and a panel driving circuit for driving the display panel 100 .

[0031] The panel driving circuit driving the display panel 100 may include a data driving circuit 200 , a scan driving circuit 500 , a timing control circuit 300 , and a power supply circuit 400 .

[0032] Regarding the display panel 100 , the display panel 100 may include a display area (or active area) AA in which pixel areas are arranged and an image is displayed, and a non-display area (or non-active area) NA located outside the display area AA and surrounding the display area AA.

[0033] Each pixel in the display area AA may include a plurality of sub-pixels emitting different colors. For example, each pixel may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel arranged adjacently along each row line direction. Pixels and sub-pixels are described in detail below.

[0034] Various signal lines that transmit drive signals to drive pixels (or sub-pixels) can be formed on the substrate in the display panel 100. In this regard, for example, each of the multiple data lines that transmit data signals (or data voltages) as image signals can extend along the column line direction (or vertical direction or first direction) and be connected to the sub-pixels on the corresponding column lines. In addition, each of the multiple gate lines that transmit gate signals can extend along the row line direction (or horizontal direction or second direction) and be connected to the sub-pixels on the corresponding row lines. In addition, each of the multiple emission lines that are parallel to the gate lines and extend along the row direction can be connected to the sub-pixels on the corresponding column lines. These signal lines of the display panel 100 are described in detail below.

[0035] The timing control circuit 300 may control the driving timing of the data driving circuit 200 and the scan driving circuit 500 .

[0036] In this regard, the timing control circuit 300 may process the digital data signal Da input from the external system according to the optical characteristics of the display panel 100 and provide a processed data signal.

[0037] The timing control circuit 300 can generate a data control signal (DCS) for controlling the driving timing of the data driving circuit 200 and a scan control signal (SCS) for controlling the driving timing of the scan driving circuit 500 based on timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and a data enable signal input from an external system.

[0038] The power supply circuit 400 may provide various voltages for driving components of the electroluminescent display device 10. For example, the power supply circuit 400 may output a first logic voltage (or a low logic voltage) VGL and a second logic voltage (or a high logic voltage) VGH for driving the scan driving circuit 500 and a first power voltage (or a low potential driving voltage) VSS and a second power voltage (or a high potential driving voltage) VDD for driving the display panel 100.

[0039] The data driving circuit 200 may drive the data lines. In this regard, the data driving circuit 200 may convert the digital data signal Da into an analog data signal (ie, a data voltage) based on the data control signal DCS and provide the analog data signal to the corresponding data line.

[0040] The data driving circuit 200 may be configured in an IC type. In this regard, the data driving circuit 200 may include at least one driving IC. In the present embodiment, the data driving circuit 200 may be configured with a plurality of driving ICs. Each driving IC may be mounted on a flexible circuit film 210 and connected to the display panel 100. Alternatively, the driving IC may be directly mounted on a substrate of the display panel 100, such as in a COG type IC configuration.

[0041] In the flexible circuit film 210 , lines for transmitting the control signal SCS and the voltages VGL and VGH driving the scan driving circuit 500 and the voltages VSS and VDD driving the display panel 100 to the display panel 100 may be formed at a portion outside the driving IC.

[0042] The scanning driving circuit 500 can output corresponding scanning signals to the gate lines and emission lines connected thereto, and drive the gate lines and emission lines. In this regard, the scanning driving circuit 500 can generate scanning signals such as gate signals and emission signals based on the scanning control signal SCS, and provide these signals to the corresponding signal lines. In this regard, the scanning driving circuit 500 can output the gate signal to the gate line in a sequential line scanning manner, and output the emission signal to the emission line in a sequential line scanning manner.

[0043] The scan driving circuit 500 may be directly formed at the array substrate of the display panel 100 in a GIP type.

[0044] In the present embodiment, the scan driving circuit 500 may not be formed in the non-display area NA, but may be formed to be dispersed in the display area AA.

[0045] In this regard, the display area AA may include a plurality of pixel arrangement areas DA in which pixels are arranged, and a plurality of scan circuit areas SA located between the plurality of pixel arrangement areas DA and forming the scan driving circuit 500 .

[0046] A plurality of pixels arranged in a matrix may be located in each pixel arrangement area DA, and the pixel arrangement area DA may substantially generate an image. The pixel arrangement areas DA may extend parallel to each other in a column line direction and may be spaced apart from each other in a row line direction with a scanning circuit area SA therebetween.

[0047] Each scanning circuit area SA may be located between adjacent pixel arrangement areas DA, and a partial circuit constituting the scanning driving circuit 500 may be formed at each scanning circuit area SA. The scanning circuit areas SA may extend parallel to each other in a column line direction, and may be spaced apart from each other in a row line direction with the pixel arrangement areas DA therebetween.

[0048] As described above, the display area AA may be configured such that the scanning circuit area SA is dispersed inside the display area AA and the pixel arrangement area DA as an actual image display area is divided.

[0049] The plurality of pixel arrangement areas DA arranged in the display area AA may be formed to have substantially the same width in the row line direction. In this regard, the plurality of pixel arrangement areas DA may have the same number of pixels arranged along the row line direction.

[0050] The plurality of scanning circuit areas SA arranged in the display area AA may be formed to have substantially the same width in the row line direction. In addition, the scanning circuit areas SA may have the same interval (or pitch), and in this case, the plurality of pixel arrangement areas DA have substantially the same width.

[0051] As described above, in this embodiment, the scan driving circuit 500 generating the scan signal may be formed in the display area AA. Therefore, since the scan driving circuit 500 does not need to be formed in the non-display area NA, the width of the non-display area NA may be reduced and a narrow frame may be effectively realized.

[0052] In addition, the scan drive circuit 500 can be configured so that a plurality of scan signal generating circuits can be formed above a plurality of scan circuit regions SA, each of which is a unit circuit for generating a scan signal. For example, for m scan circuit regions SA defined in the display area AA, k scan signal generating circuits can be formed (where k is a natural number greater than 1 and less than m). A plurality of scan signal generating circuits can be spaced apart from each other over the entire display area AA. Therefore, the deviation of the scan signal due to the position in the row direction of the display area AA can be significantly reduced, thereby improving the uniformity of the driving characteristics over the entire display area AA and improving the display quality.

[0053] The configuration of the scan driving circuit 500 is described in detail.

[0054] Figure 2 is a view showing a conceptual configuration of a gate signal generating circuit of a scan driving circuit according to an embodiment of the present disclosure, and Figure 3 is a view showing a conceptual configuration of an emission signal generating circuit of a scan driving circuit according to an embodiment of the present disclosure.

[0055] Reference Figures 1 to 3 , the scan driving circuit 500 may include a gate signal generating circuit GC as a scan signal generating circuit generating a gate signal Vg and an emission signal generating circuit EC as a scan signal generating circuit generating an emission signal Vem.

[0056] Reference Figure 2 , the gate signal generating circuit GC may include a plurality of stages STGg that are cascade-connected to each other and sequentially generate gate signals Vg to corresponding row lines. For the purpose of illustration, stages (STGg[1], STGg[2], STGg[n-1], and STGg[n]) corresponding to some row lines (1st line, 2nd line, (n-1)th line, and nth line) are shown.

[0057] Although not shown in the drawings, each level STGg may include a plurality of transistors and at least one capacitor to output a gate signal Vg as a scan signal. For example, each level STGg may include a Q transistor and a Qb transistor connected in series to each other and a control circuit for controlling the switching operation of the Q transistor and the Qb transistor, wherein an output node (or output terminal) is connected to a corresponding gate line GL and is located between the Q transistor and the Qb transistor. The Q transistor may output a gate signal Vg of a conduction level to the gate line GL, and the Qb transistor may output a gate signal Vg of a cutoff level to the gate line GL. For example, in the case where the switching transistor of the sub-pixel connected to the gate line GL is a P-type transistor, the Q transistor may output a low-level gate signal Vg and the Qb transistor may output a high-level gate signal Vg.

[0058] Each stage STGg can receive, for example, a gate signal Vg output from the previous stage and use it as a start signal. For example, stage STGg[2] can receive a gate signal Vg[1] output from stage STGg[1] and use it as a start signal, stage STGg[n] can receive a gate signal Vg[n-1] output from stage STGg[n-1] and use it as a start signal, and so on. Stage STGg[1] of the first row line can receive an additional start signal GVST.

[0059] The stage STGg may receive clock signals having different phases from each other, for example, the first and second gate clock signals GCLK and GCLKb, and the first and second logic voltages VGL and VGH having opposite phases to each other.

[0060] The stage STGg can output the corresponding gate clock signal as the gate signal Vg through the Q transistor during the horizontal period of the corresponding row line. For example, the first stage STGg[1] can output the first gate clock signal GCLK as the gate signal Vg[1] through its Q transistor, and the second stage STGg[2] can output the second gate clock signal GCLKb as the gate signal Vg[2] through its Q transistor.

[0061] The stage STGg can output the first logic voltage VGL or the second logic voltage VGH of the off-level voltage as the gate signal Vg through the Qb transistor after the horizontal period. For example, in the case where the switching transistor of the sub-pixel connected to the gate line GL is a P-type transistor, the second logic voltage VGH which is a high logic voltage can be output as the gate signal Vg.

[0062] As described above, with respect to the gate signal generating circuit GC that generates the gate signal Vg on each row line, a plurality of gate signal generating circuits GC may be arranged in the display area AA. In other words, a plurality of gate signal generating circuits GC may be arranged in the display area AA, and for this purpose, a scanning circuit area SA formed with a plurality of gate signal generating circuits GC may be located in the display area AA.

[0063] Reference Figure 3 , the emission signal generating circuit EC can be configured similarly to the gate signal generating circuit GC. The emission signal generating circuit EC may include a plurality of stages STGe connected in cascade to each other and sequentially generating emission signals Vem to corresponding row lines. For the purpose of illustration, stages (STGe[1], STGe[2], STGe[n-1], and STGe[n]) corresponding to some row lines (1st line, 2nd line, (n-1)th line, and nth line) are shown.

[0064] Although not shown in the drawings, each level STGe may include a plurality of transistors and at least one capacitor to output a gate signal Vem as a scan signal. For example, each level STGe may include a Q transistor and a Qb transistor connected in series to each other and a control circuit for controlling the switching operation of the Q transistor and the Qb transistor, wherein the output node (or output terminal) is connected to the corresponding emission line EL and is located between the Q transistor and the Qb transistor. The Q transistor may output an emission signal Vem of a conduction level to the emission line EL, and the Qb transistor may output an emission signal Vem of a cutoff level to the emission line EL. For example, in the case where the switching transistor of the sub-pixel connected to the emission line EL is a P-type transistor, the Q transistor may output a low-level emission signal Vem, and the Qb transistor may output a high-level emission signal Vem.

[0065] Each stage STGe can receive, for example, an emission signal Vem output from the previous stage and use it as a start signal. For example, stage STGe[2] can receive an emission signal Vem[1] output from stage STGe[1] and use it as a start signal, stage STGe[n] can receive an emission signal Vem[n-1] output from stage STGe[n-1] and use it as a start signal, and so on. Stage STGe[1] of the first row line can receive an additional start signal EVST.

[0066] The stage STGe may receive clock signals having different phases from each other, for example, first and second emission clock signals ECLK and ECLKb, and first and second logic voltages VGL and VGH having opposite phases to each other.

[0067] The stage STGe may output one of the first logic voltage VGL and the second logic voltage VGH of the on-level voltage as the emission signal Vem through the Q transistor during the emission period of the corresponding row line, and the stage STGe may output the other of the first logic voltage VGL and the second logic voltage VGH of the off-level voltage as the emission signal Vem through the Qb transistor after the emission period (i.e., during the non-emission period). For example, in the case where the switching transistor of the sub-pixel connected to the emission line EL is a P-type transistor, the first logic voltage VGL of the low logic voltage may be output through the Q transistor during the emission period, and the second logic voltage VGH of the high logic voltage may be output through the Qb transistor during the non-emission period.

[0068] As described above, with respect to the emission signal generating circuit EC that generates the emission signal Vem on each row line, a plurality of emission signal generating circuits EC may be arranged in the display area AA. In other words, a plurality of emission signal generating circuits EC may be arranged in the display area AA, and for this purpose, a scanning circuit area SA formed with a plurality of emission signal generating circuits EC may be located in the display area AA.

[0069] The arrangement of the gate signal generating circuit GC and the emission signal generating circuit EC in the display area AA is described below.

[0070] Figure 4 is a view schematically showing an example of the arrangement of a gate signal generating circuit and an emission signal generating circuit of a scan driving circuit according to an embodiment of the present disclosure, and Figure 5 is a view schematically showing a configuration of a pixel block according to an embodiment of the present disclosure.

[0071] exist Figure 4 In the embodiment, for the purpose of illustration, one gate signal generating circuit GC and one emission signal generating circuit EC arranged in the display area AA are shown. Figure 4 , and a plurality of gate signal generating circuits GC and a plurality of emission signal generating circuits EC may be formed in the display area AA.

[0072] Reference Figures 1 to 4 , each gate signal generating circuit GC may be formed, for example, at an adjacent scanning circuit area SA, and each emission signal generating circuit EC may be formed, for example, at an adjacent scanning circuit area SA.

[0073] In this embodiment, as Figure 4 In the example shown in FIG. 1 , the gate signal generating circuit GC is formed at two adjacent scanning circuit areas SA, the emission signal generating circuit EC is formed at two adjacent scanning circuit areas SA, and the gate signal generating circuit GC and the emission signal generating circuit EC are formed at different scanning circuit areas SA.

[0074] The gate signal generating circuit GC may be formed in a structure in which the gate signal generating circuit GC is divided into two scanning circuit areas SA. For example, the stage STGg of the gate signal generating circuit GC may be configured with a first circuit portion Dg1 and a second circuit portion Dg2 separately formed in the two scanning circuit areas SA. In the present embodiment, a configuration in which the output terminal of the stage STGg is located in the first circuit portion Dg1 and the first circuit portion Dg1 outputs the gate signal Vg to the corresponding gate line GL is shown by way of example.

[0075] Similar to the gate signal generating circuit GC, the emission signal generating circuit EC may be formed in a structure in which the emission signal generating circuit EC is divided into two scanning circuit areas SA. For example, the stage STGe of the emission signal generating circuit EC may be configured with a first circuit portion De1 and a second circuit portion De2 separately formed in the two scanning circuit areas SA. In the present embodiment, a configuration in which the output end of the stage STGe is located in the first circuit portion De1 and the first circuit portion De1 outputs an emission signal Ve to the corresponding emission line EL is shown by way of example.

[0076] In the pixel arrangement area DA, the pixel block PB may be located on each of the plurality of row lines. In other words, the plurality of pixel blocks PB may be arranged along the column line direction.

[0077] For pixel block PB, refer to Figure 5 , a plurality of pixels P arranged along the row direction may be formed in the pixel block PB of each row line. In the pixel block PB, the common control circuit block C may be located between adjacent pixels P. For example, in the pixel block PB, i pixels P may be arranged, and (i-1) common control circuit blocks C inserted between adjacent pixels P may be arranged.

[0078] In this embodiment, for the purpose of explanation, the arrangement of two pixels P and one common control circuit block C between the two pixels P is shown by way of example.

[0079] Each pixel P may include a plurality of sub-pixels SP adjacent to each other in a row direction and having different colors. For example, the plurality of sub-pixels SP may include a red first sub-pixel SP1, a green second sub-pixel SP2, and a blue third sub-pixel SP3.

[0080] The common control circuit block C of the pixel block PB may be commonly connected to the first to third subpixels SP1 to SP3 of the pixels P adjacent to the common control circuit block C, and may commonly control storage capacitors of the subpixels SP1 to SP3.

[0081] like Figure 5 As shown, in the case where two pixels P and one common control circuit block C are located in the pixel block PB, the common control circuit block C may be commonly connected to all two pixels P located on both sides of the common control circuit block C (i.e., all first sub-pixels SP1 to third sub-pixels SP3 of the two pixels P). In the case where 3 or more pixels P and common control circuit blocks C whose number is one less than the number of pixels P are located in the pixel block PB, one of the common control circuit blocks C may be connected to one of the pixels P, and each of the other common control circuit blocks C may be connected to the pixels P at both sides of each of the other common control circuit blocks C.

[0082] In the pixel block PB configured as described above, the pixels P may be located at the two outermost sides (ie, the left outermost side and the right outermost side) of the pixel block PB.

[0083] The scan circuit area SA may be an area in which the common control circuit area C may be placed.

[0084] In this regard, regarding the arrangement on each row line, the pixel blocks PB and the scanning circuit areas SA are arranged alternately, and, in the pixel blocks PB, the pixels P and the common control circuit blocks C are arranged alternately and the pixels P are arranged at both sides of the pixel blocks PB. Therefore, like the common control circuit blocks C, the scanning circuit area SA is located between two adjacent pixels P.

[0085] Therefore, the common control circuit block C may be formed to have a width substantially equal to that of the scan circuit area SA.

[0086] Therefore, in the present embodiment, the area that can be allocated as the area of ​​the common control circuit block C can be used for the scanning circuit area SA, so that there is no need to prepare an additional area for the scanning driving circuit 500 in the display area AA. In addition, the regularity of alternately arranging the pixels P and the driving circuit (the common control circuit block C or the scanning driving circuit 500) driving the pixels in the display area AA can be substantially maintained, so that the display quality is not reduced, but can be fully realized.

[0087] In the present embodiment, a voltage line for transmitting the first power voltage VSS, that is, a low potential driving voltage VSS, which is a driving voltage for driving a light emitting diode included in a sub-pixel SP and is applied to a cathode of the light emitting diode, may be located in the scanning circuit area SA. Therefore, there is no need to form a wide transmission line for transmitting the low potential driving voltage VSS in the non-display area NA located on both sides of the display area AA, and thus the width of the non-display area NA may be reduced and a narrow frame may be effectively achieved.

[0088] It is described that a voltage line transmitting the low potential driving voltage VSS is embedded in the display area AA.

[0089] Figure 6 is a view schematically showing a signal line formed along a scanning circuit region where a gate signal generating circuit is located according to an embodiment of the present disclosure. Figure 7 is a view schematically showing a signal line formed along a scanning circuit region where a transmission signal generating circuit is located according to an embodiment of the present disclosure.

[0090] Reference Figure 6 and Figure 7 , in the scanning circuit area SA, a plurality of transmission lines that transmit signals along a column line direction on which the scanning circuit area SA extends may extend.

[0091] In this regard, for example, Figure 6 As shown, in each scanning circuit area SA where the gate signal generating circuit GC is located, a clock signal line CL for transmitting the gate clock signal GCLK or GCLKb, a first voltage line PL1 for transmitting the low-potential driving voltage VSS, and a second voltage line PL2 for transmitting the logic voltage VGL or VGH can be arranged.

[0092] The clock signal lines CL that transmit the first gate clock signal GCLK and the second gate clock signal GCLKb, respectively, may be located in different scanning circuit areas SA. For example, the clock signal line CL that transmits the first gate clock signal GCLK may be located in the scanning circuit area SA in which the first circuit portion Dg1 of the stage STGg may be formed, and the clock signal line CL that transmits the second gate clock signal GCLKb may be located in the scanning circuit area SA in which the second circuit portion Dg2 of the stage STGg may be formed.

[0093] In a similar manner, the second voltage line PL2 that transmits the first logic voltage VGL and the second logic voltage VGH, respectively, may be located in different scanning circuit areas SA. For example, the second voltage line PL2 that transmits the first logic voltage VGL may be located in the scanning circuit area SA in which the first circuit portion Dg1 of the stage STGg may be formed, and the second voltage line PL2 that transmits the second logic voltage VGH may be located in the scanning circuit area SA in which the second circuit portion Dg2 of the stage STGg may be formed.

[0094] The first voltage line PL1 transmitting the low potential driving voltage VSS may be located in the scan circuit area SA where the first circuit portion Dg1 of the stage STGg may be formed and in the scan circuit area SA where the second circuit portion Dg2 of the stage STGg may be formed.

[0095] In the present embodiment, regarding the arrangement of the signal transmission line of each scan circuit area SA, the clock signal line CL may be configured to be located between the first voltage line PL1 and the second voltage line PL2 .

[0096] In this regard, the gate clock signal GCLK or GCLKb transmitted along the clock signal line CL is a signal having a pulse waveform with a periodic phase change, that is, a signal having an alternating current (AC) waveform. The AC waveform signal interferes with the driving of the sub-pixels SP in the pixel blocks PB adjacent to both sides of the scanning circuit area SA, so that the display quality may be reduced.

[0097] In the present embodiment, at each of the two sides of the clock signal line CL, there is placed a first voltage line PL1 transmitting a low potential driving voltage VSS as a voltage signal having a DC waveform, and a second voltage line PL2 transmitting a logic voltage VGL or VGH as a voltage signal having a DC waveform. In other words, the clock signal line CL is located between the first voltage line PL1 and the second voltage line PL2.

[0098] Therefore, the first voltage line PL1 to which the low potential driving voltage VSS of the DC waveform is applied can be used to block the interference of the gate clock signal GCLK or GCLKb to the sub-pixel SP in the pixel block PB placed adjacent to the first voltage line PL1. Similarly, the second voltage line PL2 to which the logic voltage VGL or VGH of the DC waveform is applied can be used to block the interference of the gate clock signal GCLK or GCLKb to the sub-pixel SP in the pixel block PB placed adjacent to the second voltage line PL2.

[0099] Therefore, the clock signal may be prevented from interfering with the driving of the sub-pixels SP in the pixel block PB adjacent to the scan circuit area SA, and thus the display quality may be ensured.

[0100] A transmission line TL for transmitting a signal between adjacent scanning circuit areas SA may be formed. Figure 6 As shown, in the case where the gate signal generating circuit GC is configured to be divided at adjacent scanning circuit areas SA, the first circuit portion Dg1 and the second circuit portion Dg2 of stage STGg may need to be connected to each other for signal transmission therebetween, and for this purpose, a transmission line TL may be formed.

[0101] In addition, depending on the design of the scan driving circuit 500, etc., it may be necessary to provide the first logic voltage VGL or the second logic voltage VGH to a circuit portion in another scanning circuit area SA that is different from the scanning circuit area SA where the second voltage line PL2 transmitting the first logic voltage VGL or the second logic voltage VGH is located, or to provide the first gate clock signal GCLK or the second gate clock signal GCLKb to a circuit portion in another scanning circuit area SA that is different from the scanning circuit area SA where the clock signal line CL transmitting the first gate clock signal GCLK or the second gate clock signal GCLKb is located. For this purpose, a transmission line TL can be used.

[0102] The transmission line TL may extend in parallel with the gate line GL along a row extending direction.

[0103] like Figure 7 As shown, each scanning circuit area SA where the emission signal generating circuit EC is located may be configured similarly to each scanning circuit area SA where the gate signal generating circuit GC is located.

[0104] In this regard, in each scanning circuit area SA where the emission signal generating circuit EC is located, a clock signal line CL transmitting the emission clock signal ECLK or ECLKb and a first voltage line PL1 transmitting the low potential driving voltage VSS and a second voltage line PL2 transmitting the logic voltage VGL or VGH can be arranged.

[0105] The clock signal lines CL that transmit the first emission clock signal ECLK and the second emission clock signal ECLKb, respectively, may be located in different scanning circuit areas SA. For example, the clock signal line CL that transmits the first emission clock signal ECLK may be located in the scanning circuit area SA where the first circuit portion De1 of the stage STGe may be formed, and the clock signal line CL that transmits the second emission clock signal ECLKb may be located in the scanning circuit area SA where the second circuit portion De2 of the stage STGe may be formed.

[0106] In a similar manner, the second voltage line PL2 that transmits the first logic voltage VGL and the second logic voltage VGH, respectively, may be located in different scanning circuit areas SA. For example, the second voltage line PL2 that transmits the first logic VGL may be located in the scanning circuit area SA that may form the first circuit portion De1 of the stage STGe, and the second voltage line PL2 that transmits the second logic voltage VGH may be located in the scanning circuit area SA that may form the second circuit portion De2 of the stage STGe.

[0107] The first voltage line PL1 transmitting the low potential driving voltage VSS may be located in the scan circuit area SA where the first circuit portion De1 of the stage STGe may be formed and in the scan circuit area SA where the second circuit portion De2 of the stage STGe may be formed.

[0108] In the present embodiment, regarding the arrangement of the signal transmission line of each scan circuit area SA, the clock signal line CL may be configured to be located between the first voltage line PL1 and the second voltage line PL2 .

[0109] In this regard, the emission clock signal ECLK or ECLKb transmitted along the clock signal line CL is a signal having a pulse waveform with a periodic phase change, that is, a signal having an AC waveform. The AC waveform signal interferes with the driving of the sub-pixels SP in the pixel blocks PB adjacent to both sides of the scanning circuit area SA, so that the display quality may be reduced.

[0110] In the present embodiment, at each of the two sides of the clock signal line CL, there is placed a first voltage line PL1 transmitting a low potential driving voltage VSS as a voltage signal having a DC waveform, and a second voltage line PL2 transmitting a logic voltage VGL or VGH as a voltage signal having a DC waveform. In other words, the clock signal line CL is located between the first voltage line PL1 and the second voltage line PL2.

[0111] Therefore, the first voltage line PL1 to which the low potential driving voltage VSS of the DC waveform is applied can be used to block the interference of the emission clock signal ECLK or ECLKb to the sub-pixel SP in the pixel block PB placed adjacent to the first voltage line PL1. Similarly, the second voltage line PL2 to which the logic voltage VGL or VGH of the DC waveform is applied can be used to block the interference of the emission clock signal ECLK or ECLKb to the sub-pixel SP in the pixel block PB placed adjacent to the second voltage line PL2.

[0112] Therefore, the clock signal may be prevented from interfering with the driving of the sub-pixels SP in the pixel block PB adjacent to the scan circuit area SA, and thus the display quality may be ensured.

[0113] A transmission line TL for transmitting a signal between adjacent scanning circuit areas SA may be formed. Figure 7 As shown, in the case where the emission signal generating circuit EC is configured to be divided at adjacent scanning circuit areas SA, the first circuit portion De1 and the second circuit portion De2 of the stage STGe may need to be connected to each other for signal transmission therebetween, and for this purpose, a transmission line TL may be formed.

[0114] In addition, depending on the design of the scan driving circuit 500, etc., it may be necessary to provide the first logic voltage VGL or the second logic voltage VGH to a circuit portion in another scanning circuit area SA that is different from the scanning circuit area SA where the second voltage line PL2 that transmits the first logic voltage VGL or the second logic voltage VGH is located, or to provide the first emission clock signal ECLK or the second emission clock signal ECLKb to a circuit portion in another scanning circuit area SA that is different from the scanning circuit area SA where the clock signal line CL that transmits the first emission clock signal ECLK or the second emission clock signal ECLKb is located. For this purpose, a transmission line TL can be used.

[0115] The transmission line TL may extend in parallel with the gate line GL along a row extending direction.

[0116] As described above, in the present embodiment, the voltage line PL1 for transmitting the low potential driving voltage VSS may be formed in the plurality of scanning circuit regions SA. Therefore, since it may not be necessary to form a wide width transmission line for transmitting the low potential driving voltage VSS in the non-display region NA located at both sides of the display region AA, the width of the non-display region NA may be reduced and a narrow frame may be effectively implemented.

[0117] This reference Figure 8 . Figure 8 is a view schematically illustrating an example of a cathode electrode of a display panel and a line transmitting a low potential driving voltage according to an embodiment of the present disclosure.

[0118] Reference Figure 8 In the display panel 100, the cathode 150 may be formed corresponding to the display area AA. The cathode 150 may be formed as a single body on the entire display area AA, for example, and may correspond to all sub-pixels SP arranged in the display area AA.

[0119] In the non-display area NA located at the upper and lower sides of the display area AA, first and second power lines 161 and 162 may be formed to be lines having relatively wide widths and to extend along a row line direction as a horizontal direction.

[0120] The first power line 161 may be located at the upper non-display area NA of the display panel 100 to which the low potential driving voltage VSS output from the power supply circuit 400 is input, and may receive the low potential driving voltage VSS input to the display panel 100 .

[0121] The second power line 162 may be located at a lower non-display area NA of the display panel 100 opposite to the first power line 161 .

[0122] Multiple first voltage lines PL1 formed in multiple scan circuit areas SA in the display area AA can be connected to the first power line 161 at one end (or upper end) of the first voltage line PL1, and can be connected to the second power line 162 at the other end (or lower end) of the first voltage line PL1.

[0123] The first and second power lines 161 and 162 may have relatively wide widths, and the width of each may be greater than the width of each first voltage line PL1 .

[0124] The low potential driving voltage VSS applied to the first power line 161 may be transmitted in a downward direction through the plurality of first voltage lines PL1 formed in the plurality of scan circuit areas SA in the display area AA, and then may supply power to the second power line 162 .

[0125] At least one contact hole CHc may be formed on the first power line 161. Similarly, at least one contact hole CHc may be formed on the second power line 162.

[0126] The cathode 150 may extend so that an upper edge portion (or a first edge portion) of the cathode 150 overlaps the first power line 161, and the upper edge portion may contact the first power line 161 thereunder through the contact hole CHc. Similarly, the cathode 150 may extend so that a lower edge portion (or a second edge portion) of the cathode 150 overlaps the second power line 162, and the lower edge portion may contact the second power line 162 thereunder through the contact hole CHc.

[0127] Therefore, the cathode 150 can receive the low potential driving voltage VSS provided to the first power line 161 and the second power line 162. Since the cathode 150 receives the low potential driving voltage VSS from the upper edge portion and the lower edge portion, the deviation of the low potential driving voltage VSS due to the position in the display area AA (i.e., the rising deviation of the low potential driving voltage VSS) can be prevented from occurring. Therefore, the display quality degradation caused by the deviation of the low potential driving voltage VSS can be prevented.

[0128] Furthermore, in the present embodiment, in order to transmit the low potential driving voltage VSS in a downward direction, the voltage line PL1 may be formed in the scanning circuit area SA defined in the display area AA.

[0129] Therefore, there is no need to form wide transmission lines for transmitting the low potential driving voltage VSS in the downward direction at both side portions of the non-display area NA. In other words, the voltage line PL1 formed in the display area AA may replace the wide transmission line of the non-display area NA.

[0130] Therefore, the width of the non-display area NA can be reduced, and a narrow bezel can be effectively implemented.

[0131] Therefore, even if the display device is large-sized, the low potential driving voltage VSS may be uniform in the display area AA and a narrow frame may be effectively implemented.

[0132] An example of the structure of the pixels P and the common control circuit block C in the pixel block PB according to the embodiment of the present disclosure is described below.

[0133] Fig. 9 is a view showing an example of the structure of pixels and a common control circuit block in a pixel block according to an embodiment of the present disclosure. Fig.10 Yes Drive Fig. 9 Waveform diagram of signals of pixels and common control circuit blocks.

[0134] Reference Fig. 9 The pixel block PB of this embodiment may include a plurality of pixels P arranged along a row line direction and a common control circuit block C located between adjacent pixels P.

[0135] In this embodiment, for the purpose of explanation, a pixel block PB configured with two pixels P and a common control circuit block C between the two pixels P is shown by way of example, and the row line where the pixel block PB is located is assumed to be the nth row line.

[0136] Each pixel P may be configured with a plurality of sub-pixels SP adjacent to each other along a row line direction and having different colors. For example, the plurality of sub-pixels SP of the pixel P may include a red first sub-pixel SP1, a green second sub-pixel SP2, and a blue third sub-pixel SP3.

[0137] The common control circuit block C may be commonly connected to the first to third sub-pixels SP1 to SP3 of the pixels P adjacent to the common control circuit block C, and may commonly control the storage capacitors Cst of the sub-pixels SP1 to SP3.

[0138] Regarding the structure of each sub-pixel SP, in the present embodiment, an internal compensation structure may be used to compensate for the threshold voltage of the driving transistor DT. In this regard, a 7T1C structure is described by way of example.

[0139] Each sub-pixel SP may include a driving element which is first to sixth transistors T1 to T6 as switching transistors, a driving transistor DT, and a storage capacitor Cst. Each sub-pixel SP may include a light emitting element driven by the driving element which is a light emitting diode OD.

[0140] For the purpose of explanation, the transistors T1 to T6 and DT formed of P-type transistors are described by way of example. In another example, the transistors T1 to T6 and DT may be formed of N-type transistors.

[0141] Regarding the first transistor T1, the gate electrode can be connected to its corresponding row line, ie, the gate line of the nth row line, the source electrode can be connected to the data line DL, and the drain electrode can be connected to the first node N1, ie, the drain electrode of the second transistor T2 and the source electrode of the driving transistor DT.

[0142] The first transistor T1 may be turned on in response to the gate signal Vg[n] of the n-th row line, and thus the data signal Vda provided through the data line DL may be applied to the first node N1.

[0143] Regarding the second transistor T2 , a gate electrode may be connected to an emission line of an n-th row line, a source electrode may be applied with a high potential driving voltage VDD as a second power voltage, and a drain electrode may be connected to the first node N1 .

[0144] The second transistor T2 may be turned on in response to the emission signal Vem[n] of the n-th row line, and thus the high potential driving voltage VDD may be applied to the first node N1 .

[0145] Regarding the third transistor T3, the gate electrode can be connected to the gate line of the nth row line, the source electrode can be connected to the drain electrode of the driving transistor DT and the source electrode of the fifth transistor T5, that is, the third node N3, and the drain electrode can be connected to the gate electrode of the driving transistor DT and the first electrode of the storage capacitor Cst, that is, the second node N2.

[0146] The third transistor T3 may be turned on in response to the gate signal Vg[n] of the n-th row line, and thus the driving transistor may be in a diode connection state.

[0147] Regarding the fourth transistor T4 , a gate electrode may be connected to a gate line of a previous row line, ie, the (n−1)th row line, a source electrode may be applied with the initialization voltage Vini, and a drain electrode may be connected to the second node N2 .

[0148] The fourth transistor T4 may be turned on in response to the gate signal Vg[n-1] of the (n-1)th row line, and thus the second node N2, ie, the gate electrode of the driving transistor may be initialized with the initialization voltage Vini.

[0149] Regarding the fifth transistor T5 , a gate electrode may be connected to the emission line of the nth row line, a source electrode may be connected to the third node N3 , and a drain electrode may be connected to the light emitting diode OD and the drain electrode of the sixth transistor T6 , ie, the fourth node N4 .

[0150] The fifth transistor T5 may be turned on in response to the emission signal Vem[n] of the n-th row line, and thus the emission driving current generated by the driving transistor DT may be applied to the light emitting diode OD to make the light emitting diode OD emit light.

[0151] Regarding the sixth transistor T6 , a gate electrode may be connected to the gate line of the n-th row line, a source electrode may be applied with the initialization voltage Vini, and a drain electrode may be connected to the fourth node N4 .

[0152] The sixth transistor T6 may be turned on in response to the gate signal Vg[n] of the n-th row line, and thus the fourth node N4 , ie, the light emitting diode OD may be initialized with the initialization voltage Vini.

[0153] Regarding the storage capacitor Cst, a first electrode may be connected to the second node N2, and a second electrode may be connected to a common control node Nc. The common control node Nc may be connected to a voltage output terminal of the common control circuit block C.

[0154] The common control circuit block C may be commonly coupled to a common control node Nc of the subpixels SP of the pixel P connected to the common control circuit block C. Therefore, the subpixels SP of the pixel P may be commonly applied with an output voltage output from an output terminal of the common control circuit block C and thus controlled.

[0155] In this regard, the common control circuit block C may include a plurality of switch transistors, such as first to third common control transistors Tc1 to Tc3. In the present embodiment, the first to third common control transistors Tc1 to Tc3 may be formed by P-type transistors. Alternatively, the first to third common control transistors Tc1 to Tc3 may be formed by N-type transistors.

[0156] The first common control transistor Tc1 and the second common control transistor Tc2 may be connected to each other in parallel.

[0157] Regarding the first common control transistor Tc1, the gate electrode can be connected to the gate line of the (n-1)th row line, the source electrode can be applied with the reference voltage Vref, and the drain electrode can be connected to the output end of the common control circuit block C, that is, the common control node Nc of the subpixel SP.

[0158] Regarding the second common control transistor Tc2 , the gate electrode may be connected to the gate line of the nth row line, the source electrode may be applied with the reference voltage Vref, and the drain electrode may be connected to the output terminal of the common control circuit block C, ie, the common control node Nc of the subpixel SP.

[0159] In this case, the first common control transistor Tc1 may be turned on in response to the gate signal Vg[n-1] of the (n-1)th row line, and thus may output the reference voltage Vref.

[0160] The second common control transistor Tc2 may be turned on in response to the gate signal Vg[n] of the n-th row line, and thus may output the reference voltage Vref.

[0161] For the horizontal period of the previous row line and the horizontal period of the current row line, the common control circuit block C may be operated to output the reference voltage Vref.

[0162] Regarding the third common control transistor Tc3, the gate electrode can be connected to the emission line of the nth row line, the source electrode can be applied with the high potential driving voltage VDD, and the drain electrode can be connected to the output end of the common control circuit block C, that is, the common control node Nc of the subpixel SP.

[0163] In this case, the third common control transistor Tc3 may be turned on in response to the emission signal Vem[n] of the n-th row line, and thus may output the high potential driving voltage VDD.

[0164] The operation of the sub-pixels SP in the pixel P using the common control circuit block C is described.

[0165] The sub-pixel SP of the present embodiment may perform an initialization operation in the initialization time t1 , perform a sampling operation of the threshold voltage of the driving transistor DT in the sampling time t2 , and perform an emission operation in the emission time t3 , frame by frame.

[0166] Regarding the initialization operation, for the sub-pixels SP on the n-th row line, the initialization time t1 may be set within the horizontal period H of the (n-1)-th row line, and the initialization operation may be performed.

[0167] In the initialization time t1, the fourth transistor T4 of the subpixel SP may be turned on by the gate signal Vg[n-1] of the (n-1)th row line. Therefore, the initialization voltage Vini may be applied to the second node N2, and the gate electrode of the driving transistor DT may be initialized.

[0168] In the initialization time t1, the first common control transistor Tc1 of the common control circuit block C may be turned on by the gate signal Vg[n-1] of the (n-1)th row line. Therefore, the reference voltage Vref may be output from the common control circuit block C and applied to the common control node Nc of the subpixel SP.

[0169] Regarding the sampling operation, for the sub-pixels SP on the n-th row line, the sampling time t2 may be set within the horizontal period H of the n-th row line, and the sampling operation may be performed.

[0170] In the sampling time t2, the first transistor T1, the third transistor T3, and the sixth transistor T6 of the sub-pixel SP can be turned on by the gate signal Vg[n] of the nth row line. Therefore, the gate electrode and the drain electrode of the driving transistor DT can be in a short-circuit state, that is, a connected state, and the threshold voltage Vth of the driving transistor DT can be sampled, so that the second node N2, that is, the gate electrode of the driving transistor DT can be charged to the sum of the data voltage Vda and the threshold voltage Vth (Vda+Vth). In addition, by turning on the sixth transistor T6, the initialization voltage Vini can be applied to the fourth node N4, and thus the anode of the light emitting diode OD can be initialized.

[0171] In the sampling time t2, the second common control transistor Tc2 of the common control circuit block C may be turned on by the gate signal Vg[n] of the n-th row line. Therefore, the reference voltage Vref may be output and applied to the common control node Nc of the sub-pixel SP.

[0172] Regarding the emission operation, after a predetermined time (eg, a horizontal period of the (n+1)th row line) ends from the sampling time t2, the emission time t3 may be set and the emission operation may be performed.

[0173] In the emission time t3, the second transistor T2 and the fifth transistor T5 of the sub-pixel SP can be turned on by the emission signal Vem[n] of the nth row line. Therefore, by turning on the second transistor T2, the high potential driving voltage VDD can be applied to the first node N1, that is, the source electrode of the driving transistor DT. In addition, by turning on the fifth transistor T5, the emission driving current generated by the driving transistor DT can be applied to the light emitting diode OD, and thus the light emitting diode OD can be made to emit light.

[0174] In the emission time t3 , the third common control transistor Tc3 of the common control circuit block C may be turned on by the emission signal Vem[n] of the nth row line. Therefore, the high potential driving voltage VDD may be output and applied to the common control node Nc of the sub-pixel SP.

[0175] Since the high potential driving voltage VDD may be applied to the common control node Nc in the emission time t3, the second node N2 connected to the first electrode of the storage capacitor Cst may have a voltage change by the voltage change amount (VDD-Vref) of the common control node Nc. In other words, the voltage of the second node N2 may become (VDD-Vref+Vda+Vth).

[0176] Based on this, the emission drive current can be generated according to the following formula.

[0177] Iod=K*{Vgs-Vth} 2 =K*{((VDD-Vref+Vda+Vth)-VDD)-Vth} 2 = {Vda-Vref} 2 Vgs is a voltage difference between a gate electrode and a source electrode of the driving transistor DT, and K is a constant.

[0178] As described above, according to this embodiment, the variation in the threshold voltage Vth of the driving transistor DT can be compensated, and the variation in the high potential driving voltage VDD can be compensated.

[0179] Regarding compensation of the high potential driving voltage VDD, the high potential driving voltage VDD may drop along a line transmitting the high potential driving voltage VDD in the display panel 100 , and deviation of the high potential driving voltage VDD due to position may occur.

[0180] In this embodiment, the charging voltage of the storage capacitor Cst can be collectively controlled using the common control circuit block C. Therefore, the component of the high potential driving voltage VDD can be reduced when generating the emission driving current, and thus the emission deviation caused by the deviation of the high potential driving voltage VDD can be prevented and the display quality can be ensured.

[0181] Furthermore, the common control circuit block C can collectively control the pixel P as the minimum unit. Therefore, compared with configuring a voltage control circuit in units of sub-pixels to compensate for the deviation of the high potential driving voltage VDD, the control circuit can be greatly reduced.

[0182] In addition, in this embodiment, the threshold voltage Vth can be directly detected by the data voltage Vda, and during the driving process, the electrical short circuit between the high potential driving voltage VDD and the reference voltage Vref can be prevented. Therefore, the detection performance of the threshold voltage Vth can be improved.

[0183] In addition, refer to Fig.10 It can be seen from the driving timing that after the initialization time and sampling time of two adjacent row lines (for example, the (n-1)th row line and the nth row line) are over, the two row lines can be applied to the same emission signal and emit at the same time. Therefore, the emission signal generating circuit can be configured by two row lines, and the size of the scan driving circuit 500 can be reduced.

[0184] As described above, according to the embodiments of the present disclosure, a GIP type scan driving circuit can be formed at a plurality of scan circuit regions in a display region, so that it is not necessary to form a scan driving circuit in a non-display region, thereby effectively realizing a narrow frame.

[0185] In addition, the line for transmitting the low potential driving voltage can be located in the scanning circuit area. Therefore, it is not necessary to form a wide line for transmitting the low potential driving voltage in the non-display area, so the width of the non-display area can be reduced, thereby effectively realizing a narrow frame.

[0186] In addition, the lines that transmit the DC waveform voltage and can block the interference of the clock signal can be located on both sides of the clock signal line formed in the scanning circuit area. Therefore, the clock signal can be prevented from interfering with the pixel arrangement area adjacent to the scanning circuit area, and the display quality can be ensured.

[0187] In addition, the pixel block in which the pixels and the common control circuit block are alternately arranged can be located in the pixel arrangement area, and the scanning circuit area can be placed in the area where the common control circuit block can be positioned in the arrangement order. Therefore, there is no need to prepare an additional area for the scanning drive circuit in the display area, and the regularity of the pixels and the driving circuit driving the pixels can be basically maintained, and the driving circuit is the common control circuit block and the scanning drive circuit alternately arranged in the display area, so that the display quality can be ensured.

[0188] The following describes arrangements of scan drive circuits other than the arrangements of the scan drive circuits as examples of the above-described embodiments.

[0189] Fig.11is a view schematically showing an example of the arrangement of a gate signal generating circuit of a scan driving circuit according to another embodiment of the present disclosure.

[0190] exist Fig.11 In the embodiment, for the purpose of illustration, one gate signal generating circuit GC located in the display area AA is shown. Detailed description of parts identical or similar to those in the above-mentioned embodiment may be omitted.

[0191] Reference Fig.11 , each gate signal generating circuit GC may be formed at an adjacent scanning circuit area SA, for example, may be formed to be dispersed at two adjacent scanning circuit areas SA. In this regard, some stages STGg of the gate signal generating circuit GC may be formed at one of the two scanning circuit areas SA, and other stages STGg of the gate signal generating circuit GC may be formed at the other of the two scanning circuit areas SA.

[0192] Regarding the stage STGg constituting the gate signal generating circuit GC, two stages STGg respectively corresponding to two adjacent row lines may be respectively formed at the two scanning circuit areas SA.

[0193] For example, the first stage STG[1] that generates a gate signal for driving the first row line may be located at the left scanning circuit area SA, and the second stage STG[2] that generates a gate signal for driving the second row line may be located at the right scanning circuit area SA. Similarly, the (n-1)th stage STG[n-1] that generates a gate signal for driving the (n-1)th row line may be located at the left scanning circuit area SA, and the nth stage STG[n] that generates a gate signal for driving the nth row line may be located at the right scanning circuit area SA.

[0194] In the present embodiment, instead of each stage STGg being formed to be divided in adjacent scan circuit areas SA, each stage STGg may be formed in a corresponding one of the scan circuit areas SA.

[0195] In this case, for example, each stage STGg may be formed to correspond to a region of approximately two row lines.

[0196] In this embodiment, each stage STGg may be located in a corresponding scanning circuit area SA, which may simplify the circuit design compared to the above embodiment.

[0197] Also in this embodiment, a transmission line TL for transmitting a signal between adjacent scanning circuit areas SA may be formed.

[0198] For example, similar to the above embodiment, it may be necessary to provide the first logic voltage VGL or the second logic voltage VGH to a circuit (i.e., stage) in another scanning circuit area SA that is different from the scanning circuit area SA where the second voltage line PL2 that transmits the first logic voltage VGL or the second logic voltage VGH is located, or to provide the first gate clock signal GCLK or the second gate clock signal GCLKb to a circuit (i.e., stage) in another scanning circuit area SA that is different from the scanning circuit area SA where the clock signal line CL that transmits the first gate clock signal GCLK or the second gate clock signal GCLKb is located. To this end, a transmission line TL can be used.

[0199] Fig.11 The arrangement can be applied to the arrangement of the emission signal generating circuit. In other words, with respect to the emission signal generating circuit formed in a plurality of scanning circuit regions, each stage of the emission signal generating circuit can be formed in a corresponding one of the scanning circuit regions.

[0200] Fig.12 is a view schematically showing an example of the arrangement of an emission signal generating circuit of a scan driving circuit according to another embodiment of the present disclosure.

[0201] exist Fig.12 In the embodiment, for the purpose of illustration, one emission signal generating circuit EC located in the display area AA is shown. Detailed description of parts identical or similar to those in the above-mentioned embodiment may be omitted.

[0202] Reference Fig.12 Each emission signal generating circuit EC may be formed at adjacent scanning circuit areas SA, for example, may be formed to be dispersed at two adjacent scanning circuit areas SA.

[0203] Regarding the stages STGe constituting the emission signal generating circuit EC, each stage STGe may be configured with a first circuit portion De1 and a second circuit portion De2 separately formed at two scanning circuit areas SA.

[0204] In this embodiment, the emission signal output from each stage STGe can be applied to two adjacent row lines in common. In other words, one emission signal for two row lines can be generated so that the output from each stage STGe can drive two row lines.

[0205] Regarding this structure, as Fig.12 The emission signal generating circuit EC may be one in which one stage STGe is formed corresponding to two row lines.

[0206] In this case, the number of circuits constituting the transmission signal generating circuit EC can be reduced by approximately half.

[0207] Fig.13 is a view schematically showing a display panel of an electroluminescent display device according to another embodiment of the present disclosure.

[0208] In the present embodiment, detailed description of parts that are the same as or similar to those in the above-described embodiment may be omitted.

[0209] Reference Fig.13 The display panel 100a of the electroluminescent display device of the present embodiment may have a special shape (or a free shape) different from a general (or conventional) rectangular shape.

[0210] In this regard, the profiled display panel 100a may have, for example, at least one of an upper side line, a lower side line, a left side line, and a right side line, and the side line is not straight but has a curvature or is bent. Fig.13 In FIG. 1 , it is shown by way of example that all four lateral lines are not straight.

[0211] In the display panel 100a of the special shape, the lengths of the row line direction and / or the column line direction may not be equal but may be different. In other words, the horizontal resolution and / or the vertical resolution may be different. For example, referring to Fig.13 , the lengths in the row line direction may not be equal as a whole but may be different, and furthermore, the lengths in the column line direction may not be equal as a whole but may be different.

[0212] Even for the display panel 100 a having a special shape, the scan driving circuit 500 may be formed in the display area AA in a GIP type as in the above-mentioned embodiment.

[0213] In this regard, the display area AA may include a plurality of pixel arrangement areas DA as areas where pixels are arranged and a plurality of scan circuit areas SA as areas between the plurality of pixel arrangement areas DA and where the scan driving circuit 500 is formed.

[0214] A plurality of pixels arranged in a matrix may be located in each pixel arrangement area DA, and the pixel arrangement area DA may substantially generate an image. The pixel arrangement areas DA may extend parallel to each other in a column line direction and may be spaced apart from each other in a row line direction with a scanning circuit area SA therebetween.

[0215] Each scanning circuit area SA may be located between adjacent pixel arrangement areas DA, and a partial circuit constituting the scanning driving circuit 500 may be formed at each scanning circuit area SA. The scanning circuit areas SA may extend parallel to each other in a column line direction, and may be spaced apart from each other in a row line direction with the pixel arrangement areas DA therebetween.

[0216] As described above, the display area AA may be configured such that the scanning circuit area SA is dispersed inside the display area AA and the pixel arrangement area DA as an actual image display area is divided.

[0217] In the present embodiment, a special-shaped display panel 100 a may be used, and the display area AA of the special-shaped display panel 100 a may also have the same special-shaped shape as that of the display panel 100 a .

[0218] Therefore, the number of scanning circuit areas SA along the row line direction may be different depending on the position. In this regard, since the display area AA has an irregular shape, the lengths of all row lines may not be equal, but may be different depending on the position. Fig.13 , the number of the scanning circuit areas SA located in a relatively upward line may be greater than the number of the scanning circuit areas SA located in a relatively downward line.

[0219] Therefore, the number of gate signal generating circuits and the number of emission signal generating circuits may be different depending on the location of the row lines.

[0220] As in the above embodiment, the clock signal line CL transmitting the clock signal may be located in the scanning circuit area SA. Through the clock signal line CL, the corresponding clock signal may be provided to the gate signal generating circuit or the emission signal generating circuit located in the corresponding scanning circuit area SA.

[0221] In addition, as in the above embodiment, in the scanning circuit area SA, a voltage line transmitting a voltage of a DC waveform may be placed. In this regard, a first voltage line PL1 transmitting a low potential driving voltage and a second voltage line PL2 transmitting a logic voltage may be located on both sides of the clock signal line CL.

[0222] As described above, the electroluminescent display device may include the special-shaped display panel 100 a , and the special-shaped display panel 100 a may be configured such that a GIP type scan driving circuit may be formed in a plurality of scan circuit regions in a display region.

[0223] Therefore, it is possible to prevent the positional deviation of the scanning signal and the positional deviation of the brightness caused in the display panel having a special shape including the scanning driving circuit formed in the non-display area of ​​the display panel. In addition, a narrow frame can be realized, and the display panel can be formed into any shape among various shapes as needed without limitation.

[0224] Although not described in detail, the same or similar configuration as that of the electroluminescent display device of the above-described embodiment can be applied to the electroluminescent display device of this embodiment.

[0225] According to the above-mentioned embodiment of the present disclosure, the GIP type scan driving circuit can be formed in multiple scan circuit areas in the display area. Therefore, it is not necessary to form a scan driving circuit in the non-display area, so that the width of the non-display area can be reduced and a narrow frame can be effectively achieved.

[0226] In addition, the line transmitting the low potential driving voltage can be located in the scanning circuit area. Therefore, it is not necessary to form a wide line transmitting the low potential driving voltage in the non-display area, so that the width of the non-display area can be reduced and a narrow frame can be effectively achieved.

[0227] In addition, the lines of the voltage of the DC waveform that block the interference of the clock signal can be located on both sides of the clock signal line formed in the scanning circuit area. Therefore, the interference of the clock signal to the pixel arrangement area adjacent to the scanning circuit area can be prevented, and the display quality can be ensured.

[0228] In addition, the pixel block in which the pixels and the common control circuit block are alternately arranged can be located in the pixel arrangement area, and the scanning circuit area can be placed in the area where the common control circuit block can be located in the arrangement order. Therefore, there is no need to prepare an additional area for the scanning drive circuit in the display area, and the regularity of the pixels and the driving circuit driving the pixels can be basically maintained, and the driving circuit is the common control circuit block and the scanning drive circuit alternately arranged in the display area, so that the display quality can be ensured.

[0229] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. An electroluminescent display device, comprising: A display panel, the display panel comprising a display area and a non-display area surrounding the display area, the display area comprising a plurality of pixel arrangement areas and a plurality of scanning circuit areas between the plurality of pixel arrangement areas; a scan driving circuit, wherein the scan driving circuit is formed in the plurality of scan circuit regions; as well as A clock signal line, a first voltage line, and a second voltage line for transmitting a clock signal located in a scanning circuit region, wherein in a single scanning circuit region, the first voltage line and the second voltage line are located on both sides of the clock signal line, The first voltage line transmits a low potential driving voltage, and the low potential driving voltage is provided to a cathode corresponding to the display area.

2. The electroluminescent display device according to claim 1, wherein: The second voltage line transmits a low logic voltage or a high logic voltage provided to the scan driving circuit.

3. The electroluminescent display device according to claim 1, further comprising a first power line and a second power line, wherein the first power line and the second power line are located at opposite sides and are respectively connected to two ends of the first voltage line, and the display area is located between the first power line and the second power line. in, The first and second power lines overlap and contact a first and a second edge portion of the cathode, respectively.

4. The electroluminescent display device according to claim 1, wherein: The pixel arrangement area includes a pixel block located along each row line of the display panel, The pixel block includes a plurality of pixels and at least one common control circuit block located between the plurality of pixels. Wherein, a pixel includes a plurality of sub-pixels emitting different colors, and The common control circuit block controls a plurality of sub-pixels of pixels adjacent to the common control circuit block.

5. The electroluminescent display device according to claim 4, wherein: The width of the common control circuit block is equal to the width of the scanning circuit area.

6. The electroluminescent display device according to claim 4, wherein: The sub-pixel includes a light emitting diode, a plurality of transistors including a driving transistor, and a storage capacitor connected between a gate electrode of the driving transistor and a common control node, and The common control node is applied with a voltage output from an output terminal of the common control circuit block.

7. The electroluminescent display device according to claim 6, wherein: The plurality of transistors of the sub-pixels on the nth row line include: the drive transistor connected to the storage capacitor at a second node between the storage capacitor and the drive transistor; A first transistor connected to the gate line and the data line of the nth row line; a second transistor connected to the emission line of the nth row line, to which a high potential driving voltage is applied, and connected to the first transistor at a first node; a third transistor connected between the drain electrode and the gate electrode of the driving transistor; a fourth transistor connected to the gate line of the (n-1)th row line, to which an initialization voltage is applied, and connected to the second node; a fifth transistor connected to the emission line of the nth row line, connected to the drain electrode of the driving transistor at a third node, and connected to the light emitting diode at a fourth node; and A sixth transistor is connected to the gate line of the n-th row line, is applied with the initialization voltage, and is connected to the fourth node.

8. The electroluminescent display device according to claim 6, wherein: The common control circuit blocks located on the nth row include: A first common control transistor connected to the gate line of the (n-1)th row line, to which a reference voltage is applied, and connected to an output terminal of the common control circuit block; a second common control transistor connected to the gate line of the nth row line, to which the reference voltage is applied, and connected to an output terminal of the common control circuit block; and The third common control transistor is connected to the emission line of the nth row line, is applied with a high potential driving voltage, and is connected to the output end of the common control circuit block.

9. The electroluminescent display device according to claim 1, wherein: The scan driving circuit includes a scan signal generating circuit that generates a scan signal as a gate signal or an emission signal, and The scanning signal generating circuit includes a plurality of stages that sequentially output the scanning signal.

10. The electroluminescent display device according to claim 9, wherein: Each of the plurality of stages is separately formed in two adjacent scan circuit regions.

11. The electroluminescent display device according to claim 9, wherein: At least one of the plurality of stages is formed in one of two adjacent scan circuit regions, and the other of the plurality of stages is formed in the other of the two adjacent scan circuit regions.

12. The electroluminescent display device according to claim 9, wherein: Each of the plurality of stages of the scan signal generating circuit that generates the emission signal outputs an emission signal that is commonly applied to two adjacent row lines of the display panel.

13. The electroluminescent display device according to claim 1, further comprising a transmission line for transmitting a signal between adjacent scanning circuit regions.

14. An electroluminescent display device, comprising: A display panel, the display panel comprising a display area and a non-display area surrounding the display area, the display area comprising a plurality of pixel arrangement areas and a plurality of scanning circuit areas between the plurality of pixel arrangement areas; a scan driving circuit, wherein the scan driving circuit is formed in the plurality of scan circuit regions; as well as A clock signal line, a first voltage line, and a second voltage line for transmitting a clock signal located in a scanning circuit region, wherein in a single scanning circuit region, the first voltage line and the second voltage line are located on both sides of the clock signal line, The first voltage line and the second voltage line transmit voltages with different DC waveforms.

15. The electroluminescent display device according to claim 14, wherein: The first voltage line transmits a low potential driving voltage, and the low potential driving voltage is supplied to a cathode corresponding to the display area.

16. The electroluminescent display device according to claim 14, wherein: The second voltage line transmits a low logic voltage or a high logic voltage provided to the scan driving circuit.

17. The electroluminescent display device according to claim 15, further comprising a first power line and a second power line, wherein the first power line and the second power line are located at opposite sides and are respectively connected to two ends of the first voltage line, and the display area is located between the first power line and the second power line. in, The first and second power lines overlap and contact a first and a second edge portion of the cathode, respectively.

18. The electroluminescent display device according to claim 14, wherein: The pixel arrangement area includes a pixel block located along each row line of the display panel, The pixel block includes a plurality of pixels and at least one common control circuit block located between the plurality of pixels. Wherein, a pixel includes a plurality of sub-pixels emitting different colors, and The common control circuit block controls a plurality of sub-pixels of pixels adjacent to the common control circuit block.

19. The electroluminescent display device according to claim 18, wherein: The width of the common control circuit block is equal to the width of the scanning circuit area.

20. The electroluminescent display device according to claim 18, wherein: The sub-pixel includes a light emitting diode, a plurality of transistors including a driving transistor, and a storage capacitor connected between a gate electrode of the driving transistor and a common control node, and The common control node is applied with a voltage output from an output terminal of the common control circuit block.

Images