Driving circuit and display device having the same

Abstract

A driving circuit and a display device having the same are provided. The driving circuit includes a plurality of scan stages each corresponding to a plurality of scan lines, receiving a clock signal and a carry signal, and outputting a scan signal, and a plurality of masking circuits corresponding to some of the plurality of scan stages, respectively. Each masking circuit outputs one of the scan signal output from the corresponding scan stage and a first voltage as a masking carry signal in response to a masking signal. When a (j-a)th scan stage is not one of the some of the scan stages, a jth scan stage receives the scan signal output from the (j-a)th scan stage as the carry signal, and when the (j-a)th scan stage is one of the some of the scan stages, the jth scan stage receives the masking carry signal output from the masking circuit corresponding to the (j-a)th scan stage as the carry signal.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0145488, filed on November 3, 2020, which is hereby incorporated by reference for all purposes, as if fully set forth herein. Technical Field

[0002] This disclosure relates to display devices. Background Technology

[0003] In display devices, organic light-emitting diodes (OLEDs) use organic light-emitting diodes (OLEDs) to generate light through electron-hole recombination to display images. OLEDs offer advantages such as fast response times and low power consumption.

[0004] An organic light-emitting display device includes data lines, scan lines, and pixels connected to the data lines and scan lines. Each pixel includes an organic light-emitting diode (OLED) and a circuit unit that controls the amount of current flowing through the OLED. The circuit unit controls the amount of current flowing from a first driving voltage through the OLED to a second driving voltage in response to a data signal. In this case, light with a predetermined brightness corresponding to the amount of current flowing through the OLED is generated.

[0005] As the application areas of display devices diversify, multiple different images are displayed simultaneously on a single display device. Consequently, technologies that can reduce the power consumption of display devices displaying multiple images become desirable. Summary of the Invention

[0006] This disclosure provides a drive circuit that can reduce power consumption.

[0007] This disclosure provides a display device including a driving circuit.

[0008] An embodiment of the present invention provides a driving circuit comprising: a plurality of scan levels, each corresponding to a plurality of scan lines, receiving a clock signal and a carry signal, and outputting a scan signal; and a plurality of masking circuits, each corresponding to some of the scan levels. Each of the plurality of masking circuits, in response to a masking signal, outputs one of i) the scan signal output from the corresponding scan level and ii) a first voltage as a masking carry signal via a carry output terminal. The j-th scan level (j is a natural number greater than 1) among the plurality of scan levels: i) when the (ja)-th scan level (a is a natural number less than j) is not one of the scan levels, receives the scan signal output from the (ja)-th scan level as a carry signal; and ii) when the (ja)-th scan level is one of the scan levels, receives the masking carry signal output from the masking circuit corresponding to the (ja)-th scan level as a carry signal.

[0009] The masking signal may include a first masking signal and a second masking signal.

[0010] When the first masking signal has a first level and the second masking signal has a second level, each of the plurality of masking circuits may output a scan signal from the corresponding scan level as a masking carry signal, and when the first masking signal has a second level and the second masking signal has a first level, each of the plurality of masking circuits may not output a scan signal from the corresponding scan level as a masking carry signal.

[0011] When the first masking signal has a second level and the second masking signal has a first level, each of the plurality of masking circuits can maintain the first voltage as a masking carry signal.

[0012] Each of the plurality of scan stages may include: an output terminal for outputting a scan signal; and a first voltage terminal for receiving a first voltage, and the masking circuit may include: a first transistor connected between the output terminal and the carry output terminal of the corresponding scan stage, and including a gate electrode connected to a first masking input terminal for receiving a first masking signal; and a second transistor connected between the carry output terminal and the first voltage terminal of the corresponding scan stage, and including a gate electrode connected to a second masking input terminal for receiving a second masking signal.

[0013] Embodiments of the present invention provide a display device comprising: a display panel including a plurality of data lines, a plurality of first scan lines, and a plurality of pixels connected to the plurality of data lines and the plurality of first scan lines; a data driving circuit for driving the plurality of data lines; a driving circuit including a first scan driving circuit for driving the plurality of first scan lines; and a driving controller for controlling the data driving circuit and the driving circuit to drive a first display area of ​​the display panel at a first driving frequency during a multi-frequency mode and to drive a second display area of ​​the display panel at a second driving frequency during a multi-frequency mode. The first scan driving circuit includes a plurality of first scan levels, each of which corresponds to some of the plurality of first scan lines, receives a clock signal and a carry signal, and outputs a first scan signal. The driving circuit also includes a plurality of masking circuits, each of which corresponds to some of the plurality of first scan levels. Each of the plurality of masking circuits outputs, in response to a masking signal, one of i) a first scan signal output from the corresponding first scan level and ii) a first voltage as a mask carry signal via a carry output terminal. The j-th (j is a natural number greater than 1) first scan level among multiple first scan levels: i) when the (ja)-th (ja)-th (a is a natural number less than j) first scan level is not one of some first scan levels, the first scan signal output from the (ja)-th first scan level is received as a carry signal; and ii) when the (ja)-th first scan level is one of some first scan levels, the mask carry signal output from the masking circuit corresponding to the (ja)-th first scan level is received as a carry signal.

[0014] The masking circuit can correspond to the yth (y is a natural number) first scan level among a plurality of first scan levels and outputs a first scan signal from the yth first scan level as the yth carry signal in response to the masking signal, and the (y+a)th first scan level among a plurality of first scan levels can receive the yth carry signal output from the corresponding masking circuit as the carry signal.

[0015] The masking signal may include a first masking signal and a second masking signal.

[0016] When the first masking signal has a first level and the second masking signal has a second level, each of the plurality of masking circuits may output a first scan signal from the corresponding first scan level as a masking carry signal, and when the first masking signal has a second level and the second masking signal has a first level, each of the plurality of masking circuits may not output a first scan signal from the corresponding first scan level as a masking carry signal.

[0017] When the first masking signal has a second level and the second masking signal has a first level, each of the plurality of masking circuits can maintain the first voltage as a masking carry signal.

[0018] Each of the plurality of first scan stages may include an output terminal for outputting a scan signal and a first voltage terminal for receiving a first voltage. The masking circuit may include: a first transistor connected between the output terminal and carry output terminal of the corresponding first scan stage, and including a gate electrode connected to a first masking input terminal for receiving a first masking signal; and a second transistor connected between the carry output terminal and the first voltage terminal of the corresponding first scan stage, and including a gate electrode connected to a second masking input terminal for receiving a second masking signal.

[0019] The drive controller can control the data drive circuit and the drive circuit to drive the first display area and the second display area at a predetermined frequency in normal frequency mode, and the second drive frequency can be lower than the predetermined frequency.

[0020] The first driving frequency can be higher than the predetermined frequency.

[0021] The display panel may also include a plurality of second scan lines respectively connected to a plurality of pixels, and the driving circuit may also include a second scan driving circuit, the second scan driving circuit including a plurality of second scan levels, each of the plurality of second scan levels corresponding to some of the plurality of second scan lines, receiving a clock signal and a carry signal, and outputting a second scan signal.

[0022] The display panel may also include a plurality of third scan lines respectively connected to a plurality of pixels, and the driving circuit may also include a third scan driving circuit, which includes a plurality of third scan levels, each of the plurality of third scan levels corresponding to some of the plurality of third scan lines, receiving a clock signal and a carry signal, and outputting a third scan signal.

[0023] The display panel may also include multiple light-emitting control lines connected to multiple pixels respectively, and the driving circuit may also include a light-emitting driving circuit, which includes multiple light-emitting levels, each of the multiple light-emitting levels corresponding to some of the multiple light-emitting control lines, receiving a clock signal and a carry signal, and outputting a light-emitting control signal.

[0024] Multiple first scan lines, multiple second scan lines, multiple third scan lines, and multiple light emission control lines may extend in a first direction and be arranged in a second direction spaced apart from each other.

[0025] Each of the plurality of first scan levels, each of the plurality of second scan levels, and each of the plurality of light emission levels may have the same length in the second direction, and the length of each of the plurality of first scan levels in the second direction may be twice the length of each of the plurality of third scan levels in the second direction.

[0026] Each of the plurality of first scan levels may apply a substantially identical first scan signal to a plurality of pixels arranged in four rows, and each of the plurality of light emission levels may apply a substantially identical light emission control signal to a plurality of pixels arranged in four rows.

[0027] Each of the plurality of second scan levels may apply a substantially identical second scan signal to a plurality of pixels arranged in two rows, and each of the plurality of third scan levels may apply a substantially identical third scan signal to a plurality of pixels arranged in one row.

[0028] As described above, when a moving image is displayed in the first display area and a still image is displayed in the second display area, the display device drives the first display area at a first driving frequency and the second display area at a second driving frequency in a multi-frequency mode. Since the second driving frequency of the second display area displaying the still image decreases, the power consumption of the display device is reduced. In particular, the starting position of the second display area can be changed in the display device, thus improving the power consumption reduction effect. Furthermore, although the display device also includes a masking circuit for setting the starting position of the second display area, the increase in circuit area is minimized. Attached Figure Description

[0029] The above and other advantages of this disclosure will become readily apparent when considered in conjunction with the accompanying drawings, and by referring to the following detailed description, in which:

[0030] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure;

[0031] Figure 2A and Figure 2B This is a perspective view showing a display device according to an embodiment of the present disclosure;

[0032] Figure 3A This is a view showing the operation of the display device in normal frequency mode;

[0033] Figure 3B This is a view showing the operation of the display device in multi-frequency mode;

[0034] Figure 4 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0035] Figure 5 This is an equivalent circuit diagram showing pixels according to embodiments of the present disclosure;

[0036] Figure 6 It is shown Figure 5 The timing diagram of the operations of the pixels shown;

[0037] Figure 7 It is shown Figure 4 A block diagram of the first driving circuit shown;

[0038] Figure 8 It is shown Figure 4 The block diagram of the second driving circuit shown;

[0039] Figure 9 It is shown Figure 7 The first drive circuit shown and Figure 8 The block diagram of the second driving circuit shown;

[0040] Figure 10 This is a view showing the light-emitting stage, the first scanning stage, and the second scanning stage in the first driving circuit;

[0041] Figure 11 This is a circuit diagram illustrating a third first scan stage and a first masking circuit in a first driving circuit according to an embodiment of the present disclosure;

[0042] Figure 12 This shows the output from the multi-frequency mode. Figure 10 The timing diagram shown includes the scan signal output from the first scan stage, the scan signal output from the second scan stage, and the first masking signal to the fourth masking signal.

[0043] Figure 13A and Figure 13B This is a timing diagram showing the scan signal in multiple frequency modes; and

[0044] Figure 14 This is a circuit diagram illustrating a third first scan stage and a first masking circuit in a first driving circuit according to an embodiment of the present disclosure. Detailed Implementation

[0045] In this disclosure, it will be understood that when an element or layer is referred to as being “on,” “connected to,” or “attached to” another element or layer, it can be directly on, connected to, or attached to the other element or layer, or an intermediary element or layer may exist.

[0046] Similar reference numerals always refer to similar elements. In the figures, the thickness of layers, films, and regions is exaggerated for clarity. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms as well.

[0048] For ease of description, spatial relative terms, such as “below,” “under,” “down,” “above,” “up,” and similar terms, may be used herein to describe the relationship between one element or feature and another element(s) as shown in the figure.

[0049] It will also be understood that the terms “include” and / or “including”, when used in this specification, indicate the presence of the stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or clusters thereof.

[0050] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, without departing from the teachings herein, the first element, component, area, layer, or part discussed below can be referred to as the second element, component, area, layer, or part.

[0051] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0052] This disclosure will be explained in detail below with reference to the accompanying drawings.

[0053] Figure 1 This is a plan view showing a display device DD according to an embodiment of the present disclosure.

[0054] Reference Figure 1 Portable terminals are shown as representative examples of display devices DD according to embodiments of the present disclosure. Portable terminals may include tablet PCs, smartphones, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), game consoles, watch-type electronic devices, or the like; however, the present disclosure according to the invention should not be limited thereto or thereby. Display devices DD can be applied to large display devices such as televisions, billboards, or the like, or to small to medium-sized display devices such as personal computers, laptops, kiosks, vehicle navigation units, cameras, or the like. However, these are merely examples, and display devices DD can be used in other electronic products as long as the other electronic products do not depart from the inventive concept of the present disclosure.

[0055] like Figure 1 As shown, the display surface displaying the first image IM1 and the second image IM2 is substantially parallel to the surface defined by the first direction DR1 and the second direction DR2. The display device DD includes a plurality of regions on the display surface that are distinct from each other. The display surface includes a display area DA for displaying the first image IM1 and the second image IM2 and a non-display area NDA surrounding the display area DA. The non-display area NDA may be referred to as a border area. As an example, the display area DA has a quadrilateral shape. The non-display area NDA surrounds the display area DA. Furthermore, although not shown in the figure, the display area DA may have a curved shape in a portion thereof. As a result, the display device DD may have a curved shape in its area.

[0056] The display area DA of the display device DD includes a first display area DA1 and a second display area DA2. In a specific application, a first image IM1 is displayed in the first display area DA1, and a second image IM2 is displayed in the second display area DA2. For example, the first image IM1 may be a moving image, and the second image IM2 may be a still image or text information with a long change period.

[0057] The display device DD can drive the first display area DA1, which displays moving images, at a normal frequency, and can drive the second display area DA2, which displays still images, at a lower frequency than the normal frequency. The display device DD can reduce the driving frequency of the second display area DA2, and therefore, reduce the power consumption of the display device DD.

[0058] Each of the first display area DA1 and the second display area DA2 may have a predetermined size, and the sizes of the first display area DA1 and the second display area DA2 may vary depending on the application. In an embodiment, when a still image is displayed in the first display area DA1 and a moving image is displayed in the second display area DA2, the first display area DA1 may be driven at a low frequency, and the second display area DA2 may be driven at a normal frequency. Furthermore, the display area DA may be divided into three or more display areas, and the driving frequency of each of the multiple display areas may be determined based on the type of image (still image or moving image) displayed in each of the multiple display areas.

[0059] Figure 2A and Figure 2B This is a perspective view showing a display device DD2 according to an embodiment of the present disclosure. Figure 2A The unfolded state of the display device DD2 is shown, and Figure 2B The folded state of the display device DD2 is shown.

[0060] Reference Figure 2A and Figure 2B The display device DD2 may include a display area DA and a non-display area NDA. The display device DD2 can display images through the display area DA. When the display device DD2 is in an unfolded state, the display area DA may include a plane defined by a first direction DR1 and a second direction DR2. The thickness direction of the display device DD2 may be substantially parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Accordingly, the front (or upper) surface and rear (or lower) surface of each component of the display device DD2 may be defined relative to the third direction DR3. The non-display area NDA may be referred to as a border area. As an example, the display area DA may have a quadrilateral shape. The non-display area NDA may surround the display area DA.

[0061] The display area DA may include a first non-foldable area NFA1, a foldable area FA, and a second non-foldable area NFA2. The foldable area FA may be folded about a folding axis FX extending in the first direction DR1.

[0062] When the display device DD2 is folded, the first non-folded area NFA1 and the second non-folded area NFA2 can face each other. Accordingly, when the display device DD2 is fully folded, the display area DA may not be exposed to the outside, and this folding operation of the display device DD2 can be referred to as an inward folding operation. However, this is merely an example, and the operation of the display device DD2 should not be limited to or restricted by this.

[0063] For example, when the display device DD2 is folded, the first non-folding region NFA1 and the second non-folding region NFA2 may face opposite directions. Accordingly, when the display device DD2 is folded, the first non-folding region NFA1 may be exposed to the outside, and this folding operation may be referred to as an outward folding operation.

[0064] Display device DD2 can be operated using only one of the inward folding and outward folding operations. Alternatively, display device DD2 can be operated using both inward folding and outward folding operations. In this case, the same area of ​​display device DD2, for example, the folding area FA, can be folded inward ("inward folding") and folded outward ("outward folding"). Alternatively, a portion of display device DD2 can be folded inward (inward folding), and the remaining portion of display device DD2 can be folded outward (outward folding).

[0065] Figure 2A and Figure 2B One folded region and two non-folded regions are shown as a representative example; however, the number of folded regions and non-folded regions should not be limited thereto or restricted by this. For example, display device DD2 may include two or more non-folded regions and multiple folded regions arranged between the non-folded regions.

[0066] exist Figure 2A and Figure 2B In this embodiment, the folding axis FX is substantially parallel to the minor axis of the display device DD2; however, the present disclosure according to the invention should not be limited to or restricted by this. For example, the folding axis FX may extend in a direction substantially parallel to the major axis of the display device DD2 (e.g., the second direction DR2). In this case, the first non-folding region NFA1, the folding region FA, and the second non-folding region NFA2 may be arranged sequentially in the first direction DR1.

[0067] Multiple display areas DA1 and DA2 can be defined within the display area DA of the display device DD2. Figure 2A Two display areas, DA1 and DA2, are shown; however, the number of display areas DA1 and DA2 should not be limited to or restricted by this.

[0068] Display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. For example, the first display area DA1 may be the area displaying a first image IM1, and the second display area DA2 may be the area displaying a second image IM2; however, they should not be limited thereto or restricted by this. For example, the first image IM1 may be a moving image, and the second image IM2 may be a still image or text information with a long period of change.

[0069] The display device DD2 can operate differently depending on the operating mode. The operating modes may include a normal frequency mode and a multi-frequency mode. In normal frequency mode, the display device DD2 can drive both the first display area DA1 and the second display area DA2 at a normal frequency. In multi-frequency mode, the display device DD2 can drive the first display area DA1, which displays the first image IM1, at a first driving frequency, and can drive the second display area DA2, which displays the second image IM2, at a second driving frequency lower than the normal frequency. According to an embodiment, the first driving frequency may be the same as the normal frequency.

[0070] Each of the first display area DA1 and the second display area DA2 may have a predetermined size, and the sizes of the first display area DA1 and the second display area DA2 may vary depending on the application. According to an embodiment, the first display area DA1 may correspond to a first non-folding area NFA1, and the second display area DA2 may correspond to a second non-folding area NFA2. Furthermore, a first portion of the folding area FA may correspond to the first display area DA1, and a second portion of the folding area FA may correspond to the second display area DA2.

[0071] According to an embodiment, the entire folded area FA may correspond to either the first display area DA1 or the second display area DA2.

[0072] According to an embodiment, the first display area DA1 may correspond to a first portion of the first non-foldable area NFA1, and the second display area DA2 may correspond to a second portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2. That is, the size of the second display area DA2 may be larger than the size of the first display area DA1.

[0073] According to an embodiment, the first display area DA1 may correspond to the first non-folding area NFA1, the folding area FA, and the first portion of the second non-folding area NFA2, and the second display area DA2 may correspond to the second portion of the second non-folding area NFA2. That is, the size of the first display area DA1 may be larger than the size of the second display area DA2.

[0074] like Figure 2B As shown, when the folded area FA is folded, the first display area DA1 may correspond to the first non-folded area NFA1, and the second display area DA2 may correspond to the folded area FA and the second non-folded area NFA2.

[0075] exist Figure 2A and Figure 2BThe display device DD2, which defines a folding area, is shown as a representative example; however, the present disclosure according to the invention should not be limited thereto or thereby restricted. For example, the present disclosure can be applied to display devices, rollable display devices, or slidable display devices that include two or more folding areas.

[0076] The following text will describe in detail, as a representative example. Figure 1 The display device DD shown is described below; however, the following description applies to... Figure 2A and Figure 2B The display device DD2 shown is shown.

[0077] Figure 3A This is a view showing the operation of the display device DD in normal frequency mode, and Figure 3B This is a view showing the operation of the display device DD in multi-frequency mode.

[0078] Reference Figure 3A The first image IM1 displayed in the first display area DA1 may be a moving image, and the second image IM2 displayed in the second display area DA2 may be a still image or an image with a long change period, such as a keyboard for game control. Figure 1 The first image IM1 shown is displayed in the first display area DA1. Figure 1 The second image IM2 shown in the second display area DA2 is merely an example, and various images can be displayed in the display device DD.

[0079] In the following text, for better understanding, the normal frequency mode will be assigned the reference character "NFM", and the multi-frequency mode will be assigned the reference character "MFM".

[0080] In Normal Frequency Mode (NFM), the driving frequency of the first display area DA1 and the second display area DA2 of the display device DD can be a normal frequency. For example, the normal frequency can be approximately 60 Hz. In Normal Frequency Mode (NFM), images from the first frame F1 to the 60th frame F60 can be displayed in the first display area DA1 and the second display area DA2 of the display device DD within 1 second.

[0081] Reference Figure 3BDuring Multi-Frequency Mode (MFM), the display device DD can set the driving frequency of a first display area DA1 displaying a first image IM1 (i.e., a moving image) to a first driving frequency, and can set the driving frequency of a second display area DA2 displaying a second image IM2 (i.e., a still image) to a second driving frequency lower than the first driving frequency. When the normal frequency is approximately 60 Hz, the first driving frequency can be approximately 120 Hz, and the second driving frequency can be approximately 1 Hz. The first and second driving frequencies can be changed in various ways. For example, the first driving frequency can be approximately 144 Hz, higher than the normal frequency, or approximately 60 Hz, the same as the normal frequency. For example, the second driving frequency can be one of approximately 30 Hz, approximately 10 Hz, and approximately 1 Hz, lower than the normal frequency.

[0082] In multi-frequency mode MFM, when the first driving frequency is approximately 120 Hz and the second driving frequency is approximately 1 Hz, the first image IM1 can be displayed in each of the first frames F1 to F120 within 1 second through the first display area DA1. The second image IM2 can be displayed only in the second display area DA2 in the first frame F1, and no image can be displayed in the remaining frames F2 to F120. The operation of the display device DD in multi-frequency mode MFM will be described in detail later.

[0083] Figure 4 This is a block diagram illustrating a display device DD according to an embodiment of the present disclosure.

[0084] Reference Figure 4 The display device DD includes a display panel DP, a drive controller 100, a data drive circuit 200, and a voltage generator 500. The display panel DP includes a first drive circuit 300 and a second drive circuit 400.

[0085] The drive controller 100 receives an input signal including an image signal RGB and a control signal CTRL. The drive controller 100 converts the RGB data format into a data format suitable for the interface between the data drive circuit 200 and the drive controller 100 to generate an image data signal DATA. The drive controller 100 controls the data drive circuit 200, the first drive circuit 300, and the second drive circuit 400 to display the image on the display panel DP. The drive controller 100 outputs a first scan control signal SCS1, a second scan control signal SCS2, and a data control signal DCS.

[0086] The data drive circuit 200 receives a data control signal DCS and an image data signal DATA from the drive controller 100. The data drive circuit 200 converts the image data signal DATA into a data signal and outputs the data signal to multiple data lines DL1 to DLm (described later). The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0087] Voltage generator 500 generates voltages to operate the display panel DP. In this embodiment, voltage generator 500 generates a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0088] The display panel DP includes scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, light emission control lines EML1 to EMLn, data lines DL1 to DLm and pixels PX. Here, "n" and "m" are natural numbers. A first driving circuit 300 may be arranged on a first side of the display panel DP, and a second driving circuit 400 may be arranged on a second side of the display panel DP. The scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1 and the light emission control lines EML1 to EMLn may be electrically connected to the first driving circuit 300 and the second driving circuit 400.

[0089] Scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, as well as light emission control lines EML1 to EMLn, may extend in the first direction DR1 and be arranged in the second direction DR2, spaced apart from each other. Data lines DL1 to DLm may extend from the data driving circuit 200 in the opposite direction to the second direction DR2 (i.e., Figure 4 Extending downwards in the middle, and arranged spaced apart from each other in the first direction DR1.

[0090] exist Figure 4 In the display device DD shown, the first driving circuit 300 and the second driving circuit 400 may be arranged facing each other with pixels PX between them; however, the present disclosure according to the invention should not be limited thereto or thereby restricted. According to another embodiment, the display panel DP may include only one of the first driving circuit 300 and the second driving circuit 400.

[0091] Multiple pixels (PX) can be electrically connected to scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. Each of the multiple pixels (PX) can be electrically connected to four scan lines and one emission control line. For example, as... Figure 4As shown, the pixels PX arranged in the first row can be connected to scan lines GIL1, GCL1, GWL1, and GWL2, as well as the first emission control line EML1. Furthermore, the pixels PX arranged in the j-th row can be connected to scan lines GILj, GCLj, GWLj, and GWLj+1, as well as the j-th emission control line EMLj.

[0092] Each of the multiple pixels PX may include a light-emitting diode (ED) (see reference). Figure 5 ) and the pixel circuit PXC (refer to) that controls the light emission of the light-emitting diode ED. Figure 5 The pixel circuit PXC may include one or more transistors and one or more capacitors. The first driving circuit 300 and the second driving circuit 400 may include transistors formed using the same process as the transistors in the pixel circuit PXC.

[0093] Each of the multiple pixels PX can receive a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0094] The first driving circuit 300 can receive a first scan control signal SCS1 from the driving controller 100. In response to the first scan control signal SCS1, the first driving circuit 300 can output scan signals to scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1 and can output light emission control signals to light emission control lines EML1 to EMLn.

[0095] The second driving circuit 400 can receive a second scan control signal SCS2 from the drive controller 100. In response to the second scan control signal SCS2, the second driving circuit 400 can output scan signals to scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, and can output light emission control signals to light emission control lines EML1 to EMLn.

[0096] According to an embodiment, the drive controller 100 can divide the display panel DP into a first display area DA1 (see reference). Figure 1 ) and the second display area DA2 (refer to) Figure 1Furthermore, the driving frequency of the first display area DA1 and the driving frequency of the second display area DA2 can be independently set based on input signals including image signals RGB and control signals CTRL. For example, the drive controller 100 can drive each of the first display area DA1 and the second display area DA2 at a normal frequency (e.g., about 60 Hz) in normal frequency mode NFM. The drive controller 100 can output a first scan control signal SCS1, a second scan control signal SCS2, and a data control signal DCS to drive the first display area DA1 at a first driving frequency (e.g., about 120 Hz) and the second display area DA2 at a second driving frequency (e.g., about 1 Hz) in multi-frequency mode MFM.

[0097] Figure 5 This is an equivalent circuit diagram illustrating a pixel PXij according to an embodiment of the present disclosure.

[0098] Figure 5 It shows the relationship with Figure 4 The equivalent circuit diagram of pixel PXij connected by the i-th data line DLi (hereinafter referred to as data line DLi) among the data lines DL1 to DLm, the j-th scan lines GILj, GCLj and GWLj among the scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, the (j+1)-th scan line GWLj+1 (hereinafter referred to as scan line GILj, scan line GCLj, scan line GWLj and scan line GWLj+1 respectively), and the j-th light emission control line EMLj (hereinafter referred to as light emission control line EMLj) among the light emission control lines EML1 to EMLn.

[0099] Figure 4 Each of the plurality of pixels PX shown may have the same as Figure 5The equivalent circuit diagrams of the pixel PXij shown are configured substantially the same. In this embodiment, the pixel circuit PXC of pixel PXij may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Among the first transistors T1 to the seventh transistors T7, each of the third transistor T3 and the fourth transistor T4 is an N-type transistor comprising an oxide semiconductor as its semiconductor layer, and each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is a P-type transistor comprising low-temperature polycrystalline silicon (“LTPS”) as its semiconductor layer. However, the present disclosure according to the present invention should not be limited thereto or thereby. In another embodiment, all of the first transistors T1 to the seventh transistor T7 may be either P-type or N-type transistors. According to another embodiment, at least one of the first transistors T1 to the seventh transistor T7 may be an N-type transistor, and the remainder of the first transistors T1 to the seventh transistor T7 may be P-type transistors. Furthermore, the circuit configuration of the pixel PX according to the present disclosure should not be limited to... Figure 5 The circuit configuration of pixel PXij is shown. Figure 5 The pixel circuit PXC shown is merely an example, and the configuration of the pixel circuit PXC can be changed.

[0100] Reference Figure 5 The pixel PXij of the display device DD may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a capacitor Cst, and at least one light-emitting diode ED. In this embodiment, the structure of a pixel PXij including a light-emitting diode ED will be described.

[0101] Scan lines GILj, GCLj, GWLj, and GWLj+1 can transmit scan signals GIj, GCj, GWj, and GWj+1 respectively, and the light emission control line EMLj can transmit the light emission control signal EMj. Data line DLi can transmit data signal Di. Data signal Di can have the same image signal RGB (refer to) input to the display device DD. Figure 4 The corresponding voltage levels are: the first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3, and the fourth driving voltage line VL4, which can respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1, and the second initialization voltage VINT2.

[0102] The first transistor T1 may include a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting diode ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 may receive the data signal Di transmitted by the data line DLi according to the switching operation of the second transistor T2, and may supply the drive current Id to the light-emitting diode ED.

[0103] The second transistor T2 may include a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line GWLj. The second transistor T2 may be turned on in response to a scan signal GWj applied to it via the scan line GWLj, and may transmit a data signal Di applied to it via the data line DLi to the first electrode of the first transistor T1.

[0104] The third transistor T3 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the scan line GCLj. The third transistor T3 may be turned on in response to a scan signal GCj applied to it via the scan line GCLj, and the gate electrode and the second electrode of the first transistor T1 may be connected to each other to allow the first transistor T1 to be connected in a diode configuration.

[0105] The fourth transistor T4 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third drive voltage line VL3 that transmits the first initialization voltage VINT1, and a gate electrode connected to the scan line GILj. The fourth transistor T4 may be turned on in response to a scan signal GIj applied to it via the scan line GILj, and may transmit the first initialization voltage VINT1 to the gate electrode of the first transistor T1 to perform an initialization operation that initializes the voltage of the gate electrode of the first transistor T1.

[0106] The fifth transistor T5 may include a first electrode connected to the first drive voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the light emission control line EMLj.

[0107] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode ED, and a gate electrode connected to the light-emitting control line EMLj.

[0108] The fifth transistor T5 and the sixth transistor T6 can be turned on substantially simultaneously in response to the light emission control signal EMj applied to them via the light emission control line EMLj, and the first drive voltage ELVDD can be compensated by the first transistor T1 connected in a diode configuration and can be transmitted to the light emission diode ED.

[0109] The seventh transistor T7 may include a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth drive voltage line VL4, and a gate electrode connected to the scan line GWLj+1. The seventh transistor T7 may be turned on in response to a scan signal GWj+1 applied to it via the scan line GWLj+1, and may bypass the current of the anode of the light-emitting diode ED to the fourth drive voltage line VL4.

[0110] As described above, one end of capacitor Cst can be connected to the gate electrode of the first transistor T1, and the other end of capacitor Cst can be connected to the first driving voltage line VL1. The cathode of the light-emitting diode ED can be connected to the second driving voltage line VL2, which transmits the second driving voltage ELVSS. The structure of pixel PXij according to the present invention should not be limited to... Figure 5 The structure shown can be varied in various ways, including the number of transistors, capacitors, and connections included in a pixel PXij.

[0111] Figure 6 It is shown Figure 5 The timing diagram shows the operation of pixel PXij. (Refer to...) Figure 5 and Figure 6 Describe in detail the operation of pixel PXij on display device DD.

[0112] Reference Figure 5 and Figure 6 During the initialization period within a frame Fs, a high-level scan signal GIj is provided via scan line GILj. The fourth transistor T4 is turned on in response to the high-level scan signal GIj, and the first initialization voltage VINT1 is applied to the gate electrode of the first transistor T1 via the fourth transistor T4, thus initializing the first transistor T1.

[0113] Then, when a high-level scan signal GCj is provided via scan line GCLj during the data programming and compensation period, the third transistor T3 is turned on. The first transistor T1 is connected via the turned-on third transistor T3 in a diode configuration and is forward biased. Furthermore, the second transistor T2 is turned on in response to a low-level scan signal GWj. Then, a compensation voltage Di-Vth, equal to the value of the data signal Di provided via data line DLi minus the threshold voltage Vth of the first transistor T1, is applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 can be the compensation voltage Di-Vth.

[0114] The first driving voltage ELVDD and the compensation voltage Di-Vth are applied to the opposite ends of the capacitor Cst, and the capacitor Cst can be charged with a charge corresponding to the voltage difference between the opposite ends of the capacitor Cst.

[0115] The seventh transistor T7 is turned on in response to a low-level scan signal GWj+1 applied to it via scan line GWLj+1. A portion of the drive current Id is bypassed to the fourth drive voltage line VL4 by the seventh transistor T7. This portion of the drive current Id is the bypass current Ibp flowing through the seventh transistor T7.

[0116] When the light-emitting diode (LED) emits light even when the minimum current required to display a black image (Id) flows through the first transistor T1, the black image is not displayed correctly. Accordingly, the seventh transistor T7 of the pixel PXij, according to the embodiment, can allocate a portion of the minimum current of the first transistor T1 to a current path other than the current path of the LED as a bypass current Ibp. In this embodiment, the minimum current of the first transistor T1 means the current under the condition that the gate-source voltage of the first transistor T1 (i.e., the voltage difference between the gate electrode and the first electrode) is less than the threshold voltage Vth and the first transistor T1 is turned off. In this way, the minimum drive current Id under the condition that the first transistor T1 is turned off, for example, a current less than about 10 picoamperes (pA), is transmitted to the LED and displayed as an image with black brightness. When the minimum drive current Id for displaying a black image flows, the effect of the bypass current Ibp is large; however, when a large drive current Id flows for displaying images such as general images or white images, the effect of the bypass current Ibp is almost negligible. Accordingly, when the drive current Id for displaying a black image flows, the luminous current Ied of the light-emitting diode ED, which is the result of subtracting the bypass current Ibp passing through the seventh transistor T7 from the drive current Id, has a minimum current level sufficient to clearly display a black image. Consequently, contrast can be improved by using the seventh transistor T7 to provide an accurate black luminance image. In this embodiment, the bypass signal corresponds to the scan signal GWj+1 with a low level; however, it should not be limited to or constrained by this.

[0117] Then, during the light-emitting period, the level of the light-emitting control signal EMj provided from the light-emitting control line EMLj changes from high to low. During the light-emitting period, in response to the low-level light-emitting control signal EMj, the fifth transistor T5 and the sixth transistor T6 are turned on. As a result, a drive current Id is generated due to the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD. The drive current Id is supplied to the light-emitting diode ED via the sixth transistor T6, and therefore, the light-emitting current Ied flows through the light-emitting diode ED.

[0118] Figure 7 It is shown Figure 4 The block diagram of the first drive circuit 300 shown is shown.

[0119] Reference Figure 7 The first driving circuit 300 may include a light-emitting driving circuit 310, a first scanning driving circuit 320, a second scanning driving circuit 330, and a third scanning driving circuit 340.

[0120] In response to the first scan control signal SCS1, the light-emitting driving circuit 310 can output light-emitting control signals EM1 to EMk, which will be applied to... Figure 4 The light emission control lines EML1 to EMLn are shown in the diagram. In this embodiment, "k" is a natural number, and "n" can be greater than "k" (n>k). That is, each of the light emission control signals EM1 to EMk can be applied to one or more corresponding light emission control lines among the light emission control lines EML1 to EMLn.

[0121] In response to the first scan control signal SCS1, the first scan drive circuit 320 can output scan signals GI1 to GIk, and the scan signals GI1 to GIk will be applied to... Figure 4 The scan lines GIL1 to GILn are shown in the diagram. In this embodiment, "k" is a natural number, and "n" can be greater than "k" (n>k). That is, each of the scan signals GI1 to GIk can be applied to one or more corresponding scan lines among the scan lines GIL1 to GILn.

[0122] In response to the first scan control signal SCS1, the second scan drive circuit 330 can output scan signals GC1 to GCs, which will be applied to... Figure 4 The scan lines GCL1 to GCLn are shown in the diagram. In this embodiment, "s" is a natural number, and "n" can be greater than "s" (n>s). That is, each of the scan signals GC1 to GCs can be applied to one or more corresponding scan lines among the scan lines GCL1 to GCLn.

[0123] In response to the first scan control signal SCS1, the third scan drive circuit 340 can output scan signals GW1 to GWn+1, which will be applied to the following respectively: Figure 4 The scan lines shown are GWL1 to GWLn+1.

[0124] Figure 8 It is shown Figure 4 The block diagram of the second drive circuit 400 shown is shown.

[0125] Reference Figure 8 The second driving circuit 400 may include a light-emitting driving circuit 410, a first scanning driving circuit 420, a second scanning driving circuit 430, and a third scanning driving circuit 440.

[0126] In response to the second scan control signal SCS2, the light-emitting driving circuit 410 can output light-emitting control signals EM1 to EMk, which will be applied to... Figure 4 The light emission control lines EML1 to EMLn are shown in the diagram.

[0127] In response to the second scan control signal SCS2, the first scan drive circuit 420 can output scan signals GI1 to GIk, which will be applied to... Figure 4 The scan lines shown are GIL1 to GILn.

[0128] In response to the second scan control signal SCS2, the second scan drive circuit 430 can output scan signals GC1 to GCs, which will be applied to... Figure 4 The scan lines GCL1 to GCLn are shown in the diagram.

[0129] In response to the second scan control signal SCS2, the third scan drive circuit 440 can output scan signals GW1 to GWn+1, which will be applied to the following respectively: Figure 4 The scan lines shown are GWL1 to GWLn+1.

[0130] Figure 9 It is shown Figure 7 The first drive circuit 300 shown and Figure 8 The block diagram of the second drive circuit 400 shown is shown.

[0131] Reference Figures 7 to 9 Pixels PX11 to PX14, PX21 to PX24, PX31 to PX34, PX41 to PX44, PX51 to PX54, PX61 to PX64, PX71 to PX74, and PX81 to PX84 are arranged as examples in a portion of the display area DA.

[0132] Figure 9 Thirty-two pixels are shown arranged in an eight-row, four-column matrix (i.e., an arrangement of eight pixels in the second direction DR2 and four pixels in the first direction DR1). However, the number of pixels arranged in the display area DA can be varied in various ways.

[0133] Each of pixels PX11, PX23, PX31, PX43, PX51, PX63, PX71, and PX83 is a first color pixel, such as a red pixel; each of pixels PX13, PX21, PX33, PX41, PX53, PX61, PX73, and PX81 is a second color pixel, such as a blue pixel; and each of pixels PX12, PX14, PX22, PX24, PX32, PX34, PX42, PX44, PX52, PX54, PX62, PX64, PX72, PX74, PX82, and PX84 is a third color pixel, such as a green pixel.

[0134] The first driving circuit 300 includes a light-emitting driving circuit 310 comprising light-emitting stages EMD1 to EMD2. The first scanning driving circuit 320 of the first driving circuit 300 includes first scanning stages GID1 to GID2. The second scanning driving circuit 330 of the first driving circuit 300 includes second scanning stages GCD1 to GCD4. The third scanning driving circuit 340 of the first driving circuit 300 includes third scanning stages GWD1 to GWD8.

[0135] Each of the luminescent stages EMD1 to EMD2 can drive pixels arranged in four rows. For example, luminescent stage EMD1 can drive pixels PX11 to PX14, PX21 to PX24, PX31 to PX34, and PX41 to PX44. Luminescent stage EMD2 can drive pixels PX51 to PX54, PX61 to PX64, PX71 to PX74, and PX81 to PX84.

[0136] Each of the first scan levels GID1 to GID2 can drive pixels arranged in four rows. For example, the first scan level GID1 can drive pixels PX11 to PX14, PX21 to PX24, PX31 to PX34, and PX41 to PX44 arranged in the first four rows. The first scan level GID2 can drive pixels PX51 to PX54, PX61 to PX64, PX71 to PX74, and PX81 to PX84 arranged in the second four rows. Each of the second scan levels GCD1 to GCD4 can drive pixels arranged in two rows. For example, the second scan level GCD1 can drive pixels PX11 to PX14 and PX21 to PX24 arranged in the first two rows. The second scan level GCD2 can drive pixels PX31 to PX34 and PX41 to PX44 arranged in the second two rows.

[0137] Each of the third scan levels GWD1 through GWD8 can drive pixels arranged in a row. For example, the third scan level GWD1 can drive pixels PX11 through PX14 arranged in the first row. The third scan level GWD2 can drive pixels PX21 through PX24 arranged in the second row.

[0138] Each of the light-emitting stages EMD1 and EMD2, the first scan stages GID1 and GID2, and the second scan stages GCD1 to GCD4 may have substantially the same length in the second direction DR2. According to an embodiment, each of the light-emitting stages EMD1 and EMD2, the first scan stages GID1 and GID2, and the second scan stages GCD1 to GCD4 may have substantially the same circuit area.

[0139] The length of each of the third scan levels GWD1 to GWD8 in the second direction DR2 may be half (1 / 2) the length of each of the second scan levels GCD1 to GCD4 in the second direction DR2.

[0140] The light-emitting driving circuit 410 of the second driving circuit 400 may include light-emitting stages EMS1 to EMS2. The first scanning driving circuit 420 of the second driving circuit 400 may include first scanning stages GIS1 to GIS2. The second scanning driving circuit 430 of the second driving circuit 400 may include second scanning stages GCS1 to GCS4. The third scanning driving circuit 440 of the second driving circuit 400 may include third scanning stages GWS1 to GWS8.

[0141] Each of the luminous levels EMS1 to EMS2 is a driveable pixel arranged in four rows.

[0142] Each driveable pixel in the first scan level GIS1 to GIS2 is arranged in four rows.

[0143] Each of the driven pixels in the second scan levels GCS1 to GCS4 is arranged in two rows.

[0144] Each of the driveable pixels in the third scan levels GWS1 to GWS8 is arranged in a row.

[0145] Each of the light-emitting stages EMS1 and EMS2, the first scanning stages GIS1 and GIS2, and the second scanning stages GCS1 to GCS4 may have substantially the same length in the second direction DR2. According to an embodiment, each of the light-emitting stages EMS1 and EMS2, the first scanning stages GIS1 and GIS2, and the second scanning stages GCS1 to GCS4 may have substantially the same circuit area.

[0146] The length of each of the third scan levels GWS1 to GWS8 in the second direction DR2 may be half (1 / 2) the length of each of the second scan levels GCS1 to GCS4 in the second direction DR2.

[0147] exist Figure 9 In the illustrated embodiment, the first scan levels GID1 to GID2 and the second scan levels GCD1 to GCD4 may have independent circuit configurations. Furthermore, the first scan levels GIS1 to GIS2 and the second scan levels GCS1 to GCS4 may have independent circuit configurations.

[0148] Figure 10 The first driving circuit 300 is shown with light emission levels EMD1 to EMD7, first scan levels GID1 to GID7, and second scan levels GCD1 to GCD14.

[0149] Reference Figure 9 and Figure 10 The first driving circuit 300 also includes masking circuits MS11, MS12, MS21 and MS22.

[0150] The first masking circuit MS11 responds to the first masking signal MSK1 and the second masking signal MSK2, and selectively outputs the scan signal GI3 from the third first scan level GID3 as a masking carry signal for the fourth first scan level GID4.

[0151] The second masking circuit MS12 responds to the first masking signal MSK1 and the second masking signal MSK2, and selectively outputs the scan signal GI6 from the sixth first scan level GID6 as a masking carry signal for the seventh first scan level GID7.

[0152] The third masking circuit MS21 responds to the third masking signal MSK3 and the fourth masking signal MSK4, and selectively outputs the scan signal GC6 from the sixth second scan level GCD6 as a masking carry signal for the seventh second scan level GCD7.

[0153] The fourth masking circuit MS22 responds to the third masking signal MSK3 and the fourth masking signal MSK4, and selectively outputs the scan signal GC12 from the twelfth second scan level GCD12 as a masking carry signal for the thirteenth second scan level GCD13.

[0154] Each of the light-emitting stages EMD1 to EMD7 receives a first clock signal CLK1, a second clock signal CLK2, and a carry signal, and outputs a corresponding light-emitting control signal. Each of the light-emitting control signals EM1 to EM7 can be jointly applied to pixels PX arranged in four consecutive rows along the second direction DR2. For example, the light-emitting control signal EM1 output from the first light-emitting stage EMD1 can be applied to pixels PX arranged in the first to fourth rows.

[0155] The first light-emitting stage EMD1 receives the start signal FLM_EM as a carry signal. Each of the other light-emitting stages EMD2 to EMD7 receives the light-emitting control signal output from the previous light-emitting stage as a carry signal. For example, the second light-emitting stage EMD2 receives the light-emitting control signal EM1 output from the first light-emitting stage EMD1 as a carry signal.

[0156] Each of the first scan levels GID1 to GID7 receives the first clock signal CLK1, the second clock signal CLK2, and the carry signal, and outputs the corresponding scan signal.

[0157] Each of the scan signals GI1 to GI7 can be jointly applied to a pixel PX arranged in four consecutive rows along the second direction DR2. For example, the scan signal GI1 output from the first scan level GID1 can be applied to the pixels PX arranged in the first to fourth rows.

[0158] The first scan level GID1 receives the start signal FLM_GI as a carry signal. The fourth scan level GID4 receives the mask carry signal output from the first masking circuit MS11. The seventh scan level GID7 receives the mask carry signal output from the second masking circuit MS12. Each of the first scan levels GID2, GID3, GID5, and GID6, other than the first scan levels GID1, GID4, and GID7, receives the scan signal output from the previous first scan level as a carry signal. For example, the second scan level GID2 receives the scan signal GI1 output from the first scan level GID1 as a carry signal.

[0159] Each of the second scan levels GCD1 to GCD14 receives the third clock signal CLK3, the fourth clock signal CLK4, and the carry signal, and outputs the corresponding scan signal.

[0160] Each of the scan signals GC1 to GC14 can be jointly applied to pixels PX arranged in two consecutive rows along the second direction DR2. For example, scan signal GC1 output from the first and second scan levels GCD1 can be applied to pixels PX arranged in the first and second rows.

[0161] The first second scan stage GCD1 receives the start signal FLM_GC as the carry signal. The seventh second scan stage GCD7 receives the masked carry signal output from the third masking circuit MS21. The thirteenth second scan stage GCD13 receives the masked carry signal output from the fourth masking circuit MS22. Each of the second scan stages GCD2 to GCD6, GCD8 to GCD12, and GCD14, excluding the second scan stages GCD1, GCD7, and GCD13, receives the scan signal output from the previous second scan stage as the carry signal. For example, the j-th (j is a natural number greater than 1) second scan stage GCDj receives the scan signal GCj-a output from the (ja)-th (a is a natural number) second scan stage GCDj-a as the carry signal. Figure 10 In the embodiment shown, "a" is 1.

[0162] exist Figure 10 In the first scan levels GID1 to GID7, masking circuits MS11 and MS12 are arranged for every three first scan levels, and masking circuits MS21 and MS22 are arranged for every six second scan levels GCD1 to GCD14. This disclosure according to the invention should not be limited to... Figure 10The embodiments shown can be modified in various ways, and the positions of masking circuits MS11, MS12, MS21, and MS22 can be changed. For example, the first masking circuit MS11 corresponds to the y-th (y is a natural number greater than 1) first scan level GIDy, and outputs the scan signal GIy from the y-th first scan level GIDy as a mask carry signal in response to the first masking signal MSK1 and the second masking signal MSK2. The (y+a)-th (a is a natural number) first scan level GIDy+a receives the mask carry signal (i.e., the scan signal GIy) output from the first masking circuit MS11 as a carry signal.

[0163] exist Figure 10 The third scan drive circuit 340 is not shown in the figure (see reference). Figure 7 The third scan level. However, the third scan level may have a configuration that is substantially the same as that of the first scan levels GID1 to GID7 and the second scan levels GCD1 to GCD14.

[0164] also, Figure 8 The second drive circuit 400 shown may have the same characteristics as... Figure 10 The circuit configuration of the first drive circuit 300 shown is similar to that of the circuit configuration shown.

[0165] Figure 11 This is a circuit diagram showing the third first scan level GID3 and the first masking circuit MS11 of the first driving circuit 300 according to an embodiment of the present disclosure.

[0166] Figure 11 It shows Figure 10 The third first scan level GID3 is shown among the first scan levels GID1 to GID7. Figure 10 Each of the first scan levels GID1, GID2, and GID4 through GID7 shown may have the same characteristics as... Figure 11 The circuit configuration of the third first scan level GID3 shown is essentially the same as that of the circuit configuration shown.

[0167] Figure 10 The masking circuits MS12, MS21, and MS22 shown may have the same characteristics as... Figure 11 The circuit configuration of the first masking circuit MS11 shown is essentially the same as that of the first masking circuit shown.

[0168] Reference Figure 11The third first scan stage GID3 includes a first input terminal IN1, a second input terminal IN2 and a third input terminal IN3, a first voltage terminal V1 and a second voltage terminal V2, a scan output terminal OUT1, transistors M1, M2, M3, M4-1, M4-2, M5, M6, M7, M8, M9, M10, M11 and M12, and capacitors NC1, NC2 and NC3. Each of transistors M1 to M12 is shown as a P-type transistor; however, the present disclosure according to the invention should not be limited thereto or thereby restricted. In another embodiment, all or some of transistors M1 to M12 may be N-type transistors.

[0169] The third first scan level GID3 receives the first clock signal CLK1, the second clock signal CLK2, and the carry signal CR2 via the first input terminal IN1 to the third input terminal IN3, and receives the first voltage VGL and the second voltage VGH via the first voltage terminal V1 and the second voltage terminal V2, respectively. The third first scan level GID3 outputs the scan signal GI3 via the scan output terminal OUT1. In this embodiment, the carry signal CR2 provided via the third input terminal IN3 is the scan signal GI2 output from the second first scan level GID2.

[0170] Figure 10 The first input terminal IN1 of some of the first scan levels GID1 to GID7 (e.g., odd scan levels) shown receives the first clock signal CLK1, and the second input terminal IN2 of the same scan levels GID1 to GID7 receives the second clock signal CLK2. Furthermore, Figure 10 The first input terminal IN1 of the remaining scan levels (e.g., even scan levels) of the first scan levels GID1 to GID7 shown receives the second clock signal CLK2, and the second input terminal IN2 of the remaining scan levels of the first scan levels GID1 to GID7 receives the first clock signal CLK1.

[0171] Transistor M1 is connected between the third input terminal IN3 and the first node N1 and includes a gate electrode connected to the first input terminal IN1. Transistor M2 is connected between the second voltage terminal V2 and the sixth node N6 and includes a gate electrode connected to the fourth node N4. Transistor M3 is connected between the sixth node N6 and the second input terminal IN2 and includes a gate electrode connected to the second node N2.

[0172] Transistors M4-1 and M4-2 are connected in series between the fourth node N4 and the first input terminal IN1. Each of transistors M4-1 and M4-2 includes a gate electrode connected to the first node N1. Transistor M5 is connected between the fourth node N4 and the first voltage terminal V1 and includes a gate electrode connected to the first input terminal IN1. Transistor M6 is connected between the third node N3 and the seventh node N7 and includes a gate electrode connected to the second input terminal IN2. Transistor M7 is connected between the seventh node N7 and the second input terminal IN2 and includes a gate electrode connected to the fifth node N5.

[0173] Transistor M8 is connected between the second voltage terminal V2 and the third node N3 and includes a gate electrode connected to the first node N1. Transistor M9 is connected between the second voltage terminal V2 and the scan output terminal OUT1 and includes a gate electrode connected to the third node N3. Transistor M10 is connected between the scan output terminal OUT1 and the first voltage terminal V1 and includes a gate electrode connected to the second node N2. Transistor M11 is connected between the fourth node N4 and the fifth node N5 and includes a gate electrode connected to the first voltage terminal V1. Transistor M12 is connected between the first node N1 and the second node N2 and includes a gate electrode connected to the first voltage terminal V1.

[0174] Capacitor NC1 is connected between the second voltage terminal V2 and the third node N3. Capacitor NC2 is connected between the fifth node N5 and the seventh node N7. Capacitor NC3 is connected between the sixth node N6 and the second node N2.

[0175] The first masking circuit MS11 includes a first masking transistor MT1 and a second masking transistor MT2, a first masking input terminal MIN1 and a second masking input terminal MIN2, and a carry output terminal OUT2.

[0176] The first masking circuit MS11 stops (or masks) the output of the carry signal CR3 in response to the first masking signal MSK1 applied to it via the first masking input terminal MIN1, and sets the carry signal CR3 to the first voltage VGL in response to the second masking signal MSK2 applied to it via the second masking input terminal MIN2.

[0177] The first masking transistor MT1 is connected between the scan output terminal OUT1 and the carry output terminal OUT2, and includes a gate electrode connected to the first masking input terminal MIN1. The second masking transistor MT2 is connected between the first voltage terminal V1 and the carry output terminal OUT2, and includes a gate electrode connected to the second masking input terminal MIN2.

[0178] When the first masking signal MSK1 provided through the first masking input terminal MIN1 is at a low level and the second masking signal MSK2 provided through the second masking input terminal MIN2 is at a high level, the first masking circuit MS11 can output a scan signal GI3 as a carry signal CR3.

[0179] When the first masking signal MSK1 provided through the first masking input terminal MIN1 is at a high level and the second masking signal MSK2 provided through the second masking input terminal MIN2 is at a low level, the first masking circuit MS11 may not output the scan signal GI3 as the carry signal CR3, and the carry signal CR3 may be maintained at the first voltage VGL.

[0180] Figure 12 This shows the output from the multi-frequency mode. Figure 10 The timing diagram shown is a sequence diagram of the scan signals GI3 to GI7 output by the first scan level GID3 to GID7, the scan signals GC6 to GC14 output by the second scan level GCD6 to GCD14, and the first masking signal MSK1 to the fourth masking signal MSK4. Figure 12 The scan signals GW6 to GW9 applied to scan lines GWL6 to GWL9 are also shown.

[0181] Reference Figure 10 , Figure 11 and Figure 12 When the first masking signal MSK1 provided through the first masking input terminal MIN1 is at a low level and the second masking signal MSK2 provided through the second masking input terminal MIN2 is at a high level, the first masking circuit MS11 can output a scan signal GI3 as a carry signal CR3. Accordingly, scan signals GI3 to GI6 can be activated sequentially at high levels.

[0182] Furthermore, when the third masking signal MSK3 is low and the fourth masking signal MSK4 is high, the third masking circuit MS21 can output a scan signal GC6 as a carry signal for the seventh second scan stage GCD7. Accordingly, scan signals GC6 to GC12 can be activated sequentially with high levels.

[0183] When the first masking signal MSK1 goes high and the second masking signal MSK2 goes low, the second masking circuit MS12 may not output the scan signal GI6 as a carry signal for the seventh first scan level GID7, and the carry signal output from the second masking circuit MS12 may be maintained at the first voltage VGL. Correspondingly, the scan signal GI7 output from the seventh first scan level GID7 may be maintained at a low level.

[0184] Furthermore, when the third masking signal MSK3 goes high and the fourth masking signal MSK4 goes low, the fourth masking circuit MS22 may not output the scan signal GC12 as a carry signal for the thirteenth second scan stage GCD13, and the carry signal output from the fourth masking circuit MS22 may be maintained at the first voltage VGL. Correspondingly, the scan signals GC13 and GC14 output from the second scan stages GCD13 and GCD14 may be maintained at a low level.

[0185] As described above, Figure 1 The lengths of the first display area DA1 and the second display area DA2 shown in the second direction DR2 can be adjusted according to the levels of the first masking signal MSK1 to the fourth masking signal MSK4.

[0186] Figure 13A and Figure 13B This is a timing diagram showing the scan signals GI1 to GI3840 in multi-frequency mode.

[0187] Reference Figure 1 and Figure 13A The frequencies of the scan signals GI1 to GI1920 in the multi-frequency mode MFM are approximately 120 Hz, and the frequencies of the scan signals GI1921 to GI3840 in the multi-frequency mode MFM are approximately 1 Hz.

[0188] For example, scan signals GI1 to GI1920 correspond to Figure 1 The first display area DA1 of the display device DD shown is shown, and the scan signals GI1921 to GI3840 correspond to the second display area DA2.

[0189] Scan signals GI1 to GI1920 are activated at a high level in each of the first frame F1 to the 120th frame F120, and scan signals GI1921 to GI3840 are activated at a high level only in the first frame F1.

[0190] Accordingly, the first display area DA1, displaying moving images, is driven in response to scan signals GI1 to GI1920 at a normal frequency (e.g., about 120 Hz), and the second display area DA2, displaying still images, is driven in response to scan signals GI1921 to GI3840 at a low frequency (e.g., about 1 Hz). Since only the second display area DA2, displaying still images, is driven at a low frequency, the display device DD (refer to...) Figure 1 The power consumption can be reduced without degrading the display quality.

[0191] Figure 13A Only scan signals GI1 to GI3840 are shown; however, Figure 7The light-emitting driving circuit 310, the second scanning driving circuit 330, and the third scanning driving circuit 340 shown are as follows: Figure 8 The light-emitting driving circuit 410, the second scanning driving circuit 430 and the third scanning driving circuit 440 shown can generate scanning signals GC1 to GC3840 and GW1 to GW3841 similar to scanning signals GI1 to GI3840, as well as light-emitting control signals EM1 to EM3840.

[0192] Reference Figure 1 and Figure 13B In the multi-frequency mode (MFM), the frequency of scan signals GI1 to GI1300 is approximately 120 Hz, and the frequency of scan signals GI1301 to GI3840 is approximately 1 Hz.

[0193] For example, scan signals GI1 to GI1300 correspond to Figure 1 The first display area DA1 of the display device DD shown is shown, and the scan signals GI1301 to GI3840 correspond to the second display area DA2.

[0194] Scan signals GI1 to GI1300 are activated at a high level in each of the first frame F1 to the 120th frame F120, and scan signals GI1301 to GI3840 are activated at a high level only in the first frame F1.

[0195] Accordingly, the first display area DA1, displaying moving images, is driven in response to scan signals GI1 to GI1300 at a normal frequency (e.g., about 120 Hz), and the second display area DA2, displaying still images, is driven in response to scan signals GI1301 to GI3840 at a low frequency (e.g., about 1 Hz). Since only the second display area DA2, displaying still images, is driven at a low frequency, the display device DD (refer to...) Figure 1 The power consumption can be reduced without degrading the display quality.

[0196] like Figure 13A and Figure 13B As shown, the size of the first display area DA1 driven at a normal frequency and the size of the second display area DA2 driven at a low frequency can vary. Figure 13B As shown, when the size of the second display area DA2, which is driven at a low frequency, increases, the power consumption of the display device DD can be reduced even more.

[0197] Figure 14 This is a circuit diagram showing the third first scan level GID3' and the first masking circuit MS11 in the first driving circuit 300 according to an embodiment of the present disclosure.

[0198] Figure 14The third first scan level GID3' shown has the same Figure 11 The circuit configuration of the third first scan level GID3 shown is similar to that of the circuit configuration shown, and also includes transistor M13 and fourth input terminal IN4.

[0199] Transistor M13 is connected between the second voltage terminal V2 and the second node N2 and includes a gate electrode connected to the fourth input terminal IN4. The fourth input terminal IN4 receives a reset signal ESR. The reset signal ESR may be included from... Figure 4 The signals provided by the drive controller 100 shown are the first scan control signal SCS1 and the second scan control signal SCS2.

[0200] The reset signal ESR is activated at a low level when the display device DD is powered on or reset. When the reset signal ESR is low, transistor M13 is turned on, and therefore, the first node N1 and the second node N2 remain at the voltage level of the second voltage VGH, i.e., high. Accordingly, since transistors M3, M4-1, M4-2, M8, and M10 remain in the off state, it is possible to prevent the scan signal GI3 output to the scan output terminal OUT1 from being output at an undesirable level.

[0201] Although embodiments of this disclosure have been described, it is to be understood that this disclosure based on the invention should not be limited to these embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the appended and claimed disclosure. Accordingly, the subject matter disclosed should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined according to the appended claims.

Claims

1. A driving circuit, comprising: Multiple scan levels, each corresponding to multiple scan lines, receive clock signals and carry signals, and output scan signals; as well as Multiple masking circuits, each corresponding to a certain scan level among the multiple scan levels. Each of the plurality of scan levels includes: The output terminal outputs the scan signal; and The first voltage terminal receives the first voltage. Each of the plurality of masking circuits includes: Carry output terminal; A first transistor, connected between the output terminal and the carry output terminal of the corresponding scan stage, and including a gate electrode connected to a first masking input terminal receiving a first masking signal; and The second transistor is connected between the carry output terminal and the first voltage terminal of the corresponding scan stage, and includes a gate electrode connected to the second masking input terminal for receiving the second masking signal. Each of the plurality of masking circuits, in response to a first masking signal and a second masking signal, selectively outputs i) one of the scan signal output from the corresponding scan stage and ii) the first voltage as a masking carry signal via the carry output terminal. Among the plurality of scan levels, the j-th scan level is: i) When the (ja)th scan level is not one of the scan levels, receive the scan signal output from the (ja)th scan level as the carry signal, and ii) When the (ja)th scan level is one of the scan levels, the masking carry signal output from the masking circuit corresponding to the (ja)th scan level is received as the carry signal, and the masking circuit corresponding to the (ja)th scan level is connected only between the jth scan level and the (ja)th scan level among the plurality of scan levels. Where j is a natural number greater than 1, and a is a natural number less than j.

2. The driving circuit as described in claim 1, wherein, When the first masking signal has a first level and the second masking signal has a second level, each of the plurality of masking circuits outputs the scan signal output from the corresponding scan level as the masking carry signal; and when the first masking signal has the second level and the second masking signal has the first level, each of the plurality of masking circuits does not output the scan signal output from the corresponding scan level as the masking carry signal.

3. The driving circuit as described in claim 1, wherein, When the first masking signal has a second level and the second masking signal has a first level, each of the plurality of masking circuits maintains the first voltage as the masking carry signal.

4. A display device, comprising: The display panel includes multiple data lines, multiple first scan lines, and multiple pixels connected to the multiple data lines and the multiple first scan lines; Data driving circuit, driving the plurality of data lines; The driving circuit includes a first scan driving circuit that drives the plurality of first scan lines; as well as A drive controller controls the data drive circuit and the drive circuit to drive a first display area of ​​the display panel at a first drive frequency during a multi-frequency mode and to drive a second display area of ​​the display panel at a second drive frequency during the multi-frequency mode. The first scan driving circuit includes multiple first scan stages, each of which corresponds to some of the multiple first scan lines, receives a clock signal and a carry signal, and outputs a first scan signal. The driving circuit also includes multiple masking circuits, each of which corresponds to a certain first scan level among the multiple first scan levels. Each of the plurality of first scan levels includes: The output terminal outputs the first scan signal; and The first voltage terminal receives the first voltage. Each of the plurality of masking circuits includes: Carry output terminal; A first transistor, connected between the output terminal and the carry output terminal of the corresponding first scan stage, and including a gate electrode connected to a first masking input terminal for receiving a first masking signal; and The second transistor is connected between the carry output terminal and the first voltage terminal of the corresponding first scan stage, and includes a gate electrode connected to the second masking input terminal for receiving the second masking signal. Each of the plurality of masking circuits, in response to a first masking signal and a second masking signal, selectively outputs i) one of the first scan signal output from the corresponding first scan stage and ii) the first voltage as a masking carry signal via the carry output terminal. The j-th first scan level among the plurality of first scan levels: i) When the first scan level (ja) is not one of the said first scan levels, receive the first scan signal output from the first scan level (ja) as the carry signal, and ii) When the (ja)th first scan level is one of the plurality of first scan levels, the masking carry signal output from the masking circuit corresponding to the (ja)th first scan level is received as the carry signal, and the masking circuit corresponding to the (ja)th first scan level is connected only between the jth first scan level and the (ja)th first scan level among the plurality of first scan levels. Where j is a natural number greater than 1, and a is a natural number less than j.

5. The display device as claimed in claim 4, wherein, The masking circuit corresponds to the y-th first scan level among the plurality of first scan levels and outputs the first scan signal from the y-th first scan level in response to the masking signal as the y-th carry signal, and the (y+a)-th first scan level among the plurality of first scan levels receives the y-th carry signal output from the corresponding masking circuit as the carry signal, and y is a natural number greater than 1.

6. The display device as claimed in claim 4, wherein, When the first masking signal has a first level and the second masking signal has a second level, each of the plurality of masking circuits outputs the first scan signal output from the corresponding first scan level as the masking carry signal; and when the first masking signal has the second level and the second masking signal has the first level, each of the plurality of masking circuits does not output the first scan signal output from the corresponding first scan level as the masking carry signal.

7. The display device as claimed in claim 6, wherein, When the first masking signal has the second level and the second masking signal has the first level, each of the plurality of masking circuits maintains the first voltage as the masking carry signal.

Images