Semiconductor memory devices and their layout and local rescue methods

Abstract

This application relates to semiconductor memory devices and their layouts, as well as localized rescue methods thereof. A semiconductor memory device includes: a plurality of planes defined in a plurality of chip regions; and a rescue circuit configured to disable a faulty plane among the plurality of planes and enable a normal plane among the plurality of planes, wherein the semiconductor memory device operates only using the enabled normal planes.

Description

TECHNICAL FIELD

[0001] Various embodiments relate generally to semiconductor technology, and more particularly, to a semiconductor memory device and a partial rescue method thereof. BACKGROUND

[0002] A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Semiconductor memory devices are generally classified into volatile memory devices and non-volatile memory devices.

[0003] A volatile memory device is a memory device whose stored data is lost when power is interrupted. Examples of the volatile memory device include SRAM (static RAM), DRAM (dynamic RAM), and SDRAM (synchronous DRAM). A non-volatile memory device is a memory device that retains stored data even when power is interrupted. Examples of the non-volatile memory device include ROM (read only memory), PROM (programmable ROM), EPROM (electrically programmable ROM), EEPROM (electrically erasable programmable ROM), flash memory, PRAM (phase change RAM), MRAM (magnetic RAM), RRAM (resistive RAM), and FRAM (ferroelectric RAM).

[0004] Examples of devices using non-volatile memory include MP3 players, digital cameras, mobile phones, camcorders, flash memory cards, and solid state disks (SSDs). As the number of devices using non-volatile memory as a storage device increases, the capacity of non-volatile memory is rapidly increasing. SUMMARY

[0005] Various embodiments relate to a semiconductor memory device and a partial rescue method thereof capable of improving yield.

[0006] In an embodiment, a semiconductor memory device can include a plurality of planes defined in a plurality of chip regions, and a rescue circuit configured to disable a faulty plane among the plurality of planes and enable a normal plane among the plurality of planes, wherein the semiconductor memory device operates only with the enabled normal plane.

[0007] In an embodiment, a rescue method of a semiconductor memory device including a plurality of planes can include obtaining a status signal of each of the plurality of planes indicating whether a fault exists in each of the plurality of planes by individually testing each of the plurality of planes for a fault, and controlling whether each of the plurality of planes is enabled based on the status signal of each of the plurality of planes such that a faulty plane is disabled and a normal plane is enabled.

[0008] In an embodiment, a layout of a semiconductor memory device includes: a plurality of chip regions, each of the plurality of chip regions including a plurality of planes arranged in a first direction; a main pad region extending in a second direction perpendicular to the first direction and including a plurality of main pads arranged in the second direction; a plurality of sub-pad regions, each of the plurality of sub-pad regions extending in the second direction and including a plurality of sub-pads arranged in the second direction; wherein each of the plurality of planes corresponds to one of the plurality of main pads; wherein each of the plurality of planes is directly connected to at least one of the plurality of sub-pads, the at least one sub-pad being connected to a respective one of the main pads by a redistribution line; and wherein a width of the main pad region in the first direction is greater than a width of the sub-pad region in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is an exemplary block diagram illustrating Figure 1 one of the chip regions included in

[0011] Figure 3 is an equivalent circuit diagram of a memory block included in a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 4A and Figure 4B is an exemplary cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 5 is a top view illustrating a layout of a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 6 is an exemplary top view illustrating a redistribution line coupling Figure 5 a main pad and a sub-pad of

[0015] Figures 7A to 7C is a top view illustrating a semiconductor memory device according to other embodiments of the present disclosure.

[0016] Figure 8 is a flowchart illustrating a partial rescue method of a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 9 part (a) of is an exemplary top view illustrating a semiconductor memory device different from an embodiment of the present disclosure, and Figure 9FIG. 1 is a block diagram schematically illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 10 FIG. 1 is a block diagram schematically illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0019] Figure 11 FIG. 1 is a block diagram schematically illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Advantages and features of the present disclosure and methods of achieving them will become apparent from the description of example embodiments given hereinafter and the accompanying drawings. However, the present disclosure is not limited to the example embodiments disclosed herein but can be implemented in various different ways. The example embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0021] Because the figures, sizes, ratios, angles, numbers, and the like of elements given in the drawings accompanying the description of the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to the illustrated matters. Throughout the specification, like reference numerals refer to like components. In describing the present disclosure, detailed descriptions of related technologies will be omitted when it is determined that such detailed descriptions can obscure the gist or clarity of the present disclosure. It should be understood that the terms "include", "have", "comprise" and the like used in the specification and claims should not be interpreted as limiting to the means listed thereafter, unless otherwise explicitly stated. When an indefinite article or a definite article (for example, "a", "an", or "the") is used with reference to a singular noun, unless otherwise explicitly stated, the article can include a plural form of the noun.

[0022] In interpreting elements in the embodiments of the present disclosure, they should be interpreted to include error margins even if not explicitly mentioned.

[0023] In addition, in describing components of the present disclosure, terms such as first, second, A, B, (a), and (b) can be used. These are only to distinguish one component from another component, and do not limit the substance, order, sequence, or number of the components. In addition, the components in the embodiments of the present disclosure are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, as used herein, a first component can be a second component within the technical spirit of the present disclosure.

[0024] If a component is described as being "connected," "coupled," or "linked" to another, it can be interpreted that the component is not only directly "connected," "coupled," or "linked" to the other but also indirectly "connected," "coupled," or "linked" to the other via a third component. In describing positional relationships such as "element A on element B," "element A above element B," "element A below element B," and "element A next to element B," unless the terms "directly" or "immediately" are explicitly used, one or more other elements can be positioned between elements A and B.

[0025] Features of various exemplary embodiments of the present disclosure can be partially or wholly coupled, combined, or separated. Various interactions and operations are technically feasible. Various exemplary embodiments can be practiced individually or in combination.

[0026] Hereinafter, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0028] Referring to Figure 1 A semiconductor memory device according to an embodiment of the present disclosure can include a plurality of planes (Plane) defined in a plurality of chip regions (Chip) 10, and a rescue circuit 211 that disables a faulty plane among the plurality of planes (Plane) and enables a normal plane among the plurality of planes (Plane).

[0029] In more detail, the semiconductor memory device can include a plurality of chip regions 10 and a main pad region MP. Although Figure 1 Two chip regions 10 included in the semiconductor memory device are exemplified, but this is for the purpose of example only, and the number of chip regions 10 in an embodiment of the present disclosure can be three or more.

[0030] Each of the plurality of chip regions 10 can include a memory cell array 100 and a control circuit 200. The memory cell array 100 can include a plurality of planes (Plane), and the control circuit 200 can include a rescue circuit 211 and a plane state storage unit (MRS) 212. Although Figure 1 Two planes (Plane) included in one chip region 10 are exemplified, but this is for the purpose of example only, and the number of planes (Plane) included in one chip region 10 in an embodiment of the present disclosure can be one or at least three.

[0031] Although not shown, each plane (Plane) can include a plurality of memory blocks. As will be described later with reference to Figure 3

[0032] Hereinafter, a case where the memory cells of the device are flash memory cells will be described, but it is noted that the present disclosure is not limited thereto. In other embodiments, the memory cells can be resistive memory cells such as resistive RAM (ReRAM), phase-change RAM (PRAM), or magnetic RAM (MRAM).

[0033] A plurality of main pads 20 can be disposed in a main pad area MP. The semiconductor memory device can interface with an external device through the plurality of main pads 20. As will be described later with reference to Figure 6

[0034] The plurality of planes (Plane) included in the semiconductor memory device can be independently enabled or disabled under the control of a rescue circuit 211.

[0035] After the semiconductor memory device is manufactured, the plurality of planes (Plane) included in the semiconductor memory device can be individually tested to check whether there is a failure.

[0036] In the test mode, the rescue circuit 211 can individually enable the planes (Plane) in response to the plane enable signals input through the plane enable pads. Accordingly, each of the plurality of planes (Plane) can be independently tested for whether there is a failure.

[0037] In the test, whether there is a failure in the plane (Plane) can be monitored by writing data in the test target plane (Plane) and reading the written data. Alternatively, whether there is a failure in the plane (Plane) can also be monitored by checking the lifespan of the memory cells included in the test target plane (Plane). In the present disclosure, a specific test method is not prescribed, and any suitable test method can be utilized as long as it is capable of checking whether there is a failure in the plane. The test can be performed by an external device such as a controller or a test equipment. ​​

[0038] The plane status storage unit 212 can store a test result, i.e., a status signal (hereinafter referred to as a "plane status signal (Plane Status)") indicating whether there is a failure in each of the plurality of planes (Plane).

[0039] The plane status signal (Plane Status) can be, for example, 1-bit binary data. When the plane (Plane) is in a normal state, the plane status signal (Plane Status) of the corresponding plane can be set to a logical "1", and when the plane (Plane) is in a failure state, the plane status signal (Plane Status) of the corresponding plane can be set to a logical "0". The normal state refers to a state in which there is no failure or there is a partial failure but it can be repaired. The failure state refers to a state in which a fatal failure has occurred and it is not possible to repair.

[0040] The rescue circuit 211 can control whether to enable each plane (Plane) based on the plane status signal (Plane Status) stored in the plane status storage unit 212. When access to a specific plane (Plane) is requested by a command of an external system, the rescue circuit 211 can determine whether to enable the plane (Plane). For example, the rescue circuit 211 can determine whether there is a failure in the plane (Plane) to be accessed based on the plane status signal (Plane Status) of the corresponding plane. If the plane status signal (Plane Status) of the plane (Plane) to be accessed is a logical "1", the corresponding plane (Plane) is in a normal state and can be enabled. If the plane status signal (Plane Status) of the plane (Plane) to be accessed is a logical "0", the corresponding plane (Plane) is in a failure state, and the corresponding plane (Plane) can be disabled, and a different plane (Plane) in a normal state can be enabled.

[0041] Figure 2 is an example block diagram illustrating Figure 1 one chip region included in the memory device 1.

[0042] Referring to Figure 2 , the chip region 10 can include a memory cell array 100 and a control circuit 200.

[0043] As described above with reference to Figure 1 , the memory cell array 100 can include a plurality of planes (Plane), and each plane (Plane) can include a plurality of memory blocks.

[0044] The memory block can be coupled to the row decoder 210 through a word line WL, and can be coupled to the page buffer circuit 220 through a bit line BL. Later, a description will be made with reference to Figure 3 The memory block is described.

[0045] The control circuit 200 can include the row decoder 210 and the page buffer circuit 220.

[0046] The row decoder 210 can select a plane (Plane) to be accessed in response to a row address RADD, and can select an arbitrary one memory block from among the memory blocks included in the selected plane (Plane). The row decoder 210 can transfer an operation voltage to a word line WL coupled to the selected memory block.

[0047] The rescue circuit 211 and the plane status storage unit 212 can be included in the row decoder 210. However, this is for the purpose of example only, and the rescue circuit 211 and the plane status storage unit 212 can be provided separately from the row decoder 210.

[0048] The rescue circuit 211 can control the planes (Planes) based on the status signal (Plane Status) of each plane stored in the plane status storage unit 212, so that the planes (Planes) can be independently enabled or disabled.

[0049] In this way, by controlling the configuration of the planes (Planes), it is possible to independently enable or disable the planes. Therefore, if a certain plane has a failure, the plane is disabled to prevent the use of the failed plane, so that a semiconductor memory device that operates only with the remaining normal planes can be configured for partial rescue.

[0050] The page buffer circuit 220 can include a plurality of page buffers coupled to the bit lines BL, respectively. The page buffers can be coupled to the memory cell array 100 through the bit lines BL, and can detect data stored in the memory cells of the memory cell array 100 by sensing signals of the bit lines BL. The page buffers can apply signals to the bit lines BL based on the data signals DATA received therein, and thus can write data to the memory cells of the memory cell array 100.

[0051] Figure 3 is an equivalent circuit diagram of a memory block included in a semiconductor memory device according to an embodiment of the disclosure.

[0052] Referring to Figure 3 , the memory block BLK can include a plurality of cell strings CSTR coupled between a plurality of bit lines BL and a common source line CSL.

[0053] Each of the cell strings CSTR can be coupled between a corresponding bit line BL and a common source line CSL. Each of the cell strings CSTR can include a source select transistor SST coupled to the common source line CSL, a drain select transistor DST coupled to the bit line BL, and a plurality of memory cells MC coupled between the source select transistor SST and the drain select transistor DST. A gate of the source select transistor SST can be coupled to a source select line SSL. Gates of the memory cells MC can be coupled to corresponding word lines WL, respectively. A gate of the drain select transistor DST can be coupled to a drain select line DSL.

[0054] The source select lines SSL, the word lines WL, and the drain select lines DSL can be disposed in a direction perpendicular to the bit lines BL. The source select lines SSL, the word lines WL, and the drain select lines DSL can form a three-dimensional structure by being stacked in the vertical direction on a surface of a substrate.

[0055] The memory cells MC included in the memory block BLK can be divided into physical page units or logical page units. For example, the memory cells MC sharing one word line WL and coupled to different cell strings CSTR can configure one physical page PG. Such a page can be a basic unit of a read operation.

[0056] For example, Figure 3 One drain select transistor DST and one source select transistor SST are exemplified in each of the cell strings CSTR. However, it is noted that at least two drain select transistors or at least two source select transistors can be provided in each of the cell strings CSTR.

[0057] Figure 4A and Figure 4B is an exemplary cross-sectional view exemplifying a semiconductor memory device according to an embodiment of the disclosure.

[0058] Referring to Figure 4A In an embodiment, the semiconductor memory device can include a peripheral wafer PW and a cell wafer CW bonded to the peripheral wafer PW. The memory cell array 100 can be disposed in the cell wafer CW, and the control circuit 200 can be disposed in the peripheral wafer PW.

[0059] The chip regions 10 of the semiconductor memory device can be coupled to each other by scribe lanes SL. Each of the chip regions 10 can include the memory cell array 100 and the control circuit 200 disposed in a vertical direction one above the other.

[0060] In another embodiment, as Figure 4BAs shown, the semiconductor memory device can include a cell wafer CW, a first peripheral wafer PW1, and a second peripheral wafer PW2. Each control circuit 200 can be divided into a first circuit portion 200a and a second circuit portion 200b. The first circuit portion 200a of the control circuit 200 can be provided in the first peripheral wafer PW1, and the second circuit portion 200b of the control circuit 200 can be provided in the second peripheral wafer PW2.

[0061] Although Figure 4B The cell wafer CW bonded to the first peripheral wafer PW1 and the second peripheral wafer PW2 is illustrated, but this is for example purposes only. As another example, the first peripheral wafer can be bonded to the cell wafer, and the second peripheral wafer can be bonded to the first peripheral wafer.

[0062] As Figure 4A and Figure 4B shown, if the memory cell array 100 and the control circuit 200 are manufactured on separate wafers, the memory cell array 100 will not be affected by the manufacturing process of the control circuit 200, and the control circuit 200 will not be affected by the manufacturing process of the memory cell array 100. Thus, in selecting materials used in manufacturing the memory cell array 100 and the control circuit 200, the selection range becomes wider, and the materials can be selected considering performance and cost, which is advantageous in improving performance and reducing cost.

[0063] A laminate packaging technique is known in which a plurality of semiconductor memory devices are vertically laminated to form one package. The semiconductor memory devices have a structure in which a plurality of wafers are bonded and each have a large thickness, so it can be difficult to manufacture a large capacity package equal to or less than a thickness required in a specification. However, according to the embodiment of the disclosure, the chip region 10 included in the semiconductor memory device is horizontally coupled by a scribe lane SL. Thus, even if the height of the package is reduced by reducing the number of semiconductor memory devices to be laminated, a high capacity package such as in the example shown in Figure 4A and Figure 4B can be achieved.

[0064] Figure 5 is a top view illustrating a layout of a semiconductor memory device according to an embodiment of the disclosure. Figure 6 is an exemplary top view illustrating a redistribution line coupling Figure 5 a main pad and a sub pad. To simplify the illustration, the illustration of the sealing region is omitted in Figure 6

[0065] Referring to Figure 5 ​A sealing region SEAL can be formed at an edge of the semiconductor memory device. The plurality of chip regions 10 and the main pad region MP can be disposed in a region surrounded by the sealing region SEAL. The sealing region SEAL can be disposed to surround the plurality of chip regions 10 and the main pad region MP as constituent parts, and can function to protect the plurality of chip regions 10 and the main pad region MP.

[0066] The semiconductor memory device can be manufactured at a wafer level, and can be individualized by a wafer cutting process after being completely manufactured. A crack can occur when the wafer is cut. The crack can travel from an edge of the semiconductor memory device to the inside. The sealing region SEAL can function to inhibit or stop the crack from traveling, thereby preventing the chip regions 10 and the main pad region MP from being damaged by the crack. In addition, the sealing region SEAL can function to block the infiltration of moisture, thereby preventing the chip regions 10 from being damaged by the moisture.

[0067] The plurality of chip regions 10 and the main pad region MP can be disposed or arranged in the first direction FD within an inner region surrounded by the sealing region SEAL.

[0068] For example, the main pad region MP can be disposed at an edge of the inner region to have a shape extending in the second direction SD. In the main pad region MP, a plurality of main pads 20 can be arranged in the second direction SD, which can be an extension direction of the main pad region MP. Although not shown, an external coupling member such as a bump or a wire can be bonded to each of the main pads 20. That is, the main pads 20 are bonding pads to which the external coupling member is bonded. To allow the external coupling member to be bonded thereto, the main pads 20 have a minimum predetermined size.

[0069] Each of the plurality of chip regions 10 can include a plurality of planes (Plane) and a sub-pad region SP disposed in parallel with the plurality of planes (Plane). The plurality of planes (Plane) and the sub-pad region SP can be disposed in the first direction FD, and the sub-pad region SP can be configured to have a shape extending in the second direction SD. In the sub-pad region SP, a plurality of sub-pads 11 can be arranged in the second direction SD, which can be an extension direction of the sub-pad region SP. Each of the sub-pads 11 can be coupled to a corresponding main pad 20 by a redistribution line described below, and thus can be coupled to an external device through the corresponding main pad 20. Figure 6

[0070] ​The sub-pads 11 are non-bonding pads that are not engaged with external coupling members, and can have a size smaller than the main pads 20. Unlike the main pads 20 engaged to external coupling members such as bumps or wires, since no external coupling members are engaged to the sub-pads 11, the sub-pads 11 can be configured to have a size smaller than the main pads 20.

[0071] The width of the sub-pad area SP in the first direction FD can be smaller than the width of the main-pad area MP in the first direction FD. The width of the sub-pads 11 in the first direction FD can be smaller than the width of the main pads 20 in the first direction FD, which makes the sub-pad area SP for disposing the sub-pads 11 configured to have a width in the first direction FD smaller than the width of the main-pad area MP for disposing the main pads 20 in the first direction FD.

[0072] Referring to Figure 6 , each of the sub-pads 11 can be coupled to a corresponding main pad 20 through a redistribution line RDL.

[0073] The main pads 20 can include a plurality of plane enable pads. The plane enable pads can respectively correspond to planes (Plane) included in the semiconductor memory device, and a plane enable signal for enabling a corresponding plane (Plane) can be input to each plane enable pad. The plane enable pads can be disposed in the same number as the number of planes (Plane) included in the semiconductor memory device. Figure 6 A structure including four planes (Plane) is exemplified. In this case, four of the main pads 20 can be allocated as plane enable pads for inputting plane enable signals PE1 to PE4.

[0074] In addition to the plane enable pads, other main pads 20 can include, for example, a power supply pad (Vcc), a ground pad (Vss), control pads (nCE, CLE, ALE, nWE, etc.), and data pads (DQ0 to DQ7). Since these pads are well known in the art, detailed descriptions of these pads will be omitted.

[0075] Figures 7A to 7C is a top view illustrating a semiconductor memory device according to other embodiments of the present disclosure. For simplicity of illustration, the illustration of redistribution lines coupling the main pads and the sub-pads is omitted in Figures 7A to 7C

[0076] Referring to Figure 7A ​, the semiconductor memory device can include four chip regions 10. The main pad region MP can be configured at a central portion of the inner region surrounded by the sealing region SEAL to have a shape extending in the second direction SD. Two chip regions 10 can be disposed on each of two sides of the main pad region MP in the first direction FD.

[0077] Each chip region 10 can include four planes. The sub-pad region SP can be configured at a central portion of the chip region 10 to have a shape extending in the second direction SD. Two planes can be disposed on two sides of the sub-pad region SP in the first direction FD. The planes on one side of the sub-pad region SP can be disposed along the second direction SD. For example, the four planes in the chip region can be arranged in two rows and two columns, and the sub-pad region SP is arranged between the columns.

[0078] All chip regions 10 included in the semiconductor memory device can have substantially the same structure. In this example, the sub-pad layout structure of all chip regions 10 can be the same.

[0079] The chip regions 10 included in the semiconductor memory device do not necessarily have to have the same structure. As another example, some chip regions 10 can have a structure symmetrical to other chip regions. In this case, the sub-pad layout structure of some chip regions 10 and the sub-pad layout structure of other chip regions 10 can be symmetrical to each other.

[0080] For example, in Figure 7B , the chip region 10 located on the left side of the main pad region MP and the chip region 10 located on the right side of the main pad region MP can be symmetrical to each other across the main pad region MP. The sub-pads 11 of the chip region 10 located on the left side of the main pad region MP and the sub-pads 11 of the chip region 10 located on the right side of the main pad region MP can be located on opposite sides of a virtual line L-L' extending in the first direction FD.

[0081] Referring to Figure 7C , the sub-pad regions SP can be disposed outside the chip regions 10, and the chip regions 10 disposed on both sides of each sub-pad region SP in the first direction FD can be commonly coupled to one sub-pad region SP and share the one sub-pad region SP.

[0082] The semiconductor memory device can include a plurality of main pad regions MP. The number of main pad regions MP is less than the number of sub-pad regions SP. As an example, Figure 7C An example is illustrated in which the number of main pad regions MP is two and the number of sub-pad regions SP is four.

[0083] Figures 7A to 7C The structure of the semiconductor memory device shown is for the purpose of illustration only, and the structure of the semiconductor memory device according to the embodiments of the present disclosure can be changed in various ways.

[0084] Figure 8 is a flowchart illustrating a partial rescue method of a semiconductor memory device according to an embodiment of the present disclosure.

[0085] Referring to Figure 1 and Figure 8 , first, in a test mode, when a plurality of Planes are tested individually, a Plane Status of each Plane indicating whether there is a fault in each of the Planes can be obtained (S810).

[0086] At step S810, the rescue circuit 211 can independently enable a plurality of Planes in response to Plane enable signals input through Plane enable pads, respectively. Accordingly, each of the plurality of Planes can be tested for whether there is a fault. A Plane Status of each Plane obtained by the respective test can be stored in a Plane status storage unit 212.

[0087] Based on the Plane Status of each Plane, each Plane can be controlled such that a faulty Plane is disabled. Only the remaining normal Planes are enabled in step S820.

[0088] At step S820, an address is applied from the outside.

[0089] Thereafter, the rescue circuit 211 can discriminate, based on the Plane Status of each Plane stored in the Plane status storage unit 212, whether a Plane corresponding to the received address is in a normal state or in a faulty state. If the Plane corresponding to the received address is normal, the rescue circuit 211 can enable the corresponding Plane. If the Plane corresponding to the received address is faulty, the rescue circuit 211 can disable the corresponding Plane, and can enable another normal Plane instead of the corresponding faulty Plane.

[0090] Thus, according to embodiments of this disclosure, if the plane corresponding to an externally applied address is a faulty plane, the corresponding plane can be disabled, thereby suppressing access to the faulty plane, and thus operations can be performed using only the remaining normal planes. Therefore, even when some planes are faulty, the remaining normal planes can be salvaged, allowing for the configuration of semiconductor memory devices with reduced storage capacity. Semiconductor memory devices salvaged in this way can be mass-produced as partially salvaged semiconductor memory devices.

[0091] For example, such as Figure 5 As shown, in the structure of a 128Gb×2 planar×2 chip, if two planes are found to be faulty, semiconductor memory devices can be mass-produced according to product specifications that reduce the capacity to half through partial rescue.

[0092] Figure 9 Part (a) is an exemplary top view illustrating a semiconductor memory device that differs from an embodiment of this disclosure, and Figure 9 Part (b) is an exemplary top view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0093] Reference Figure 9 Part (a) may provide a main pad region MP and a sealing region SEAL for each chip region 10. For example, two main pad regions MP may be provided corresponding to two chip regions 10 respectively, and two sealing regions SEAL may be provided, each sealing region SEAL surrounding one chip region 10 and one main pad region MP.

[0094] Reference Figure 9 In part (b), according to embodiments of this disclosure, a main pad region MP and a sealing region SEAL can be provided for multiple chip regions 10. Because of this fact, with Figure 9 Compared to part (a), the area consumed by the main pad region MP and the sealing region SEAL can be reduced, and therefore, the semiconductor memory device can be configured to a smaller size.

[0095] Of course, according to the embodiments of this disclosure, although there is a factor that leads to an increase in size due to the increase in the sub-pad area SP, as mentioned above... Figure 5 The described sub-pad 11 has a smaller size than the main pad 20, so the sub-pad region SP can be configured with a smaller area than the main pad region MP. Therefore, even considering the slight increase in the size of the semiconductor memory device due to the sub-pad region SP, the effect of reducing the overall size of the semiconductor memory device according to this disclosure remains effective. By comparison...Figure 9 Part (a) and Figure 9 As can be seen from part (b), the embodiments of this disclosure ( Figure 9 The width of part (b) is greater than that of the control example ( Figure 9 Part (a) has a smaller width H. Therefore, the size of the device in part (b) is smaller than the size of the device in part (a) by the dimension corresponding to the width H.

[0096] Figure 10 This is a block diagram illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0097] Reference Figure 10 The memory system 600 according to the embodiment may include a non-volatile memory device (VNM device) 610 and a memory controller 620.

[0098] The non-volatile memory device (VNM device) 610 can be constructed from the aforementioned semiconductor memory device and can operate in the manner described above. The memory controller 620 can be configured to control the non-volatile memory device (VNM device) 610. By combining the non-volatile memory device (VNM device) 610 and the memory controller 620, a memory card or solid-state drive (SSD) can be provided. SRAM 621 serves as the working memory for the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol for the host connected to the memory system 600.

[0099] Error correction code block (ECC) 624 detects and corrects errors included in data read from non-volatile memory device (VNM device) 610.

[0100] The memory interface (memory I / F) 625 is interfaced with the non-volatile memory device (VNM device) 610 of this embodiment. The processing unit (CPU) 622 performs general control operations for data exchange with the memory controller 620.

[0101] Although not shown in the accompanying drawings, it will be apparent to those skilled in the art that the memory system 600 according to the embodiment may additionally include a ROM storing code data for interfacing with a host. The non-volatile memory device (VNM device) 610 may be configured as a multi-chip package consisting of multiple flash memory chips.

[0102] As described above, the memory system 600 according to the present embodiment can be provided as a high-reliability storage medium having a low possibility of error occurrence. Specifically, the nonvolatile memory device of the present embodiment can be included in a memory system such as a solid state disk (SSD) that is currently being actively researched. In this case, the memory controller 620 can be configured to communicate with an external (e.g., host) through one of various interface protocols such as a USB (Universal Serial Bus) protocol, an MMC (Multi Media Card) protocol, a PCI-E (Peripheral Component Interconnect Express) protocol, a SATA (Serial Advanced Technology Attachment) protocol, a PATA (Parallel Advanced Technology Attachment) protocol, a SCSI (Small Computer System Interface) protocol, an ESDI (Enhanced Small Disk Interface) protocol, and an IDE (Integrated Drive Electronics) protocol.

[0103] Figure 11 is a block diagram schematically illustrating a computing system including a semiconductor memory device according to an embodiment of the present disclosure.

[0104] Referring to Figure 11 , the computing system 700 according to the embodiment can include a memory system 710, a microprocessor (CPU) 720, a RAM 730, a user interface 740, and a modem 750 (such as a baseband chipset) electrically coupled to a system bus 760. In the case where the computing system 700 according to the embodiment is a mobile device, a battery (not shown) for supplying an operating voltage of the computing system 700 can be additionally provided. Although not shown in the drawing, it will be apparent to those skilled in the art to which the present embodiment pertains that the computing system 700 according to the present embodiment can be additionally provided with an application chipset, a camera image processor (CIS), a mobile DRAM, etc. For example, the memory system 710 can be configured as an SSD (Solid State Drive / Disk) using a nonvolatile memory to store data. Otherwise, the memory system 710 can be provided as a fusion flash memory (e.g., OneNAND flash memory).

[0105] Although exemplary embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in the above and the drawings should be considered in a descriptive sense only and not for purposes of limiting the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the drawings. The spirit and scope of the present disclosure should be construed by the appended claims and should encompass all modifications falling within the scope of the appended claims.

[0106] Cross Reference to Related Applications

[0107] This application claims priority to Korean Patent Application No. 10-2020-0147595, filed on November 6, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: a plurality of planes defined in a plurality of chip regions; a rescue circuit configured to disable a faulty plane among the plurality of planes and enable a normal plane among the plurality of planes; and a main pad region having a plurality of main pads capable of interfacing with an external device, the plurality of main pads including a plurality of plane enable pads respectively corresponding to the plurality of planes, the plurality of plane enable pads receiving a plane enable signal for enabling a corresponding plane to individually enable or independently test the corresponding plane, wherein the semiconductor memory device operates with only the enabled normal planes, and wherein a sub-pad region included in each chip region and having a plurality of sub-pads is located between the plurality of planes in the corresponding chip region, and each of the plurality of sub-pads is coupled to a corresponding one of the plurality of main pads through a redistribution line. 2.The semiconductor memory device of claim 1, wherein the rescue circuit configured to individually enable each of the plurality of planes in response to a plurality of the plane enable signals input through the plurality of plane enable pads in a test mode. 3.The semiconductor memory device of claim 2, further comprising: a storage unit configured to store a corresponding status signal for each of the plurality of planes, the status signal being a result of a test determining whether a fault exists in each of the plurality of planes, wherein the rescue circuit is configured to independently enable or disable each of the plurality of planes based on the corresponding status signal.

4. The semiconductor memory device according to claim 1, wherein, the plurality of chip regions are coupled to each other through a scribe lane. 5.The semiconductor memory device of claim 1, wherein the plurality of main pads are bond pads bonded to a plurality of external coupling members, and wherein the plurality of sub-pads are non-bond pads not bonded to external coupling members.

6. The semiconductor memory device of claim 1, wherein, a size of each of the plurality of sub-pads is smaller than a size of each of the plurality of main pads. 7.The semiconductor memory device of claim 1, further comprising: a sealing region disposed to surround the plurality of chip regions and the main pad region.

8. The semiconductor memory device of claim 7, wherein, the plurality of planes are disposed on a cell wafer, and the rescue circuit is disposed on a peripheral wafer seated to the cell wafer in a vertical direction.

9. A rescue method of a semiconductor memory device including a plurality of chip regions each having a plurality of planes, wherein, the semiconductor memory device including a main pad region having a plurality of main pads capable of interfacing with an external device, the plurality of main pads including a plurality of plane enable pads respectively corresponding to the plurality of planes, the plurality of plane enable pads receiving a plane enable signal for enabling a corresponding plane to individually enable or independently test the corresponding plane, the rescue method including the steps of: obtaining a status signal of each of the plurality of planes indicating whether there is a fault in each of the plurality of planes by individually testing each of the plurality of planes for the fault; and controlling whether each of the plurality of planes is enabled based on the status signal of each of the plurality of planes such that a faulty plane is disabled and a normal plane is enabled, wherein a sub-pad region included in each chip region and having a plurality of sub-pads is located between the plurality of planes in the corresponding chip region, and each of the plurality of sub-pads is coupled to a corresponding one of the plurality of main pads by a redistribution line.

10. The rescue method according to claim 9, wherein, The step of controlling whether each of the plurality of planes is enabled includes the steps of: receiving an address corresponding to a plane to be accessed among the plurality of planes; determining whether the plane is normal or faulty based on a status signal of the plane corresponding to the address; and enabling the plane when the plane is normal, and enabling another plane when the plane is faulty.

11. A layout of a semiconductor memory device, the layout of the semiconductor memory device comprising: a plurality of chip regions, each of the plurality of chip regions including a plurality of planes arranged in a first direction; a main pad region extending in a second direction perpendicular to the first direction and including a plurality of main pads arranged in the second direction, the plurality of main pads being interfaceable with an external device; a plurality of sub-pad regions, each of the plurality of sub-pad regions extending in the second direction and including a plurality of sub-pads arranged in the second direction, the sub-pad region being located between the plurality of planes in the corresponding chip region, wherein each of the plurality of planes corresponds to one of the plurality of main pads, and a plane enable signal for enabling the corresponding plane is input to a plane enable pad corresponding to the corresponding plane to individually enable or independently test the corresponding plane, wherein each of the plurality of planes is directly connected to at least one of the plurality of sub-pads, the at least one sub-pad being connected to a corresponding one of the main pads by a redistribution line, and wherein a width of the main pad region in the first direction is greater than a width of the sub-pad region in the first direction.

12. The layout of a semiconductor memory device according to claim 11, wherein, The plurality of chip regions, the main pad region, and the sub-pad region are disposed within an area surrounded by a sealing region.

13. The layout of a semiconductor memory device according to claim 11, wherein, Each of the plurality of sub-pad regions corresponds to at least two planes of the plurality of planes arranged on both sides of the sub-pad region in the first direction.

14. The layout of a semiconductor memory device according to claim 12, wherein, The main pad region is disposed at an edge of the area surrounded by the sealing region in the first direction, and the plurality of main pads are arranged in the second direction along the edge.

15. The layout of a semiconductor memory device according to claim 12, wherein, The main pad region is disposed at a center of the area surrounded by the sealing region, and the plurality of chip regions and the plurality of sub-pad regions on opposite sides of the main pad region are symmetrical.

16. The layout of a semiconductor memory device of claim 11, further comprising: a rescue circuit configured to disable a failed plane among the plurality of planes and enable a normal plane among the plurality of planes based on a corresponding state signal stored in a plane state storage unit, wherein the plurality of chip regions are coupled to each other by a scribe lane.

17. The layout of a semiconductor memory device according to claim 16, wherein, The plurality of planes are disposed on a cell wafer, and the rescue circuit and the plane state storage unit are disposed on a peripheral wafer.

18. The layout of a semiconductor memory device according to claim 16, wherein, The semiconductor memory device operates in a case where some normal planes among the plurality of planes are enabled and other failed planes are disabled.

19. The layout of the semiconductor memory device of claim 11, wherein The plurality of main pads are bond pads bonded to a plurality of external coupling members, and wherein the plurality of sub-pads are non-bond pads not bonded to external coupling members.

Images