Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure comprises: performing a first planarization process on a first dielectric material layer until the top surface of the hard mask layer is exposed, thereby forming an initial interlayer dielectric layer, wherein the lowest point of the surface of the initial interlayer dielectric layer is higher than or flush with the top surfaces of the first dummy gate and the second dummy gate; after removing the hard mask layer, etching the initial interlayer dielectric layer until the initial interlayer dielectric layer above the top surface of the first dummy gate in the first region is removed, thereby forming a transition interlayer dielectric layer; forming a second dielectric material layer on the top surfaces of the first dummy gate, the second dummy gate, and the transition interlayer dielectric layer; performing a second planarization process on the second dielectric material layer and the transition interlayer dielectric layer until the top surfaces of the first dummy gate and the second dummy gate are exposed, thereby finally forming an interlayer dielectric layer with a flat surface, thereby improving device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, integrated circuit chips are moving towards higher device density and higher integration levels to achieve faster computing speeds, larger data storage capacities, and more functionality. As device feature sizes continue to shrink to the nanometer scale, polysilicon gate processes are unable to meet the requirements of existing technologies. The semiconductor industry is replacing polysilicon gate electrodes with metal gates (MGs) to address issues such as threshold voltage drift, polysilicon gate depletion, excessive gate resistance, and Fermi level pinning.

[0003] In the metal replacement gate process, a mechanical chemical polishing (CMP) process is required to grind away the silicon oxide and silicon nitride isolation layers on the top of the polycrystalline gate, and stop polishing after the top of the polycrystalline gate is exposed. This CMP process will affect the subsequently formed metal gate, thereby affecting the performance of the device. Therefore, the CMP technology needs to be further improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming a plurality of first dummy gates on the first region, and forming a plurality of second dummy gates on the second region, wherein the distance between adjacent first dummy gates is smaller than the distance between adjacent second dummy gates, and the top surfaces of the first dummy gates and the second dummy gates both have a hard mask layer; forming a first dielectric material layer on the surface of the substrate, the first dielectric material layer being located on the sidewalls of the first dummy gates, the sidewalls of the second dummy gates, the sidewalls of the hard mask layer, and the top surface; performing a first planarization process on the first dielectric material layer until the top surface of the hard mask layer is exposed , forming an initial interlayer dielectric layer, wherein the lowest point of the surface of the initial interlayer dielectric layer is higher than or flush with the top surface of the first dummy gate and the top surface of the second dummy gate; after forming the initial interlayer dielectric layer, removing the hard mask layer; after removing the hard mask layer, etching the initial interlayer dielectric layer until the initial interlayer dielectric layer above the top surface of the first dummy gate on the first region is removed to form a transition interlayer dielectric layer; after forming the transition interlayer dielectric layer, forming a second dielectric material layer on the top surfaces of the first dummy gate, the second dummy gate, and the transition interlayer dielectric layer; performing a second planarization process on the second dielectric material layer and the transition interlayer dielectric layer until the top surfaces of the first dummy gate and the second dummy gate are exposed.

[0006] Optionally, the hard mask layer has a thickness greater than 550 angstroms.

[0007] Optionally, before forming the first dielectric material layer, the method further includes: forming sidewall spacers on sidewalls of the first dummy gate and the second dummy gate.

[0008] Optionally, the material of the sidewall spacer is different from the material of the hard mask layer; the material of the sidewall spacer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0009] Optionally, after removing the hard mask layer and before forming the transition interlayer dielectric layer, the method further includes: removing sidewalls higher than top surfaces of the first dummy gate and the second dummy gate.

[0010] Optionally, the process of removing the sidewalls higher than the top surfaces of the first dummy gate and the second dummy gate is a third etching process; the selectivity range of the third etching process for the sidewalls and the transition interlayer dielectric layer is greater than 10:1.

[0011] Optionally, before forming the hard mask layer, the method further includes: forming an adhesion layer on top surfaces of the first dummy gate and the second dummy gate.

[0012] Optionally, the material of the adhesion layer includes oxide.

[0013] Optionally, while etching the initial interlayer dielectric layer, the method further includes: removing the adhesion layer.

[0014] Optionally, after forming the initial interlayer dielectric layer and before removing the hard mask layer, the method further includes: performing a fourth etching process on the surface of the hard mask layer to remove the first dielectric material layer remaining on the surface of the hard mask layer.

[0015] Optionally, the fourth etching process has a selectivity ratio between the hard mask layer and the initial interlayer dielectric layer in a range of 0.9 to 1.1.

[0016] Optionally, a material of the first dummy gate includes silicon; a material of the second dummy gate includes silicon.

[0017] Optionally, the first planarization process is a mechanochemical polishing process; and the second planarization process is a mechanochemical polishing process.

[0018] Optionally, the material of the first dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride; the material of the second dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0019] Optionally, the material of the hard mask layer is different from that of the first dielectric material layer; the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0020] Optionally, the process of removing the hard mask layer is a first etching process; the selectivity ratio of the first etching process to the hard mask layer and the initial interlayer dielectric layer is greater than 25:1.

[0021] Optionally, it includes: the process of etching the initial interlayer dielectric layer is a second etching process; in the second etching process, the etching selectivity ratio of the initial interlayer dielectric layer and the first pseudo gate is greater than 25:1; the etching selectivity ratio of the second etching process to the initial interlayer dielectric layer and the second pseudo gate is also greater than 25:1.

[0022] Optionally, the thickness of the second dielectric material layer is greater than 200 angstroms.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first planarization treatment is performed on the first dielectric material layer. By adjusting the thickness of the hard mask layer, the first planarization process, and other factors, the lowest point of the surface of the initial interlayer dielectric layer can be made higher than or flush with the top surfaces of the first and second dummy gates. Because the initial interlayer dielectric layer between the first dummy gates in the first region is smaller than the initial interlayer dielectric layer between the second dummy gates in the second region, the initial interlayer dielectric layer above the top surface of the first dummy gates in the first region is easier to remove. The initial interlayer dielectric layer above the top surface of the second dummy gates in the second region is etched inward from the outer edge. After the initial interlayer dielectric layer above the top surface of the first dummy gates in the first region is removed, a portion of the initial interlayer dielectric layer above the top surface of the second dummy gates in the second region remains, and the "concave" surface of the initial interlayer dielectric layer in the second region is transformed into a convex surface, resulting in a centrally convex surface structure of the transition interlayer dielectric layer in the second region. When a second dielectric material layer is formed on the top surfaces of the first dummy gate, the second dummy gate, and the transition interlayer dielectric layer and a second planarization process is performed on the second dielectric material layer and the transition interlayer dielectric layer, even if the distance between adjacent second dummy gates is large, it is unlikely that a depression will appear in the middle of the surface of the transition interlayer dielectric layer on the second region, ultimately forming an interlayer dielectric layer with a flat surface. In a subsequent metal replacement gate process, it is unlikely that an abnormal area will form on the surface of the interlayer dielectric layer, thereby improving the performance of the formed device.

[0025] Furthermore, the thickness of the hard mask layer ranges from 550 angstroms to 750 angstroms. Due to the large thickness of the hard mask layer, the depth of the "depression" defect on the surface of the initial interlayer dielectric layer is lower than the thickness of the hard mask layer, so that the lowest point of the surface of the initial interlayer dielectric layer is not lower than the plane of the top surfaces of the first pseudo gate and the second pseudo gate.

[0026] Furthermore, the thickness of the second dielectric material layer is greater than 200 angstroms. During the second planarization process, the second dielectric material layer is used to protect the first dummy gate and the second dummy gate, so as to improve the performance of the subsequently formed gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 4 It is a structural schematic diagram of each step of a conventional method for forming a semiconductor structure;

[0028] Figures 5 to 12 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0030] As described in the background art, the existing CMP technology needs to be further improved. A method for forming a semiconductor structure is now described and analyzed.

[0031] Figures 1 to 4 The present invention is a structural schematic diagram of each step of a conventional method for forming a semiconductor structure.

[0032] Please refer to Figure 1 , providing a substrate 101, the substrate 101 having a first region I and a second region II, the substrate further comprising a base 102, and a dummy gate 103 located on a portion of the base 102.

[0033] Please refer to Figure 2 A hard mask layer 104 is formed on the top surface of the dummy gate 103; a sidewall spacer 105 is formed on the sidewall of the dummy gate 103; an interlayer dielectric material layer 106 is formed on the surface of the substrate 101, and the interlayer dielectric material layer 106 is also located on the surface of the hard mask layer 104 and the surface of the sidewall spacer 105.

[0034] Please refer to Figure 3 , using a first CMP process to planarize the interlayer dielectric material layer 106 to form a transition interlayer dielectric layer 107 ; etching the surface of the hard mask layer 104 to remove the residual interlayer dielectric material layer 106 on the surface of the hard mask layer 104 .

[0035] Please refer to Figure 4 A second CMP process is used to planarize the transition interlayer dielectric layer 107 , the hard mask layer 104 , and the sidewall spacer 105 until the top surface of the dummy gate 103 is exposed, thereby forming an interlayer dielectric layer 108 .

[0036] In the above method, the first region I is used to form a short channel device, and the second region II is used to form a long channel device. The distance between the dummy gates 103 in the first region I is much smaller than the distance between the dummy gates 103 in the second region II. The interlayer dielectric material layer 106 formed has a "step" structure, that is, the surface of the interlayer dielectric layer between adjacent dummy gates 103 is lower than the surface of the interlayer dielectric layer above the dummy gates 103, forming a pit X (such as Figure 2As shown). During the mechanical chemical polishing process, for large-sized patterns, the middle part thereof is easily over-polished to produce "depression" defects. The larger the size of the polished area is, the more likely it is to produce "depression" defects during the mechanical chemical polishing process, and the deeper the "depression" defects are. After the interlayer dielectric material layer 106 is planarized using the first CMP process, since the lateral size of the interlayer dielectric material layer 106 between the pseudo gates 102 located on the first region I is relatively small, the interlayer dielectric material layer 106 on the first region I is not prone to "depression" defects after planarization, while the lateral size of the interlayer dielectric material layer 106 between the pseudo gates 102 located on the second region II is relatively large, and is prone to "depression" defects, forming a first depression Y (as shown) on the surface of the transition interlayer dielectric layer 107 on the second region II. Figure 3 As shown in FIG, the pit X also further deepens the depth of the first recess Y. When etching the surface of the hard mask layer 104, the depth of the first recess Y also deepens. When the second CMP process is used to planarize the transition interlayer dielectric layer 107, the depth of the first recess Y further deepens to form a second recess Z (as shown in FIG. Figure 4 The second recess Z will be filled with metal material in the subsequent metal replacement gate process, forming an abnormal area that is difficult to remove. The abnormal area will cause device leakage or even short circuit, seriously affecting the performance of the formed device.

[0037] To address the above-mentioned problem, the present invention provides a method for forming a semiconductor structure, wherein a first planarization process is performed on the first dielectric material layer. By adjusting the thickness of the hard mask layer, the first planarization process, and other factors, the lowest point of the surface of the initial interlayer dielectric layer is made higher than or flush with the top surfaces of the first and second dummy gates. Because the initial interlayer dielectric layer between the first dummy gates in the first region is smaller than the initial interlayer dielectric layer between the second dummy gates in the second region, the initial interlayer dielectric layer above the top surfaces of the first dummy gates in the first region is easier to remove. The initial interlayer dielectric layer above the top surfaces of the second dummy gates in the second region is etched inward from the outer edges. After the initial interlayer dielectric layer above the top surfaces of the first dummy gates in the first region is removed, a portion of the initial interlayer dielectric layer above the top surfaces of the second dummy gates in the second region remains. This allows the "concave" surface of the initial interlayer dielectric layer in the second region to become a convex surface, resulting in a centrally convex surface structure of the transition interlayer dielectric layer in the second region. After forming the transition interlayer dielectric layer, a second dielectric material layer is formed on the top surfaces of the first dummy gate, the second dummy gate, and the transition interlayer dielectric layer. When the second dielectric material layer and the transition interlayer dielectric layer are subjected to a second planarization process, even if the distance between adjacent second dummy gates is large, it is unlikely that a depression will appear in the middle of the surface of the transition interlayer dielectric layer on the second region. Ultimately, an interlayer dielectric layer with a flat surface is formed. In a subsequent metal replacement gate process, abnormal regions are unlikely to form on the surface of the interlayer dielectric layer, thereby improving the performance of the formed device.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 5 to 12 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0040] Please refer to Figure 5 , providing a substrate 201, wherein the substrate 201 includes a first region I and a second region II.

[0041] The substrate 201 may be single crystal silicon, polycrystalline silicon, or amorphous silicon, or may be a semiconductor material such as germanium, silicon germanium, or gallium arsenide, or may be a semiconductor-on-insulator structure. The substrate 201 may be a planar structure or a non-planar structure, such as one having fins formed therein. In this embodiment, the substrate 201 is single crystal silicon and has a planar structure.

[0042] The first region is used to form a short channel device; the second region is used to form a long channel device.

[0043] Please refer to Figure 6 , multiple first pseudo gates 202 are formed on the first region I, and multiple second pseudo gates 203 are formed on the second region II, the distance between adjacent first pseudo gates 202 is smaller than the distance between adjacent second pseudo gates 203, and the top surfaces of the first pseudo gates 202 and the second pseudo gates 203 both have a hard mask layer 204.

[0044] The material of the first dummy gate 202 includes silicon; the material of the second dummy gate 203 includes silicon. In this embodiment, the material of the first dummy gate 202 is silicon, and the material of the second dummy gate 203 is silicon. In other embodiments, the material of the first dummy gate may be polycrystalline silicon, amorphous carbon, etc.; the material of the second dummy gate may be polycrystalline silicon, amorphous carbon, etc.

[0045] The hard mask layer 204 has a thickness greater than 550 angstroms. The thickness of the hard mask layer 204 refers to a dimension perpendicular to the substrate.

[0046] In this embodiment, the hard mask layer 204 has a thickness of 600 angstroms. Subsequently, a first dielectric material layer is formed on the surface of the substrate 201, and a first planarization process is performed on the first dielectric material layer until the top surface of the hard mask layer is exposed, thereby forming an initial interlayer dielectric layer. The significance of the selected thickness range of the hard mask layer 204 is that after the first planarization process, due to the relatively large thickness of the hard mask layer 204, the lowest point of the surface of the initial interlayer dielectric layer is higher than or flush with the top surfaces of the first dummy gate 202 and the second dummy gate 203. Furthermore, the hard mask layer 204 is used to protect the first dummy gate 202 and the second dummy gate 203 during the subsequent etching process.

[0047] The material of the hard mask layer 204 is different from that of the first dielectric material layer; the material of the hard mask layer 204 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the hard mask layer 204 is silicon nitride. The material of the hard mask layer 204 is different from that of the first dielectric material layer, so that when the hard mask layer 204 is subsequently removed, the hard mask layer 204 can be etched more easily than the first dielectric material layer.

[0048] In this embodiment, before forming the hard mask layer 204, the process further includes forming an adhesion layer 205 on the top surfaces of the first dummy gate 202 and the second dummy gate 203. The adhesion layer 205 is used to improve the adhesion between the hard mask layer 204 and the first dummy gate 202, and between the hard mask layer 204 and the second dummy gate 203.

[0049] The material of the adhesion layer 205 includes oxide. In this embodiment, the material of the adhesion layer 205 is silicon oxide. In other embodiments, the material of the adhesion layer 205 can be silicon oxynitride, etc.

[0050] In this embodiment, the method further includes forming spacers 206 on the sidewalls of the first dummy gate 202 and the second dummy gate 203 .

[0051] The material of the spacer 206 is different from that of the hard mask layer 204; the material of the spacer 206 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the spacer 206 is silicon oxynitride. The spacer 206 is used to protect the first dummy gate 202 and the second dummy gate 203 during the subsequent etching process.

[0052] The method for forming the sidewall spacer 206 includes: forming a sidewall spacer material layer (not shown) on the surfaces of the substrate 201, the first dummy gate 202, and the second dummy gate 203; and etching back the sidewall spacer material layer until the top surfaces of the substrate 201, the first dummy gate 202, and the second dummy gate 203 are exposed, thereby forming the sidewall spacer 206. In this embodiment, due to the difference in the amount of sidewall spacer material etched in the first region I and the second region II during the back etching of the sidewall spacer material, the sidewall spacer 206 in the second region II is slightly lower than the sidewall spacer 206 in the first region I.

[0053] Please refer to Figure 7 A first dielectric material layer 207 is formed on the surface of the substrate 201 , and the first dielectric material layer 207 is located on the sidewalls of the first dummy gate 202 , the sidewalls of the second dummy gate 203 , and the sidewalls and top surface of the hard mask layer 204 .

[0054] The first dielectric material layer 207 is deposited on the top surfaces of the first dummy gate 202 and the second dummy gate 203 simultaneously with the deposition on the surface of the substrate 201. Since the first dummy gate 202 and the second dummy gate 203 protrude from the substrate 201, the formed first dielectric material layer 207 has a "stepped" structure, that is, the top surface of the first dielectric material layer 207 located on the surfaces of the first dummy gate 202 and the second dummy gate 203 is higher than the top surface of the first dielectric material layer 207 between adjacent first dummy gates 202 and between adjacent second dummy gates 203, and a pit A is formed on the surface of the first dielectric material layer 207.

[0055] The first dielectric material layer 207 is formed by a chemical vapor deposition process. In this embodiment, the first dielectric material layer 207 is formed by a fluid chemical vapor deposition process. The fluid chemical vapor deposition process can reduce the generation of defects such as voids.

[0056] The material of the first dielectric material layer 207 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the first dielectric material layer 207 is silicon oxide. The first dielectric material layer 207 is used to provide electrical insulation between different devices.

[0057] The first dielectric material layer 207 is used to subsequently form an interlayer dielectric layer.

[0058] Please refer to Figure 8 , performing a first planarization process on the first dielectric material layer 207 until the top surface of the hard mask layer 204 is exposed, thereby forming an initial interlayer dielectric layer 208, wherein the lowest point of the surface of the initial interlayer dielectric layer 208 is higher than or flush with the top surface of the first dummy gate 202 and the top surface of the second dummy gate 203.

[0059] The first planarization process is a mechanochemical polishing process.

[0060] The first dielectric material layer 207 located below the top surface of the hard mask layer 204 is divided into regions of different sizes by the first dummy gate 202, the second dummy gate 203, and the hard mask layer on top of them. Due to the large distance between adjacent second dummy gates 203, the initial interlayer dielectric layer 208 on the second region II cannot be planarized when polished to the top surface of the hard mask layer 204. Due to the large size of the initial interlayer dielectric layer 208 between adjacent second dummy gates 203, the initial interlayer dielectric layer 208 between adjacent second dummy gates 203 has a structure with convex edges and a concave center, forming multiple concavities B on the surface of the initial interlayer dielectric layer 208.

[0061] Subsequently, the hard mask layer 204 is removed. Since some of the first dielectric material layer 207 typically remains on the surface of the hard mask layer 204 during the first planarization process, in this embodiment, after forming the initial interlayer dielectric layer 208 and before removing the hard mask layer 204, the process further includes: performing a fourth etching process on the surface of the hard mask layer 204 to remove the remaining first dielectric material layer 207 on the surface of the hard mask layer 204. The fourth etching process has a selectivity ratio between the hard mask layer 204 and the initial interlayer dielectric layer 208 ranging from 0.9 to 1.1. During the fourth etching process, the hard mask layer 204 is etched slightly more than the initial interlayer dielectric layer 208. The fourth etching process is used to remove the remaining first dielectric material layer on the surface of the hard mask layer 204, facilitating the subsequent removal of the hard mask layer 204 using the first etching process having a high selectivity ratio to the hard mask layer 204.

[0062] Please refer to Figure 9 After forming the initial interlayer dielectric layer 208 , the hard mask layer 204 is removed.

[0063] The process of removing the hard mask layer 204 is a first etching process.

[0064] The first etching process includes one of a dry etching process and a wet etching process, or a combination of the two. In this embodiment, the first etching process is a wet etching process, and its parameters include: a temperature range of 155 degrees to 165 degrees, and a chemical solution of hot phosphoric acid with a concentration (volume fraction) of 86%.

[0065] In the first etching process, the etching selectivity ratio between the hard mask layer 204 and the initial interlayer dielectric layer is greater than 25:1. In this embodiment, under the conditions of the first etching process, the selectivity ratio of the chemical solution to silicon nitride and silicon oxide is 50:1, that is, in the first etching process, the etching selectivity ratio between the hard mask layer 204 and the initial interlayer dielectric layer 208 is 50:1. The first etching process has a high etching selectivity for the hard mask layer 204, which is conducive to removing the hard mask layer 204, while the etching amount of the initial interlayer dielectric layer 208 is small, thereby preventing the lowest point of the recess B from deepening further.

[0066] In this embodiment, after removing the hard mask layer 204, the process further includes removing the spacers 206 above the top surfaces of the first dummy gate 202 and the second dummy gate 203. The initial interlayer dielectric layer 208 above the top surface of the second gate 203 on the second region II forms a plurality of defect layers C with protruding edges and recessed centers. These defect layers C need to be removed in subsequent processes to form a planarized interlayer dielectric layer surface.

[0067] The process of removing the spacers 206 that are higher than the top surfaces of the first dummy gate 202 and the second dummy gate 203 is the third etching process.

[0068] The third etching process includes one of a dry etching process and a wet etching process, or a combination of the two. In this embodiment, the third etching process is a wet etching process, and its chemical solution includes 0.5% (volume ratio) hydrofluoric acid, 60% (volume ratio) hydrogen peroxide, and 40% (volume ratio) deionized water, with the hydrofluoric acid concentration being 49% and the hydrogen peroxide concentration being 31%.

[0069] The third etching process has a selectivity ratio of greater than 10:1 for the sidewall spacers 206 and the transition interlayer dielectric layer 208. In this embodiment, under the conditions of the third etching process, the chemical solution has a fast etching rate (greater than 150 g / min) for SiON and good etching selectivity. The selectivity ratio for the sidewall spacers 206 and the transition interlayer dielectric layer 208 (i.e., silicon oxynitride and silicon oxide) is 12:1. This allows the sidewall spacers 206 above the top surfaces of the first dummy gate 202 and the second dummy gate 203 to be removed while the etching amount of the transition interlayer dielectric layer 208 is small, thereby preventing the lowest point of the recess B from deepening further.

[0070] Please refer to Figure 10 After removing the hard mask layer 204 , the initial interlayer dielectric layer 208 is etched until the initial interlayer dielectric layer 208 on the first region I that is higher than the top surface of the first dummy gate 202 is removed to form a transition interlayer dielectric layer 209 .

[0071] In this embodiment, etching the initial interlayer dielectric layer 208 also includes removing the adhesion layer 205. In this embodiment, the initial interlayer dielectric layer 208 and the adhesion layer 205 are both made of silicon oxide and can be removed in the same process step.

[0072] The process of etching the initial interlayer dielectric layer 208 is a second etching process. The second etching process includes one of a dry etching process and a wet etching process, or a combination of the two. In this embodiment, the second etching process is a wet etching process, and the chemical solution includes hydrofluoric acid.

[0073] The second etching process has a selectivity range of greater than 25:1 between the initial interlayer dielectric layer 208 and the first dummy gate 202; and a selectivity range of greater than 25:1 between the initial interlayer dielectric layer 208 and the second dummy gate 202. In this embodiment, under the conditions of the second etching process, since hydrofluoric acid readily reacts with silicon oxide but not with polysilicon, the second etching process has a very high selectivity between the initial interlayer dielectric layer 208 and the first dummy gate 202 and the second dummy gate 203. Therefore, the second etching process does not damage the first dummy gate 202 and the second dummy gate 203.

[0074] Since the small portion is most easily etched and removed during the etching process, the initial interlayer dielectric layer 208 (eg, Figure 9 (As shown in the figure), the initial interlayer dielectric layer 208 between the second dummy gates 203 in the second region II is smaller in volume than the initial interlayer dielectric layer 208. Therefore, after the initial interlayer dielectric layer 208 above the top surface of the first dummy gate 202 in the first region I is removed, a portion of the initial interlayer dielectric layer 208 above the top surface of the second dummy gate 203 in the second region II remains. Furthermore, because the etching process proceeds from the outermost layer of the material toward the innermost layer, the initial interlayer dielectric layer 208 above the top surface of the second gate 203 in the second region II has multiple defect layers C on its surface with protruding edges and recessed centers. Due to their smaller volume, the edges of these defect layers C are etched away first, thereby transforming the recesses B on the surface of the initial interlayer dielectric layer 208 in the second region II into protrusions D, resulting in multiple structures with protruding centers on the surface of the transition interlayer dielectric layer 209 in the second region II.

[0075] Please refer to Figure 11 After forming the transition interlayer dielectric layer 209 , a second dielectric material layer 210 is formed on the top surfaces of the first dummy gate 202 , the second dummy gate 203 and the transition interlayer dielectric layer 209 .

[0076] The material of the second dielectric material layer 210 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second dielectric material layer 210 is silicon oxide.

[0077] The second dielectric material layer 210 is formed by a chemical vapor deposition process. In this embodiment, the second dielectric material layer 210 is formed by a fluid chemical vapor deposition process. The fluid chemical vapor deposition process can reduce the generation of defects such as voids.

[0078] Because the surface of the transition interlayer dielectric layer 209 exhibits multiple centrally protruding structures, after the second dielectric material layer 210 is formed, the surface of the second dielectric material layer 210 between adjacent second dummy gates 203 in the second region II also exhibits multiple centrally protruding structures. Therefore, during the subsequent second planarization process, even if "depression" defects are likely to occur in the transition interlayer dielectric layer 209 (second dielectric material layer 210) between adjacent second dummy gates 203, the centrally protruding structures of the transition interlayer dielectric layer 209 (second dielectric material layer 210) prevent depressions from occurring on the surface of the transition interlayer dielectric layer in the second region II. Ultimately, an interlayer dielectric layer with a flat surface is formed. In the subsequent metal replacement gate process, abnormal regions are less likely to form on the surface of the interlayer dielectric layer, thereby improving the performance of the resulting device.

[0079] The thickness of the second dielectric material layer 210 is greater than 200 angstroms. The thickness of the second dielectric material layer 210 is selected to be sufficient to protect the first dummy gate 202 and the second dummy gate 203 .

[0080] The material of the second dielectric material layer 210 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0081] Please refer to Figure 12 A second planarization process is performed on the second dielectric material layer 210 and the transition interlayer dielectric layer 209 until the top surfaces of the first dummy gate 202 and the second dummy gate 203 are exposed.

[0082] The second planarization process is a mechanochemical polishing process.

[0083] After planarization, the surface of the interlayer dielectric layer is smooth without "depression" defects. In the subsequent metal replacement gate process, abnormal areas are not easily formed on the surface of the interlayer dielectric layer, thereby improving the performance of the formed device.

[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate comprising a first region and a second region; forming a plurality of first dummy gates on the first region, and forming a plurality of second dummy gates on the second region, wherein a distance between adjacent first dummy gates is smaller than a distance between adjacent second dummy gates, and a hard mask layer is formed on top surfaces of the first dummy gates and top surfaces of the second dummy gates; forming a first dielectric material layer on the surface of the substrate, wherein the first dielectric material layer is located on the sidewalls of the first dummy gate, the sidewalls of the second dummy gate, the sidewalls of the hard mask layer, and the top surface; Performing a first planarization process on the first dielectric material layer until the top surface of the hard mask layer is exposed to form an initial interlayer dielectric layer, wherein the lowest point of the surface of the initial interlayer dielectric layer is higher than or flush with the top surface of the first dummy gate and the top surface of the second dummy gate; After forming the initial interlayer dielectric layer, removing the hard mask layer; After removing the hard mask layer, etching the initial interlayer dielectric layer until the initial interlayer dielectric layer above the top surface of the first dummy gate on the first region is removed to form a transition interlayer dielectric layer, wherein the etching process of the initial interlayer dielectric layer includes one of a dry etching process and a wet etching process or a combination of the two; After forming the transition interlayer dielectric layer, forming a second dielectric material layer on the top surfaces of the first dummy gate, the second dummy gate and the transition interlayer dielectric layer; The second dielectric material layer and the transition interlayer dielectric layer are subjected to a second planarization process until top surfaces of the first dummy gate and the second dummy gate are exposed.

2. The method for forming a semiconductor structure according to claim 1, wherein: The hard mask layer has a thickness greater than 550 angstroms.

3. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first dielectric material layer, the method further includes: forming sidewall spacers on the sidewalls of the first dummy gate and the second dummy gate.

4. The method for forming a semiconductor structure according to claim 3, wherein: The material of the spacer is different from the material of the hard mask layer; the material of the spacer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

5. The method for forming a semiconductor structure according to claim 3, wherein: After removing the hard mask layer and before forming the transition interlayer dielectric layer, the method further includes: removing the sidewalls higher than the top surfaces of the first dummy gate and the second dummy gate.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process for removing the sidewalls higher than the top surfaces of the first dummy gate and the second dummy gate is a third etching process; the selectivity range of the third etching process to the sidewalls and the transition interlayer dielectric layer is greater than 10:

1.

7. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the hard mask layer, the method further includes: forming an adhesion layer on the top surfaces of the first dummy gate and the second dummy gate.

8. The method for forming a semiconductor structure according to claim 7, wherein: The material of the adhesion layer includes oxide.

9. The method for forming a semiconductor structure according to claim 8, wherein: While etching the initial interlayer dielectric layer, the process also includes: removing the adhesion layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: After forming the initial interlayer dielectric layer and before removing the hard mask layer, the method further includes: performing a fourth etching process on the surface of the hard mask layer to remove the first dielectric material layer remaining on the surface of the hard mask layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The selectivity ratio of the fourth etching process to the hard mask layer and the initial interlayer dielectric layer is in a range of 0.9 to 1.

1.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first dummy gate includes silicon; the material of the second dummy gate includes silicon.

13. The method for forming a semiconductor structure according to claim 1, wherein: The first planarization process is a mechanochemical polishing process; the second planarization process is a mechanochemical polishing process.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride; the material of the second dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the hard mask layer is different from that of the first dielectric material layer; the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

16. The method for forming a semiconductor structure according to claim 1, wherein: The process for removing the hard mask layer is a first etching process; the selectivity ratio of the first etching process to the hard mask layer and the initial interlayer dielectric layer is greater than 25:

1.

17. The method for forming a semiconductor structure according to claim 1, wherein: include: The process of etching the initial interlayer dielectric layer is a second etching process; In the second etching process, an etching selectivity ratio between the initial interlayer dielectric layer and the first dummy gate is greater than 25:1, and an etching selectivity ratio between the initial interlayer dielectric layer and the second dummy gate is also greater than 25:

1.

18. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the second dielectric material layer is greater than 200 angstroms.

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