A capacitor hole manufacturing method and a DRAM manufacturing method
By using a sidewall material layer as a mask during the capacitor aperture manufacturing process, and combining chlorine-based gas etching and an etching stop layer, the problems of bending and increased top size caused by etching were solved, achieving uniformity and verticality of the capacitor aperture.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2020-11-03
- Publication Date
- 2026-04-28
AI Technical Summary
In existing capacitor via manufacturing methods, the problems of curved grooves and increased critical dimensions at the top caused by the etching step are difficult to solve effectively.
By using a top-covered sidewall material layer as a mask during the etching process, combined with chlorine-based gas for self-aligned anisotropic etching, the size of the capacitor aperture is defined, and the etching stop layer is used to control the etching stop, thus avoiding sidewall corrosion and bending.
It effectively prevents the critical dimensions of the top sidewall of the capacitor hole from increasing, maintains the verticality of the sidewall, avoids bending and tilting of the sidewall, and ensures the uniformity of the critical dimensions of the capacitor hole.
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Figure CN114446888B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing capacitor vias and a method for manufacturing DRAM. Background Technology
[0002] Memory is a device or component in a digital system used to store large amounts of information, and it is an important part of computers and digital devices. Memory can be divided into two main categories: Random Access Memory (RAM) and Read-Only Memory (ROM). RAM includes DRAM, PRAM, MRAM, etc., and capacitors are one of the key components in the manufacture of these RAMs. Each memory cell in a DRAM device consists of 1T1C (i.e., one transistor and one capacitor).
[0003] With the increasing integration of devices, such as Figure 1 As shown, in existing capacitor via manufacturing methods, the etching step leads to the following problems: unopened allowance 102, bent trenches 104, and tilted trench sidewalls 106. The problem of increased top critical dimension CD due to bending and top mask etching persists. Currently, references... Figure 2 In many stages of capacitor manufacturing, bending is controlled through etching processes, typically by improving the performance of the etching tools to reduce bending (see reference). Figure 2 (Capacitor hole 202 in the middle). However, the above measures are difficult to solve the technical problem of increased top critical dimensions caused by bending and top mask corrosion. Summary of the Invention
[0004] Based on the above analysis, the embodiments of the present invention aim to provide a method for manufacturing capacitor holes and a method for manufacturing DRAM, so as to solve the problem that the existing technology is difficult to solve due to the increase in critical top dimensions caused by bending and top mask corrosion.
[0005] On one hand, embodiments of the present invention provide a method for manufacturing a capacitor aperture, comprising: providing a semiconductor substrate; sequentially forming an etch stop layer and an etchable layer above the semiconductor substrate, wherein the etchable layer sequentially comprises, from bottom to top, a first support layer, a first molding layer, a second support layer, a second molding layer, and a third support layer; etching the third support layer and over-etching the second molding layer to form a first trench; forming a sidewall material layer above the first trench by a deposition process; performing an opening etching on the sidewall material at the bottom surface of the first trench, wherein the size of the capacitor aperture is defined by the remaining sidewall material; using the top-covering sidewall material layer as a mask, etching the second support layer, the first molding layer, and the first support layer at the bottom of the first trench until the etch stop layer is reached.
[0006] The beneficial effects of the above technical solution are as follows: by using the top-covered sidewall material layer as a mask, during the etching process of the second support layer, the first molding layer and the first support layer at the bottom of the first trench, the overall critical dimensions of the sidewall of the first trench can be prevented from increasing, while bending is avoided.
[0007] Further improvements to the above method include forming a sidewall material layer above the first trench by a deposition process: forming a sidewall material layer on the top surface and sidewall of the third support layer, the sidewall of the second molding layer, and part of the sidewall and bottom of the second support layer by a deposition process.
[0008] A further improvement to the above method involves etching the sidewall material at the bottom of the first trench using a chlorine-based gas to perform self-aligned anisotropic etching on the sidewall material at the bottom of the first trench, thereby preventing the top surface of the third support layer and the sidewall material on the sidewall of the first trench from being completely etched. The chlorine-based gas includes Cl2 and BCl3, and the first trench passes through the third support layer, the second molding layer, and a portion of the second support layer.
[0009] A further improvement to the above method involves using the top-covering sidewall material layer as a mask to etch the second support layer, the first molding layer, and the first support layer until the etching stop layer is reached. This includes: using the top surface of the third support layer and the sidewall material on the sidewall of the first trench as a mask to over-etch the remaining second support layer at the bottom of the first trench to form a second trench; using the top surface of the third support layer and the sidewall material on the sidewall of the first trench as a mask to over-etch the remaining first molding layer at the bottom of the second trench to form a third trench; and using the top surface of the third support layer and the sidewall material on the sidewall of the first trench as a mask to etch the remaining first support layer at the bottom of the third trench until the etching stop layer is reached, thereby forming a capacitor hole.
[0010] Based on further improvements to the above methods, the deposition process includes PVD, CVD, and ALD processes.
[0011] Based on a further improvement of the above method, the first molding layer and the second molding layer comprise silicon dioxide; and the first support layer, the second support layer and the third support layer comprise silicon nitride.
[0012] Based on a further improvement of the above method, the sidewall material includes TiN or TaN, wherein the etching rate of the sidewall material is less than the etching rate of the silicon dioxide.
[0013] Based on a further improvement of the above method, the thickness of the sidewall material is 10 nm to 50 nm to define the size of the capacitor aperture.
[0014] On the other hand, embodiments of the present invention provide a DRAM manufacturing method, which forms a capacitor hole using the capacitor hole manufacturing method described above; forms a lower electrode inside the capacitor hole; removes the sidewall material layer, the first molding layer, the second molding layer, a portion of the first support layer and a portion of the second support layer outside the lower electrode, retaining a ring of the first support layer and a ring of the second support layer located outside the lower electrode; and sequentially forms a capacitor dielectric layer and an upper electrode inside and outside the capacitor hole.
[0015] Based on further improvements to the above method, the materials of the lower electrode and the upper electrode include TaN or TiN.
[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0017] 1. By using the top-covered sidewall material layer as a mask, during the etching process of the support layer and molding layer at the bottom of the first trench, it is possible to prevent the overall critical dimension of the top sidewall of the capacitor hole from increasing, while avoiding bending and sidewall tilting.
[0018] 2. The etching rate of the sidewall material is lower than that of silicon dioxide. This ensures that during subsequent etching processes, the sidewall material is minimally etched or not completely etched when etching the bottom support layer and molding layer, thus guaranteeing the uniformity of the critical dimensions of the capacitor vias; and
[0019] 3. The etching rate of the etch stop layer is less than that of the support layer, so that etching can stop at the etch stop layer.
[0020] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0021] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0022] Figure 1 This is a schematic diagram illustrating the technical problems existing in the manufacturing process of current capacitor holes.
[0023] Figure 2A schematic diagram of a capacitor hole manufactured using existing capacitor hole manufacturing methods;
[0024] Figure 3 This is a schematic diagram of an intermediate stage in a capacitor aperture manufacturing method according to an embodiment of the present invention;
[0025] Figure 4 This is a schematic diagram of an intermediate stage in a capacitor aperture manufacturing method according to an embodiment of the present invention;
[0026] Figure 5 This is a schematic diagram of an intermediate stage in a capacitor aperture manufacturing method according to an embodiment of the present invention;
[0027] Figure 6 This is a schematic diagram of an intermediate stage in a capacitor aperture manufacturing method according to an embodiment of the present invention;
[0028] Figure 7 This is a schematic diagram of an intermediate stage in a capacitor aperture manufacturing method according to an embodiment of the present invention;
[0029] Figure 8 This is a schematic diagram of an intermediate stage in a capacitor aperture manufacturing method according to an embodiment of the present invention;
[0030] Figure 9 A schematic diagram of an intermediate stage in a capacitor aperture manufacturing method according to an embodiment of the present invention; and
[0031] Figure 10 This is a schematic diagram of an intermediate stage in a capacitor aperture manufacturing method according to an embodiment of the present invention.
[0032] Figure label:
[0033] 102 - Unopened allowance; 104 - Curved trench; 106 - Inclined trench sidewall; 202 - Capacitor via; 302 - Semiconductor substrate; 304 - Etch stop layer; 306 - First support layer; 308 - First molding layer; 310 - Second support layer; 312 - Second molding layer; 314 - Third support layer; 316, 318 - Opening; 320 - First trench; 322 - Sidewall portion; 324 - Top portion; 326 - Bottom portion; 328 - Top surface of the second support layer; 330 - Second trench; 332 - Third trench; 334 - Fourth trench; 336 - Capacitor via Detailed Implementation
[0034] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0035] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0036] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0037] A specific embodiment of the present invention discloses a method for manufacturing a capacitor aperture. Hereinafter, reference will be made to... Figures 3 to 10 The method for manufacturing capacitor holes is described in detail.
[0038] refer to Figure 3 A semiconductor substrate 302 is provided. This semiconductor substrate 302 is only... Figure 3 As shown in the diagram, to simplify the view, in Figures 4 to 10 The semiconductor substrate is not shown in the image.
[0039] Refer again Figure 3 After providing the semiconductor substrate 302, an etch stop layer 304 and an etchable layer are sequentially formed above the semiconductor substrate 302. The etchable layer, from bottom to top, includes a first support layer 306, a first molding layer 308, a second support layer 310, a second molding layer 312, and a third support layer 314. The first support layer 306, the second support layer 310, and the third support layer 314 comprise silicon nitride. The first molding layer 308 and the second molding layer 312 comprise silicon dioxide.
[0040] Refer again Figures 3 to 5 After sequentially forming the etch stop layer 304 and the layer to be etched, the third support layer 314 is etched and the second molding layer 312 is etched to form the first trench 320. First, refer to Figure 3 A hard mask layer is formed above the third support layer 314. Then, multiple openings are formed in the hard mask layer by an etching process to form a hard mask layer pattern with multiple openings. Next, refer to Figure 3 and Figure 4The third support layer 314 is etched using the hard mask layer pattern as a mask to form multiple openings 316. Then, the second molding layer 312 at the bottom of the multiple openings 316 is etched to form multiple openings 318. (Reference) Figure 5 Using the hard mask layer pattern as a mask, oxide over-etching is performed on a portion of the second molding layer 312 at the bottom of multiple openings 318 to form a first trench 320. The first trench 320 passes through the third support layer 314, the second molding layer 312, and a portion of the second support layer 310.
[0041] refer to Figure 6 After the first trench 320 is formed, a sidewall material layer is formed above the first trench 320 by a deposition process. Forming the sidewall material layer above the first trench 320 by deposition includes forming the sidewall material layer on the top surface and sidewalls of the third support layer 314, the sidewalls of the second molding layer 312, and a portion of the sidewalls and bottom of the second support layer 310. In embodiments, the deposition process includes PVD, CVD, and ALD processes. In embodiments, the sidewall material layer includes a top portion 324 of the sidewall material layer located on the top surface of the third support layer 314, a sidewall portion 322 of the sidewall material layer located on the sidewalls of the first trench 320, and a bottom portion 326 of the sidewall material layer located on the bottom surface of the first trench 320. The sidewall portion 322 of the sidewall material layer includes a first sidewall portion covering the third support layer 314 in the first trench 320, a second sidewall portion covering the second molding layer 312, and a third sidewall portion covering a portion of the second support layer 310. The sidewall material includes TiN or TaN, wherein the etching rate of the sidewall material is lower than that of silicon dioxide. Specifically, SiO2 needs to have a good selectivity for the sidewall material so that the top and sidewalls can be well protected during SiO2 etching.
[0042] refer to Figure 7After forming the sidewall material layer, the sidewall material at the bottom surface of the first trench 320 is etched with an opening, wherein the size of the capacitor hole is defined by the remaining sidewall material. The etching of the sidewall material at the bottom surface of the first trench 320 includes: using a chlorine-based gas to perform self-aligned anisotropic etching of the sidewall material at the bottom surface of the first trench 320 to expose the top surface 328 of the remaining second support layer, while keeping the top surface of the third support layer 314 and the sidewall material on the sidewall of the first trench 320 from being completely etched, wherein the chlorine-based gas includes Cl2 and BCl3. Specifically, since the first trench 320 passes through the third support layer 314, the second molding layer 312, and part of the second support layer 310, the sidewall material at the bottom surface of the first trench 320 is etched with an opening to etch away the bottom portion 326 of the sidewall material layer, while keeping the sidewall portions 322 and the top portion 324 of the sidewall material layer from being completely etched. The size of the capacitor aperture can be defined by the sidewall portion 322 and the top portion 324 of the sidewall material layer. Specifically, the thickness of the sidewall material is 10 nm to 50 nm to define the size of the capacitor aperture. For example, the size of the capacitor aperture can be defined by adjusting the thickness of the sidewall material (e.g., between 10 nm and 50 nm).
[0043] refer to Figures 8 to 10 After etching the opening of the sidewall material at the bottom of the first trench 320, the second support layer 310, the first molding layer 308 and the first support layer 306 at the bottom of the first trench 320 are etched using the top-covered sidewall material layer as a mask until the etching stops at the etch stop layer 304.
[0044] Compared with existing technologies, the etching rate of the etch stop layer is lower than that of the support layer, which allows etching to stop at the etch stop layer.
[0045] refer to Figure 8 Using the top-covering sidewall material layer as a mask, the second support layer 310, the first molding layer 308, and the first support layer 306 are etched until the etching stops at the stop layer 304. This includes: using the top surface of the third support layer 314 and the sidewall material on the sidewall of the first trench 320 as a mask, the remaining second support layer 310 at the bottom of the first trench 320 is over-etched to form a second trench 330. The second trench 330 passes through the remaining second support layer 310 and part of the first molding layer. The width of the second trench 330 is smaller than the width of the first trench 320.
[0046] refer to Figure 9Using the top surface of the third support layer 314 and the sidewall material on the sidewall of the first trench 320 as a mask, the remaining first molding layer at the bottom of the second trench 330 is over-etched to form the third trench 332. The third trench 332 passes through the remaining first molding layer and part of the first support layer. The width of the third trench 332 is less than the width of the first trench 320, and the width of the third trench 332 is equal to the width of the second trench 330.
[0047] refer to Figure 10 Using the top surface of the third support 314 and the sidewall material on the sidewall of the first trench as a mask, the remaining first support layer 306 at the bottom of the third trench 332 is etched to form the fourth trench 334 until the etching stop layer 304 stops etching, ultimately forming the capacitor hole 336. The capacitor hole 336 passes through the first support layer 306, the first molding layer 308, the second support layer 310, the second molding layer 312, and the third support layer 314. The capacitor hole 336 includes the first trench 320, the second trench 330, the third trench 332, and the fourth trench 334. The fourth trench 334 passes through the remaining first support layer 306. The width of the fourth trench 334 is less than the width of the first trench 320, and the width of the fourth trench 334 is equal to the width of the third trench 332 and equal to the width of the second trench 330.
[0048] Compared to existing technologies, this method limits the size of the capacitor hole by forming a sidewall material layer on top of the first trench passing through the third support layer, the second molding layer, and part of the second support layer during the formation of the capacitor hole. The sidewall and top portions of the sidewall material layer then serve as a mask for etching the remaining layer to be etched. Protecting the top surface of the third support layer and the sidewalls of the first trench by the sidewall and top portions of the sidewall material layer prevents corrosion of these structures. This method also maintains the top size and uniformity of the capacitor hole, ensures the verticality of the sidewalls, and avoids bending the trench during the etching of the remaining layer.
[0049] One specific embodiment of the present invention discloses a DRAM manufacturing method, which involves forming a capacitor aperture using the capacitor aperture manufacturing method described above; forming a lower electrode inside the capacitor aperture; removing the sidewall material layer, first molding layer, second molding layer, a portion of the first support layer, and a portion of the second support layer outside the lower electrode, retaining a ring of first support layer and a ring of second support layer located outside the lower electrode; and sequentially forming a capacitor dielectric layer and an upper electrode inside and outside the capacitor aperture. The lower electrode, together with the inner capacitor dielectric layer and the inner upper electrode, forms a first capacitor, and the lower electrode, together with the outer capacitor dielectric layer and the outer upper electrode, forms a second capacitor. The materials of the lower electrode, the inner upper electrode, and the outer upper electrode include TaN or TiN.
[0050] Compared with the prior art, since a sidewall material layer is formed on top of the first trench passing through the third support layer, the second molding layer and part of the second support layer during the process of forming the capacitor hole, and the material of the sidewall material layer is the same as that of the metal electrode material, the metal electrode material can be directly deposited in the capacitor hole after the capacitor hole is formed, thus omitting the sidewall material removal step.
[0051] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0052] 1. By using the top-covered sidewall material layer as a mask, during the etching process of the support layer and molding layer at the bottom of the first trench, it is possible to prevent the overall critical dimension of the top sidewall of the capacitor hole from increasing, while avoiding bending and sidewall tilting.
[0053] 2. The etching rate of the sidewall material is lower than that of silicon dioxide. This ensures that during subsequent etching processes, the sidewall material is not completely etched when etching the bottom support layer and molding layer, thus guaranteeing the uniformity of the critical dimensions of the capacitor vias; and
[0054] 3. The etching rate of the etch stop layer is less than that of the support layer, so that etching can stop at the etch stop layer.
[0055] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0056] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A method for manufacturing a capacitor aperture, characterized in that, include: Provide semiconductor substrates; An etch stop layer and an etchable layer are sequentially formed above a semiconductor substrate, wherein the etchable layer includes, from bottom to top, a first support layer, a first molding layer, a second support layer, a second molding layer, and a third support layer; The third support layer is etched and the second molding layer is over-etched to form the first trench; A sidewall material layer is formed above the first trench using a deposition process; An opening is etched into the sidewall material at the bottom of the first trench, wherein the size of the capacitor hole is defined by the remaining sidewall material, and the size of the capacitor hole is defined by adjusting the thickness of the sidewall material; Using the top-covering sidewall material layer as a mask, the second support layer, the first molding layer, and the first support layer at the bottom of the first trench are etched until the etching stops at the stop layer. This etching process includes: using the top surface of the third support layer and the sidewall material on the sidewall of the first trench as a mask to over-etch the remaining second support layer at the bottom of the first trench to form a second trench; and using the top surface of the third support layer and the sidewall material on the sidewall of the first trench as a mask to over-etch the remaining second support layer at the bottom of the first trench. The process involves etching the remaining first molding layer at the bottom of the second trench to form a third trench; and using the top surface of the third support layer and the sidewall material on the sidewall of the first trench as a mask, etching the remaining first support layer at the bottom of the third trench to form a fourth trench, until the etching stop layer stops etching to form a capacitor hole, wherein the capacitor hole includes the first trench, the second trench, the third trench, and the fourth trench, the width of the fourth trench is less than the width of the first trench, and the width of the fourth trench is equal to the width of the third trench and equal to the width of the second trench. Wherein, the first molding layer and the second molding layer comprise silicon dioxide; and the first support layer, the second support layer and the third support layer comprise silicon nitride; The etching rate of the sidewall material is less than that of silicon dioxide.
2. The capacitor aperture manufacturing method according to claim 1, characterized in that, The formation of a sidewall material layer above the first trench via a deposition process includes: A sidewall material layer is formed on the top surface and sidewalls of the third support layer of the first trench, the sidewalls of the second molding layer, and the sidewalls and bottom of a portion of the second support layer by a deposition process.
3. The capacitor aperture manufacturing method according to claim 1, characterized in that, The process of etching an opening in the sidewall material at the bottom of the first trench includes: The sidewall material at the bottom of the first trench is self-aligned and anisotropically etched using a chlorine-based gas to prevent complete etching of the sidewall material on the top surface of the third support layer and the sidewall of the first trench. The chlorine-based gas includes Cl2 and BCl3, and the first trench passes through the third support layer, the second molding layer, and a portion of the second support layer.
4. The method for manufacturing a capacitor aperture according to claim 1 or 2, characterized in that, The deposition processes include PVD, CVD, and ALD.
5. The capacitor aperture manufacturing method according to claim 1, characterized in that, The sidewall material includes TiN or TaN.
6. The method for manufacturing a capacitor aperture according to claim 1, characterized in that, The thickness of the sidewall material is 10 nm to 50 nm to define the size of the capacitor aperture.
7. A method for manufacturing DRAM, characterized in that, The capacitor aperture is formed using the capacitor aperture manufacturing method according to any one of claims 1 to 6; A lower electrode is formed inside the capacitor hole; Remove the sidewall material layer, first molding layer, second molding layer, part of the first support layer and part of the second support layer outside the lower electrode, and retain a ring of first support layer and a ring of second support layer located outside the lower electrode; as well as A capacitor dielectric layer and an upper electrode are sequentially formed inside and outside the capacitor hole.
8. The DRAM manufacturing method according to claim 7, characterized in that, The materials of the lower electrode and the upper electrode include TaN or TiN.
Citation Information
Patent Citations
Method for improving morphology of capacitor holes
CN110943163A