Integrated assembly

Abstract

This application relates to integrated assemblies. Some embodiments include an integrated assembly having a set of true digit lines and a set of complementary digit lines. Each of the complementary digit lines is oppositely coupled with an associated one of the true digit lines. A semiconductor substrate is beneath the true digit lines. The semiconductor substrate includes semiconductor features that protrude upward from a semiconductor base and extend along a first direction. Each of the semiconductor features has opposing sidewalls. First source / drain regions are within the semiconductor features, and second source / drain regions are within the semiconductor base. The true digit lines are coupled with the first source / drain regions. A word line along the opposing sidewalls and includes a gating region that gates coupling of the first source / drain regions with the second source / drain regions. A storage element is coupled with the second source / drain regions. In some embodiments, memory can utilize a 4F 2 layout.

Description

Technical Field

[0001] Memory arrays (e.g., DRAM arrays). Including integrated assemblies with vertically stacked layers. Background Technology

[0002] Modern computing architectures utilize memory to store data. One type of memory is Dynamic Random Access Memory (DRAM). Compared to alternative types of memory, DRAM offers advantages such as simple structure, low cost, and high speed.

[0003] DRAM can utilize memory cells that have a combination of a capacitor and a transistor (so-called 1T-1C memory cell), wherein the capacitor is coupled to the source / drain region of the transistor. Figure 1 Example 1T-1C memory cell 2 is shown, where the transistor is labeled T and the capacitor is labeled C. The capacitor has one node coupled to the source / drain region of the transistor and another node coupled to a common plate CP. The common plate can be coupled to any suitable voltage in the range of greater than or equal to ground to less than or equal to VCC (i.e., ground ≤ CP ≤ VCC). In some applications, the common plate is at approximately half VCC (i.e., approximately VCC / 2). The transistor has a gate coupled to the word line WL (i.e., access line, routing line, first linear structure, etc.) and a source / drain region coupled to the bit line BL (i.e., digital line, sense line, second linear structure, etc.). In operation, the electric field generated by the voltage along the word line can gatingly couple the bit line to the capacitor during read / write operations.

[0004] Figure 2 The image shows another existing technology, the 1T-1C memory cell configuration. Figure 2 The configuration shows two memory cells 2a and 2b, where memory cell 2a includes transistor T1 and capacitor C1, and memory cell 2b includes transistor T2 and capacitor C2. Word lines WL0 and WL1 are electrically coupled to the gates of transistors T1 and T2, respectively. The connection to bit line BL is shared by memory cells 2a and 2b.

[0005] The memory cells described above can be incorporated into a memory array, and in some applications, the memory array can have an open bitline layout. Figure 3 The image shows an example integrated assembly 9 with an open bitline architecture. Assembly 9 comprises two laterally adjacent memory arrays (“Array 1” and “Array 2”), each of which contains Figure 2 The type of memory cell described in (in) Figure 3(No markings are used for simplicity). Word lines WL0 to WL7 extend across the array and are coupled to word line drivers. Digital lines D0 to D8 are associated with the first array (array 1), and digital lines D0* to D8* are associated with the second array (array 2). Sensing amplifiers SA0 to SA8 are positioned between the first and second arrays. Digital lines at the same height are paired with each other and compared via sensing amplifiers (e.g., digital lines D0 and D0* are paired with each other and compared with sensing amplifier SA0). During readout operations, one of the paired digital lines can serve as a reference for determining the electrical characteristics (e.g., voltage) of the other paired digital line.

[0006] Memory performance can be degraded due to crosstalk between adjacent digital lines. New memory architectures that reduce crosstalk between adjacent digital lines are needed. Furthermore, new memory architectures with smaller footprints are required to save valuable semiconductor space. Summary of the Invention

[0007] In one aspect, this application provides an integrated assembly comprising: a set of true digital lines and a set of complementary digital lines; each of the complementary digital lines being oppositely coupled to an associated one of the true digital lines; a semiconductor substrate below the true digital lines; the semiconductor substrate including semiconductor features projecting upward from a semiconductor substrate and extending along a first direction; each of the semiconductor features having opposing sidewalls; a first source / drain region within the semiconductor features, and a second source / drain region within the semiconductor substrate; the true digital lines extending along a second direction intersecting the first direction; the true digital lines being coupled to the first source / drain region; a word line along the opposing sidewalls and including a gating region that gating the first source / drain region to the second source / drain region in a gating manner; and a memory element coupled to the second source / drain region; the memory element being contained within a memory cell.

[0008] In another aspect, this application provides an integrated assembly comprising: semiconductor features projecting upward from a semiconductor substrate and extending along a first direction; each of the semiconductor features having opposing sidewalls; a second source / drain region within the substrate; a dielectric structure along the opposing sidewalls of the semiconductor features, the dielectric structure having a first region along the opposing sidewalls and a second region along the substrate; a first conductive structure along the dielectric structure; the first conductive structure being above the second region of the dielectric structure and spaced apart from the semiconductor features by at least the first region of the dielectric structure, the first conductive structure extending along the first direction; the first conductive structure including a gate region that selectively couples the first source / drain region and the second source / drain region to each other; a second conductive structure being above the semiconductor features and extending along a second direction intersecting the first direction; the second conductive structure alternating between a true second conductive structure and a complementary second conductive structure; the true second conductive structure being coupled to the first source / drain region; the complementary second conductive structure being coupled to the true second conductive structure; and a memory element coupled to the second source / drain region.

[0009] In another aspect, this application provides an integrated assembly comprising: a set of true digital lines and a set of complementary digital lines; each of the complementary digital lines being oppositely coupled to an associated one of the true digital lines; a semiconductor substrate below the true digital lines and the complementary digital lines; the semiconductor substrate including semiconductor features projecting upward from a semiconductor substrate and extending along a first direction; each of the semiconductor features having opposing sidewalls; a first source / drain region within the semiconductor features, and a second source / drain region within the semiconductor substrate; the true digital lines and the complementary digital lines extending along a second direction intersecting the first direction and alternating with each other along the first direction; the true digital lines being coupled to the first source / drain region; word lines extending along the opposing sidewalls and including gating regions that selectively couple the first source / drain region to the second source / drain region; a memory element coupled to the second source / drain region and contained within a memory cell; and the complementary digital lines being coupled to a reference voltage source. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a prior art memory cell having one transistor and one capacitor.

[0011] Figure 2 This is a schematic diagram of a pair of prior art memory cells, each having one transistor and one capacitor and sharing a bit line connection.

[0012] Figure 3This is a schematic diagram of an existing technology integration assembly with an open bitline architecture.

[0013] Figure 4 This is a top-down diagram of the instance layout of the regions of the instance memory array.

[0014] Figure 5 It is along Figure 4 A schematic cross-sectional side view of the arrangement of line AA.

[0015] Figure 6 It is along Figure 4 Another example of the arrangement of line AA is shown in the schematic cross-sectional side view.

[0016] Figures 7 to 9 This is a schematic plan view of the instance area of ​​the instance memory array. Detailed Implementation

[0017] Some embodiments include an integrated assembly with real digital lines and complementary digital lines, which are coupled relative to each other via a sense amplifier circuitry. The digital lines may be located above a linearly extending semiconductor feature and may be coupled to source / drain regions within such feature. In some embodiments, the complementary digital lines may be coupled to a reference voltage source and may provide shielding between the real digital lines in a folded architecture. In other embodiments, the complementary digital lines may be laterally spaced from the real digital lines in an open architecture. Reference Figures 4 to 9 Describe an example implementation.

[0018] refer to Figure 4 and 5 The example shows a top-down cross-sectional view of the area of ​​the integrated assembly 10 in an embodiment. Figure 4 ) and cross-sectional side view ( Figure 5 To simplify the diagram, what is not shown is usually associated with... Figure 4 and 5 Most of the insulation material associated with the integrated assembly. Figure 5 The cross section is usually along Figure 4 Line AA, and Figure 4 Some of the characteristics described are along Figure 5 BB line. Figure 4 and 5 The illustrations are not drawn to scale relative to each other, but are used to illustrate representative features associated with example assembly 10.

[0019] Assembly 10 includes a semiconductor substrate 12 and includes semiconductor features 14 projecting upward from the substrate. The substrate 12 is shown to include semiconductor material 16, and semiconductor feature 14 is shown to include semiconductor material 18. Semiconductor materials 16 and 18 may include any suitable composition; and in some embodiments may include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., primarily composed of, or composed of; wherein the term III / V semiconductor material refers to semiconductor materials comprising elements selected from Groups III and V of the periodic table (where Groups III and V are older nomenclature and are now referred to as Groups 13 and 15). Semiconductor materials 16 and 18 may be the same composition or may be different compositions from each other. In some embodiments, semiconductor materials 16 and 18 may both include silicon, are primarily composed of, or are composed of silicon.

[0020] Semiconductor feature 14 and substrate 12 can be considered together as semiconductor substrate 8.

[0021] Semiconductor feature 14 extends along a first direction corresponding to the illustrated y-axis direction. Although semiconductor feature 14 is shown as straight, it should be understood that in other embodiments, such a feature may be curved, wavy, etc. In any case, semiconductor feature 14 can be considered to generally extend along the illustrated y-axis direction.

[0022] Each of the semiconductor features 14 includes a pair of opposing sidewalls 15 and 17 (in Figure 4 (Only two of them are shown in the view). Sidewalls 15 and 17 also extend along the illustrated y-axis.

[0023] The first source / drain region 20 is located in the upper portion of the semiconductor feature 14 (wherein) Figure 5 Example source / drain region 20 is shown in the figure, and the second source / drain region 22 is within the semiconductor substrate 12 (wherein) Figure 5 Example source / drain region 22 is shown in the figure. The dashed lines are used to illustrate the approximate lower boundary of source / drain regions 20 and 22.

[0024] The first electrical interconnect 24 is electrically coupled to the first source / drain region 20, and the second electrical interconnect 26 is electrically coupled to the second source / drain region 22. Figure 4 Only some of interconnects 24 and 26 are marked. Interconnect 24 is... Figure 4 In the top-down view, interconnects 24 and 26 are shown as squares, and interconnect 26 is shown as a circle. These shapes are chosen to help the reader distinguish interconnects 24 and 26 from one another. It should be understood that interconnects 24 and 26 can have any suitable shape, and in some embodiments, interconnects 24 and 26 may have the same shape as each other.

[0025] Dielectric structure 28 is along the opposite sidewalls 15 and 17 of semiconductor feature 14. Figure 5 Example dielectric structure 28 is shown in the diagram. To simplify the illustration, [the diagram is omitted here]. Figure 4 The dielectric structure is not shown in the top-down view.

[0026] Dielectric structure 28 includes dielectric material 30. Such dielectric material may include any suitable composition, and in some embodiments may include silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide. In some embodiments, dielectric material 30 may be referred to as gate dielectric material.

[0027] The illustrated dielectric structure 30 is L-shaped. Specifically, the dielectric structure 30 has a first segment (region) 32 along the sidewall surfaces 15 and 17 of the semiconductor feature 14, and a second segment (region) 34 along the substrate 12. In the illustrated embodiment, the first segment 32 is a vertically extending segment (vertical leg), and the second segment 34 is a horizontally extending segment (horizontal leg), wherein the first segment 32 extends orthogonally (or at least substantially orthogonally) relative to the second segment 34. The term "substantially orthogonal" means orthogonal within reasonable tolerances for manufacturing and measurement. In other embodiments, the first and second segments 32 and 34 may extend along directions other than those illustrated, and may or may not be substantially orthogonal relative to each other. For example, the sidewalls 15 and 17 may be tapered instead of the illustrated vertical sidewalls.

[0028] The conductive structure 36 extends along the dielectric structure 28. The conductive structure 36 includes a conductive material 38. The conductive material 38 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the conductive material 38 may include one or more of tungsten, tungsten nitride, titanium nitride, etc.

[0029] The conductive structure 36 may be referred to as the first conductive structure and is shown extending along a first direction (i.e., the illustrated y-axis direction). The conductive structure 36 may correspond to word lines, and in the illustrated embodiment corresponds to word lines WL-1, WL-2, WL-3, WL-4, WL-5, WL-6, WL-7, WL-8, WL-9, WL-10, WL-11, WL-12, WL-13, and WL-14.

[0030] In some embodiments, the conductive structure 36 can be formed by spacer etching following deposition (e.g., atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc.). Therefore, the conductive structure 36 can advantageously be formed to be very thin. For example, in some embodiments, the conductive structure 36 may have a width W (in nanometers) less than about 100 nanometers (nm), less than about 50 nanometers, etc. Figure 5 (As shown in the figure). For example, in some embodiments, the conductive structure 36 may have a width W in the range of about 2 nanometers to about 100 nanometers, or in the range of about 2 nanometers to about 50 nanometers, etc.

[0031] The first conductive structure 36 is above the second region 34 of the dielectric structure 28 (e.g., Figure 5 (as shown in the figure), and is spaced apart from the semiconductor feature 14 by at least the first region 32 of the dielectric structure.

[0032] The first conductive structure 36 (i.e., word line) includes a gating area 40 (in Figure 5 The channel region 42 (marked in the middle) selectively couples the first and second source / drain regions 20 and 22 to each other. Specifically, the channel region 42 is within the semiconductor material of the substrate 12 and feature 14, and is located between the source / drain regions 20 and 22. The channel region 40 can be considered operably adjacent to (operably close to) the channel region 42 such that a sufficient voltage applied to the channel region will induce an electric field that allows current to flow through the channel region to electrically couple the source / drain regions 20 and 22 to each other. If the voltage along the word line including the channel region is below a threshold level, current will not flow through the channel region, and the source / drain regions on opposite sides of the channel region will not be electrically coupled to each other. This selective control of the coupling / decoupling of the source / drain regions by the voltage level applied to the selected word line is referred to as the selective coupling of the source / drain regions. In some operating modes, the channel region 42 may be referred to as the depletion region.

[0033] Word lines 36 (e.g., WL-1) are shown coupled to a word line driver circuitry 60 (driver). Such a word line driver circuitry can be used to provide the desired voltage along the word line during operation. The word line driver circuitry 60 is configured to drive each of the word lines 36 independently, and in some embodiments may include separate drivers arranged in a one-to-one relationship with the individual word lines. It should be understood that the illustrated word lines are coupled to the illustrated word line driver circuitry 60 in an arrangement such that each of the word lines can operate independently of the other word lines.

[0034] Transistor (access device) 44 includes a gate region 40, source / drain regions 20 and 22, and a channel region 42, wherein in Figure 5 In the view, a pair of instance transistors 44 are marked, and in which... Figure 4 This pair of example transistors 44 is also marked in the text.

[0035] The second conductive structure 46 is above the semiconductor feature 14 and along the corresponding Figure 4 The second conductive structure 46 extends along the illustrated x-axis direction. While shown as straight, it may be curved, wavy, etc., in other embodiments. Regardless, the second conductive structure can be considered to generally extend along the illustrated x-axis direction. The second conductive structure 46 extends along a second direction intersecting the first direction of the first conductive structure 14. In the illustrated embodiment, such a second direction is substantially orthogonal to the first direction. In other embodiments, the second direction may not be substantially orthogonal to the first direction. For simplicity, the second conductive structure 46 is described without crosshairs, although crosshairs are generally used to indicate conductive structures in the diagrams provided herein.

[0036] The second conductive structure 46 may correspond to a digital line (bit line, sense line, etc.). The digital lines alternate between real digital lines (BL-1, BL-2, and BL-3) and complementary digital lines (BL-1*, BL-2*, and BL-3*). Adjacent digital lines provide a sense amplifier circuit system 48 (indicated to include sense amplifiers SA-1, SA-2, and SA-3). Each of the real digital lines is relatively coupled to one of the complementary digital lines via the sense amplifier circuit system (e.g., BL-1 is relatively coupled to BL-1* via the sense amplifier circuit system SA-1). For the purposes of understanding this disclosure and the appended claims, the first digital line is "relatively coupled" to the second digital line via the sense amplifier circuit system if the sense amplifier circuit system is configured to compare the electrical characteristics (e.g., voltage) of the first and second digital lines with each other. The terms "real" and "complementary" are arbitrary and used to distinguish between digital lines compared with each other via the sense amplifier circuit system.

[0037] In some embodiments, the true digital lines (e.g., BL-1) may be considered as the first set of digital lines, and the complementary digital lines (e.g., BL-1*) may be considered as the second set of digital lines. Figure 4 In the illustrated embodiment, the first group of digital lines alternates with the second group of digital lines along the y-axis direction. The digital lines can be considered as being within a folded architecture. Specifically, the relatively coupled digital lines (e.g., BL-1 and BL-1*) can be considered as folded over a sensing amplifier (e.g., SA-1) between them.

[0038] In the illustrated embodiment, the actual digital line (e.g., BL-1) is above interconnect 24 and coupled to the first source / drain region 20 via such interconnect. Figure 4The top-down view illustrates the interconnect 24 to help the reader understand the relationship between such interconnects and the digital lines 46, even though in the actual top-down view of the assembly 10, the interconnect 24 would actually be hidden by the digital lines 46.

[0039] A complementary digital line (e.g., BL-1*) is coupled to a reference voltage source 56 (REF). The reference voltage source can be at any suitable voltage, and in some embodiments, it can be at a voltage ranging from greater than or equal to VSS to less than or equal to VCC.

[0040] The second interconnect 26 connects to the storage element 50 (in...) Figure 5 (As shown in the illustration) coupling. The storage element can be any suitable device having at least two detectable states; and in some embodiments, it can be, for example, a capacitor, a resistive memory device, a conductive bridge device, a phase-change memory (PCM) device, a programmable metallized cell (PMC), etc. In the illustrated embodiment, storage element 50 is a capacitor. Each of the capacitors has one node coupled to interconnect 26 and another node coupled to a reference voltage source 52. The reference voltage source can be at any suitable reference voltage, including, for example, ground, VCC / 2, etc.

[0041] In operation, storage element 50 may be incorporated into memory cell 54. In operation, transistor 44 may be used to selectively couple storage element 52 of memory cell 54 to associated bit line 46 during read / write operations.

[0042] Memory cell 54 may be located within memory array 58. Reference voltage source 56 may be used to provide a static reference voltage (i.e., a substantially constant reference voltage) during operation of the memory cells of the memory array, or to provide a dynamic reference voltage (i.e., a reference voltage that varies along some or all of the complementary digital lines) during at least some operating modes of the memory cells of the memory array. Hundreds, millions, hundreds of millions, etc., of memory cells may exist within the memory array.

[0043] In the illustrated embodiment, the memory cell 54 spans the gate channel region at approximately a 45° angle, such as... Figure 4 As shown in the top-down view. In other embodiments, memory cells may be formed at other suitable locations relative to the gated channel region.

[0044] exist Figure 4 The active regions are illustrated using dashed ellipses. These active regions are tightly packed together to achieve the desired high-density memory structure. Adjacent (adjoining) active regions can be separated from each other by one or more suitable insulating materials to mitigate unwanted crosstalk between adjacent active regions.

[0045] In some embodiments, complementary digital lines can be used to provide shielding between adjacent real digital lines during one or more operating modes associated with the memory array 58 (e.g., complementary digital line BL-1* can be used to provide shielding between real digital lines BL-1 and BL-2). This can mitigate or even prevent unwanted crosstalk between adjacent real digital lines. Figure 4 The folded architecture allows both the real digital line (e.g., BL-1) and the complementary digital line (e.g., BL-1*) to be equally affected by the same noise (so-called common-mode noise), thereby enabling such noise to self-cancel within the real digital line and the complementary digital line, thus improving the signal-to-noise ratio relative to the non-folded architecture.

[0046] In some embodiments, the real digital lines (e.g., BL-1) can be considered as EVEN digital lines coupled to word line 36 (i.e., having a channel region controlled by the gating region of word line 36), while the complementary digital lines (e.g., BL-1*) can be considered as ODD digital lines not coupled to word line 36 (i.e., not having a channel region controlled by the gating region of word line 36). Therefore, the gating of the word lines only selects half of the digital lines (specifically, only the EVEN digital lines), while the other half (ODD digital lines) remains at a reference voltage to provide shielding between the selected digital lines. The unselected digital lines (complementary digital lines) are coupled relative to the selected digital lines (real digital lines) via a sense amplifier 48.

[0047] In some embodiments, the memory array 58 may be considered to include unit cells 62, wherein the instance unit cells are composed of Figure 4 Within the area C defined by the dashed line shown in the illustration. Unit cell 62 contains one of the interconnects 26. In some embodiments, the digital line 46 may be fabricated using a photolithography process (e.g., a photolithography process) having an associated minimum feature size F. Therefore, the spacing of the digital line 46 is 2F. In some embodiments, semiconductor features 14 may be fabricated to have the same 2F spacing, as shown. Unit cell 62 may have a spacing of no more than 4F. 2 The area allows for compact packaging of individual cells, thereby saving valuable semiconductor space.

[0048] In some applications, the smaller unit cell 62, together with the low signal-to-noise ratio achievable using the folded architecture described herein, can enable improved performance, including, for example, faster reads, more efficient signal sensing, etc.; it can also enable higher yields of memory from the manufacturing process and / or memory chips that perform better than memory chips with conventional architectures.

[0049] Figure 4The illustrated embodiment shows a digital line 46 extending along the x-axis and having opposing first ends 64 and second ends 66. A sense amplifier 48 is laterally offset from the first end 64 of the digital line 46, and a reference voltage source 56 is laterally offset from the second end 66 of the digital line 46. In other embodiments, the sense amplifier 48 and / or the reference voltage source 56 may be located in one or more other locations, including, for example, below the memory array 58, above the memory array 58, etc.

[0050] Figure 6 Showing with Figure 5 The region of the integrated assembly 10 is similar to that of the integrated assembly 10, but shows a substrate 12 and feature 14 including a common semiconductor material 16. This semiconductor material can be any of the semiconductor materials described above, and in some embodiments may include one or both of silicon and germanium, be primarily composed of one or both of silicon and germanium, or be composed of one or both of silicon and germanium. The semiconductor material can be in any suitable crystalline form, and in some embodiments may be single-crystal. Furthermore, Figure 6 An insulating material 68 is shown extending over and between conductive structures 24, 26, and 36. The insulating material 68 may also extend over and between digital lines 46. The insulating material 68 may include any suitable composition and, in some embodiments, may include one or more of silicon dioxide, silicon nitride, aluminum oxide, etc. In some applications, the insulating material 68 may be used at least partially to prevent current leakage between adjacent memory cells 54.

[0051] Figure 7 Showcasing a folded digital line architecture Figure 4 Another diagrammatic representation of the area of ​​the integrated assembly 10. Figure 7 Digital lines 46 are shown, wherein such digital lines are subdivided into a first group comprising real digital lines BL-1 and BL-2 and a second group comprising complementary digital lines BL-1* and BL-2*. The real digital lines and complementary digital lines are paired, wherein each of the real digital lines is relatively coupled to one of the complementary digital lines via a sensing amplifier 48.

[0052] Complementary digital lines BL-1* and BL-2* are electrically coupled to reference voltage source 56.

[0053] Memory device 70 (some of which are labeled) is coupled to real digital lines BL-1 and BL-2, with such coupling illustrated by rods 72 (some of which are labeled). The memory device may contain elements referenced above. Figure 4 and 5 The interconnect 26 and storage element 50 (e.g., capacitor) are described. For simplicity of the diagram, Figure 7 Not shown in China Figure 4 and 5Word line 36 (e.g., WL-1). Memory device 70 can be considered as being comprised of memory cells. Therefore, Figure 7 An embodiment can be considered to include memory cells associated with real digital lines but not memory cells associated with complementary digital lines.

[0054] Figure 7 The folding architecture and the reference above Figure 4 The described folding architecture is the same. This type of folding architecture includes real digital lines and complementary digital lines that extend along the illustrated x-axis and alternate with each other along the illustrated y-axis. In some embodiments, Figure 7 The configuration can be viewed as including real digital lines and complementary digital lines within a single memory pad 74.

[0055] Figure 8 Display relative to Figure 7 An alternative configuration to the configuration, and specifically, the area of ​​the instance integration assembly 10a. Figure 8 The configuration features complementary digital lines BL-1* and BL-2* that are laterally offset from the real digital lines BL-1 and BL-2 in an open architecture. Specifically, digital line 46 extends along the illustrated x-axis direction, and the complementary digital lines are offset from the real digital lines along the x-axis direction. Memory device 70 is associated with the real digital lines (BL-1 and BL-2), and thus the real digital lines are incorporated into memory array 58. In contrast, no memory cells are associated with the complementary digital lines (BL-1* and BL-2*), and instead, the complementary digital lines are coupled to a reference voltage source 56.

[0056] Figure 8 The configuration can be considered as including a pair of memory pads 76 and 78, wherein memory pad 76 includes real digital lines and memory pad 78 includes complementary digital lines.

[0057] Figure 9 This demonstrates another instance configuration of the open architecture, and more specifically, it demonstrates the area of ​​instance integration component 10b. Figure 9 The configuration has a first memory device 70a associated with a real digital line (e.g., BL-1) and a second memory device 70b associated with a complementary digital line (e.g., BL-1*). The second memory device 70b may be substantially the same as the first memory device 70a; wherein the term “substantially the same” means identical within reasonable tolerances of manufacture and measurement.

[0058] A first memory device 70a is located within a first memory array 58a within a memory pad 76, and a second memory device 70b is located within a second memory array 58b within a memory pad 78. In some embodiments, Figure 9An embodiment can be considered to include a first memory cell associated with a real digital line and a second memory cell associated with a complementary digital line.

[0059] Depend on Figure 7 The folding architecture illustrated in the embodiments is superior to that of... Figure 8 and 9 The embodiments illustrate an open architecture because complementary digital lines within the folded architecture can provide shielding between adjacent real digital lines. However, there may be applications that require an open architecture due to constraints imposed during manufacturing, for example.

[0060] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" refers to electronic circuitry supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0061] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0062] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be for the purpose of providing linguistic variation within this disclosure to simplify the premises of the following claims, and not to indicate any significant chemical or electrical differences.

[0063] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some cases and another in others may be to provide linguistic variation within this disclosure to simplify the premises of the following claims. The term "coupling" (couple, coupling, coupled, etc.) may refer to an electrical connection.

[0064] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The description provided herein and the appended claims relate to any structure having the described relationships between various features, whether the structure is in a specific orientation of the drawings or rotated relative to such an orientation.

[0065] Unless otherwise specified, the accompanying cross-sectional views show only the features within the cross-sectional plane and not the material behind the cross-sectional plane in order to simplify the drawings.

[0066] When a structure is referred to above as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be intervening structures. In contrast, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0067] A structure (e.g., a layer, material, etc.) may be described as “vertically extending” to indicate that the structure typically extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may extend substantially orthogonally relative to or not relative to the upper surface of the substrate.

[0068] Some embodiments include an integrated assembly having a set of true digital lines and a set of complementary digital lines. Each of the complementary digital lines is coupled to an associated true digital line. A semiconductor substrate lies beneath the true digital lines. The semiconductor substrate includes semiconductor features projecting upward from a semiconductor substrate and extending along a first direction. Each of the semiconductor features has opposing sidewalls. A first source / drain region is within the semiconductor feature, and a second source / drain region is within the semiconductor substrate. The true digital lines extend along a second direction intersecting the first direction. The true digital lines are coupled to the first source / drain regions. Word lines extend along the opposing sidewalls and include gating regions that selectively couple the first source / drain regions to the second source / drain regions. A memory element is coupled to the second source / drain region. The memory element is contained within a memory cell.

[0069] Some embodiments include an integrated assembly having semiconductor features projecting upward from a semiconductor substrate and extending along a first direction. Each of the semiconductor features has opposing sidewalls. A first source / drain region is located within an upper portion of the semiconductor feature. A second source / drain region is located within the substrate. A dielectric structure is located along the opposing sidewalls of the semiconductor features. The dielectric structure has a first region along the opposing sidewalls and a second region along the substrate. A first conductive structure is located along the dielectric structure. The first conductive structure is located above the second region of the dielectric structure and is spaced apart from the semiconductor feature by at least the first region of the dielectric structure. The first conductive structure extends along a first direction. The first conductive structure includes a gated region that selectively couples the first source / drain region and the second source / drain region to each other. A second conductive structure is located above the semiconductor feature and extends along a second direction intersecting the first direction. The second conductive structure alternates between a true second conductive structure and a complementary second conductive structure. The true second conductive structure is coupled to the first source / drain region. The complementary second conductive structure is coupled to the true second conductive structure. A memory element is coupled to the second source / drain region.

[0070] Some embodiments include an integrated assembly having a set of true digital lines and a set of complementary digital lines. Each of the complementary digital lines is coupled to an associated true digital line. A semiconductor substrate lies beneath the true digital lines and the complementary digital lines. The semiconductor substrate includes semiconductor features projecting upward from a semiconductor substrate and extending along a first direction. Each of the semiconductor features has opposing sidewalls. A first source / drain region is within the semiconductor feature, and a second source / drain region is within the semiconductor substrate. The true digital lines and the complementary digital lines extend along a second direction intersecting the first direction and alternate with each other along the first direction. The true digital lines are coupled to the first source / drain region. Word lines extend along opposing sidewalls and include gating regions that couple the first source / drain region to the second source / drain region in a gating manner. A memory element is coupled to the second source / drain region and is contained within a memory cell. The complementary digital lines are coupled to a reference voltage source.

[0071] As specified, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writing and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: A set of real digital lines and a set of complementary digital lines; each of the complementary digital lines is relatively coupled to an associated real digital line. A semiconductor substrate located beneath the actual digital line; the semiconductor substrate includes semiconductor features that project upward from a semiconductor substrate and extend along a first direction; Each of the semiconductor features has opposing sidewalls; a first source / drain region is located within the semiconductor feature, and a second source / drain region is located within the semiconductor substrate; The real digital line extends along a second direction that intersects the first direction; The real digital line is coupled to the first source / drain region; Word lines, which run along the opposite sidewalls and include gating regions that couple the first source / drain region to the second source / drain region in a gating manner; and A storage element coupled to the second source / drain region; the storage element is contained within a memory cell.

2. The integrated assembly of claim 1, wherein the complementary digital lines alternate with the real digital lines in the folded architecture.

3. The integrated assembly of claim 2, wherein the complementary digital line is coupled to a reference voltage source.

4. The integrated assembly of claim 1, wherein the complementary digital line is laterally offset from the real digital line in an open architecture.

5. The integrated assembly of claim 4, wherein the memory cell is a first memory cell associated with the real digital line, and the integrated assembly further includes a second memory cell associated with the complementary digital line.

6. The integrated assembly of claim 4, wherein the complementary digital line is coupled to a reference voltage source.

7. The integrated assembly of claim 1, wherein the second direction is orthogonal to the first direction.

8. The integrated assembly of claim 1, wherein the storage element is a capacitor.

9. An integrated assembly comprising: Semiconductor features that protrude upward from the semiconductor substrate and extend along a first direction; Each of the semiconductor features has opposing sidewalls; The first source / drain region is located within the upper portion of the semiconductor feature; A second source / drain region is located within the substrate; A dielectric structure having a first region along the opposing sidewalls of the semiconductor feature and a second region along the substrate; A first conductive structure is provided along the dielectric structure; the first conductive structure is above the second region of the dielectric structure and spaced apart from the semiconductor feature by at least the first region of the dielectric structure, the first conductive structure extending along the first direction; the first conductive structure includes a gating region that couples the first source / drain region and the second source / drain region to each other in a gating manner. A second conductive structure extends above the semiconductor feature and along a second direction intersecting the first direction; The second conductive structure alternates between a real second conductive structure and a complementary second conductive structure; the real second conductive structure is coupled to the first source / drain region; the complementary second conductive structure is coupled to the real second conductive structure. and A storage element coupled to the second source / drain region.

10. The integrated assembly of claim 9, wherein the semiconductor feature and the semiconductor substrate comprise the same semiconductor composition as each other.

11. The integrated assembly of claim 10, wherein the semiconductor feature and the semiconductor substrate comprise silicon.

12. The integrated assembly of claim 9, wherein the semiconductor feature and the semiconductor substrate comprise semiconductor compositions that are different from each other.

13. The integrated assembly of claim 9, wherein the dielectric structure comprises silicon dioxide.

14. The integrated assembly of claim 9, wherein the first conductive structure includes a width ranging from about 2 nanometers to about 100 nanometers.

15. The integrated assembly of claim 9, wherein the first conductive structure includes a width ranging from about 2 nanometers to about 50 nanometers.

16. The integrated assembly of claim 9, wherein the first conductive structure is a word line and coupled to a word line driver circuit system.

17. The integrated assembly of claim 9, wherein the second conductive structure is a digital line, and wherein the relative coupling utilizes a sense amplifier circuit system that couples the real digital line to the complementary digital line.

18. The integrated assembly of claim 9, wherein the complementary second conductive structure is coupled to a reference voltage source.

19. The integrated assembly of claim 18, wherein the storage element is contained within a memory cell of a memory array; and wherein the reference voltage source provides a static reference voltage during operation of the memory array.

20. The integrated assembly of claim 18, wherein the storage element is contained within a memory cell of a memory array; and wherein the reference voltage source provides a dynamic reference voltage during operation of the memory array.

21. The integrated assembly of claim 9, wherein the storage element is a capacitor.

22. The integrated assembly of claim 21, wherein the capacitor is coupled to the second source / drain region via a conductive interconnect.

23. The integrated assembly of claim 22, wherein the second conductive structure is manufactured using a photolithography process having an associated minimum feature size F; wherein the conductive interconnects are located within a unit cell of the memory array; and wherein each unit cell has a feature size not greater than approximately 4F. 2 The area.

24. An integrated assembly comprising: A set of real digital lines and a set of complementary digital lines; each of the complementary digital lines is relatively coupled to an associated real digital line. A semiconductor substrate is located beneath the real digital lines and the complementary digital lines; the semiconductor substrate includes semiconductor features that project upward from a semiconductor substrate and extend along a first direction; Each of the semiconductor features has opposing sidewalls; a first source / drain region is located within the semiconductor feature, and a second source / drain region is located within the semiconductor substrate; The real digital line and the complementary digital line extend along a second direction that intersects the first direction and alternate with each other along the first direction; the real digital line is coupled to the first source / drain region; Word lines, which run along the opposite sidewalls and include gating regions that couple the first source / drain region to the second source / drain region in a gating manner; A storage element coupled to the second source / drain region and contained within a memory cell; and The complementary digital line is coupled to a reference voltage source.

25. The integrated assembly of claim 24, comprising a sense amplifier circuit system configured to provide the relative coupling between the real digital line and the complementary digital line; wherein the sense amplifier circuit system is laterally offset from a first end of the real digital line and the complementary digital line; and wherein the reference voltage source is laterally offset from a second end of the complementary digital line, wherein the second end is relative to the first end.

26. The integrated assembly of claim 24, wherein the memory cell is contained within a memory array; wherein the memory element is coupled to the second source / drain region via conductive interconnects; wherein the real digital line and the complementary digital line are fabricated using a photolithography process having an associated minimum feature size F; wherein the conductive interconnects are located within a unit cell of the memory array; and wherein each unit cell has a feature size not greater than approximately 4F. 2 The area.

27. The integrated assembly of claim 24, wherein the word lines are spaced apart from the semiconductor substrate by a gate dielectric material.

28. The integrated assembly of claim 27, wherein the gate dielectric material is configured in an L-shape, wherein the vertical legs of the L-shape extend along the semiconductor feature, and wherein the horizontal legs of the L-shape extend along the semiconductor substrate.

29. The integrated assembly of claim 28, wherein the gate dielectric material comprises silicon dioxide.

30. The integrated assembly of claim 24, wherein the complementary digital lines are configured to provide shielding between the real digital lines in a folded digital line architecture.

31. The integrated assembly of claim 24, wherein the storage element is a capacitor.

32. The integrated assembly of claim 24, wherein the reference voltage source provides a voltage in the range from greater than or equal to VSS to less than or equal to VCC.

Images