Semiconductor element and method for manufacturing the same

Abstract

This invention discloses a semiconductor device and its fabrication method. The method for fabricating the semiconductor device involves first forming a magnetic tunneling junction (MTJ) on a substrate, then forming an upper electrode on the MTJ, forming an intermetallic dielectric layer surrounding the upper electrode and the MTJ, forming a contact layer on the intermetallic dielectric layer and the MTJ, and then patterning the contact layer to form a contact pad, wherein the contact pad is disposed on the upper electrode and the intermetallic dielectric layer on one side of the upper electrode.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a magnetic tunneling junction (MTJ) is formed on a substrate. Then, an upper electrode is formed on the MTJ. An intermetallic dielectric layer is formed around the upper electrode and the MTJ. A contact layer is formed on the intermetallic dielectric layer and the MTJ. The contact layer is then patterned to form a contact pad, wherein the contact pad is disposed on the upper electrode and the intermetallic dielectric layer on one side of the upper electrode.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, an upper electrode disposed on the MTJ, an intermetallic dielectric layer surrounding the upper electrode and the MTJ, and a contact pad disposed on the upper electrode and the intermetallic dielectric layer, wherein the contact pad is disposed on the upper electrode and the intermetallic dielectric layer on one side of the upper electrode. Attached Figure Description

[0006] Figures 1 to 9 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 12: Base

[0009] 14: MRAM region

[0010] 16: Logical Area

[0011] 18: Interlayer dielectric layer

[0012] 20: Metal interconnect structure

[0013] 22: Metal interconnect structure

[0014] 24: Intermetallic dielectric layer

[0015] 26: Metal interconnects

[0016] 28: Stop Layer

[0017] 30: Intermetallic dielectric layer

[0018] 32: Metal interconnects

[0019] 34: Barrier Layer

[0020] 36: Metal layer

[0021] 38: MTJ stacked structure

[0022] 42: Lower electrode

[0023] 44: Fixed layer

[0024] 46: Barrier Layer

[0025] 48: Free Layer

[0026] 50: Upper electrode

[0027] 52:MTJ

[0028] 56: Covering layer

[0029] 58: Interstitial wall

[0030] 60: Interstitial wall

[0031] 62: Intermetallic dielectric layer

[0032] 64: Contact layer

[0033] 66: Contact pad

[0034] 68: Intermetallic dielectric layer

[0035] 70: Metal interconnects

[0036] 72: Stop Layer

[0037] 74: Intermetallic Dielectric Layer

[0038] 76: Metal interconnects

[0039] 78: Stop Layer Detailed Implementation

[0040] Please refer to Figures 1 to 9 , Figures 1 to 9 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0041] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0042] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0043] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethylorthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0044] Next, a lower electrode 42, an MTJ stack structure 38, an upper electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer 44 can also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 46 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layer 48 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field.

[0045] Subsequently, as Figure 2 As shown, a patterned mask is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 38, a portion of the lower electrode 42, and a portion of the intermetallic dielectric layer 30 to form multiple MTJs 52 in the MRAM region 14. It is worth noting that the etching process performed on the patterned upper electrode 50, MTJ stack structure 38, lower electrode 42, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, it is preferable to remove part of the metal interconnects 32 at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 52.

[0046] A masking layer 56 is then formed on the MTJ 52 and covers the surface of the inter-metal dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 56 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.

[0047] Then as Figure 3 As shown, a portion of the masking layer 56 is first removed by etch-back to form spacer walls 58 and 60 on the sidewalls of each MTJ 52. Then, an atomic layer deposition process is performed to form an intermetallic dielectric layer 62 covering each MTJ 52 and the intermetallic dielectric layer 30 of the logic region 16. In this embodiment, the intermetallic dielectric layer 62 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, for example, but not limited to silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0048] like Figure 4 As shown, one or more etch-back processes are then performed to remove part of the intermetallic dielectric layer 62 of the MRAM region 14 and the logic region 16. For example, in this embodiment, part of the intermetallic dielectric layer 62 of the MRAM region 14 and the logic region 16 can be completely removed first, so that the top of the intermetallic dielectric layer 62 is aligned with the top of the upper electrode 50. Then, a patterned mask (not shown) is used to cover the MRAM region 14, removing all the remaining intermetallic dielectric layer 62 of the logic region 16 and exposing the underlying intermetallic dielectric layer 30. At the same time, the remaining intermetallic dielectric layer 62 is only disposed around the MTJ 52 of the MRAM region 14.

[0049] Subsequently, as Figure 5 As shown, a contact layer 64 is formed in the MRAM region 14 and the logic region 16. The contact layer 64 is preferably disposed on the top of the upper electrode 50 and the top and sidewalls of the intermetallic dielectric layer 62 in the MRAM region 14, and on the top of the intermetallic dielectric layer 30 in the logic region 16. In this embodiment, the contact layer 64 preferably comprises a conductive material, such as, but not limited to, titanium, tantalum, titanium nitride, or tantalum nitride.

[0050] like Figure 6 As shown, the contact layer 64 is then patterned to form contact pads 66 on each MTJ 52 in the MRAM region. More specifically, in this stage, a photolithography and etching process is preferably used to remove part of the contact layer 64 of the MRAM region 14 and all of the contact layer 64 of the logic region 16, so that the remaining contact layer 64 of the MRAM region 14 forms a plurality of contact pads 66 on the MTJ 52, wherein each contact pad 66 preferably completely covers the upper electrode 50 directly above the MTJ 52 and the gap wall 60 and intermetallic dielectric layer 62 on one side of the upper electrode 50, but does not cover the gap wall 60 and intermetallic dielectric layer 62 on the other side of the upper electrode 50.

[0051] Then as Figure 7 As shown, an intermetallic dielectric layer 68 is first formed on the MRAM region 14 and the logic region 16, covering the contact pad 66 and intermetallic dielectric layer 62 of the MRAM region 14 and the intermetallic dielectric layer 30 of the logic region 16. Then, a pattern transfer fabrication process is performed. For example, a patterned mask (not shown) can be used to remove part of the intermetallic dielectric layer 68, part of the intermetallic dielectric layer 30 and part of the stop layer 28 of the logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. Then, the contact holes are filled with the required metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization process is performed, such as chemical mechanical polishing, to remove some of the metal material to form contact plugs or metal interconnects 70 that electrically connect the metal interconnects 26 within the contact holes. In this embodiment, the intermetallic dielectric layer 68 preferably comprises an ultra-low dielectric constant dielectric layer, which may comprise a porous dielectric material such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0052] like Figure 8 As shown, a planarization process is then performed, for example, by using chemical mechanical polishing (CMP) to remove part of the intermetallic dielectric layer 68 of the MRAM region 14 and part of the intermetallic dielectric layer 68 and the metal interconnect 70 of the logic region 16, thereby exposing the contact pad 66 of the MRAM region 14 and aligning the top of the metal interconnect 70 of the logic region 16 with the top of the intermetallic dielectric layer 68 and the contact pad 66 of the MRAM region 14.

[0053] Subsequently, as Figure 9As shown, a stop layer 72 is first formed on the MRAM region 14 and logic region 16, covering the contact pad 66, the intermetallic dielectric layer 68, and the metal interconnects 70. An intermetallic dielectric layer 74 is then formed on the stop layer 72. One or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 74 and part of the stop layer 72 in the MRAM region 14 and logic region, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 76 in the MRAM region 14 and logic region 16, connecting the underlying MTJ 52 and metal interconnects 70. Preferably, the metal interconnects 76 in the MRAM region 14 directly contact the contact pad 66 below, while the metal interconnects 76 in the logic region 16 contact the underlying metal interconnects 70. Then, another stop layer 78 is formed on the intermetallic dielectric layer 70, covering the metal interconnects 70.

[0054] In this embodiment, stop layer 72 and stop layer 78 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 76 disposed within the intermetallic dielectric layer 74 can be embedded within the intermetallic dielectric layer 74 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 76 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0055] Please refer to again Figure 9 , Figure 9 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 9As shown, the semiconductor device mainly includes at least one MTJ 52 disposed on the substrate 12 in an MRAM region 14, an upper electrode 50 disposed on the MTJ 52, a spacer wall 58 disposed on one side of the upper electrode 50, a spacer wall 60 disposed on the other side of the upper electrode 50, a contact pad 66 disposed on the upper electrode 50 and the inter-metal dielectric layer 62 next to the upper electrode 50, an inter-metal dielectric layer 68 disposed on the MRAM region 14 and the logic region 16 and surrounding the inter-metal dielectric layer 62 and the contact pad 66 in the MRAM region 14, a metal interconnect 70 disposed within the inter-metal dielectric layer 68 in the logic region 16, a stop layer 72 disposed on the contact pad 66 in the MRAM region 14 and the inter-metal dielectric layer 68 in the logic region 16, an inter-metal dielectric layer 74 disposed on the stop layer 72 and the metal interconnect 76 disposed within the inter-metal dielectric layer 74, respectively electrically connecting the contact pad 66 and the metal interconnect 70 in the logic region 16.

[0056] In detail, the top of the contact pads 66 in the MRAM region 14 is preferably flush with the top of the metal interconnects 70 in the logic region 16. One sidewall of each contact pad 66, for example, the left sidewall, is preferably flush with the sidewall of the upper electrode 50, while the other sidewall of the contact pad 66, for example, the right sidewall, is disposed on the intermetallic dielectric layer 62. It is worth noting that since the metal interconnects 76 connecting the upper electrode 50 are generally located directly above the MTJ 52 and / or the upper electrode 50, the downward pressing of the metal interconnects 76 can easily increase the stress on the lower MTJ 52. Therefore, in this invention, the center point of the metal interconnects 76 connecting the MTJ 52 and / or the upper electrode 50 is preferably slightly offset from the center point of the MTJ 52 or the upper electrode 50, so that the bottom of the metal interconnects 76 contacts the contact pads 66 located on one side of the upper electrode 50 rather than the contact pads 66 located directly above the upper electrode 50, while the left and right sidewalls of the upper electrode 50 are still flush with the left and right sidewalls of the lower MTJ 52.

[0057] In other words, the bottom portion of the metal interconnect 76 that directly contacts the contact pad 66 is preferably located directly above the intermetallic dielectric layer 62 on the side of the upper electrode 50, or even overlapping a portion of the gap wall 60 on the side of the upper electrode 50, but preferably does not overlap any of the upper electrode 50 and MTJ 52. Furthermore, at least one sidewall of the metal interconnect 76 may be flush with or not flush with the sidewall of the contact pad 66 below. If one sidewall of the metal interconnect 76 is not flush with the sidewall of the contact pad 66 below, the bottom of the metal interconnect 76 can simultaneously contact the contact pad 66 and the top of the intermetallic dielectric layer 68, for example... Figure 9 The metal interconnect 76 connecting the right side MTJ 52 is included; these variations are all within the scope of this invention. In this embodiment, the contact pad 66 and the upper electrode 50 may contain the same or different materials, and both may contain conductive materials such as, but not limited to, titanium, tantalum, titanium nitride, or tantalum nitride.

[0058] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, comprising: forming a magnetic tunneling junction (MTJ) on a substrate, the substrate comprising an MRAM region and a logic region; forming an upper electrode on the magnetic tunneling junction; forming a first intermetallic dielectric layer around the upper electrode and the magnetic tunneling junction; forming a contact layer on the MRAM region and the logic region; and patterning the contact layer to form a contact pad on the upper electrode and the first intermetallic dielectric layer.

2. The method of claim 1, wherein the method comprises: forming a second intermetallic dielectric layer on the MRAM region and the logic region; forming a first metal interconnect within the second intermetallic dielectric layer of the MRAM region; forming the magnetic tunneling junction on the first metal interconnect; forming the first intermetallic dielectric layer on the MRAM region and the logic region; removing the first intermetallic dielectric layer of the logic region; forming the contact layer on the MRAM region and the logic region; patterning the contact layer to form the contact pad on the MRAM region; forming a third intermetallic dielectric layer on the first intermetallic dielectric layer of the MRAM region and the second intermetallic dielectric layer of the logic region; and forming a second metal interconnect on the logic region.

3. The method of claim 2, further comprising: forming a capping layer on the upper electrode and the second intermetallic dielectric layer; removing the capping layer to form a spacer around the magnetic tunneling junction; and forming the first intermetallic dielectric layer on the spacer.

4. The method of claim 2, further comprising: forming the contact layer on the upper electrode, the first intermetallic dielectric layer sidewall, and the second intermetallic dielectric layer top; and patterning the contact layer to form the contact pad on the upper electrode and the first intermetallic dielectric layer.

5. The method of claim 2, wherein the contact pad top is aligned with the second metal interconnect top.

6. The method of claim 2, further comprising: forming a stop layer on the contact pad and the second metal interconnect; forming a fourth intermetallic dielectric layer on the stop layer; and forming a third metal interconnect on the MRAM region to connect the contact pad and fourth metal interconnect on the logic region to connect the second metal interconnect.

7. The method of claim 1, wherein the contact pad sidewall is aligned with the upper electrode sidewall.

8. The method of claim 1, wherein the contact pad and the upper electrode comprise the same material.

9. The method of claim 1, wherein the contact pad and the upper electrode comprise different materials. comprising:

10. A semiconductor element characterized by comprising: a magnetic tunneling junction (MTJ) on a substrate, the substrate comprising an MRAM region and a logic region; an upper electrode on the magnetic tunneling junction; a first intermetallic dielectric layer around the upper electrode and the magnetic tunneling junction; a contact pad on the upper electrode and the first intermetallic dielectric layer of the MRAM region; a first metal interconnect on the logic region; and a second metal interconnect on the logic region. ​ a second intermetal dielectric layer surrounding the first intermetal dielectric layer, the contact pad, and the first metal interconnect.

11. The semiconductor device of claim 10, further comprising: a first spacer disposed on one side of the upper electrode; and a second spacer disposed on another side of the upper electrode, wherein the contact pad is disposed on the upper electrode, the second spacer, and the first intermetal dielectric layer.

12. The semiconductor device of claim 10, further comprising: a stop layer disposed on the contact pad and the second intermetal dielectric layer; a third intermetal dielectric layer disposed on the stop layer; a second metal interconnect disposed in the MRAM region and connected to the contact pad; and a third metal interconnect disposed in the logic region and connected to the first metal interconnect.

13. The semiconductor device of claim 10, wherein a top of the contact pad is aligned with a top of the first metal interconnect.

14. The semiconductor device of claim 10, wherein a sidewall of the contact pad is aligned with a sidewall of the upper electrode.

15. The semiconductor device of claim 10, wherein the contact pad and the upper electrode comprise a same material.

16. The semiconductor device of claim 10, wherein the contact pad and the upper electrode comprise different materials.

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