Semiconductor device and method for manufacturing semiconductor device

Abstract

For a semiconductor device having a longitudinal structure, problems caused by the influence of crystal defects introduced into the wafer during the formation of a buffer layer are solved, and improvements in various characteristics are achieved. The semiconductor device includes: an N- drift layer (14) of a first conductivity type, which is formed on a semiconductor substrate; a P base layer (9), which is formed on the N- drift layer (14); and an N buffer layer (15) of the first conductivity type, which is formed under the N- drift layer (14) and has a peak impurity concentration higher than that of the N- drift layer (14). The N buffer layer (15) includes: a first buffer layer (15-1), which is a layer in which trap levels originating from lattice defects are not detected by photoluminescence; and a second buffer layer (15-2), which is provided between the first buffer layer (15-1) and the N- drift layer (14) and in which two trap levels originating from lattice defects are detected by photoluminescence.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Existing vertical semiconductor devices such as trench gate IGBT (Insulated Gate Bipolar Transistor) and PiN (P-intrinsic-N) diodes have a vertical structure. In the case of IGBT, the region including the N-type drift layer, the N-type buffer layer and the P-type collector layer is a region of the vertical structure, and in the case of diode, the region including the N-type drift layer, the N-type buffer layer and the N-type cathode layer is a region of the vertical structure. Patent document 1 discloses an IGBT having a vertical structure. In addition, Patent document 2 discloses a structure having a stacked structure in which a plurality of layers constitute an N-type buffer layer.

[0003] In conventional semiconductor devices such as IGBTs and diodes having a vertical structure, a wafer manufactured by the FZ method is sometimes used as a Si wafer for forming the semiconductor device instead of a wafer manufactured by epitaxial growth. In this case, the vertical structure region of the wafer, such as the N-type buffer layer of the IGBT, has a high impurity concentration, and the impurity distribution has a steep gradient until the junction with the N-type drift layer.

[0004] Patent Document 1: International Publication No. 2014 / 054121

[0005] Patent Document 2: Japanese Patent Application Publication No. 2020-027921

[0006] The above impurity distribution in the buffer layer of a semiconductor device having a vertical structure has various problems such as poor controllability of the turn-off operation and reduction in the interruption capability during turn-off.

[0007] The purpose of the technology of Patent Document 2 is to solve these problems. However, in Patent Document 2, there are descriptions related to the depth, impurity concentration, and impurity distribution of the N-type buffer layer, but there is no discussion on the relationship between the crystal defects introduced into the Si wafer during the formation of the N-type buffer layer and the device characteristics, and the feasibility of power semiconductor elements is lacking. As described later, the crystal defects introduced into the Si wafer are an important cause that affects the controllability of the carrier plasma layer and electric field intensity, which are important during the dynamic operation of the power semiconductor element. Summary of the invention

[0008] The present invention is proposed to solve the above-mentioned problems, and its purpose is to solve the problems caused by the influence of crystal defects introduced into the chip when the buffer layer is formed in a semiconductor device with a vertical structure, and to achieve stable withstand voltage characteristics, low turn-off loss accompanied by reduced leakage current when turned off, improved controllability of the turn-off action and improved circuit breaking capacity when turned off.

[0009] The semiconductor device according to the present invention comprises: a semiconductor substrate having a first main surface and a second main surface; a drift layer of a first conductivity type formed on the semiconductor substrate; an impurity diffusion layer of a second conductivity type formed on the first main surface side of the drift layer; and a buffer layer of a first conductivity type formed on the second main surface side of the drift layer, the peak impurity concentration of which is higher than that of the drift layer, the buffer layer comprising: a first buffer layer, which is a layer in which no trap energy levels originating from lattice defects are detected by a photoluminescence method; and a second buffer layer, which is a layer arranged between the first buffer layer and the drift layer, and in which two types of trap energy levels originating from lattice defects are detected by the photoluminescence method.

[0010] Effects of the Invention

[0011] According to the present invention, the problem caused by the influence of crystal defects introduced into the chip when forming the N-type buffer layer can be solved, and stable voltage resistance characteristics, low disconnection loss accompanied by reduced leakage current during disconnection, improved controllability of the cut-off action and improved circuit breaking capacity during cut-off can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a top view of the semiconductor device according to Embodiments 1 to 3.

[0013] Figure 2 This is a cross-sectional view of the RFC diode according to the first embodiment.

[0014] Figure 3 1 is a cross-sectional view showing an example of the structure of the outer peripheral portion of a semiconductor device including the RFC diode according to the first embodiment.

[0015] Figure 4 This is a diagram for explaining the target function of the N buffer layer.

[0016] Figure 5 This is a diagram for explaining the target function of the N buffer layer.

[0017] Figure 6 This is a diagram for explaining the target function of the N buffer layer.

[0018] Figure 7 It is a diagram showing the PL spectrum results of the first buffer layer and the second buffer layer.

[0019] Figure 8 represents the area from the lower surface of the second buffer layer to N - Plot of the variation of the trap B ratio of the drift layer.

[0020] Fig. 9 It is a diagram showing the simulation results of the recovery waveforms (1200 V class) of the conventional structure RFC diode and the new structure RFC diode.

[0021] Fig.10 yes Fig. 9 A magnified view of a portion of .

[0022] Fig.11 The PNP transistor area of ​​the conventional RFC diode is shown in FIG. Fig.10 A diagram showing simulation results of the carrier concentration distribution and the electric field intensity distribution between the first main surface and the second main surface at the analysis point.

[0023] Fig.12 The PNP transistor area of ​​the new RFC diode structure is shown in FIG. Fig.10 Graph showing simulation results of carrier concentration distribution and electric field intensity distribution between the first main surface and the second main surface at analysis points shown.

[0024] Fig.13 It is a diagram showing the simulation results of the recovery waveforms (4.5 kV level) of the conventional structure RFC diode and the new structure RFC diode during the rapid recovery operation.

[0025] Fig.14 Yes means Fig.13 Graph showing the current density distribution in the conventional RFC diode and the new RFC diode at the analysis points T1 to T7.

[0026] Fig.15 This is a graph showing the PiN diode area of ​​the conventional RFC diode. Fig.13 Graph of the electron concentration distribution at analysis points T1 to T7.

[0027] Fig.16 The PiN diode area of ​​the new structure RFC diode is shown in Fig.13 Graph of the electron concentration distribution at analysis points T1 to T7.

[0028] Fig.17 This is a graph showing the PiN diode area of ​​the conventional RFC diode. Fig.13 Graph of the hole concentration distribution at the analysis points T1 to T7.

[0029] Fig.18 The PiN diode area of ​​the new structure RFC diode is shown in Fig.13 Graph of the hole concentration distribution at the analysis points T1 to T7.

[0030] Fig.19 This is a graph showing the PiN diode area of ​​the conventional RFC diode. Fig.13 Graph of the electric field intensity distribution at analysis points T1 to T7.

[0031] Fig. 20 The PiN diode area of ​​the new structure RFC diode is shown in Fig.13 Graph of the electric field intensity distribution at analysis points T1 to T7.

[0032] Fig.21 The PNP transistor area of ​​the conventional RFC diode is shown in FIG. Fig.13 Graph of the electron concentration distribution at analysis points T1 to T7.

[0033] Fig. 22 The PNP transistor area of ​​the new RFC diode structure is shown in FIG. Fig.13 Graph of the electron concentration distribution at analysis points T1 to T7.

[0034] Fig.23 The PNP transistor area of ​​the conventional RFC diode is shown in FIG. Fig.13 Graph of the hole concentration distribution at the analysis points T1 to T7.

[0035] Fig.24 The PNP transistor area of ​​the new RFC diode structure is shown in FIG. Fig.13 Graph of the hole concentration distribution at the analysis points T1 to T7.

[0036] Fig.25 The PNP transistor area of ​​the conventional RFC diode is shown in FIG. Fig.13 Graph of the electric field intensity distribution at analysis points T1 to T7.

[0037] Fig.26 The PNP transistor area of ​​the new RFC diode structure is shown in FIG. Fig.13 Graph of the electric field intensity distribution at analysis points T1 to T7.

[0038] Fig. 27 This shows the J at 298K of the 1200V class new structure RFC diode produced on trial basis. R -V R Plot of the Trap B ratio dependence of the characteristics.

[0039] Fig.28 This is a diagram showing the Trap B ratio dependency of the fast recovery waveform of a trial-produced 1200V class new structure RFC diode at low temperature.

[0040] Fig.29 This is a graph summarizing the relationship between the performance of the 1200V class new structure RFC diode device and the Trap B ratio.

[0041] Fig.30 This is a graph showing the relationship between the safe operating temperature range and the Trap B ratio in the fast mode of a 1200V class new structure RFC diode.

[0042] Fig.31 This is a graph showing the operating temperature dependency of the output characteristics of a prototype 1200V class RFC diode with a new structure.

[0043] Fig.32 J indicates the newly manufactured 1200V class RFC diode. R -V R Plot of the operating temperature dependence of the characteristics.

[0044] Fig.33 The graph shows the recovery waveforms of a conventional structure RFC diode and a new structure RFC diode of a 1200V class that were trial-produced.

[0045] Fig.34 This is a diagram showing the recovery waveforms of the fast mode at low temperature of the conventional structure RFC diode and the new structure RFC diode of the 1200V class produced by trial.

[0046] Fig.35 This is a graph showing the relationship between the power supply voltage and the reverse recovery charge at 253K of a 1200V class RFC diode with a conventional structure and a RFC diode with a new structure that were trial-produced.

[0047] Fig.36 This is a graph showing the relationship between the operating temperature and the reverse recovery charge amount at a power supply voltage of 1000 V for a conventional structure RFC diode and a new structure RFC diode of a 1200 V class that were trial-produced.

[0048] Fig.37 This is a diagram showing the comparison results of the safe operating temperature range of the fast mode under low temperature of the 1200V class conventional structure RFC diode and the new structure RFC diode which were trial-produced.

[0049] Fig.38 This is a diagram showing the recovery waveform of a 1200V class new structure RFC diode produced at a high temperature (473K).

[0050] Fig.39 This shows the V of the 1200V class conventional RFC diode and the new RFC diode that were produced. F -E RECPlot of trade-off characteristics.

[0051] Fig.40 This is a cross-sectional view of a PiN diode according to the second embodiment.

[0052] Fig.41 1 is a cross-sectional view showing an example of the structure of the peripheral portion of a semiconductor device including the PiN diode according to the second embodiment.

[0053] Fig.42 The graph shows waveforms of the conventional structure PiN diode and the new structure PiN diode of the 4.5 kV class produced by trial production during the rapid recovery operation.

[0054] Fig.43 This is a diagram showing the relationship between the power supply voltage and the step voltage at 298K for a conventional structure PiN diode and a new structure PiN diode of a 4.5 kV class that were trial-produced.

[0055] Fig.44 This is a graph showing the relationship between the power supply voltage and the reverse recovery charge at 298K of a conventional structure PiN diode and a new structure PiN diode of a 4.5 kV class that were trial-produced.

[0056] Fig.45 It is a cross-sectional view of an IGBT according to the third embodiment.

[0057] Fig.46 1 is a cross-sectional view showing an example of the structure of the outer peripheral portion of a semiconductor device including the IGBT according to the third embodiment.

[0058] Fig.47 1 is a cross-sectional view showing an example of the structure of the outer peripheral portion of a semiconductor device including the IGBT according to the third embodiment.

[0059] Fig.48 The diagram shows simulation results of the electric field intensity distribution inside the device in the short-circuit state of the conventional structure IGBT and the new structure IGBT.

[0060] Fig.49 The figure shows the simulation results of the relationship between the electric field intensity and the on-voltage at the device surface and back surface in the short-circuit state of the conventional structure IGBT and the new structure IGBT.

[0061] Fig.50 The diagram shows the simulation results of the temperature distribution inside the device in the short-circuit state of the conventional structure IGBT and the new structure IGBT.

[0062] Fig.51 It is analyzing Fig.50 The short-circuit waveform in the simulation when the temperature distribution inside the device is shown.

[0063] Fig.52 This is a diagram showing the turn-off waveforms at 298K of a 1200V class conventional structure IGBT and a new structure IGBT produced by trial.

[0064] Fig.53 The graph shows the short-circuit waveforms at 423K of a 1200V-class conventional structure IGBT and a new structure IGBT produced on a trial basis.

[0065] Fig.54 This is a diagram showing the relationship between the maximum energy density that can be cut off during a short circuit and the thickness of the device for a 1200V class conventional structure IGBT and a new structure IGBT that were trial-produced.

[0066] Fig.55 This is a diagram showing the trade-off characteristics between the on-voltage and the off-time loss of a 1200V class conventional structure IGBT and a new structure IGBT that were trial-produced.

[0067] Fig.56 This is a diagram showing the relationship between the main junction leakage current and the collector-emitter voltage at 423K of a 6.5 kV class conventional structure IGBT and a new structure IGBT that were trial-produced.

[0068] Fig.57 This is a diagram showing the turn-off waveforms at 213K of a 6.5 kV class IGBT of conventional structure and a new structure IGBT produced by trial.

[0069] Fig.58 This is the process flow chart of IGBT.

[0070] Fig.59 This is the process flow chart of IGBT.

[0071] Fig.60 This is the process flow chart of IGBT.

[0072] Fig.61 This is the process flow chart of IGBT.

[0073] Fig.62 This is the process flow chart of IGBT.

[0074] Fig.63 This is the process flow chart of IGBT.

[0075] Fig.64 This is the process flow chart of IGBT.

[0076] Fig.65 This is the process flow chart of IGBT.

[0077] Fig.66This is the process flow chart of IGBT.

[0078] Fig.67 This is the process flow chart of IGBT.

[0079] Fig.68 This is the process flow chart of IGBT.

[0080] Fig.69 This is the process flow chart of IGBT.

[0081] Fig.70 This is the process flow chart of IGBT.

[0082] Fig.71 This is the process flow chart of RFC diode.

[0083] Fig.72 This is the process flow chart of RFC diode.

[0084] Fig.73 This is the process flow chart of RFC diode.

[0085] Fig.74 This is the process flow chart of RFC diode.

[0086] Fig.75 This is the process flow chart of RFC diode.

[0087] Fig.76 This is the process flow chart of RFC diode.

[0088] Fig.77 This is the process flow chart of RFC diode.

[0089] Fig.78 This is the process flow chart of RFC diode.

[0090] Fig.79 This is the process flow chart of RFC diode.

[0091] Fig.80 It is a comparison diagram of the process flow.

[0092] Fig.81 is the carrier lifetime and N obtained from the simulation - The thickness of the drift layer (t N- ) is a graph of the relationship between .

[0093] Fig.82 is a summary of Fig.80 The performance of 1200V class RFC diodes produced by trial production using the compared process flows is shown in the figure.

[0094] Fig.83 It is a graph showing the relationship between the Trap B ratio and the annealing temperature.

[0095] Fig.84 This is a diagram showing the relationship between the PL intensity of the trap A and the trap B and the annealing time. DETAILED DESCRIPTION

[0096] In the following embodiments, IGBT and freewheeling diode (FWD) are shown as representative examples of power semiconductor elements, and "diode" refers to FWD. However, the technology involved in the present invention can also achieve the same effect for power semiconductor elements such as RC (Reverse Conducting)-IGBT, RB (Reverse Blocking)-IGBT, MOSFET (Metal-Oxide-Semiductor Field Effect Transistor), etc.

[0097] In addition, Si is used as the semiconductor material in each embodiment, but not only Si, but also semiconductor devices using wide bandgap materials such as SiC and GaN can obtain the same effect. In addition, in each embodiment, as the Si material, a Si wafer (FZ wafer) manufactured by the FZ (Floating Zone) method is representatively shown, but a Si material having a higher residual oxygen concentration than the FZ wafer and an oxygen content of 10 17 cm -3 In addition, in each embodiment, although the semiconductor device with a withstand voltage level of 1200V and 4.5kV is exemplified, the same effect can be obtained regardless of the withstand voltage level.

[0098] <Implementation Method 1>

[0099] In the first embodiment, an RFC (Relaxed Field of Cathode) diode having a structure in which a cathode layer is partially replaced with a P-type region is described as a semiconductor element included in a power semiconductor device.

[0100] Figure 1 FIG. 1 is a top view of the semiconductor device according to Embodiment 1. Figure 1As shown in FIG. 1 , a plurality of active cell regions R1 are provided in the central portion of the semiconductor device, a surface gate wiring portion R11 is provided between two adjacent active cell regions R1, and a gate pad portion R12 is provided in a portion of the central portion. In addition, an intermediate region R2 is provided in a manner surrounding the active cell region R1, the gate pad portion R12, and the surface gate wiring portion R11, and an edge termination region R3 is provided in a manner surrounding the intermediate region R2. In the diode, the gate pad portion R12 and the surface gate wiring portion R11 may not exist.

[0101] The active cell region R1 is an element formation region that guarantees the basic performance of the power semiconductor chip. The middle region R2 and the edge termination region R3 are regions for maintaining withstand voltage. Among them, the middle region R2 is a region that joins the active cell region R1 and the edge termination region R3, which guarantees the breakdown tolerance during dynamic operation of the semiconductor device and supports the original performance of the semiconductor element formed in the active cell region R1. In addition, the edge termination region R3 is responsible for maintaining the withstand voltage of the semiconductor device in a static state, ensuring the stability and reliability of the withstand voltage characteristics, and suppressing poor breakdown tolerance during dynamic operation of the semiconductor device, and supports the original performance of the semiconductor element formed in the active cell region R1.

[0102] Figure 2 is a cross-sectional view of the semiconductor element according to the first embodiment, namely, the RFC diode, and Figure 1 The cross section of the A1-A2 line is equivalent. In addition, Figure 3 is a cross-sectional view showing an example of the structure of the peripheral portion of a semiconductor device, and Figure 1 The cross section taken along the line A3-A4 of is equivalent to that of the semiconductor device, which has the RFC diode involved in Embodiment 1. Here, the upper surface of the semiconductor substrate in the cross-sectional view is defined as the "first main surface", and the lower surface is defined as the "second main surface". Sometimes, the first main surface is expressed as the "upper surface", and the second main surface is expressed as the "lower surface" or "back surface".

[0103] First, refer to Figure 2 The structure of the RFC diode formed in the active cell region R1 is described below. An N-type (first conductivity type) N - Drift layer 14. N - The drift layer 14 has a peak impurity concentration ratio N - The drift layer 14 is a high N-type N buffer layer 15. In this embodiment, the N buffer layer 15 has a two-layer structure consisting of a lower first buffer layer 15-1 and an upper second buffer layer 15-2. That is, the second buffer layer 15-2 is disposed between the first buffer layer 15-1 and the N -The drift layer 14 is provided between the two layers. Although not shown in the figure, Figure 3 The N buffer layer 15 also includes a first buffer layer 15-1 and a second buffer layer 15-2. The details of the N buffer layer 15 will be described later.

[0104] Under the N buffer layer 15 of the semiconductor substrate, an N-type N + The cathode layer 17 and the P-type (second conductivity type) P cathode layer 18 are formed adjacent to each other. + The cathode layer 17 and the P cathode layer 18 are formed on the surface layer portion of the back side (second main surface side) of the semiconductor substrate. On the back side of the semiconductor device, the cathode electrode 19 is connected to the N + The cathode layer 17 and the P cathode layer 18 are formed in contact with each other.

[0105] N in semiconductor substrate - A P-type P anode layer 10 is formed on the drift layer 14. In the RFC diode, the P anode layer 10 and the N - The junction of the drift layer 14 is the main junction. The P anode layer 10 is formed on the surface layer portion of the upper surface (first main surface) side of the semiconductor substrate, and the anode electrode 5 is formed on the upper surface of the semiconductor substrate so as to be in contact with the P anode layer 10 .

[0106] like Figure 2 As shown, P anode layer 10, N - The drift layer 14, the N buffer layer 15, and the N + The cathode layer 17 forms a PiN diode region R21, and the P anode layer 10 and N - The drift layer 14, the N buffer layer 15, and the P cathode layer 18 constitute the PNP transistor region R22. That is, in terms of the RFC diode, if expressed by an equivalent circuit, it becomes a structure in which a PiN diode and a PNP transistor are connected in parallel. In addition, when the RFC diode is turned on, the carrier concentration changes due to conductivity modulation, so that the N - The drift layer 14 serves as a variable resistance region.

[0107] Compared with PiN diodes, RFC diodes show characteristic effects in diode performance, such as the electric field relaxation phenomenon that relaxes the electric field strength on the cathode side. In particular, in the second half of the recovery action, the hole injection from the P cathode layer 18 is promoted, thereby relaxing the electric field strength on the cathode side, suppressing the step (snap-off) phenomenon (voltage jump phenomenon) at the end of the recovery action and the subsequent oscillation phenomenon, thereby improving the breakdown tolerance during the recovery action. For example, these effects are described in Japanese Patent No. 5256357, Japanese Patent No. 6301776, etc. From the viewpoint of ensuring the above effects, N +The cathode layer 17 and the P cathode layer 18 are arranged to satisfy the relationship shown in Japanese Patent No. 5256357 or Japanese Patent No. 6301776 (US8686469).

[0108] Next, refer to Figure 3 , the structures of the middle region R2 and the edge termination region R3 of the RFC diode are described.

[0109] N - The drift layer 14 is formed across the active cell region R1, the middle region R2, and the edge termination region R3. - A P-type guard ring 22 is formed on the surface of the drift layer 14 and is deeper than the P-type anode layer 10. The guard ring 22 extends toward the active cell region R1 and is connected to the P-type anode layer 10. - A P-type field limiting ring 23 is selectively formed on the surface portion of the drift layer 14 .

[0110] Moreover, outside the field limiting ring 23, at N - The surface layer of the drift layer 14 selectively forms N + The channel stop layer 24 is used to make the guard ring 22 and the field limiting ring 23 and the N - The purpose of the depletion layer extending from the junction of the drift layer 14 is to stop the extension. The more the number of field limiting rings 23 increases, the higher the withstand voltage level of the RFC diode.

[0111] An insulating film 25 is formed on the upper surface of the semiconductor substrate in the middle region R2 and the edge termination region R3, and an interlayer insulating film 26 is formed on the insulating film 25. On the interlayer insulating film 26, an FLR electrode 27 connected to the field limiting ring 23 through a contact hole and a channel stopper electrode 28 connected to the channel stopper layer 24 through a contact hole are formed. In addition, the FLR electrode 27 and the channel stopper electrode 28 can be formed simultaneously with the anode electrode 5 of the active cell region R1.

[0112] Furthermore, a passivation film 29 which is a protective film covering the FLR electrode 27 and the channel stopping electrode 28 is formed across the middle region R2 and the edge termination region R3 , and a passivation film 30 is formed on the passivation film 29 .

[0113] like Figure 3 As shown, there is a layer N stacked across the active cell region R1, the middle region R2 and the edge termination region R3. - Drift layer 14, N buffer layer 15, N + The structure formed by the cathode layer 17 and the P cathode layer 18 is a vertical structure 35 of the RFC diode. The region where the vertical structure 35 is formed is referred to as a "vertical structure region".

[0114] The vertical structure 35 is a region that guarantees the total loss performance (the sum of the loss in the on state, the loss in the conducting state, and the loss in the off state), the withstand voltage maintenance in the static state, the stability of the withstand voltage characteristics, the leakage characteristics when the voltage is maintained at high temperature (disconnection loss), the reliability guarantee, the controllability during dynamic operation, the destruction tolerance, etc., and supports the basic performance of the semiconductor device.

[0115] Here, the concept of the vertical structural region in the present invention is explained. In the manufacture of a semiconductor device having a vertical structure 35 such as a vertical IGBT or a diode, on the back side (N - The process of forming the vertical structure 35 at the bottom of the drift layer 14 (described later) Fig.69 and Fig.70 ,or Fig.78 and Fig.79 The process shown in FIG. 1 is performed after the formation process of the aluminum wiring such as the anode electrode 5 and the formation process of the passivation films 29 and 30. Therefore, the diffusion layer (N buffer layer 15, N + For annealing of the cathode layer 17 and the P cathode layer 18), an annealing technique at a low temperature less than or equal to the melting point of aluminum (660°C) is used, or an annealing technique (laser annealing) is used using a laser with a wavelength having a temperature gradient in the depth direction of the device and the temperature on the upper surface side of the semiconductor substrate does not exceed the melting point of aluminum.

[0116] As for the N buffer layer 15, since the N layer distribution reproduces the distribution in the depth direction when the impurity ions are injected, and is formed using the above-mentioned annealing technology, there is a process feature when the N layer is formed that it is not easy to cause diffusion in the depth direction and the lateral direction. In the formation of the N-type diffusion layer, as a technology for realizing an N-type diffusion layer with a deep and gentle concentration gradient, there is a long-term annealing technology at a high temperature (≥1100°C). However, this technology cannot be used in the process of using low-melting-point metals such as aluminum used for electrodes, and can be used in the early stages of the manufacturing process (for example, Fig.58 or Fig.71 However, in this case, the thickness of the wafer needs to be adjusted to the desired thickness (40 μm to 700 μm) before or after high-temperature annealing. In the subsequent processes, it is necessary to modify each process device in order to process wafers of this thickness, which incurs huge costs and is therefore unrealistic. In addition, high-temperature and long-term annealing is a process technology that does not match the larger diameter of Si wafers.

[0117] In addition, the IGBT and diode having the N buffer layer 15 have the following three performance problems. The first problem is that the voltage holding capability (hereinafter sometimes referred to as the withstand voltage characteristic), which is an important performance for power semiconductors, becomes uncontrollable due to the increase in the leakage current during the withstand voltage holding in the high temperature state, which leads to an increase in the disconnection loss, or the thermal runaway caused by the heat generated by the device itself at high temperature, resulting in a state in which the operation at high temperature cannot be guaranteed.

[0118] The second problem is that during dynamic operations such as the turn-off operation of IGBTs and diodes, N - The carrier plasma layer near the junction of the drift layer 14 and the N buffer layer 15 is depleted, and the N - The electric field strength at the junction of the drift layer 14 and the N buffer layer 15 increases, resulting in a voltage jump phenomenon, i.e., a step phenomenon, at the end of the cut-off operation on the cut-off waveform. This causes an oscillation phenomenon caused by the step phenomenon, or the voltage becomes a high voltage greater than or equal to the withstand voltage that can be maintained due to the step phenomenon, causing device damage. The carrier plasma layer refers to a neutral layer with a high carrier concentration where the electron and hole concentrations are roughly the same, N≈P, and the carrier density is higher than 10 16 cm -3 , carrier concentration ratio N - The drift layer 14 is a layer whose doping carrier concentration is 2 to 3 orders of magnitude higher.

[0119] As a result, the controllability of the cutoff operation of the existing IGBT and diode deteriorates and the circuit breaking capacity at the time of cutoff is reduced. In an inverter system including a power module equipped with an IGBT or diode that generates a step phenomenon and subsequent oscillation phenomenon, the main cause of noise generation is included, which becomes a cause of malfunction.

[0120] The third problem is that, according to the characteristics of the formation of the N buffer layer 15, it is easy to cause a phenomenon that a part of the N buffer layer 15 is not formed due to damage or foreign matter on the surface of the N buffer layer 15 formed in the wafer process when the vertical structure 35 is formed. As a result, the IGBT and the diode become sensitive to the withstand voltage failure phenomenon, causing an increase in the defective rate of the withstand voltage characteristics of the IGBT and diode chips.

[0121] As described in the second question, when the IGBT and diode having the N buffer layer 15 are in dynamic operation, the N - The carrier plasma layer near the junction of the drift layer 14 and the N buffer layer 15 becomes easily depleted. -The carrier plasma layer near the junction of the drift layer 14 and the N buffer layer 15 is depleted, causing N - The electric field strength at the junction of the drift layer 14 and the N buffer layer 15 increases.

[0122] Regarding the waveform during the cut-off operation, the IGBT dj at the end of the cut-off operation C / dt value becomes larger, in the diode dj A / dt value becomes larger, because V=Ld i / dt relationship, a step phenomenon and subsequent oscillation phenomenon occur in the voltage waveform. Due to the step phenomenon, the device may be damaged. As a result, the controllability of the cut-off operation of the IGBT and the diode deteriorates and the circuit breaking capacity at the time of cut-off decreases. The step phenomenon and oscillation phenomenon also depend on the cut-off operation conditions. That is, these phenomena occur when the depletion layer becomes easy to reach N - The high power supply voltage (V CC ) condition, at low current density (J C , J A ) conditions, or as a high stray inductance (L S ) conditions, and becomes significant under various conditions such as low operating temperature.

[0123] In addition, the voltage holding capability, which is an important performance for power semiconductor devices, becomes uncontrollable due to the increase in disconnection loss caused by the increase in leakage current when the withstand voltage is maintained at high temperature, or thermal runaway caused by the heat generated by the device itself at high temperature, and cannot be operated at high temperature. As the heat generation component of power semiconductors, there are losses in the on state, losses during on-off actions (conduction and cutoff), namely on-off losses, and losses in the off state, namely off losses. The above situation means that the off loss, which is one of the three heat generation components of the power semiconductor itself, becomes larger, which becomes a problem in the thermal design of power modules equipped with power semiconductors.

[0124] As for the existing IGBT and diode, in order to solve the above problems, N - The thickness of the drift layer 14 is increased, and the N - The impurity concentration of the drift layer 14 is increased to reduce the fluctuation, etc. - Optimization of the parameters of the drift layer 14. However, if N - If the thickness of the drift layer 14 is increased, the ON voltage of the IGBT and the diode will increase, resulting in a disadvantageous increase in total loss. -The reduction of the fluctuation of the impurity concentration of the drift layer 14 will impose restrictions on the Si wafer manufacturing technology and the Si wafers used, resulting in an increase in the cost of Si wafers. Thus, the existing IGBTs and diodes face a technical dilemma in improving device performance.

[0125] As a solution to the second problem, the use of protons (H + ) to form an N buffer layer 15 composed of a plurality of layers. However, in these techniques, considering the trend of reducing the total loss of IGBT or diode, that is, N - The thinning of the drift layer 14 requires a high concentration of protons in order to maintain the basic characteristic of the power semiconductor, namely, the withstand voltage. However, the high concentration of protons has the following disadvantages, namely, due to the increase in crystal defects when protons are introduced or the increase in the defect density that becomes the recombination center of carriers caused by the crystal defects, the disconnection loss of the IGBT and the diode increases (that is, the leakage current increases under high temperature and high voltage) and the breakdown tolerance decreases. Power semiconductors are required to reduce total losses and have voltage holding capabilities, and to ensure breakdown tolerance, which are basic performance. In addition, if the disconnection loss increases, the heat generated by the IGBT or the diode itself increases, which becomes a problem for high-temperature operation or the thermal design of the power module itself that carries the power semiconductor. In other words, the above technology does not meet the latest requirements of using N - The drift layer 14 tends to be thinner, which is a technology required for power semiconductors. Furthermore, if the concentration of protons is increased, the processing capacity of the ion implantation device when the protons are introduced into Si is reduced, which is disadvantageous in terms of device manufacturing technology.

[0126] Therefore, in a wafer process that uses wafers produced by the FZ method or the MCZ method and can also support the enlargement of the diameter of Si wafers, an N buffer layer structure that solves the above-mentioned problem is required. In addition, it is also necessary to be insensitive to the poor withstand voltage phenomenon of the IGBT or diode caused by the fact that part of the N buffer layer 15 is not formed due to adverse effects in the wafer process.

[0127] In view of this, the purpose of the technology involved in the present invention is to achieve the following for bipolar power semiconductors such as IGBT and FWD, which are key components of power modules (rated withstand voltage: ≥600V):

[0128] (a) Improve the voltage breaking capacity (static withstand voltage holding capacity) in the disconnected state, and reduce the leakage current when the withstand voltage (voltage) is maintained at high temperature, so as to realize a vertical structure with low disconnection loss and high temperature operation;

[0129] (b) A longitudinal structure for suppressing the step phenomenon at the end of the cut-off action and the oscillation phenomenon caused by the step phenomenon;

[0130] (c) A vertical structure that improves the interruption capacity (dynamic breakdown tolerance) during cutoff operation and expands the safe operating temperature range;

[0131] (d) A vertical structure that can be combined with a wafer process technology that also supports the increase in the diameter of semiconductor wafers (≥200 mm).

[0132] use Figures 4 to 6 , the concept of the longitudinal structure proposed in the present invention is explained. Figures 4 to 6 The meanings of the symbols in are as follows.

[0133] Q pl : Charge in the plasma layer

[0134] n pl : The electron / hole density in the plasma layer

[0135] V: Electric potential

[0136] q: basic charge (1.60218×10 -19 C)

[0137] ε 0 :Vacuum dielectric constant (8.85418×10 -14 F / cm)

[0138] ε r : Relative dielectric constant (11.9 in the case of Si)

[0139] N + D :Ionized donor concentration (cm -3 )

[0140] n, p: free electron / hole concentration (cm -3 )

[0141] J n , J p :Electron / hole current density (A / cm -3 )

[0142] ν sat(n) , ν sat(p) :Electron / hole saturation drift velocity (cm / s)

[0143] The above technical issues caused by the problems of the vertical structure of the existing IGBT and diode are considered to be solved by realizing the following vertical structure characterized by the N buffer layer 15. The concepts shown below are common to IGBT and diode. The concepts related to the N buffer layer 15 constituting the vertical structure proposed by the present invention are as follows i, ii, iii.

[0144] (i) Regarding the depletion phenomenon of the carrier plasma layer near the junction of the n-drift layer 14 and the N-buffer layer 15 during the turn-off operation, as shown in FIG. Figure 4 As shown by the arrow circle 1, the carrier plasma layer remains. That is, by generating the conductivity modulation phenomenon of the device ON state also inside the N buffer layer 15, the N buffer layer 15 is reduced in concentration so that the carrier plasma layer exists. As for this concentration, since the carrier plasma layer has a concentration greater than or equal to 10 16 cm -3 Therefore, the concentration of the layer below 10 15 cm -3 The charge of the carrier plasma layer at this time is given by Figure 4 Q shown pl The relationship expression of .

[0145] (ii) In the static state, the electric field intensity stops inside the N buffer layer 15, and the concentration gradient near the junction of the n drift layer 14 and the N buffer layer 15 is made gentle, so that the depletion layer extends smoothly inside the N buffer layer 15 during dynamic operation. Figure 5 As shown by the arrow circle 2, the electric field intensity distribution gradient is given by Figure 6 The dE / dx relationship shown is expressed as follows.

[0146] (iii) By providing a low-concentration, concentration-gradient, and thick N layer, the basic performance of power semiconductors, namely, the withstand voltage characteristic, is guaranteed. In other words, the current amplification factor (α) of the PNP transistor built into the IGBT and RFC diode when the withstand voltage is maintained is reduced. pnp ) and realize low disconnection loss due to low leakage current when disconnecting.

[0147] That is, the N buffer layer 15 plays the role of controlling the carrier plasma state inside the device when the device is operating, while ensuring the withstand voltage characteristics such as stabilization of the withstand voltage characteristics and reduction of the off-state loss.

[0148] As a result, the step phenomenon at the end of the turn-off operation and the oscillation phenomenon caused by the step phenomenon can be suppressed while ensuring the stabilization of the withstand voltage characteristics and low turn-off loss of the IGBT and the diode, so that a power semiconductor with good controllability in the on-off operation can be realized, and the breakdown tolerance in the dynamic state is improved. In addition, the following effect is shown, that is, the phenomenon of poor withstand voltage of the IGBT and the diode caused by the failure to form a part of the N buffer layer 15 due to adverse effects in the wafer process becomes insensitive, and the increase in the defective rate of the IGBT and the diode chip is suppressed.

[0149] Next, the details of the N buffer layer 15 of the semiconductor device according to Embodiment 1 are described. As described above, the N buffer layer 15 of the semiconductor device according to Embodiment 1 is composed of the first buffer layer 15 - 1 as a lower layer and the second buffer layer 15 - 2 as an upper layer.

[0150] The first buffer layer 15-1 has a peak impurity concentration (C nb1，p ) is greater than or equal to 1.0×10 16 cm -3 and less than or equal to 5.0×10 16 cm -3 , the depth from the back of the semiconductor substrate (X j，nb1 ) is greater than or equal to 1.2 μm and less than or equal to 5.0 μm.

[0151] The second buffer layer 15-2 has a maximum peak impurity concentration (C nb2，p ) max ) is greater than the impurity concentration of the semiconductor substrate (C n- :greater than or equal to 1.0×10 12 cm -3 and less than or equal to 5.0×10 14 cm -3 range) is high and is less than or equal to 1.0×10 15 cm -3 , the depth from the back of the semiconductor substrate (X j，nb2 ) is greater than or equal to 4.0 μm and less than or equal to 50 μm.

[0152] According to the above relationship, if we take into account Figures 4 to 6 As for the effect of the target N buffer structure shown, the effects of the first buffer layer 15 - 1 and the second buffer layer 15 - 2 constituting the N buffer layer 15 are as follows.

[0153] The first buffer layer 15-1 has the function of stopping the depletion layer extending from the main junction in the static state. Figure 5The area indicated by the arrow circle 2) shows the effect of stable withstand voltage characteristics and low disconnection loss obtained by low leakage current when disconnected.

[0154] When the second buffer layer 15-2 is in the on state (in which the rated main current flows), the impurity concentration is increased by the carrier plasma layer generated by the conductivity modulation phenomenon compared with the doping profile when the second buffer layer 15-2 is formed in the wafer process ( Figure 4 Therefore, the second buffer layer 15-2 has the function of expanding the base width of the PNP transistor, showing a decrease in the current amplification factor (α pnp ), the effect of low disconnection loss is obtained by low leakage current when disconnected. This carrier plasma layer acts as a residual carrier plasma layer in a dynamic state ( Figure 6 In addition, the second buffer layer 15-2 makes the extension speed of the depletion layer extending from the main junction in the static and dynamic states faster than N - The movement time in the drift layer 14 is slow, and the residual carrier plasma layer from the on state has the function of controlling the electric field intensity distribution ( Figure 6 The area indicated by the arrow circle 2) suppresses the step phenomenon at the end of the cut-off action and the oscillation phenomenon caused by the step phenomenon, showing the effect of improving the controllability of the on-off action and improving the destruction tolerance in the dynamic state.

[0155] In the following description, when simply referring to the "N buffer layer 15", it basically refers to the N buffer layer 15 composed of the above-mentioned first buffer layer 15-1 and the second buffer layer 15-2. However, when comparing and describing the semiconductor device according to the present invention and the existing semiconductor device, the N buffer layer 15 composed of the first buffer layer 15-1 and the second buffer layer 15-2 is sometimes referred to as the "new structure N buffer layer 15", and the existing single-layer structure (composed of only a layer equivalent to the first buffer layer 15-1) N buffer layer 15 is referred to as the "existing structure N buffer layer 15". In addition, the RFC diode of the first embodiment having the new structure N buffer layer 15 is sometimes referred to as the "new structure RFC diode", and the existing RFC diode having the existing structure N buffer layer 15 is sometimes referred to as the "existing structure RFC diode".

[0156] In addition, in relation to the “trap B ratio” described later, a method for forming the new-structure N buffer layer 15 will be described in the fourth embodiment.

[0157] In the RFC diode according to the first embodiment, the parameters of the diffusion layers other than the N buffer layer 15 are set as follows. - The drift layer 14 has an impurity concentration (C n-) is greater than or equal to 1.0×10 12 cm -3 and less than or equal to 5.0×10 14 cm -3 The final device thickness (t device ) is greater than or equal to 40 μm and less than or equal to 700 μm. The P anode layer 10 is set to have a surface impurity concentration greater than or equal to 1.0×10 16 cm -3 And the peak impurity concentration is greater than or equal to 2.0×10 16 cm -3 and less than or equal to 1.0×10 18 cm -3 , depth greater than or equal to 2.0 μm and less than or equal to 10.0 μm. N + The cathode layer 17 is set to have a surface impurity concentration greater than or equal to 1.0×10 18 cm -3 and less than or equal to 1.0×10 21 cm -3 The depth of the P cathode layer 18 is greater than or equal to 0.3 μm and less than or equal to 0.8 μm. The surface impurity concentration of the P cathode layer 18 is set to be greater than or equal to 1.0×10 16 cm -3 and less than or equal to 1.0×10 20 cm -3 , the depth is greater than or equal to 0.3 μm and less than or equal to 0.8 μm.

[0158] Figure 7 The PL (Photoluminescence) method is used to analyze the spectrum of the first buffer layer 15-1 and the second buffer layer 15-2 that constitute the new structure N buffer layer 15. The PL method is an analytical method that irradiates light to a semiconductor and observes the light emitted when electron-hole pairs recombine via defect energy levels. The PL measurement uses a He-Ne laser (wavelength: 633nm), sets the temperature to 30K, sets the laser intensity irradiated to the sample surface to 4.5mW, sets the laser diameter to 1.3μm, and sets the laser intensity on the sample surface to 0.339MW / cm 2 And carried out.

[0159] Figure 7 The vertical axis is the PL intensity normalized by the intensity of the band edge of each layer. Figure 7 The PL intensity on the vertical axis represents the defect density, and it is shown that the stronger the PL intensity is, the greater the defect density of the defect that is the source of the defect is. Figure 7, nothing was detected in the first buffer layer 15-1, but a PL spectrum with two characteristic peaks originating from lattice defects was obtained in the second buffer layer 15-2. These two characteristic peaks are energy levels determined by trap A (photon energy: 1.0182 eV) and trap B (photon energy: 1.0398 eV) existing in the second buffer layer 15-2.

[0160] The detected traps A and B are consistent with the photon energies of the lattice defect clusters (W-centre) generated when protons are introduced into Si and the lattice defect pairs (X-centre) generated when protons are diffused and then aggregated by annealing, respectively, according to the following paper: R. Jones, T. A. G. Berlein, N. Pinho, B. J. Coomer, J. P. Gross, P. R. Briddom and S. Oberg, "Self-interstitial Clusters in Silicon," Nucl. Instrum. Methods Phys. Res. B, Beam Interact. Mater. At., vol. 186, pp. 10.18, Jan. 2002, doi: 10.1016 / S0168-583X(01)00872-2.

[0161] Thus, the N buffer layer 15 is composed of the first buffer layer 15-1 having no lattice defects and the second buffer layer 15-2 having lattice defects. That is, the N buffer layer 15 is composed of a plurality of N layers having different carrier lifetimes, and the carrier lifetime of the first buffer layer 15-1 is longer than that of the second buffer layer 15-2.

[0162] If the carrier lifetime of the first buffer layer 15 - 1 is represented by τ 15a , the carrier lifetime of the second buffer layer 15-2 is represented by τ 15b , N - The carrier lifetime of the drift layer 14 is expressed as τ 14 , N + The carrier lifetime of the cathode layer 17 is expressed as τ 17 , the carrier lifetime of the P cathode layer 18 is expressed as τ 18 , then in the RFC diode of the first embodiment, τ 15b <τ 17 ≈τ 18 ≈τ 15a ≈τ 14 relationship (details are shown in Implementation 4).

[0163] By satisfying the above relationship of carrier lifetime, the following effect is achieved, that is, the carrier injection efficiency from the lower surface side in the on state of the diode is increased ( Figure 2 The electron injection efficiency γ is shown n，active ) is stabilized, the leakage current generated when the main junction is depleted by applying a reverse bias is reduced, and the carrier recombination caused by the second buffer layer 15-2 is promoted. As a result, a stable turn-on operation of the diode can be expected ( Fig.31 )、low disconnection loss ( Fig.32 ), high temperature action based on thermal stability action ( Fig.32 , Fig.38 ), dynamic durability improvement (e.g. Fig.34 , Fig.37 ) and other effects.

[0164] Next, in the RFC diode having the new structure N buffer layer 15, the effect of the new structure N buffer layer 15 is shown by clarifying the influence of the two traps existing in the second buffer layer 15-2 on the device performance, thereby confirming the effect of the technology involved in the present invention on the device performance. When discussing the relationship between the two traps existing in the second buffer layer 15-2 and the device performance, the ratio of the trap B defined by the following formula (1) is set as an indicator representing the relationship between the two traps and the device performance.

[0165] The ratio of trap B (%) = {S PLB / (S PLA +S PLB )}×100…Formula (1)

[0166] In formula (1), S PLB is the PL intensity of trap B, S PLA is the PL intensity of trap A.

[0167] exist Figure 8 FIG. 2 shows the change in the ratio of the trap B with respect to the depth direction of the second buffer layer 15-2. The value on the horizontal axis is calculated by the thickness of the device (t device ) is the value normalized by the device thickness. Figure 8 X j，nb1 and X j，nb2 The junction of the first buffer layer 15-1 and the second buffer layer 15-2, and the junction of the second buffer layer 15-2 and N - The junction of the drift layer 14. - The drift layer 14 detects traps A and B, so at X j，nb2 After that, the ratio of the trap B is 0. As described later, in order to obtain the effect of the new structure N buffer layer 15, it is necessary to control the ratio of the trap B within the range of 15% to 55%. Figure 8It can be seen that in the second buffer layer 15-2, the ratio of the traps B is constant within the above-mentioned allowable range. Figure 27 to Figure 30 The ratio of trap B in Figure 8 The behavior becomes a value near the center of the second buffer layer 15-2.

[0168] The middle region R2 and the edge termination region R3 of the RFC diode produced by trial production are structured as follows: Figure 3 The structure shown. The structure of the N buffer layer 15 in the middle region R2 and the edge termination region R3 is the same as that in the active cell region R1. That is, the N buffer layer 15 of the prototyped new structure RFC diode spans the active cell region R1, the middle region R2 and the edge termination region R3 and includes the first buffer layer 15-1 and the second buffer layer 15-2. In addition, the N buffer layer 15 of the prototyped existing structure RFC diode spans the active cell region R1, the middle region R2 and the edge termination region R3 and is a single-layer structure (only the layer equivalent to the first buffer layer 15-1).

[0169] Fig. 9 The following are simulation results related to the recovery behavior of the existing RFC diode and the new RFC diode. Fig.10 It will be shown in Fig. 9 The enlarged image of the part surrounded by the dotted circle in Fig. 9 In the conventional RFC diode and the new RFC diode shown in FIG. device ) and N - The impurity concentration (C n- ) are the same. In addition, in each graph, "new diode-(b)" refers to a new structure RFC diode, and "existing diode-(b)" refers to an existing structure RFC diode.

[0170] Fig.11 and Fig.12 for Fig.10 The simulation results of the carrier concentration distribution and the electric field intensity distribution between the first main surface and the second main surface of the PNP transistor region R22 of the RFC diode at the analysis point are shown. Fig.11 As a result of the existing construction of the RFC diode, Fig.12 is the result of the newly constructed RFC diode. Fig.11 and Fig.12 It can be seen that in the new structure RFC diode, unlike the existing structure RFC diode, there is a carrier plasma layer remaining on the cathode side during the recovery action. In the new structure RFC diode, the electric field strength on the cathode side in the second half of the recovery action is relaxed by the presence of this residual carrier plasma layer. As a result, Fig. 9As shown, in the new structure RFC diode, dj / dt at the end of the recovery operation becomes smaller than that of the conventional structure RFC diode, and the effect of suppressing the step phenomenon is obtained.

[0171] Fig.13 This is a diagram showing the simulation results of the recovery waveforms of the existing structure RFC diode and the new structure RFC diode in the fast recovery operation of the 4.5kV class. Fig.14 Yes means Fig.13 Graph showing the device internal states (current density distribution) of the conventional structure RFC diode and the new structure RFC diode at the device internal analysis points T1 to T7.

[0172] Figures 15 to 26 Yes means Fig.13 The diagram shows the internal states (electron and hole concentration distribution, electric field intensity distribution) of the PiN diode region R21 and the PNP transistor region R22 of the RFC diode at the internal analysis points T1 to T7 of the device. Fig.15 is the electron concentration distribution of the PiN diode region R21 of the existing RFC diode structure, Fig.16 This is the electron concentration distribution in the PiN diode region R21 of the new RFC diode structure. Fig.17 is the hole concentration distribution of the PiN diode region R21 of the existing RFC diode structure, Fig.18 This is the hole concentration distribution of the PiN diode region R21 of the newly constructed RFC diode. Fig.19 The electric field intensity distribution of the PiN diode region R21 of the existing RFC diode structure is: Fig. 20 The electric field intensity distribution of the PiN diode region R21 of the new structure RFC diode. Fig.21 The electron concentration distribution of the PNP transistor region R22 of the existing RFC diode structure is shown in FIG. Fig. 22 This is the electron concentration distribution in the PNP transistor region R22 of the newly constructed RFC diode. Fig.23 is the hole concentration distribution of the PNP transistor region R22 of the existing RFC diode structure, Fig.24 This is the hole concentration distribution of the PNP transistor region R22 of the newly constructed RFC diode. Fig.25 The electric field intensity distribution of the PNP transistor region R22 of the existing RFC diode structure is shown in FIG. Fig.26 The electric field intensity distribution of the PNP transistor region R22 of the new structure RFC diode. The values ​​of the horizontal axis of the curve graph of each figure are calculated by the thickness of the device (t device ) is the value normalized by the device thickness.

[0173] according to Fig.13It can be seen that in the conventional RFC diode, a huge tail current is generated in the second half of the recovery operation. Figures 15 to 26 It can be considered that the conventional RFC diode generates a tail current in the second half of the recovery operation in the following steps, resulting in device damage.

[0174] First, in the first step, since the operation time limited by the PiN diode region R21 and the PNP transistor region R22 are different, the operation convergence time is exceeded by J RR point( Fig.13 From time T2 in the figure, the operation of the PNP transistor region R22 is subject to the speed-limited operation mode. Next, in the second step, in order to promote hole injection, the carrier concentration increases on the cathode side, so that the electric field on the cathode side is relaxed, and the P anode layer 10 and the N - The electric field strength of the main junction between the drift layers 14 increases, promoting impact ionization. Then, in the third step, the electrons generated by the impact ionization promoted by the main junction are directed to the N - The drift layer 14 is injected, causing the base current of the PNP transistor region R22 to increase, generating a huge tail current on the recovery waveform. Finally, in the fourth step, a huge tail current is generated, and the PNP transistor starts to operate, so it becomes impossible to control the recovery operation, resulting in device damage.

[0175] In the case of the new structure RFC diode having the N buffer layer 15 with lattice defects in the second buffer layer 15-2, the above-mentioned third step mode does not occur, and the recovery operation can be controlled. This is because in the new structure RFC diode, the lattice defects in the second buffer layer 15-2 promote carrier recombination, so that the carrier plasma layer existing on the cathode side disappears, and the P anode layer 10 and the N - The increase in the electric field intensity at the main junction between the drift layers 14 is suppressed, and the depletion layer extends toward the cathode side.

[0176] As a result, in the newly constructed RFC diode, Fig.14 As shown in the current density distribution, the action of the PNP transistor region R22 is suppressed to a minimum, and the generation period of the current filament phenomenon that crosses the PiN diode region R21 and the PNP transistor region R22 at the internal analysis point T2 of the device is shortened. Fig.13As shown, the tail current is suppressed and the recovery action is terminated. As a result, the new structure RFC diode does not generate a huge tail current during the recovery action in the fast mode, and the safe operating temperature range for ensuring the recovery action can be expanded. This effect is caused by the presence of lattice defects in the second buffer layer 15-2 of the new structure N buffer layer 15.

[0177] Fig. 27 J at 298K of a 1200V class RFC diode with a new structure and various trap B ratios R -V R Characteristics. R is the leakage current density (A / cm 2 ), V R is the reverse bias voltage (V). It can be seen that the ratio of trap B to the J of the diode R -V R characteristics, if the ratio of trap B is low, then at V R =200V or more, leakage current (J R ) increases, J R -V R Characteristics deteriorate. That is, if the ratio of traps B is low, the voltage holding capability, which is the basic performance of the power semiconductor, is deteriorated.

[0178] Fig.28 The following are the fast recovery waveforms of the 1200V class new structure RFC diodes with various trap B ratios produced at low temperatures. The new structure RFC diode controls the lattice defects in the second buffer layer 15-2 and sets the trap B ratio to 40%. Thus, even at a low temperature of 233K, the tail current in the second half of the recovery action is not increased, and the reverse recovery charge (Q RR ) increases, the recovery action is cut off.

[0179] Fig.29 This is a table summarizing the relationship between the device performance and the ratio of trap B of the 1200V class new structure RFC diode. Fig.29 It is understood that the diode having the new structure N buffer layer 15 can improve diode performance by controlling the lattice defects in the second buffer layer 15 - 2 having lattice defects constituting the N buffer layer 15 .

[0180] Fig.30 This is a graph showing the relationship between the safe operating temperature range and the ratio of trap B during the fast recovery operation of a 1200V class new structure RFC diode. Figures 13 to 26 , it can be inferred that the new structure RFC diode has expanded the safe operating temperature range that ensures fast recovery operation. Fig.30By controlling the trap B in the lattice defects in the second buffer layer 15-2 to 15% to 55%, as described later, the Q RR Reduce, such as Fig.28 As shown, there is no tail current increase region, and the recovery action can be cut off even at a low temperature of 213K, and the operating temperature range can be expanded to the low temperature side.

[0181] The following is a result of verifying the device performance of a new structure RFC diode in which the trap B in the lattice defects in the second buffer layer 15-2 is controlled to 15% to 55%. Here, the structure of the intermediate region R2 and the edge termination region R3 of the RFC diode produced in the trial is also Figure 3 The structure of the N buffer layer 15 in the middle region R2 and the edge termination region R3 is the same as that in the active cell region R1.

[0182] Fig.31 The output characteristics of the 1200V class new structure RFC diode produced by trial production are shown in FIG. The new structure RFC diode has a second buffer layer 15-2 with lattice defects in the N buffer layer 15, but satisfies the above-mentioned relationship of carrier lifetime, thereby γ n，active Stabilization, no snapback occurs even at low temperatures such as 213K, and normal switching operation can be guaranteed.

[0183] In addition, power modules require a large number of power semiconductor devices to operate in parallel. For the new structure RFC diode, the voltage near the rated current density (V F ) has a positive temperature dependence from 213K to 423K (V F This is an effective performance from the perspective of current sharing when a large number of new structure RFC diodes are operated in parallel.

[0184] Fig.32 The J of the newly manufactured 1200V class RFC diode R -V R The new structure RFC diode has a second buffer layer 15-2 with lattice defects in the N buffer layer 15, but by satisfying the aforementioned carrier lifetime relationship, it does not experience thermal runaway even at a high temperature of 478K, and has both low turn-off loss performance and high voltage holding capability.

[0185] Fig.33 The recovery waveforms of the existing RFC diode and the new RFC diode at 298K are shown. Fig.33In the conventional RFC diode and the new RFC diode shown in FIG. device ) and N - The impurity concentration (C n- ) Compared with the conventional RFC diode, the new RFC diode suppresses the step phenomenon at the end of the recovery operation and the subsequent oscillation phenomenon, and shows excellent soft recovery behavior.

[0186] Fig.34 The recovery waveforms of the fast mode of the conventional RFC diode and the new RFC diode at low temperature (253K) of the 1200V class. Compared with the conventional RFC diode, the new RFC diode suppresses the huge tail current even in the fast mode and can open the circuit even under severe recovery conditions.

[0187] exist Fig.35 and Fig.36 In Fig.34 The damage phenomenon caused by the huge tail current in the recovery operation is shown in Figure 2. RR ) and the power supply voltage (V CC ), the relationship between the operating temperature. Fig.35 This is a graph showing the relationship between the power supply voltage and the reverse recovery charge at 253K for the 1200V class conventional structure RFC diode and the new structure RFC diode that were trial-produced. Fig.36 This is a graph showing the relationship between the operating temperature and the reverse recovery charge amount at a power supply voltage of 1000 V for the conventional RFC diode and the new RFC diode.

[0188] according to Fig.35 and Fig.36 It can be seen that the new structure RFC diode is Q RR V CC And the operating temperature dependence is small. That is, it can be said that Q RR The operation of the PNP transistor region R22, which is the cause of the increase, is suppressed, and the durability of the RFC diode during dynamic operation is excellent. The reason for this behavior is that the lattice defects in the second buffer layer 15-2 of the new structure N buffer layer 15 play a role in promoting the recombination of carriers in the second half of the recovery operation.

[0189] Fig.37 The figure shows the operating temperature and V at low temperatures at which the circuit can be disconnected in the fast recovery operation of the conventional structure RFC diode and the new structure RFC diode of the 1200V class trial production. CC A diagram of the relationship between . Fig.37The inside of the data shown is the safe operating area (SOA). Fig.37 The new structure of the RFC diode has the following effects: on the low temperature side less than or equal to 253K, the safe operating area is moved toward the high V CC Side expansion.

[0190] Fig.38 This is a waveform showing the high current density of the 1200V class new structure RFC diode and the breaking capacity during the recovery operation at high temperature (473K). The new structure RFC diode satisfies the above-mentioned relationship of carrier lifetime, so even at a high temperature of 473K, it can transmit a high current density (3000A / cm 2 ) is cut off and has sufficient circuit breaking capacity.

[0191] Fig.39 The on-state voltage (V) of the 1200V class RFC diodes with existing structures and the RFC diodes with new structures that were produced F ) and recovery loss (E REC ) The new structure RFC diode has a smaller device thickness (t device ), and if Figure 33 to Figure 38 As shown, the durability during dynamic operation is improved and Fig.39 The reduction in total loss performance is shown.

[0192] Thus, the new structure N buffer layer 15 includes the second buffer layer 15-2 having lattice defects, but the trap B in the lattice defects in the second buffer layer 15-2 is controlled to 15% to 55%, and the aforementioned carrier lifetime relationship is satisfied, so thermal stability is achieved. Therefore, the new structure N buffer layer 15 can ensure the following characteristics in the RFC diode: normal turn-on operation; no thermal runaway even at high temperatures, and sufficient withstand voltage holding capability with low disconnection loss; high circuit breaking capability at high temperatures, high voltages or large currents; low total loss performance; operation at high temperatures such as 473K, etc. That is, the new structure N buffer layer 15 is a technology for achieving the above-mentioned purposes (a) to (c).

[0193] <Implementation Method 2>

[0194] In the second embodiment, the new structure N buffer layer 15 is applied to the PiN diode, and in this case as well, it is confirmed that the new structure N buffer layer 15 shows the same behavior as that of the first embodiment.

[0195] Fig.40 is a cross-sectional view of a semiconductor element, namely a PiN diode, according to Embodiment 2, and Figure 1The cross section of the A1-A2 line is equivalent. In addition, Fig.41 is a cross-sectional view showing an example of the structure of the peripheral portion of a semiconductor device, and Figure 1 The cross section taken along the line A3 - A4 of is equivalent to that of , and the semiconductor device includes the PiN diode according to the first embodiment. Fig.40 and Fig.41 The structure is shown in Embodiment 1. Figure 2 and Figure 3 The structure of the P cathode layer 18 is deleted, so that the cathode layer is only N + Cathode layer 17 .

[0196] like Fig.41 As shown, there is a cross-region of the active cell R1, the middle region R2 and the edge termination region R3. - The drift layer 14, the N buffer layer 15, and the N + The cathode layers 17 are stacked to form a vertical structure 35 of a PiN diode.

[0197] like Fig.40 As shown, the N buffer layer 15 of the PiN diode involved in the second embodiment is a new structure N buffer layer 15 including a first buffer layer 15-1 and a second buffer layer 15-2. Hereinafter, the PiN diode of the second embodiment having the new structure N buffer layer 15 is sometimes referred to as a "new structure PiN diode", and the existing PiN diode having the existing structure N buffer layer 15 is sometimes referred to as a "existing structure PiN diode".

[0198] If the carrier lifetime of the first buffer layer 15 - 1 is represented by τ 15a , the carrier lifetime of the second buffer layer 15-2 is represented by τ 15b , N - The carrier lifetime of the drift layer 14 is expressed as τ 14 , N + The carrier lifetime of the cathode layer 17 is expressed as τ 17 , then in the PiN diode of the second embodiment, τ 15b <τ 17 ≈τ 15a ≈τ 14 relationship (details are shown in Implementation 4).

[0199] Next, in the PiN diode involved in the second embodiment, the step phenomenon during the recovery operation and the subsequent oscillation phenomenon are suppressed, and the breakdown tolerance during the recovery operation is improved. Here, the verification results obtained by the 4.5kV class PiN diode are shown. Figure 42 to Figure 44The new structure PiN diode described in the above is similar to the first embodiment, in that the traps B in the lattice defects in the second buffer layer 15-2 are controlled to 15% to 55%. In addition, the middle region R2 and the edge termination region R3 of the PiN diode produced in the trial are Fig.41 However, the N buffer layer 15 in the middle region R2 and the edge termination region R3 has the same structure as that in the active cell region R1.

[0200] In the PiN diode according to the second embodiment, the parameters of the diffusion layers other than the N buffer layer 15 are set as follows. - The drift layer 14 has an impurity concentration (C n- ) is greater than or equal to 1.0×10 12 cm -3 and less than or equal to 5.0×10 14 cm -3 The final device thickness (t device ) is greater than or equal to 40 μm and less than or equal to 700 μm. The P anode layer 10 is set to have a surface impurity concentration greater than or equal to 1.0×10 16 cm -3 , the peak impurity concentration is greater than or equal to 2.0×10 16 cm -3 and less than or equal to 1.0×10 18 cm -3 , depth greater than or equal to 2.0 μm and less than or equal to 10.0 μm. N + The cathode layer 17 is set to have a surface impurity concentration greater than or equal to 1.0×10 18 cm -3 and less than or equal to 1.0×10 21 cm -3 , the depth is greater than or equal to 0.3 μm and less than or equal to 0.8 μm. In addition, the parameters of the N buffer layer 15 (the first buffer layer 15 - 1 and the second buffer layer 15 - 2 ) may be the same as those in the first embodiment.

[0201] Fig.42 This is a graph showing the waveforms of the 4.5kV class PiN diodes in the existing structure and the new structure at 298K during the rapid recovery operation. Compared with the RFC diode, the PiN diode has a smaller effect of suppressing the step phenomenon during the recovery operation because the residual carrier plasma layer is easily depleted on the cathode side in the second half of the recovery operation. Fig.42 In the process, the existing structure PiN diode produces a step phenomenon, which then leads to device damage.

[0202] In contrast, in the new structure PiN diode, due to N -Due to the influence of the residual carrier plasma layer near the junction of the drift layer 14 and the second buffer layer 15-2, the speed at which the depletion layer extends from the main junction during the recovery operation is reduced in the second buffer layer 15-2, and even if a step phenomenon occurs, the step voltage is suppressed to a small value. That is, in the new structure PiN diode, Figure 4 and Figure 6 As shown in the area indicated by the arrow circle 1, a carrier plasma layer exists in the second buffer layer 15-2 from the on state. Therefore, in the conventional structure PiN diode, at the point where the step phenomenon occurs, a residual carrier plasma layer exists in the second buffer layer 15-2 area, and the electric field intensity distribution is controlled, thereby showing an effect of delaying the point where the step phenomenon occurs and preventing device damage.

[0203] Fig.43 The power supply voltage (V) at 298K of the existing structure PiN diode and the new structure PiN diode of 4.5kV class is shown. CC ) and step voltage (V snap-off ). It can be seen that the new structure PiN diode does not break down even at a voltage that would cause damage to the conventional structure PiN diode, and the breakdown tolerance during the fast recovery operation is improved. Moreover, it can be seen that the new structure PiN diode has a step voltage V of 1.17 V compared to the conventional structure PiN diode. CC dependence is not sensitive to high V CC The high damage resistance on the side is most effective.

[0204] Fig.44 The power supply voltage (V) at 298K of the existing structure PiN diode and the new structure PiN diode of 4.5kV class is shown. CC ) and reverse recovery charge (Q RR ) in the new structure PiN diode, Q is higher than that of the existing structure PiN diode. RR V CC This has the effect of improving the breakdown resistance during the snapback operation of the PiN diode with the new structure.

[0205] As described above, in the PiN diode, by using the new structure N buffer layer 15 in which the traps B among the lattice defects in the second buffer layer 15 - 2 are controlled to 15% to 55%, the effect of improving the breakdown resistance can be obtained.

[0206] <Implementation Method 3>

[0207] In the third embodiment, the new-structure N buffer layer 15 is applied to the IGBT, and in this case as well, it is confirmed that the new-structure N buffer layer 15 shows the same behavior as that of the first embodiment.

[0208] Fig.45 is a cross-sectional view of a trench gate IGBT, a semiconductor element according to the third embodiment, and Figure 1 The cross section of the A1-A2 line is equivalent. In addition, Fig.46 is a cross-sectional view showing an example of the structure of the peripheral portion of a semiconductor device, and Figure 1 The cross section taken along line A3 - A4 of is equivalent to that of , and the semiconductor device includes the IGBT involved in the third embodiment.

[0209] First, refer to Fig.45 The structure of the IGBT formed in the active cell region R1 is described below. An N-type (first conductivity type) N - Drift layer 14. N - The drift layer 14 has a peak impurity concentration ratio N - The drift layer 14 has an N-type N buffer layer 15. The N buffer layer 15 is a new structure N buffer layer 15 composed of a lower first buffer layer 15-1 and an upper second buffer layer 15-2. Fig.46 The N buffer layer 15 also includes a first buffer layer 15 - 1 and a second buffer layer 15 - 2 .

[0210] A P-type (second conductivity type) P collector layer 16 is formed below the N buffer layer 15 of the semiconductor substrate. The P collector layer 16 is formed on the surface of the back side (second main surface side) of the semiconductor substrate, and a collector electrode 20 is formed on the back side of the semiconductor device to contact the P collector layer 16.

[0211] N in semiconductor substrate - On the drift layer 14, a peak impurity concentration ratio N - The drift layer 14 is higher than the N layer 11, and a P-type P base layer 9 is formed on the N layer 11. The P base layer 9 is formed on the surface of the upper surface side (first main surface side) of the semiconductor substrate. + The emitter layer 7 has a peak impurity concentration higher than that of the P base layer 9. + Layer 8. In the IGBT, the junction of the P base layer 9 and the N layer 11 is the main junction.

[0212] On the upper surface of the semiconductor substrate, an N layer is formed which vertically penetrates the P base layer 9 and the N layer 11 and reaches below them. - The drift layer 14 has a trench. A gate insulating film 12 is formed on the inner wall of the trench, and a gate electrode 13 is formed on the gate insulating film 12 to fill the trench. The gate electrode 13 is sandwiched between the gate insulating film 12 and the N -Drift layer 14, N layer 11, P base layer 9, and N + The emitter layer 7 is opposite to the gate electrode 13. + The emitter layer 7, the P base layer 9 and the N layer 11 constitute an insulated gate transistor structure (MOS transistor structure) of the IGBT.

[0213] An interlayer insulating film 6 is formed on the upper surface of the semiconductor substrate so as to cover the gate electrode 13, and an emitter electrode 4 is formed on the interlayer insulating film 6. The emitter electrode 4 is connected to the N + The emitter layer 7 and P + In addition, the gate electrode 13 (at the outer periphery of the active cell region R1) is formed. Fig.46 The gate electrode on the right side of the two gate electrodes 13 shown in the active cell region R1 does not function as an original gate electrode, but is set as a dummy electrode with the same potential as the emitter electrode 4. The purpose and effect of the dummy electrode are described in Japanese Patent No. 4205128, Japanese Patent No. 4785334 and Japanese Patent No. 5634318, which are the suppression of the saturation current density of the IGBT, the suppression of oscillation in the no-load short-circuit state caused by the control of the capacitance characteristics, the improvement of the short-circuit tolerance achieved thereby, and the low turn-on voltage achieved by the increase of the carrier concentration on the emitter side.

[0214] Next, refer to Fig.46 , the structures of the middle region R2 and the edge termination region R3 of the IGBT are described.

[0215] N - The drift layer 14 is formed across the active cell region R1, the middle region R2, and the edge termination region R3. - A P-type guard ring 22 is formed on the surface of the drift layer 14 and is deeper than the P base layer 9. The guard ring 22 extends toward the active cell region R1 and is connected to the P base layer 9, enclosing the dummy electrode, i.e., the gate electrode 13, inside (i.e., the guard ring 22 is formed deeper than the dummy electrode, i.e., the gate electrode 13). - A P-type field limiting ring 23 is selectively formed on the surface portion of the drift layer 14 .

[0216] Furthermore, the field limiting ring 23 of the edge termination region R3 is provided with a structure consisting of an N layer 11, a gate insulating film 12 and a gate electrode 13, which is the same as that of the active cell region R1. + The channel stop layer 24 is used to make the guard ring 22 and the field limiting ring 23 and the N -The purpose of the depletion layer extending from the junction of the drift layer 14 is to stop the extension of the depletion layer.

[0217] An insulating film 25 is formed on the upper surface of the semiconductor substrate in the middle region R2 and the edge termination region R3. A surface gate electrode 13a connected to the gate electrode 13 is formed on the insulating film 25 in the middle region R2, and an interlayer insulating film 6 is formed on the insulating film 25 and the surface gate electrode 13a.

[0218] On the interlayer insulating film 6, an FLR electrode 27 connected to the field limiting ring 23 through a contact hole, a channel stopper electrode 28 connected to the channel stopper layer 24 through a contact hole, and a surface gate electrode 31 connected to the surface gate electrode 13a through a contact hole are formed. In addition, the FLR electrode 27, the channel stopper electrode 28 and the surface gate electrode 31 can be formed simultaneously with the emitter electrode 4 of the active cell region R1.

[0219] Furthermore, a passivation film 29 which is a protective film and covers the FLR electrode 27 , the channel stopper electrode 28 , and the surface gate electrode 31 is formed across the middle region R2 and the edge termination region R3 , and a passivation film 30 is formed on the passivation film 29 .

[0220] like Fig.46 As shown, there is a cross-region N across the active cell region R1, the middle region R2 and the edge termination region R3 - The drift layer 14 , the N buffer layer 15 , and the P collector layer 16 are stacked, and this structure is a vertical structure 35 of the IGBT.

[0221] In addition, Fig.46 FIG. 4 shows a structure in which a P collector layer 16 is also formed in the middle region R2 and the edge termination region R3. Fig.47 As shown, the P collector layer 16 may not be formed in the middle region R2 and the edge termination region R3. That is, the longitudinal structure 35 of the middle region R2 and the edge termination region R3 may also be composed of only N - The drift layer 14 and the N buffer layer 15 are formed. Fig.47 The IGBT and Fig.46 Compared with IGBTs, it can suppress adverse effects on on-state voltage, switching loss, SOA in short-circuit state, etc., and can significantly improve SOA during cut-off operation. Details of this technology are described in Japanese Patent No. 6165271.

[0222] As described above, the N buffer layer 15 of the IGBT according to the third embodiment is a new structure N buffer layer 15 including the first buffer layer 15-1 and the second buffer layer 15-2. Hereinafter, the IGBT according to the third embodiment having the new structure N buffer layer 15 is sometimes referred to as a "new structure IGBT", and the existing IGBT having the existing structure N buffer layer 15 is sometimes referred to as a "existing structure IGBT".

[0223] If the carrier lifetime of the first buffer layer 15 - 1 is represented by τ 15a , the carrier lifetime of the second buffer layer 15-2 is represented by τ 15b , N - The carrier lifetime of the drift layer 14 is expressed as τ 14 , the carrier lifetime of the P collector layer 16 is expressed as τ 16 , then in the IGBT of the third embodiment, τ 15b <τ 16 ≈τ 15a ≈τ 14 relationship (details are shown in Implementation 4).

[0224] By satisfying the above relationship between carrier lifetimes, the following effects are achieved: the carrier injection efficiency from the bottom surface side in the on-state of the IGBT is increased ( Fig.45 The hole injection efficiency (γ p，active ) stabilizes the main junction; reduces the leakage current generated when a reverse bias is applied to the main junction and depletes it; and promotes the carrier recombination caused by the second buffer layer 15-2. As a result, it is expected that the IGBT can achieve stable turn-on operation and low turn-off loss ( Fig.56 ), high temperature action based on thermal stability action ( Fig.56 )、Dynamic durability improvement ( Fig.53 ) and other effects.

[0225] In the IGBT according to the third embodiment, the parameters of the diffusion layer and the trench other than the N buffer layer 15 are set as follows. - The drift layer 14 has an impurity concentration (C n- ) is greater than or equal to 1.0×10 12 cm -3 and less than or equal to 5.0×10 14 cm -3 The final device thickness (t device ) is greater than or equal to 40 μm and less than or equal to 700 μm.

[0226] The peak impurity concentration of the P base layer 9 is set to be greater than or equal to 1.0×10 16 cm -3and less than or equal to 1.0×10 18 cm -3 , depth ratio N + The emitter layer 7 is deep and shallower than the N layer 11. The N layer 11 is set to have a peak impurity concentration greater than or equal to 1.0×10 15 cm -3 and less than or equal to 1.0×10 17 cm -3 , the depth is 0.5μm to 1.0μm deeper than the P base layer 9. + The emitter layer 7 is set to have a peak impurity concentration greater than or equal to 1.0×10 18 cm -3 and less than or equal to 1.0×10 21 cm -3 , the depth is greater than or equal to 0.2 μm and less than or equal to 1.0 μm. + The surface impurity concentration of layer 8 is set to be greater than or equal to 1.0×10 18 cm -3 and less than or equal to 1.0×10 21 cm -3 , depth and N + The emitter layer 7 is the same as or deeper than the emitter layer 7. The P collector layer 16 is set to have a surface impurity concentration greater than or equal to 1.0×10 16 cm -3 and less than or equal to 1.0×10 20 cm -3 The depth of the trench in which the gate electrode 13 is embedded (D trench ) is set to be greater than or equal to 2.0 μm and to reach at least the depth of the N layer 11. In addition, the parameters of the N buffer layer 15 (the first buffer layer 15-1 and the second buffer layer 15-2) may be the same as those in the first embodiment.

[0227] The structure of the middle region R2 and the edge termination region R3 of the prototype IGBT structure is as follows: Fig.46 or Fig.47 However, the N buffer layer 15 in the middle region R2 and the edge termination region R3 has the same structure as that in the active cell region R1.

[0228] Figures 48 to 50 This is the result of verifying, by simulation, the effect of the new structure N buffer layer 15 in the unique short-circuit state in the operation of the IGBT that is not seen in the diode.

[0229] Fig.48 The electric field intensity distribution inside the IGBT in the short-circuit state is shown. Fig.49It is the electric field strength and the on-state voltage (V CE (sat)). The horizontal axis is V CE (sat) is the hole injection efficiency from the collector side ( Fig.45 γ p，active The “front side” in the figure is the electric field strength of the main junction existing on the surface of the device, and the “back side” is the maximum electric field strength in the N buffer layer 15 existing on the back of the device. Fig.50 Is to make V CE (sat) is constant, and the internal temperature distribution of the upper part of the device when the device of the conventional structure IGBT and the new structure IGBT is set to a short-circuit state. In addition, Fig.50 The temperature distribution shown is measured at the time Fig.51 shown. Fig.51 It is analyzing Fig.50 The short-circuit waveform in the simulation when the temperature distribution inside the device is shown.

[0230] In the conventional IGBT, if the hole injection efficiency (γ p，active ) is high, the electric field strength of the main junction increases, so if Fig.50 The temperature rise of the upper part of the device is likely to cause a decrease in the interruption capability in the short-circuit state. On the other hand, in the new structure IGBT, the carrier plasma layer of the collector part in the short-circuit state is controlled by the effect of promoting carrier recombination brought about by the lattice defects in the second buffer layer 15-2, and the depletion layer becomes easy to extend to the back side of the device, so as Fig.48 As shown in Figure 1, the electric field strength also becomes a well-balanced distribution in the short-circuit state. As a result, in the new structure IGBT, Fig.50 As shown, the temperature rise of the upper portion of the device is suppressed compared to the conventional structure IGBT, and the interruption capability in the short-circuit state can be expected to be improved.

[0231] Fig.52 This is the cut-off waveform of the existing structure IGBT and the new structure IGBT of 1200V class at 298K. Fig.52 In the conventional structure IGBT and the new structure IGBT shown in FIG. device ) and N - The impurity concentration (C n- ). In the new structure IGBT, Fig.12 Similar to the new structure RFC diode shown, a carrier plasma layer remains on the collector side in the second half of the cut-off operation. Therefore, the electric field strength on the collector side is relaxed in the new structure IGBT, suppressing the step phenomenon and subsequent oscillation phenomenon observed in the conventional structure IGBT, thereby showing a cut-off operation with excellent controllability.

[0232] Fig.53 These are the short-circuit waveforms of 1200V class IGBTs with existing structures and new structures. Fig.54 The maximum energy density (E) that can be broken when the 1200V class IGBT with existing structure and new structure is short-circuited. SC ) and the thickness of the device (t device ) is a graph showing the relationship between Fig.53 and Fig.54 Compared with the existing IGBT structure, the new IGBT structure has a larger safe operating area (SOA) in the short-circuit state, which can ensure sufficient SOA and reduce the thickness of the device (t device ).

[0233] exist Fig.55 The figure shows the on-state voltage (V) of the conventional IGBT and the new IGBT of the 1200V class. CE (sat)) and the loss at cutoff (E OFF ) trade-off characteristics. The new structure IGBT can reduce the device thickness (t device ),like Fig.52 and Fig.53 As shown, the controllability during dynamic operation is excellent and the durability is improved, and as Fig.55 As shown, a reduction in total loss is achieved.

[0234] Fig.56 and Fig.57 This is a diagram showing the effect of the new structure N buffer layer 15 in an IGBT of a high withstand voltage class (6.5 kV). Fig.56 The main junction leakage current (J) of the existing structure IGBT and the new structure IGBT at 423K of 6.5kV class CES ) and the collector-emitter voltage (V CES ) is a graph showing the relationship between Fig.56 It can be seen that the new structure N buffer layer 15 has the effect of reducing the current amplification factor (α) of the PNP transistor built into the IGBT. pnp ) as a result of which low disconnection loss can be achieved due to low leakage current during disconnection.

[0235] Fig.57The cut-off waveforms at 213K for the conventional IGBT and the new IGBT of the 6.5kV class are shown. The cut-off waveforms at low temperatures also show that, for the IGBT having the new N buffer layer 15, a residual carrier plasma layer exists on the collector side in the second half of the cut-off operation. Therefore, in the new IGBT, the electric field strength on the collector side is relaxed, thereby suppressing the step phenomenon and the subsequent oscillation phenomenon, and showing an excellent cut-off operation even at low temperatures.

[0236] As described above, it is found that the above-mentioned objects (a) to (c) can be achieved also in an IGBT using the new structure N buffer layer 15 in which the ratio of traps B in lattice defects in the second buffer layer 15 - 2 is controlled to 15% to 55%.

[0237] <Implementation Method 4>

[0238] In the fourth embodiment, a method for manufacturing an IGBT and an RFC diode using the N buffer layer 15 having a new structure will be described.

[0239] First, refer to Figures 58 to 70 , a method for manufacturing a semiconductor device having an IGBT will be described. These drawings show a method for manufacturing an active cell region R1.

[0240] Prepare to form N - The FZ wafer of the drift layer 14, i.e., the semiconductor substrate, is subjected to ion implantation and annealing treatment, so that Fig.58 As shown in FIG. 1 , an N layer 11 and a P base layer 9 are formed on the surface layer of the semiconductor substrate. In addition, a SiO 2 Membrane 101.

[0241] Furthermore, by performing ion implantation and annealing treatment on the semiconductor substrate, Fig.59 As shown, N is selectively formed on the upper layer of the P base layer 9. + Emitter layer 7.

[0242] Then, if Fig.60 As shown, an oxide film 102 is formed on the upper surface of the semiconductor substrate and patterned using photolithography. Then, reactive ion etching using plasma is performed on the portion exposed at the opening of the oxide film 102 to form a groove 103. After that, chemical dry etching and sacrificial oxidation treatment are performed for the purpose of removing crystal defects and plasma damage layers in the peripheral portion of the groove 103, chamfering the bottom of the groove 103, and flattening the inner wall of the groove 103. For example, chemical dry etching and sacrificial oxidation treatment are disclosed in Japanese Patent Publication No. 7-263692. In addition, for example, WO2009 / 122486 discloses the appropriate depth of the groove 103.

[0243] Next, if Fig.61 As shown, a gate insulating film 12 is formed on the inner wall of a trench 103 by a thermal oxidation method or a CVD (Chemical Vapor Deposition) method (for example, refer to Japanese Patent Laid-Open No. 2001-085686). Then, a polysilicon layer 104 doped with phosphorus is formed in the trench 103 including the gate insulating film 12 to fill the trench 103. In addition, an oxide film 105 is formed on the lower surface of the semiconductor substrate while the gate insulating film 12 is formed, and a polysilicon layer 106 doped with phosphorus is formed on the oxide film 105 while the polysilicon layer 104 is formed.

[0244] Then, if Fig.62 As shown in FIG. 1 , the portion of the polysilicon layer 104 extending out of the trench 103 is etched. At this time, the polysilicon layer 104 remaining in the trench 103 becomes the gate electrode 13. Then, an oxide film 107 is formed on the exposed surface of the gate electrode 13 by thermal oxidation or CVD. Then, a P + Layer 8. Then, an oxide film 108 and a TEOS film 109 doped with boron or phosphorus are formed on the upper surface of the semiconductor substrate by CVD, thereby forming an interlayer insulating film 6. A TEOS film or silicate glass may be formed as the oxide film 108. In addition, when the oxide film 108 and the TEOS film 109 are formed, a TEOS film 110 is formed on the lower surface of the semiconductor substrate.

[0245] Then, if Fig.63 As shown, a liquid containing hydrofluoric acid or a mixed acid (for example, a mixed solution of hydrofluoric acid, nitric acid and acetic acid) is used to etch the TEOS film 110, the polysilicon layer 106 and the oxide film 105 on the lower surface of the semiconductor substrate to make the N - The drift layer 14 is exposed.

[0246] Next, if Fig.64 As shown, the N-type semiconductor substrate exposed on the lower surface of the semiconductor substrate is deposited by LPCVD (Low-Pressure Chemical Vapor Deposition) method. - A polysilicon layer 111 doped with impurities is formed on the drift layer 14. Phosphorus, arsenic, antimony, or the like is used as the impurity doped into the polysilicon layer 111 so that the polysilicon layer 111 becomes N + The impurity concentration of the polysilicon layer 111 is set to be greater than or equal to 1×10 19 (cm -3 ). In addition, the layer thickness of the polysilicon layer 111 is set to be greater than or equal to 500 (nm). When the polysilicon layer 111 is formed, a polysilicon layer 112 is also formed on the upper surface of the semiconductor substrate.

[0247] Then, if Fig.65 As shown, in a nitrogen environment, the temperature of the semiconductor substrate is heated to about 900° C. to 1000° C. so that the impurities in the polysilicon layer 111 are directed to N - The lower surface side of the drift layer 14 is diffused. - The lower surface of the drift layer 14 is formed of a high concentration of N + The gettering layer 113 is composed of a layer 113a and a high crystal defect density layer 113b. + The impurity concentration of the surface of the layer 113a is set to, for example, 1.0×10 19 cm -3 and less than or equal to 1.0×10 22 range.

[0248] After that, the temperature of the semiconductor substrate is lowered to about 600°C to 700°C at an arbitrary cooling rate, and the temperature is maintained for more than or equal to 4 hours. This process is called an annealing process. In the annealing process, the semiconductor substrate is heated to make the N - Metal impurities, contamination atoms, and damage in the drift layer 14 diffuse and are captured by the gettering layer 113 .

[0249] Then, if Fig.66 As shown, a liquid of hydrofluoric acid or a mixed acid (e.g., a mixed solution of hydrofluoric acid / nitric acid / acetic acid) is used to selectively remove the polysilicon layer 112 on the upper surface of the semiconductor substrate. For example, WO2014 / 054121 discloses Figure 64 to Figure 66 The gettering process is shown.

[0250] Then, if Fig.67 As shown, on the upper surface side of the semiconductor substrate, the interlayer insulating film 6 is partially etched to form a layer reaching N + The emitter layer 7 and P + A contact hole is formed in the layer 8, and a trench exposure portion 114 is formed in a part of the active cell region R1 to expose the upper surface of the gate electrode 13 buried in the trench. The portion other than the trench exposure portion 114 functions as a MOS transistor portion in the IGBT.

[0251] The purpose of forming the trench exposed portion 114 in a part of the region where the gate electrode 13 is formed is to reduce the effective gate width and adjust the capacitance by setting a part of the gate electrode 13 to the emitter potential. This can achieve saturation current density suppression, oscillation suppression during short circuit by capacitance control, short circuit tolerance improvement (for details, refer to WO2002 / 058160 and WO2002 / 061845), and low turn-on voltage by increasing the carrier concentration on the emitter side in the on state.

[0252] Then, if Fig.68 As shown, a metal for forming a silicide layer 115 and a barrier metal layer 116 is formed on the upper surface of the semiconductor substrate by sputtering. Furthermore, a metal wiring layer to which about 1 to 3% of Si is added is formed by sputtering, and the metal wiring layer is patterned to form an emitter electrode 4. The material of the metal wiring layer is, for example, AlSi, AlSiCu, or AlCu. The emitter electrode 4 is electrically connected to the trench exposed portion 114.

[0253] Then, if Fig.69 As shown in FIG. 1 , the gettering layer 113 and the polysilicon layer 111 formed on the lower surface side of the semiconductor substrate are removed by grinding or etching. The process of removing the gettering layer 113 and the like is referred to as a removal process. In the removal process, the N - The portion of the drift layer 14 that is in contact with the gettering layer 113. - The thickness of the drift layer 14 is set to a thickness corresponding to the withstand voltage level of the semiconductor device.

[0254] Next, if Fig.70 As shown, an N buffer layer 15 is formed on the surface layer portion of the back side of the semiconductor substrate. Phosphorus, selenium, sulfur or protons (hydrogen) are implanted from the back side of the semiconductor substrate, and then the semiconductor substrate is annealed to activate the implanted ions, thereby forming the N buffer layer 15. The details of the process flow of the N buffer layer 15 (i.e., the newly structured N buffer layer 15) of the fourth embodiment will be described later.

[0255] Thereafter, a P-type P collector layer 16 is formed on the surface portion of the back side of the N buffer layer 15. Then, a collector electrode 20 is formed in contact with the P collector layer 16. The collector electrode 20 is a portion that is solder-bonded to a semiconductor substrate or the like in the module when the semiconductor device is mounted on the module. Therefore, it is preferable to form the collector electrode 20 by stacking a plurality of metals to provide a low contact resistance.

[0256] Next, refer to Figure 71 to Figure 79 , a method for manufacturing a semiconductor device having an RFC diode is described.

[0257] exist Fig.71 The active cell region R1, the middle region R2 and the edge termination region R3 are shown in FIG. - Then, an insulating film 25 of an oxide film is formed on the semiconductor substrate and patterned, and ion implantation is performed using the insulating film 25 as a mask. Thereafter, an annealing process is performed on the semiconductor substrate, thereby forming N in the middle region R2 and the edge termination region R3. - A guard ring 22, a field limiting ring 23, and a channel stopper layer 24 are formed on the surface layer of the drift layer 14. When the insulating film 25 is formed, an oxide film 121 is formed on the lower surface of the semiconductor substrate.

[0258] Then, if Fig.72 As shown, for the active cell region R1, N - The surface layer of the drift layer 14 is subjected to ion implantation and annealing to form a P anode layer 10. In addition, the N - The surface portion of the drift layer 14 is subjected to ion implantation and annealing to form a channel stopper layer 24. Then, an interlayer insulating film 26 of a TEOS film is formed on the upper surface of the semiconductor substrate, and then a process is performed to expose the lower surface of the semiconductor substrate.

[0259] Next, if Fig.73 As shown, the N - A polysilicon layer 122 doped with impurities is formed in contact with the drift layer 14. At this time, a polysilicon layer 123 is also formed on the upper surface of the semiconductor substrate.

[0260] Then, if Fig.74 As shown, the semiconductor substrate is heated to cause the impurities in the polysilicon layer 122 to move toward N - The lower surface of the drift layer 14 is diffused, and N - The lower surface of the drift layer 14 is formed of a high concentration of N + The gettering layer 124 is composed of a layer 124a and a high crystal defect density layer 124b. Fig.65 The manufacturing method of the IGBT shown in the figure has the same process of forming the gettering layer 113. Thereafter, an annealing process is performed to capture N by the gettering layer 124. - Metal impurities, contamination atoms, and damage in the drift layer 14.

[0261] Then, if Fig.75 As shown, hydrofluoric acid or a mixed acid (eg, a mixed solution of hydrofluoric acid / nitric acid / acetic acid) is used to selectively remove the polysilicon layer 123 on the upper surface of the semiconductor substrate. This gettering process is the same as the gettering process of the IGBT described above.

[0262] Then, if Fig.76 As shown, contact holes reaching the P anode layer 10, the guard ring 22, the field limiting ring 23, and the channel stop layer 24 are formed in the insulating film 25 and the interlayer insulating film 26. Then, an aluminum film to which Si is added by about 1% to 3% is formed on the upper surface of the semiconductor substrate by sputtering and patterning, thereby forming the anode electrode 5, the FLR electrode 27, and the channel stop electrode 28.

[0263] Then, if Fig.77 As shown in FIG. 1 , passivation films 29 and 30 which are protective films are formed on the upper surface of the semiconductor substrate.

[0264] Afterwards, if Fig.78 As shown in FIG. 1 , the gettering layer 124 and the polysilicon layer 122 on the lower surface side of the semiconductor substrate are removed by grinding or etching. In addition, through this removal process, the semiconductor substrate (N - The thickness of the drift layer 14 is set to a thickness corresponding to the withstand voltage level of the semiconductor device.

[0265] Then, if Fig.79 As shown, in N - The N buffer layer 15 is formed on the lower surface of the drift layer 14. Then, the P cathode layer 18 is formed on the lower surface of the N buffer layer 15. Next, in the active cell region R1, an N + Cathode layer 17. N buffer layer 15, N + The cathode layer 17 and the P cathode layer 18 are diffusion layers formed by ion implantation and annealing. Finally, a cathode electrode 19 is formed on the lower surface of the semiconductor substrate.

[0266] The substrate concentration (C n- ) is determined in accordance with the withstand voltage level of the semiconductor element being manufactured. For example, C n- Greater than or equal to 1.0×10 12 cm -3 and less than or equal to 5.0×10 14 cm -3 The Si wafer is made by FZ method. Then, Fig.69 or Fig.78 In the wafer process shown, the thickness of the device is adjusted with high precision according to the withstand voltage level. Fig.70 or Fig.79 The vertical structure 35 is constructed in the wafer process shown. The wafer process in which the vertical structure region is constructed in the wafer process using the FZ wafer as described above is becoming more and more mainstream, and this is based on the following background.

[0267] a) As a wafer, N is produced by epitaxial method. -The wafer of drift layer 14 has the following disadvantages, that is, the cost of Si wafer depends on the thickness of Si formed by epitaxy, so the cost of Si wafer is very high. On the other hand, by FZ method, only N - The concentration of the drift layer 14 is set to an appropriate value, and N is used with the same thickness regardless of the withstand voltage level at the beginning of the wafer process. - As a result, a low-cost Si wafer can be used as the drift layer 14 .

[0268] b) For the purpose of effectively utilizing the wafers manufactured by the FZ method, Fig.69 or Fig.78 In the final stage of the wafer process shown, the thickness of the device is controlled to the value required by the withstand voltage level, and the vertical structure is constructed, so that a wafer process that minimizes the modification of the process equipment can be adopted. As a result, even in the wafer process of large-diameter Si wafers with a diameter of 200 mm or more, it is possible to cope with various wafer thicknesses ranging from 40 μm to 700 μm.

[0269] c) Based on background b), IGBTs and diodes can be manufactured directly using the latest process equipment to form MOS transistor structures, various diffusion layers, wiring structures and other device structures on the surface of the wafer.

[0270] The impurity concentration of the n-drift layer and the thickness of the device are device parameters that affect not only the withstand voltage characteristics of the IGBT and diode, but also the total loss, controllability during dynamic operation, and breakdown resistance, and require high precision.

[0271] Fig.80 This is a diagram comparing two process flows for forming the second buffer layer 15-2 of the new structure N buffer layer 15. Process A is the process flow of Embodiment 4. The trial production results shown in Embodiments 1 to 3 are the results of trial production of the second buffer layer 15-2 by Process A.

[0272] In addition, details of the above-mentioned wafer process are also described in Japanese Patent No. 3396553, Japanese Patent No. 5622814, Japanese Patent No. 6065067, and Japanese Patent No. 6558462.

[0273] That is, when forming a new structure N buffer layer 15 composed of the first buffer layer 15-1 and the second buffer layer 15-2, as described in Japanese Patent Nos. 6065067 and 6558462, in terms of IGBT and diode, the N buffer layer 15 is formed in the wafer process so as to satisfy a value greater than or equal to the carrier lifetime calculated by the following formula (2). - The process of recovering the carrier lifetime of the drift layer 14 ( Figure 64-65 process or Figure 73-74 A high concentration (for example, surface concentration greater than or equal to 1.0×10 20 cm -3 and less than or equal to 1.0×10 22 cm -3 , depth greater than or equal to 1.0 μm and less than or equal to 10 μm) + The gettering layer 113 or 124 is composed of the N buffer layer 15, the P collector layer 16, and the N + Before the cathode layer 17 and the P cathode layer 18, the gettering layer 113 or 124 is removed by a grinding process and a subsequent wet etching process ( Fig.69 process or Fig.78 process).

[0274] τ t =1.5×10 -5 exp(5.4×10 3 t N- )…Formula (2)

[0275] In formula (2), t N- N - The thickness (m) of the drift layer 14 is Figure 2 , Fig.40 and Fig.45 The t shown N- Equivalent device parameters. In addition, τ t N is the value that eliminates the effect of carrier lifetime on the on-state voltage of IGBT and diode. - Carrier lifetime in the drift layer 14 (sec).

[0276] Formula (2) is derived from the following viewpoints. That is, the on-voltage of IGBT and FWD with respect to N - The carrier lifetime of the drift layer 14 almost disappears from a certain value. As long as the relationship between the on-state voltage and the carrier lifetime can be controlled, the influence of the carrier lifetime on the on-state loss can also be controlled. In addition, as long as the carrier lifetime can be set so that the off-state loss is also affected by the carrier lifetime, and the influence of the carrier lifetime on the on-state voltage disappears, it is effective for reducing the off-state loss and suppressing thermal runaway.

[0277] Based on this concept, if the assumed withstand voltage level (600V to 6500V level) is used, the N of the on-state voltage is plotted on the vertical axis. - The carrier lifetime value at which the carrier lifetime dependence of the drift layer 14 disappears is related to N -The thickness of the drift layer (t N- ) are plotted, then Fig.81 shown. Fig.81 is the carrier lifetime and N obtained from the simulation - The thickness of the drift layer (t N- ) is a curve diagram of the relationship between Figure 2 , Fig.40 and Fig.45 The device configuration shown is the result of the study. Fig.81 The relationship between the straight lines in is the relationship of formula (2).

[0278] That is, it is believed that by Fig.81 The “device characteristic stabilization region” in (greater than or equal to τ obtained by equation (2) t The lifetime region) controls the lifetime of the wafer process, thereby enabling N - The negative effects of the carrier lifetime of the drift layer 14 on the final device characteristics can be suppressed, and the original performance of the device structure and the fluctuation of the electrical characteristics between multiple chips in the wafer can be limited to a minimum. Therefore, the manufacturing technology of this embodiment is manufactured in the following manner, that is, - The carrier lifetime of the drift layer is controlled to be greater than or equal to τ obtained by equation (2) t range (i.e., Fig.81 The device characteristics stabilization region) and the relationship between the lifespans of the elements constituting the device structure described in Embodiments 1 to 3 are satisfied.

[0279] In order to realize formula (2) and Fig.81 The "device characteristic stabilization region" is formed by the following process to form the doping layer (113 or 124) used in the manufacturing method of this embodiment. First, in order to expose the Si surface on the back side of the semiconductor substrate (wafer), only the back side of the wafer is selectively etched ( Fig.63 , Fig.72 ). At this time, the etching technology used is a liquid of hydrofluoric acid or a mixed acid (for example, a mixed solution of hydrofluoric acid / nitric acid / acetic acid).

[0280] Next, as a method for forming a high concentration N + The material source of the layer (113a or 124a) and the high crystal defect density layer (113b or 124b) is formed by LPCVD method. + A polysilicon layer (111 or 122) (hereinafter referred to as "d-polysilicon layer") ( Fig.64 , Fig.73 ). As the formation of N + The atoms of the layer, for example, phosphorus, arsenic, antimony, etc., can diffuse in Si to form N+ The d-polysilicon layer (111 or 122) is doped with a concentration greater than or equal to 1×10 19 cm -3 The high concentration impurity film has a thickness of 500 nm or more. The reason for doping with high concentration impurities is that the high concentration impurities diffuse to the Si surface on the back of the wafer through subsequent annealing. + When the layer (113a or 124a) is formed, high-density dislocations and lattice defects are introduced together with the high crystal defect density layer (113b or 124b) to capture heavy metals and pollutant atoms. At this time, the d-polysilicon layer (111 or 122) is in direct contact with the Si surface exposed on the back of the wafer.

[0281] After the d-polysilicon is deposited, thermal annealing is performed at 900°C to 1000°C in a nitrogen environment, and the temperature is lowered from 900°C to 1000°C at an arbitrary rate of 600°C to 700°C. Then, if a low-temperature thermal annealing technique is used at 500°C to 700°C in a nitrogen environment, which is lower than the previous annealing temperature, impurities diffuse from the d-polysilicon into the Si on the back side of the wafer where the Si and d-polysilicon are in direct contact, forming N + layer (113a or 124a), and at this time, crystal defects are secondary generated (ie, a high crystal defect density layer (113b or 124b)). The N + The layer (113a or 124a), the high crystal defect density layer (113b or 124b) and the d-polysilicon layer (111 or 122) are in direct contact with the exposed Si surface, so that the materials with different thermal expansion coefficients are annealed at the interface (N + The surface layer of the layer (113a or 124a) generates strain, N + layer (113a or 124a), a high crystal defect density layer (113b or 124b), and a + The strain layer at the surface of the layer (113a or 124a) becomes the target site ( Fig.65 , Fig.74 As a result, when the above-mentioned low temperature thermal annealing technology is performed, heavy metals and contamination atoms that have entered the wafer during the wafer process diffuse and move toward the target site in the crystal lattice.

[0282] Through the action of this technology, the N - The drift layer τ is restored, thereby achieving a sufficiently long carrier lifetime N that does not affect the electrical characteristics of IGBTs and FWDs of various withstand voltage levels as shown in equation (2). - Drift layer. In addition, regarding the low temperature thermal annealing time at 600℃~700℃ in a nitrogen environment, from N -As will be described later, there is an appropriate annealing time in consideration of the carrier lifetime of the drift layer and the electrical characteristics of the IGBT and FWD which are affected by the carrier lifetime.

[0283] In addition to the method using the d-polysilicon layer (111 or 122), the same effect can be obtained by forming a high crystal defect density layer (113b or 124b) on the back side of the wafer using laser annealing technology (rapid heating / cooling and local annealing technology using a laser with a wavelength of 500°C to 1000nm). In this case, the power density of the laser annealing is set to be greater than or equal to 4J / cm 2 , laser annealing and the subsequent annealing techniques (thermal annealing at 900°C to 1000°C in a nitrogen environment, and annealing at 500°C to 700°C in a nitrogen environment) are used to form a high crystal defect density layer (113b or 124b). By forming the high crystal defect density layer (113b or 124b), the effect of improving the carrier lifetime is obtained and stabilized.

[0284] The vertical structure (35) provided on the back side of the semiconductor substrate is formed in the aluminum wiring process and the passivation film forming process ( Fig.69 , Fig.78 ) is formed after forming. On the upper surface of the semiconductor substrate (the surface where the vertical structure (35) is not formed), for example, in the case of an IGBT, a MOS transistor structure is formed, and there are aluminum wiring and a passivation film. Therefore, when forming the diffusion layer (N buffer layer 15, P collector layer 16, N + When the cathode layer 17 and the P cathode layer 18 are formed, an annealing technology (laser annealing) and a low-temperature annealing technology less than or equal to the melting point of the metal are used to maintain the upper surface of the semiconductor substrate at a temperature lower than the melting point of the metal used for the aluminum wiring (the melting point of aluminum: 660°C), wherein the laser annealing uses a laser with a wavelength that has a temperature gradient in the depth direction of the device and does not conduct heat to the upper surface of the semiconductor substrate.

[0285] The thickness (t of the first buffer layer (15-1) and the second buffer layer (15-2) constituting the vertical structure (35) is device :40μm~700μm) process ( Fig.69 , Fig.78 ) is formed. At this time, the gettering layer (113 or 124) has been removed, but N - The carrier lifetime of the drift layer 14 satisfies the formula (2) to form N - A diffusion layer required for the drift layer 14 .

[0286] In the process of embodiment 4 ( Fig.80In the process A), the order of forming the first buffer layer (15-1) and the second buffer layer (15-2) and the setting of the peak position of the acceleration energy when the second buffer layer (15-2) is introduced are important. That is, after the first buffer layer (15-1) is formed by ion implantation and annealing technology (first annealing process), the second buffer layer (15-2) is formed by ion implantation and annealing technology (second annealing process). The reason is that the annealing technology used when forming the first buffer layer (15-1) is a higher temperature annealing technology than the annealing technology used when forming the second buffer layer (15-2). In addition, if the annealing technology used when forming the first buffer layer (15-1) is subsequently performed, it will have an adverse effect on the impurity distribution after activation of the second buffer layer (15-2) and the type of lattice defects in the second buffer layer (15-2) introduced to form the second buffer layer (15-2), which will have an adverse effect on the carriers (electrons or holes) in the on state of the device.

[0287] Regarding the second buffer layer 15-2, after the activation annealing of the first buffer layer (15-1), ions are introduced into Si, and the P collector layer 16 and N + After the cathode layer 17 or the P cathode layer 18 or after the metallized film (cathode electrode 19 or collector electrode 20) is formed, the second annealing step is performed, thereby forming the above-mentioned target second buffer layer (15-2).

[0288] Here, the first buffer layer 15-1 and the second buffer layer 15-2 are formed so as to satisfy the following relationship: The peak position of the second buffer layer 15-2 is set to be located at the junction (X j，nb1 ) on the upper side (knot X j，nb2 Thus, the first buffer layer 15-1 and the second buffer layer 15-2 do not interfere with each other, and the second buffer layer 15-2 can be formed with high precision.

[0289] As ion species for forming the first buffer layer 15-1 and the second buffer layer 15-2, phosphorus is used for the first buffer layer 15-1, and selenium, sulfur, phosphorus, protons (H + ), helium. When using protons (H + In the case of helium, a diffusion layer forming process technology is used to form an N layer by a donor phenomenon achieved by the annealing conditions described later. In addition to ion implantation, proton (H + ) can be introduced into Si by using cyclotron irradiation technology. + ), then there exists:

[0290] (a) The holes (V) generated during the introduction diffuse and react with impurities (hydrogen atoms (H), oxygen atoms (O), and carbon atoms (C)), and complex defects (VOH, V) are formed by substitution reactions between carbon atoms and lattice defects. 2 H, VO, CiOS (G-center), CiOi (C-center);

[0291] (b) The lattice defects generated during the introduction diffuse and self-aggregate, and then react with oxygen atoms during annealing to form complex defects (V 2 O.V 2 O 2 );

[0292] (c) An aggregate of lattice defects (trap A) generated during introduction diffuses and reaggregates during annealing to form a lattice defect pair (trap B).

[0293] Among them, since hydrogen is contained in the composite defects formed by the reaction of holes and impurities, it becomes an electron supply source (donor). The increase in the composite defect density caused by annealing increases the donor concentration, and the donor concentration increases by promoting the thermal donor phenomenon caused by the ion implantation / irradiation process. As a result, with N - The drift layer 14 contributes to the operation of the device as the second buffer layer 15-2 compared to the donor layer having a higher impurity concentration. This technology effectively utilizes the complex defects formed in the second buffer layer 15-2 to improve the device performance.

[0294] On the other hand, since the composite defects formed in the second buffer layer 15-2 also have defects that reduce the lifetime of carriers and become lifetime suppressing factors, the impurity dosage when forming the second buffer layer 15-2 and the process flow when forming the second buffer layer 15-2 (as described above, the second buffer layer 15-2 is formed by ion implantation and annealing technology after the first buffer layer 15-1 is formed) are determined. Fig.80 The process A) and the annealing conditions for donorization of the second buffer layer 15-2 are important. In addition, the first buffer layer 15-1 and the second buffer layer 15-2 are activated by using different annealing techniques.

[0295] exist Fig.82 It is shown in Fig.80The device performance of the 1200V-class new structure RFC diode produced by trial production of two process flows (process A and process B) for forming the second buffer layer 15-2 is shown. Due to the different process flows, the ratio of traps B in the lattice defects in the second buffer layer 15-2 is different. In particular, in process B where the ion implantation step for forming the second buffer layer 15-2 is located before the ion implantation step for forming the first buffer layer 15-1, the ratio of traps B is greater than or equal to 55%, which will lead to deterioration of the device performance of the RFC diode.

[0296] exist Fig.83 The results of studying the annealing temperature of the second annealing step are shown in FIG. 1 . In the second annealing step, the second buffer layer 15-2 is formed by process A to control the ratio of traps B in the lattice defects in the second buffer layer 15-2 to the target 15% to 55%. Here, the annealing time is 120 minutes. Fig.83 It can be seen that when process A is used, the setting of the annealing temperature for forming the second buffer layer 15-2 is also important. In order to control the ratio of the trap B to 15% to 55%, the annealing temperature needs to be controlled to be greater than or equal to 370°C and less than or equal to 425°C. Thus, the lifetime shown in equation (2) is satisfied.

[0297] Fig.84 is a graph showing the relationship between the PL intensity of trap A and trap B and the annealing time. Fig.84 , the relationship between the PL intensity of traps A and B and the annealing time of the annealing process when the PL method is used to analyze the PL intensity of traps A and B is shown on the basis of controlling the ratio of traps B in the lattice defects in the second buffer layer 15-2 to 15% to 55% by process A. In addition, Fig.84 Points A and B in Figure 8 The data of the positions of points A and B are shown.

[0298] Here, the annealing temperature is 400°C. Even if the ratio of trap B is controlled to 15% to 55%, it is beneficial to reduce the defect density of traps A and B in order to satisfy the lifetime shown in equation (2) from the perspective of device performance of IGBT and FWD. Fig.84 It can be seen that the annealing time dependence of the PL intensity showing the defect density of traps A and traps B becomes insensitive when the annealing time is greater than or equal to 90 minutes. That is, in order to control the ratio of trap B in the lattice defects in the second buffer layer 15-2 constituting the N buffer layer 15 to 15% to 55% through process A, and in order to reduce the defect density of traps A and traps B, the annealing time needs to be set to greater than or equal to 90 minutes.

[0299] Furthermore, the various embodiments may be freely combined, and the various embodiments may be appropriately modified or omitted.

[0300] Description of the label

[0301] R1 active cell area, R2 middle area, R3 edge termination area, R11 surface gate wiring area, R12 gate pad area, R21 PiN diode area, R22 PNP transistor area, 4 emitter electrode, 5 anode electrode, 6 interlayer insulation film, 7N + Emitter layer, 8 P + layer, 9 P base layer, 10 P anode layer, 11 N layer, 12 gate insulating film, 13 gate electrode, 13a surface gate electrode, 14 N - Drift layer, 15 N buffer layer, 15-1 first buffer layer, 15-2 second buffer layer, 16 P collector layer, 17 N + cathode layer, 18 P cathode layer, 19 cathode electrode, 20 collector electrode, 22 guard ring, 23 field limiting ring, 24 channel stop layer, 25 insulating film, 26 interlayer insulating film, 27 FLR electrode, 28 channel stop electrode, 29 passivation film, 30 passivation film, 31 surface gate electrode, 35 vertical structure, 101 SiO 2 film, 102 oxide film, 103 trench, 104 polysilicon layer, 105 oxide film, 106 polysilicon layer, 107, 108 oxide film, 109, 110 TEOS film, 111, 112 polysilicon layer, 113 gettering layer, 113a N + layer, 113b high crystal defect density layer, 114 trench exposed portion, 115 silicide layer, 116 barrier metal layer, 117 metal wiring layer, 121 oxide film, 122, 123 polysilicon layer, 124 gettering layer, 124a N + layer, 124b is a layer with high crystal defect density.

Claims

1. A semiconductor device, characterized in that: have: A semiconductor substrate having a first main surface and a second main surface; a first conductivity type drift layer formed on the semiconductor substrate; a second conductivity type impurity diffusion layer formed on the first main surface side of the drift layer; and a first conductive type buffer layer formed on the second main surface side of the drift layer and having a higher peak impurity concentration than the drift layer; The buffer layer comprises: a first buffer layer in which no trap levels derived from lattice defects are detected by a photoluminescence method; and The second buffer layer is provided between the first buffer layer and the drift layer and is a layer in which two types of trap levels derived from lattice defects are detected by the photoluminescence method.

2. The semiconductor device according to claim 1, wherein An insulated gate transistor structure is formed on the first main surface side of the impurity diffusion layer.

3. The semiconductor device according to claim 2, wherein: A second conductivity type collector layer is formed on the second main surface side of the buffer layer.

4. The semiconductor device according to claim 3, wherein: An active cell region, an edge termination region disposed outside the active cell region, and a region between the active cell region and the edge termination region, i.e., an intermediate region, are defined on the semiconductor substrate. The buffer layer and the collector layer are formed across the active cell region, the middle region, and the edge termination region.

5. The semiconductor device according to claim 3, wherein: An active cell region, an edge termination region disposed outside the active cell region, and a region between the active cell region and the edge termination region, i.e., an intermediate region, are defined on the semiconductor substrate. The buffer layer is formed across the active cell region, the middle region and the edge termination region, The collector layer is formed only in the active cell region.

6. The semiconductor device according to claim 1, wherein The impurity diffusion layer functions as the anode of the diode. A cathode layer of a first conductivity type that functions as a cathode of the diode is formed on the second main surface side of the buffer layer.

7. The semiconductor device according to claim 6, wherein: An active cell region, an edge termination region disposed outside the active cell region, and a region between the active cell region and the edge termination region, i.e., an intermediate region, are defined on the semiconductor substrate. The buffer layer and the cathode layer are formed across the active cell region, the middle region and the edge termination region.

8. The semiconductor device according to claim 1, wherein The impurity diffusion layer functions as the anode of the diode. A first cathode layer of a first conductivity type and a second cathode layer of a second conductivity type that function as a cathode of the diode are formed on the second main surface side of the buffer layer.

9. The semiconductor device according to claim 8, wherein: An active cell region, an edge termination region disposed outside the active cell region, and a region between the active cell region and the edge termination region, i.e., an intermediate region, are defined on the semiconductor substrate. The buffer layer and the first cathode layer are formed across the active cell region, the middle region and the edge termination region. The second cathode layer is formed only in the active cell region.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The two types of trap energy levels derived from lattice defects of the second buffer layer detected by photoluminescence (PL) are trap A and trap B. The photon energy of trap A is 1.0182 eV, and the photon energy of trap B is 1.0398 eV. When the PL intensity of the trap B is set to S PLB , the PL intensity of the trap A is set to S PLA hour, The ratio of trap B = {S PLB / (S PLA +S PLB )}×100, the ratio of the traps B in the second buffer layer is greater than or equal to 15% and less than or equal to 55%.

11. The semiconductor device according to claim 10, wherein The distribution of the ratio of the traps B in the depth direction of the second buffer layer is constant within a range of greater than or equal to 15% and less than or equal to 55%.

12. The semiconductor device according to any one of claims 3 to 5, wherein: The carrier lifetime of the second buffer layer is shorter than each of the first buffer layer, the drift layer, and the collector layer.

13. The semiconductor device according to claim 6 or 7, wherein: The carrier lifetime of the second buffer layer is shorter than each of the carrier lifetimes of the first buffer layer, the drift layer, and the cathode layer.

14. The semiconductor device according to claim 8 or 9, wherein: The carrier lifetime of the second buffer layer is shorter than the carrier lifetimes of the first buffer layer, the drift layer, the first cathode layer, and the second cathode layer.

15. A method for manufacturing a semiconductor device, comprising the following steps: Step (a), forming a predetermined device structure on a semiconductor substrate having a first main surface and a second main surface and having a drift layer formed thereon; Step (b), setting the thickness of the drift layer to t N- When the carrier lifetime in the drift layer is τ t =1.5×10 -5 exp(5.4×10 3 t N- ) above, after the step (a), the carrier lifetime is restored; Step (c), after step (b), forming an electrode and a protective film for protecting the electrode on the first main surface of the semiconductor substrate; as well as step (d), after step (c), forming a buffer layer including a first buffer layer and a second buffer layer provided between the first buffer layer and the drift layer on the second main surface side of the drift layer, The step (b) comprises the following steps: Step (b-1), exposing the second main surface of the semiconductor substrate by etching; Step (b-2), forming polycrystalline silicon doped with impurities of the first conductivity type on the second main surface of the semiconductor substrate; as well as Step (b-3), after the step (b-2), performing a first annealing in a nitrogen environment at a first temperature, lowering the temperature to a second temperature lower than the first temperature, and performing a second annealing in a nitrogen environment at the second temperature, thereby forming a first conductivity type high concentration layer and a high crystal defect density layer on the second main surface of the semiconductor substrate, The step (d) comprises the following steps: Step (d-1), removing the high concentration layer and the high crystal defect density layer from the second main surface of the semiconductor substrate by grinding or etching, and adjusting the thickness of the semiconductor substrate; Step (d-2) is a first impurity introduction step, in which, after step (d-1), impurities for the first buffer layer are introduced into the semiconductor substrate from the second main surface; Step (d-3) is a first annealing step, in which the first buffer layer is formed by annealing the semiconductor substrate after step (d-2); Step (d-4) is a second impurity introduction step, which is to introduce impurities for the second buffer layer into the semiconductor substrate from the second main surface after step (d-3); and Step (d-5), namely, a second annealing step, is to form the second buffer layer by annealing the semiconductor substrate after step (d-4).

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The temperature of the second annealing step is greater than or equal to 370°C and less than or equal to 425°C.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The second annealing step lasts for 90 minutes or more.

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