A two-level driver for driving an IGBT

Abstract

The application discloses a two-level driver for driving an IGBT, comprising a fault latching unit, a logic control unit, a signal logic processing unit and a power output unit; wherein the signal logic processing unit is used for realizing interlocking and fault blocking processing of a PWM input signal according to the PWM input signal provided by an external controller and a fault latching signal provided by the logic control unit, and providing a PWM pulse signal obtained after processing to the logic control unit; the logic control unit is used for generating and outputting a corresponding driving control signal according to the PWM pulse signal provided by the signal logic processing unit and the fault latching signal provided by the fault latching unit; and the power output unit is used for performing power conversion on the driving control signal provided by the logic control unit, generating and outputting a corresponding driving signal, so as to control the turn-on, turn-off and 0-level turn-off functions of the IGBT driven by the two-level driver.

Description

Technical Field

[0001] This invention relates to the field of power device technology, and in particular to a two-level driver for driving IGBTs. Background Technology

[0002] With the continuous development of high-speed train technology, the requirements for the safety and stability of train operation are becoming increasingly stringent. As a crucial component of the train's power system, the drive circuit of the converter module in the traction converter plays a vital role. Two-level drive circuits are particularly important. However, two-level circuits still present certain challenges in managing faults in both internal and external IGBTs. Summary of the Invention

[0003] To address the aforementioned problems, this invention provides a two-level driver for driving IGBTs, enabling both IGBT driving and temperature detection functions.

[0004] According to a first aspect, the present invention provides a two-level driver for driving IGBTs, comprising a fault latch unit, a logic control unit, a signal logic processing unit, and a power output unit; wherein:

[0005] The fault latch unit is used to generate and output a fault latch signal that can be locked at a time based on the various fault signals received.

[0006] The logic control unit has its first input terminal connected to the output terminal of the fault latch unit and its first output terminal connected to the first input terminal of the signal logic processing unit, and is used to forward the fault latch signal provided by the fault latch unit to the signal logic processing unit.

[0007] The signal logic processing unit has its second input terminal connected to the output terminal of an external controller, and its first output terminal connected to the second input terminal of the logic control unit. It is used to perform interlocking and fault blocking processing on the PWM input signal based on the PWM input signal provided by the controller and the fault latching signal provided by the logic control unit, and to provide the processed PWM pulse signal to the logic control unit.

[0008] The logic control unit is further configured to generate and output a corresponding drive control signal based on the PWM pulse signal provided by the signal logic processing unit and the fault latch signal provided by the fault latch unit; wherein, the PWM pulse signal determines the high and low levels of the drive control signal, and the fault latch signal controls the soft shutdown of the high and low levels of the drive control signal.

[0009] The power output unit is connected to the second output terminal of the logic control unit and is used to perform power conversion on the drive control signal provided by the logic control unit, generate and output the corresponding drive signal to control the turn-on, turn-off and 0-level turn-off functions of the IGBT driven by the two-level driver.

[0010] According to some embodiments of the present invention, the above-described two-level driver further includes:

[0011] A signal isolation unit is connected between the signal logic processing unit and the logic control unit to isolate the PWM pulse signal from the fault latch signal.

[0012] According to some embodiments of the present invention, the above-described two-level driver further includes:

[0013] The power supply unit is used to convert the external input power into the driving power used by the two-level driver to drive the IGBT.

[0014] A power monitoring unit, which is connected to the power supply unit, is used to monitor the drive power output by the power supply unit and output a power fault signal when the drive power fails to meet the preset power conditions.

[0015] The status monitoring unit is used to acquire the status parameters of the IGBT driven by the two-level driver, and output a status fault signal when the status parameters do not meet the preset status conditions.

[0016] Accordingly, the fault latching unit is connected to the power monitoring unit and the status monitoring unit, and is used to generate and output a fault latching signal that can be locked at a time based on the power fault signal provided by the power monitoring unit and the status fault signal provided by the status monitoring unit.

[0017] According to some embodiments of the present invention, in the above-described two-level driver, the power supply unit includes:

[0018] The EMI filter subunit is used to filter the external input power supply.

[0019] An auxiliary power supply unit, which is connected to the EMI filter unit, is used to convert the filtered external input power into an auxiliary power supply.

[0020] An isolated DC / DC subunit, connected to the auxiliary power supply unit, is used to achieve isolated power conversion with the support of the auxiliary power supply, and outputs the two-level driver to drive the IGBT.

[0021] According to some embodiments of the present invention, in the above-described two-level driver, the state monitoring unit includes:

[0022] Set up a sub-unit to set the threshold value of the state parameter;

[0023] A monitoring subunit is used to acquire the state parameters of the IGBT driven by the two-level driver;

[0024] The comparison subunit, which connects the setting subunit and the monitoring subunit, is used to compare the state parameter with the state parameter threshold and determine whether to output a state fault signal based on the comparison result.

[0025] According to some embodiments of the present invention, in the above-described two-level driver, the power supply fault signal includes an undervoltage fault signal; the state parameters of the IGBT include the gate voltage signal and the gate voltage signal of the IGBT.

[0026] According to some embodiments of the present invention, in the above-described two-level driver:

[0027] The fault latch signal includes the fault latch signal of the inner tube IGBT and the fault latch signal of the outer tube IGBT.

[0028] The PWM input signal includes the inner tube PWM input signal and the outer tube PWM input signal;

[0029] The PWM pulse signal includes the inner tube PWM pulse signal and the outer tube PWM pulse signal.

[0030] According to some embodiments of the present invention, in the above-described two-level driver, the signal logic processing unit includes a first subunit for implementing signal interlocking and a second subunit for implementing signal fault blocking; wherein:

[0031] The first sub-unit includes a first NAND gate and a second NAND gate. The first input terminal of the first NAND gate is used to receive the PWM input signal of the inner tube. The second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate. The first input terminal of the second NAND gate is used to receive the PWM input signal of the outer tube. The second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate.

[0032] The second subunit includes a fault determination circuit and a third NAND gate and a fourth NAND gate. The two input terminals of the fault determination circuit are used to receive the fault latch signal of the inner IGBT and the fault latch signal of the outer IGBT, so as to generate and output a fault blocking signal when the fault latch signal of the inner IGBT and / or the fault latch signal of the outer IGBT are received. The first input terminal of the third NAND gate and the first input terminal of the fourth NAND gate are respectively used to receive the output signals of the first NAND gate and the second NAND gate after inversion processing. The second input terminal of the third NAND gate and the second input terminal of the fourth NAND gate are used to receive the fault blocking signal, so as to output the inner tube PWM pulse signal and the outer tube PWM pulse signal with fault blocking function respectively according to the fault blocking signal.

[0033] According to some embodiments of the present invention, the above-mentioned two-level driver further includes an NTC detection unit, which samples the resistance value of the NTC and performs voltage-to-frequency conversion on the sampled voltage to form a frequency signal that varies with the resistance value, and feeds the signal back to an external controller.

[0034] According to some embodiments of the present invention, in the above-described two-level driver, the second output terminal of the signal logic processing unit is externally connected to the input terminal of the controller, and is used to forward the fault latch signal provided by the logic control unit to the controller.

[0035] Compared with the prior art, one or more embodiments of the above-described solutions of the present invention may have the following advantages or beneficial effects:

[0036] 1) The technical solution of the present invention acquires temperature values ​​in real time through NTC components, thereby conveniently and quickly realizing the monitoring of the internal temperature of the components. It can quickly and accurately read the internal temperature of IGBT, which is convenient for real-time control and reduces module failure caused by overheating.

[0037] 2) The technical solution of the present invention generates fault latching signals that can be locked at a time based on various types of faults, and feeds the fault latching signals back to the external controller, which can be directly used for upper-level intelligent control.

[0038] 3) The technical solution of the present invention realizes intelligent monitoring of IGBT power devices, and can monitor the changes in various voltages of IGBT power devices in real time, thereby enhancing the reliability and stability of intelligent control.

[0039] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0040] The scope of this disclosure can be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. The accompanying drawings are:

[0041] Figure 1 A schematic diagram of the composition of a two-level driver according to an embodiment of the present invention is shown;

[0042] Figure 2 A schematic diagram of each module in the two-level driver shown in the embodiment of the present invention is illustrated;

[0043] Figure 3 It shows Figure 1 The diagram shows the structural composition of the signal logic processing unit in the two-level driver. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the present invention clearer, the implementation method of the present invention will be described in detail below with reference to the accompanying drawings and embodiments, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0045] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0046] like Figure 1 As shown in the figure, this embodiment provides an exemplary two-level driver for driving IGBTs. The driver mainly includes a power supply unit 110, a power monitoring unit 120, a status monitoring unit 130, a fault latching unit 140, a signal logic processing unit 150, a signal isolation unit 160, a logic control unit 170, a power output unit 180, an external interface unit 190, and an NTC detection unit 200. These circuit modules are preferably mounted on a single driver circuit board. Functionally, these circuit modules work together to perform three main functions: voltage conversion, drive control, and fault monitoring. Specifically:

[0047] The power supply unit 110 further includes an EMI filter subunit 111, an auxiliary power supply unit 112, and an isolated DC / DC subunit 113, which are used to pass the external input power through the EMI filter subunit 111 for use inside the drive device board, and then generate a drive voltage for driving the IGBT on the high-voltage side of the IGBT through the auxiliary power supply unit 112 and the isolated DC / DC unit 113.

[0048] The signal logic processing unit 150 completes the conversion of the externally input PWM signal and the fault control of the internal and external transistors. Through the signal isolation unit 160, the logic control unit 170 and the power output unit 180, the PWM input signal is converted into a high-voltage side drive control signal for driving control of the IGBT device.

[0049] The power monitoring unit 120 monitors whether the drive voltage output by the power supply unit 110 is normal, the status monitoring unit 130 monitors and judges whether the working status of the IGBT device driven by the driver is normal, and the fault latching unit 140 realizes the fault protection function based on the fault information fed back by the power monitoring unit 120 and the status monitoring unit 130.

[0050] The NTC detection unit 200 samples the resistance value of the NTC and performs voltage-to-frequency conversion on the sampled voltage to form a frequency signal that varies with the resistance value. This signal is then fed back to an external controller to achieve upper-level intelligent control.

[0051] like Figure 2 As shown below, the circuit connections and functional configurations of each unit are described in detail.

[0052] As mentioned above, in this embodiment, the power supply unit 110 further includes an EMI filtering subunit 111, an auxiliary power supply unit 112, and an isolated DC / DC subunit 113, wherein:

[0053] EMI filter subunit 111 is used to filter the external input power supply;

[0054] Auxiliary power supply unit 112 is connected to the EMI filter unit 111 and is used to convert the filtered external input power into auxiliary power.

[0055] The isolated DC / DC subunit 113 is connected to the auxiliary power supply unit 112 and is used to realize the isolated conversion of power supply with the support of the auxiliary power supply, and output the two-level driver to drive the IGBT drive power supply.

[0056] The power monitoring unit 120 is connected to the power supply unit 110 and is used to monitor the drive power output by the power supply unit 110. When the drive power fails to meet preset power conditions, it outputs a power fault signal. In practical applications, the most common approach is for the power monitoring unit 120 to monitor the drive voltage output by the power supply unit 110 and output an undervoltage fault signal when the drive voltage is lower than a preset voltage threshold.

[0057] The status monitoring unit 130 further includes a setting subunit 131, a monitoring subunit 132, and a comparison subunit 133, wherein:

[0058] Set subunit 131 to set the state parameter threshold;

[0059] Monitoring subunit 132 is used to acquire the state parameters of the IGBT driven by the two-level driver;

[0060] The comparison subunit 133, which is connected to the setting subunit 131 and the monitoring subunit 132, is used to compare the state parameter with the state parameter threshold and determine whether to output a state fault signal based on the comparison result.

[0061] In this embodiment, the state parameters of the IGBT include at least the gate voltage signal and the gate voltage signal. Furthermore, in this embodiment, since both the inner and outer IGBTs are driven and monitored simultaneously, the obtained state parameters include both the inner and outer IGBT state parameters, and the corresponding state fault signals include two fault signals: one for the inner IGBT and one for the outer IGBT.

[0062] The fault latch unit 140 is connected to the power monitoring unit 120 and the status monitoring unit 130, and is used to generate and output a fault latch signal that can be locked at a time according to the power fault signal provided by the power monitoring unit 120 and the status fault signal provided by the status monitoring unit.

[0063] The fault latch unit 140 here is a set of logic digital circuits used to comprehensively process various fault signals (such as undervoltage fault signals and status fault signals) to form and output a fault latch signal that can be timed to be blocked. It should be noted that, in this embodiment, since the inner IGBT and the outer IGBT are driven and monitored simultaneously, the states of the inner IGBT and the outer IGBT are independent of each other, and the probability of failure is also independent of each other. The fault latch signal output by the fault latch unit 140 includes two latch signals, namely, the inner IGBT fault latch signal and the outer IGBT fault latch signal.

[0064] The logic control unit 170 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. On one hand, the first input terminal of the logic control unit 170 is connected to the output terminal of the fault latch unit 140, and the first output terminal of the logic control unit 170 is connected to the first input terminal of the signal logic processing unit 150 through the signal isolation unit 160, for forwarding the fault latch signal provided by the fault latch unit 140 to the signal logic processing unit 150. On the other hand, the second input terminal of the logic control unit 170 is connected to the first output terminal of the signal logic processing unit 150 through the signal isolation unit 160, and the second output terminal of the logic control unit 150 is connected to the input terminal of the power output unit 180, for generating a corresponding drive control signal based on the PWM pulse signal provided by the signal logic processing unit 150 and the fault latch signal provided by the fault latch unit 140, and outputting it to the power output unit 180; wherein the PWM pulse signal determines the high and low levels of the drive control signal, and the fault latch signal controls the soft shutdown of the high and low levels of the drive control signal.

[0065] It should be noted that, for the sake of simplification, Figure 1 The output terminals of the fault latch unit 140, the first and second input terminals and the first and second output terminals of the signal logic processing unit 150, the input and output terminals of the signal isolation unit 160, the first input terminal, the first output terminal, the second input terminal, and the second output terminal of the logic control unit 170, and the input and output terminals of the power output unit 180 are all indicated by a single line. However, these lines are actually used to transmit two signals: the inner tube signal and the outer tube signal. Therefore, the signal isolation unit 160 also includes two subunits, 161 and 162, for isolating the inner tube signal and the outer tube signal, respectively.

[0066] As previously mentioned, the signal logic processing unit 150 also includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. On one hand, the first input terminal of the signal logic processing unit 150 is connected to the first output terminal of the logic control unit 170, the second input terminal of the signal logic processing unit 150 is connected to the output terminal of an external controller (not shown in the figure), and the first output terminal of the signal logic processing unit 150 is connected to the second input terminal of the logic control unit 170. This is used to perform interlocking and fault blocking processing of the PWM input signal based on the PWM input signal provided by the controller and the fault latch signal provided by the logic control unit, and to provide the processed PWM pulse signal to the logic control unit 170. On the other hand, the second output terminal of the signal logic processing unit 150 is externally connected to the controller, and is used to forward the fault latch signal provided by the logic control unit 170 to the controller to provide fault information.

[0067] like Figure 3 As shown, in this embodiment, the signal logic processing unit 150 further includes a first subunit 151 for implementing signal interlocking and a second subunit 152 for implementing signal fault blocking; wherein:

[0068] The first subunit 151 includes a first NAND gate 1 and a second NAND gate 2. The first input terminal of the first NAND gate 1 is used to receive the PWM input signal of the inner tube. The second input terminal of the first NAND gate 1 is connected to the output terminal of the second NAND gate 2. The first input terminal of the second NAND gate 2 is connected to the output terminal of the first NAND gate 1. The second input terminal of the second NAND gate 2 is used to receive the PWM input signal of the outer tube.

[0069] The second subunit 152 includes a fault third NAND gate 3 and a fourth NAND gate 4, as well as a fault determination circuit 5. The two input terminals of the fault determination circuit 5 are used to receive the fault latch signal of the inner tube IGBT and the fault latch signal of the outer tube IGBT, so as to generate and output a fault blocking signal when the fault latch signal of the inner tube IGBT and / or the fault latch signal of the outer tube IGBT are received. The first input terminal of the third NAND gate 3 and the first input terminal of the fourth NAND gate 4 are respectively used to receive the output signals of the first NAND gate 1 and the second NAND gate 2 after inversion processing (e.g., through an inverting circuit, not shown in the figure). The second input terminal of the third NAND gate 3 and the second input terminal of the fourth NAND gate 4 are used to receive the fault blocking signal, so as to output the inner tube PWM pulse signal and the outer tube PWM pulse signal with fault blocking function respectively according to the fault blocking signal.

[0070] In this embodiment, the signal logic processing unit 140 further includes a first filtering circuit 6 and a second filtering circuit 7. The first filtering circuit 6 and the second filtering circuit 7 are respectively disposed between the first NAND gate 1 and the second NAND gate 2 and the controller, and are used to filter the simultaneously input inner tube PWM input signal and the outer tube PWM input signal.

[0071] like Figure 3 As shown, based on the above circuit structure, the working mechanism of the signal logic processing unit 140 is as follows:

[0072] The signal connection logic processing unit performs comprehensive logic processing on the controller's PWM input signal and fault latch signal to achieve fault blocking of the PWM signal, and at the same time outputs the fault latch signal to the controller.

[0073] Therefore, the two PWM pulse signals are input to the filter circuit and, after filtering, transmitted to the first sub-unit. Pulse interlocking is achieved through NAND gates. Specifically, when both PWM1 and PWM2 are 0, the outputs of both NAND gates are 1. When PWM1 changes to 1, NAND gate 1 outputs 0, and NAND gate 2 outputs 1. If PWM2 then changes to 1, the output of NAND gate 2 remains unchanged at 1, thus ensuring that the outputs of both NAND gates are not simultaneously 0. Similarly, when PWM2 changes to 1, NAND gate 2 outputs 0, and NAND gate 1 outputs 1. If PWM1 then changes to 1, the output of NAND gate 1 remains unchanged at 1, thus ensuring that the outputs of both NAND gates are not simultaneously 0. Afterwards, the outputs of NAND gates 1 and 2 are inverted to restore the same logic as the external input signal.

[0074] The fault latch signal is input to the fault determination circuit, which outputs a fault blocking signal. When there is no fault, the fault blocking signal is high; when there is a fault, the fault blocking signal is low. The fault blocking signal, along with the output signals of the first / second NAND gates, is then simultaneously input to the third / fourth NAND gates. At this time, when there is no fault and a pulse input is present, the output of the third / fourth NAND gates is 0; when there is no pulse input, the output of the third / fourth NAND gates is 1; and when there is a fault, regardless of whether there is a pulse input, the output of the third / fourth NAND gates is always 1, thus achieving PWM signal interlocking and completing fault blocking.

[0075] Thus, the fault blocking of the PWM signal in the technical solution of this invention is achieved through the above working mechanism.

[0076] As previously described, the logic control unit 170 generates a corresponding drive control signal based on the fault-blocked PWM pulse signal provided by the signal logic processing unit 150 and the fault latch signal provided by the fault latch unit 140, and outputs it to the power output unit 180. The second output terminal of the logic control unit 170 is used to perform power conversion on the drive control signal provided by the logic control unit 170, generate and output a corresponding drive signal to control the IGBT driven by the two-level driver. It should be noted that, in this embodiment, since both the inner and outer IGBTs are driven, the drive control signal and the drive signal each include two drive signals, namely, the drive control signal for the inner IGBT and the drive control signal for the outer IGBT, and the drive signal for the inner IGBT and the drive signal for the outer IGBT.

[0077] Furthermore, the aforementioned two-level driver also includes an external interface 190. This external interface is located between the power monitoring unit 120, the status monitoring unit 130, and the power output unit 180 and the IGBT power device driven and controlled by the two-level driver, and is used to isolate and transmit drive voltage, status parameters, and drive control signals. Since this is prior art, it will not be described in detail here.

[0078] Furthermore, the NTC detection unit 200 includes an NTC voltage divider circuit 201 and a voltage-to-frequency conversion circuit 202. It samples the resistance value of the NTC and performs voltage-to-frequency conversion on the sampled voltage to generate a frequency signal that varies with the resistance value. This signal is then output to an external controller for intelligent monitoring via the third subunit 163 of the signal isolation unit 160. The third subunit 163 of the signal isolation unit 160 is used for isolating the NTC temperature signal.

[0079] It should be understood that the apparatuses and methods disclosed in the several embodiments provided in this application can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0080] It should be noted that the method of this embodiment can be executed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this embodiment, and the multiple devices will interact with each other to complete the method described.

[0081] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0082] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0083] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed herein; however, the scope of protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A two-level driver for driving an IGBT, characterized by, The fault latching unit, the logic control unit, the signal logic processing unit and the power output unit are included. The fault latching unit is configured to generate and output a fault latching signal capable of being timed and locked according to received various fault signals. The logic control unit is configured to forward the fault latching signal provided by the fault latching unit to the signal logic processing unit. The signal logic processing unit is configured to realize interlocking and fault locking processing of the PWM input signal according to the PWM input signal provided by the controller and the fault latching signal provided by the logic control unit, and provide a PWM pulse signal obtained after processing to the logic control unit. The logic control unit is further configured to generate and output a corresponding drive control signal according to the PWM pulse signal provided by the signal logic processing unit and the fault latching signal provided by the fault latching unit, wherein the PWM pulse signal determines the high and low levels of the drive control signal, and the fault latching signal controls the high and low levels of the drive control signal. The power output unit is configured to perform power conversion on the drive control signal provided by the logic control unit, generate and output a corresponding drive signal to control the IGBT driven by the two-level driver. The signal logic processing unit includes a first sub-unit for realizing signal interlocking and a second sub-unit for realizing signal fault locking. The first sub-unit includes a first NAND gate and a second NAND gate, a first input end of the first NAND gate is configured to receive an inner tube PWM input signal included in a PWM signal, a second input end of the first NAND gate is connected to an output end of the second NAND gate, a first input end of the second NAND gate is configured to receive an outer tube PWM input signal included in the PWM signal, and a second input end of the second NAND gate is configured to be connected to an output end of the first NAND gate. The second sub-unit includes a fault judgment circuit, a third NAND gate and a fourth NAND gate, two input ends of the fault judgment circuit are configured to receive an inner tube IGBT fault latching signal and an outer tube IGBT fault latching signal included in the fault latching signal, to generate and output a fault locking signal when the fault latching signal is received, a first input end of the third NAND gate and a first input end of the fourth NAND gate are respectively configured to receive output signals of the first NAND gate and the second NAND gate after being processed by an inverter, and a second input end of the third NAND gate and a second input end of the fourth NAND gate are configured to receive the fault locking signal, to output the PWM pulse signal with the fault locking function according to the fault locking signal.

2. The two-level driver for driving an IGBT according to claim 1, wherein Further comprising: A signal isolation unit connected between the signal logic processing unit and the logic control unit, configured to realize isolation of the PWM pulse signal and the fault latching signal.

3. The two-level driver for driving an IGBT according to claim 1, wherein Further comprising: A power supply unit configured to convert an external input power supply into a drive power supply used by the two-level driver to drive the IGBT. A power supply monitoring unit is connected to the power supply unit, for monitoring the driving power output by the power supply unit, and outputting a power failure signal when the driving power does not meet a preset power supply condition; A state monitoring unit is configured to acquire a state parameter of the IGBT driven by the two-level driver, and output a state failure signal when the state parameter does not meet a preset state condition; Correspondingly, the fault latching unit is connected to the power supply monitoring unit and the state monitoring unit, for generating and outputting a fault latching signal that can be timed to be locked according to the power failure signal provided by the power supply monitoring unit and the state failure signal provided by the state monitoring unit.

4. The two-level driver for driving an IGBT according to claim 3, wherein The power supply unit comprises: An EMI filtering subunit, configured to perform filtering processing on an external input power supply; An auxiliary power supply subunit connected to the EMI filtering subunit, configured to convert the filtered external input power supply into an auxiliary power supply; An isolated DC / DC subunit connected to the auxiliary power supply subunit, configured to perform isolated conversion of the power supply under the support of the auxiliary power supply, and output a driving power for driving the IGBT by the two-level driver.

5. The two-level driver for driving an IGBT according to claim 3, wherein The state monitoring unit comprises: A setting subunit, configured to set a state parameter threshold value; A monitoring subunit, configured to acquire a state parameter of the IGBT driven by the two-level driver; A comparison subunit connected to the setting subunit and the monitoring subunit, configured to compare the state parameter with the state parameter threshold value, and determine whether to output a state failure signal according to a comparison result.

6. The two-level driver for driving an IGBT according to any one of claims 3 to 5, characterized in that: The power failure signal comprises an under-voltage failure signal; The state parameter of the IGBT comprises a gate voltage signal and a gate voltage signal of the IGBT.

7. The two-level driver for driving an IGBT according to claim 1, wherein Further comprising an NTC detection unit, which samples the resistance value of the NTC and pressure frequency converts the sampling voltage to form a frequency signal that changes with the resistance value, and feeds back the signal to an external controller.

8. The two-level driver for driving an IGBT according to claim 1, wherein A second output end of the signal logic processing unit is connected to an input end of the controller, for forwarding the fault latching signal provided by the logic control unit to the controller.

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