A drive circuit

Abstract

The present disclosure relates to a driving circuit, comprising: a current mirror; no less than two switches for controlling the amount of current accessing the driving circuit; a high-voltage PMOS connected with the current mirror; a first high-voltage NMOS and a second high-voltage NMOS connected in series; a first NMOS and a second NMOS for protecting the first high-voltage NMOS and the second high-voltage NMOS within a preset range of voltage; a third NMOS and a fourth NMOS connected in series; a third high-voltage NMOS; the gate of the first high-voltage NMOS and the gate of the second high-voltage NMOS are connected with a reference voltage; the first high-voltage NMOS is connected with the current mirror; the gate of the third NMOS and the gate of the fourth NMOS are connected; the source of the third high-voltage NMOS accesses the current of the driving circuit; the drain of the third high-voltage NMOS is connected with the drain of the second high-voltage NMOS and the source of the fourth NMOS respectively; the gate of the third high-voltage NMOS accesses a power voltage.

Description

Technical Field

[0001] This disclosure relates to the field of circuit technology, and more specifically, to a driving circuit. Background Technology

[0002] High-voltage clamping drive circuits are a widely used circuit structure in basic automotive electronic systems. Typically, clamping drive circuits use an open-loop design, employing Zener diodes or cascaded diodes for clamping communication. This open-loop structure often results in a fixed output clamping voltage, making it unsuitable for various output clamping voltage requirements. Summary of the Invention

[0003] To address the technical problem that existing high-voltage clamping drive circuits cannot meet user needs.

[0004] To achieve the above technical objectives, this disclosure provides a driving circuit, including: a current mirror;

[0005] No fewer than two switches are used to control the amount of current connected to the drive circuit;

[0006] A high-voltage PMOS transistor connected to the first current mirror;

[0007] A first high-voltage NMOS transistor and a second high-voltage NMOS transistor connected in series;

[0008] The first and second high-voltage NMOS transistors are used to protect the voltage of the first and second high-voltage NMOS transistors from being within a preset range.

[0009] The third and fourth NMOS transistors are connected in series;

[0010] Third high-voltage NMOS transistor;

[0011] The gates of the first high-voltage NMOS transistor and the second high-voltage NMOS transistor are connected to a reference voltage;

[0012] The first high-voltage NMOS transistor is connected to the current mirror;

[0013] The gates of the third NMOS transistor and the fourth NMOS transistor are connected;

[0014] The source of the third high-voltage NMOS transistor is connected to the current of the driving circuit;

[0015] The drain of the third high-voltage NMOS transistor is connected to the drain of the second high-voltage NMOS transistor and the source of the fourth NMOS transistor, respectively.

[0016] The gate of the third high-voltage NMOS transistor is connected to the power supply voltage.

[0017] Furthermore, the current mirror is composed of a first PMOS transistor and a second PMOS transistor;

[0018] The source of the first PMOS transistor and the source of the second PMOS transistor are connected together, and both are connected to the high voltage power supply voltage.

[0019] The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor;

[0020] The drain of the first PMOS transistor is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor.

[0021] Furthermore, the drain of the first high-voltage NMOS transistor is connected to the drain of the first PMOS transistor;

[0022] The drain of the first high-voltage NMOS transistor is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor.

[0023] Furthermore, the source of the high-voltage PMOS transistor and the drain of the second PMOS transistor are connected;

[0024] The drain of the high-voltage PMOS transistor is connected to the drain and gate of the third NMOS transistor.

[0025] Furthermore, the area of ​​the second PMOS transistor is X times that of the first PMOS transistor, where X is an integer greater than or equal to 2.

[0026] Furthermore, the first NMOS transistor and the second NMOS transistor are cascaded, and the drain of the first NMOS transistor is connected to the gate of the first high-voltage NMOS transistor.

[0027] The source of the second NMOS transistor is connected to the source of the second high-voltage NMOS transistor.

[0028] Furthermore, the output clamping voltage of the drive circuit is equal to

[0029] Vref-VGS_MN1-VDS_MN2+VGS_MN5+VDS_MN6;

[0030] Where VGS_MN1 is the gate-source voltage of the first high-voltage NMOS transistor; VDS_MN2 is the drain-source voltage of the second high-voltage NMOS transistor; VGS_MN5 is the gate-source voltage of the third NMOS transistor; VDS_MN6 is the drain-source voltage of the fourth NMOS transistor; and Vref is the reference voltage.

[0031] Furthermore, the output current of the drive circuit is equal to (I1 + I2 + ... I n)*X, where n is a positive integer, and n equals the number of currents connected to the drive circuit, I1, I2...I n It is the current connected to the drive circuit.

[0032] The beneficial effects of this disclosure are as follows:

[0033] This disclosure proposes an output clamping drive structure suitable for high-voltage structures, which adopts a closed-loop approach to achieve freely configurable output voltage. Attached Figure Description

[0034] Figure 1 A schematic diagram of the drive circuit of Embodiment 1 of this disclosure is shown. Detailed Implementation

[0035] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0036] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged and may have been omitted for clarity. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0037] Example 1:

[0038] like Figure 1 As shown:

[0039] This disclosure provides a driving circuit, including: a current mirror;

[0040] No fewer than two switches are used to control the amount of current connected to the drive circuit;

[0041] MP3, a high-voltage PMOS transistor connected to the first current mirror;

[0042] The first high-voltage NMOS transistor MN1 and the second high-voltage NMOS transistor MN2 are connected in series.

[0043] The first NMOS transistor MN3 and the second NMOS transistor MN4 are used to protect the voltage of the first high-voltage NMOS transistor MN1 and the second high-voltage NMOS transistor MN2 from being within a preset range.

[0044] The third NMOS transistor MN5 and the fourth NMOS transistor MN6 are connected in series;

[0045] The third high-voltage NMOS transistor MN7;

[0046] The gates of the first high-voltage NMOS transistor MN1 and the second high-voltage NMOS transistor MN2 are connected to the reference voltage Vref;

[0047] The first high-voltage NMOS transistor MN1 is connected to the current mirror;

[0048] The gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected;

[0049] The source of the third high-voltage NMOS transistor MN7 is connected to the current of the driving circuit.

[0050] The drain of the third high-voltage NMOS transistor MN7 is connected to the drain of the second high-voltage NMOS transistor MN2 and the source of the fourth NMOS transistor MN6, respectively.

[0051] The gate of the third high-voltage NMOS transistor MN7 is connected to the power supply voltage VCC.

[0052] Furthermore, the current mirror is composed of a first PMOS transistor MP1 and a second PMOS transistor MP2;

[0053] The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected together, and both are connected to the high voltage power supply voltage.

[0054] The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2;

[0055] The drain of the first PMOS transistor MP1 is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2.

[0056] Furthermore, the drain of the first high-voltage NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1;

[0057] The drain of the first high-voltage NMOS transistor MN1 is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2.

[0058] Furthermore, the source of the high-voltage PMOS transistor MP3 is connected to the drain of the second PMOS transistor MP2;

[0059] The drain of the high-voltage PMOS transistor MP3 is connected to the drain and gate of the third NMOS transistor MN5.

[0060] Furthermore, the area of ​​the second PMOS transistor MP2 is X times that of the first PMOS transistor MP1, where X is an integer greater than or equal to 2.

[0061] Furthermore, the first NMOS transistor MN3 and the second NMOS transistor MN4 are cascaded, and the drain of the first NMOS transistor MN3 is connected to the gate of the first high-voltage NMOS transistor MN1.

[0062] The source of the second NMOS transistor MN4 is connected to the source of the second high-voltage NMOS transistor MN2.

[0063] Furthermore, the output clamping voltage of the drive circuit is equal to

[0064] Vref-VGS_MN1-VDS_MN2+VGS_MN5+VDS_MN6;

[0065] Where VGS_MN1 is the gate-source voltage of the first high-voltage NMOS transistor MN1; VDS_MN2 is the drain-source voltage of the second high-voltage NMOS transistor MN2; VGS_MN5 is the gate-source voltage of the third NMOS transistor MN5; VDS_MN6 is the drain-source voltage of the fourth NMOS transistor MN6; and Vref is the reference voltage.

[0066] like Figure 1 As shown, VB is the high-voltage power supply voltage. The first PMOS transistor MP1 and the second PMOS transistor MP2 form a current mirror. The first PMOS transistor MP1 is connected in a diode configuration. The area of ​​the second PMOS transistor MP2 is X times the area of ​​the first PMOS transistor MP1 (X is any number). The gate voltage of the high-voltage PMOS transistor MP3 is equal to VB - VL, where VL is the operating voltage range of the gate-source voltage of the high-voltage PMOS transistor MP3. VB - VL can bias the high-voltage PMOS transistor MP3 to be turned on in a suitable state. The first high-voltage NMOS transistor MN1 and the second high-voltage NMOS transistor MN2 are high-voltage transistors. The first high-voltage NMOS transistor MN1 and the second high-voltage NMOS transistor MN2 form a back-to-back series structure. The first NMOS transistor MN3 and the second NMOS transistor MN4 are cascaded in a diode configuration to clamp the voltage, thereby protecting the gate voltages of the first high-voltage NMOS transistor MN1 and the second high-voltage NMOS transistor MN2 within a reasonable range. The areas of the first high-voltage NMOS transistor MN1 and the second high-voltage NMOS transistor MN2 are determined according to the actual situation. The third NMOS transistor MN5 and the fourth NMOS transistor MN6 are connected in series with their gates connected together. The third NMOS transistor MN5 is connected in a diode configuration. The gate of the third high-voltage NMOS transistor MN7 is controlled by a low power supply voltage VCC to ensure proper turn-on of the third high-voltage NMOS transistor MN7.

[0067] Switches S1, S2...Sn (n is any number and can be adjusted according to specific circumstances) Used to control currents I1, I2...I n Access.

[0068] Therefore, the drive current of the output OUT is equal to:

[0069] (I1+I2+...I n )X;

[0070] The clamping voltage of the output voltage is equal to:

[0071] Vref-VGS_MN1-VDS_MN2+VGS_MN5+VDS_MN6

[0072] Where VGS_MN1 is the gate-source voltage of MN1; VDS_MN2 is the drain-source voltage of MN2; VGS_MN5 is the gate-source voltage of MN5; and VDS_MN6 is the drain-source voltage of MN6.

[0073] This disclosure provides the embodiments described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A driving circuit, characterized in that, include: Current mirror; At least two switches are used to control the amount of current connected to the drive circuit; A high-voltage PMOS transistor connected to the current mirror; A first high-voltage NMOS transistor and a second high-voltage NMOS transistor connected in series; The first and second high-voltage NMOS transistors are used to protect the voltage of the first and second high-voltage NMOS transistors from being within a preset range. The third and fourth NMOS transistors are connected in series; The third high-voltage NMOS transistor; among them... The gates of the first high-voltage NMOS transistor and the second high-voltage NMOS transistor are connected to a reference voltage; The first high-voltage NMOS transistor is connected to the current mirror; The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor; The source of the third high-voltage NMOS transistor is connected to the current of the driving circuit; The drain of the third high-voltage NMOS transistor is connected to the drain of the second high-voltage NMOS transistor and the source of the fourth NMOS transistor, respectively. The gate of the third high-voltage NMOS transistor is connected to the power supply voltage; The drain of the high-voltage PMOS transistor is connected to the drain and gate of the third NMOS transistor.

2. The driving circuit according to claim 1, characterized in that, The current mirror is composed of a first PMOS transistor and a second PMOS transistor; The source of the first PMOS transistor and the source of the second PMOS transistor are connected together, and both are connected to the high voltage power supply voltage. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor; The drain of the first PMOS transistor is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor.

3. The driving circuit according to claim 2, characterized in that, The drain of the first high-voltage NMOS transistor is connected to the drain of the first PMOS transistor; The drain of the first high-voltage NMOS transistor is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor.

4. The driving circuit according to claim 2, characterized in that, The source of the high-voltage PMOS transistor is connected to the drain of the second PMOS transistor.

5. The driving circuit according to claim 2, characterized in that, The area of ​​the second PMOS transistor is X times that of the first PMOS transistor, where X is an integer greater than or equal to 2.

6. The driving circuit according to claim 1, characterized in that, The first NMOS transistor and the second NMOS transistor are cascaded together, and the drain of the first NMOS transistor is connected to the gate of the first high-voltage NMOS transistor. The source of the second NMOS transistor is connected to the source of the second high-voltage NMOS transistor.

7. The driving circuit according to any one of claims 1 to 6, characterized in that, The output clamping voltage of the drive circuit is equal to Vref - VGS_MN1 - VDS_MN2 + VGS_MN5 + VDS_MN6; Where VGS_MN1 is the gate-source voltage of the first high-voltage NMOS transistor; VDS_MN2 is the drain-source voltage of the second high-voltage NMOS transistor; VGS_MN5 is the gate-source voltage of the third NMOS transistor; VDS_MN6 is the drain-source voltage of the fourth NMOS transistor; and Vref is the reference voltage.

8. The driving circuit according to claim 5, characterized in that, The output current of the drive circuit is equal to (I1+I2+...In)*X, where n is a positive integer, n equals the number of currents connected to the drive circuit, and I1, I2...In are the currents connected to the drive circuit.

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