Analog equalizer

Abstract

The present disclosure provides an analog equalizer, which includes a first input module, a second input module, and an output module. The first input module includes a first input unit and a first output unit, the first input unit being configured to receive a first external voltage signal and the first output unit being configured to provide a first current signal; the second input module includes a second input unit and a second output unit, the second input unit being configured to receive a second external voltage signal and the second output unit being configured to provide a second current signal; and the output module is connected to the first input module and the second input module and is configured to convert the first current signal and / or the second current signal into a voltage signal and output the voltage signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an analog equalizer. Background Art

[0002] Compared with directly using analog signals to transmit signals, digital code transmission has the advantages of strong anti-interference ability, easy storage and processing, and easy integration. This makes this technology widely used in communication systems. However, as data transmission rates continue to increase, the impact of non-ideal effects of transmission lines becomes more and more serious, resulting in an increase in the bit error rate of the received signal.

[0003] The current approach typically adopted for normal-temperature circuits is to add an analog equalizer at the data receiving end to compensate for attenuation at high frequencies in the transmission line, ultimately flattening the overall frequency response and achieving this compensation. However, in extremely low-temperature environments, most circuits fail to operate, or operate under altered operating conditions. For example, current analog equalizer inputs require a common-mode voltage, but at low temperatures, the MOS transistor threshold voltage rises significantly, reducing the common-mode range of the input circuit. Furthermore, at low temperatures, the common-mode voltage offset of the previous stage output is unpredictable. Summary of the Invention

[0004] (1) Technical issues to be resolved

[0005] In response to the existing technical problems, the present disclosure provides an analog equalizer for at least partially solving the above technical problems.

[0006] (2) Technical solution

[0007] To achieve the above objectives, the present disclosure provides an analog equalizer. The analog equalizer includes a first input module S01, a second input module S02, and an output module S03.

[0008] The first input module S01 includes a first input unit and a first output unit, the first input unit is used to receive a first external voltage signal, and the first output unit is used to provide a first current signal; the second input module S02 includes a second input unit and a second output unit, the second input unit is used to receive a second external voltage signal, and the second output unit is used to provide a second current signal; the output module S03 is connected to the first input module S01 and the second input module S02, and is used to convert the first current signal and / or the second current signal into a voltage signal and output it.

[0009] In some embodiments of the present disclosure, the first input unit includes a first INN input terminal INN1 and a first INP input terminal INP1; the second input unit includes a second INN input terminal INN2 and a second INP input terminal INP2.

[0010] In some embodiments of the present disclosure, the output module S03 includes: a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first cascade PMOS transistor MP7, a second cascade PMOS transistor MP8, a first cascade NMOS transistor MN7, a second cascade NMOS transistor MN8, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6.

[0011] The fifth PMOS transistor MP5 has a source connected to the first external power supply; the sixth PMOS transistor MP6 has a source connected to the first external power supply, and the gate of the sixth PMOS transistor MP6 is connected to the gate of the fifth PMOS transistor MP5; the first cascade PMOS transistor MP7 has a source connected to the drain of the fifth PMOS transistor MP5; the second cascade PMOS transistor MP8 has a source connected to the drain of the sixth PMOS transistor MP6, and the gate of the second cascade PMOS transistor MP8 is connected to the gate of the first cascade PMOS transistor MP7; the first cascade NMOS transistor MN7 has a drain connected to the first cascade PMOS transistor MP8. The drain of the first cascade NMOS transistor MN7 is connected to the drain of the second cascade PMOS transistor MP8; the drain of the second cascade NMOS transistor MN8 is connected to the drain of the second cascade PMOS transistor MP8, and the gate of the second cascade NMOS transistor MN8 is connected to the first cascade NMOS transistor MN7; the drain of the fifth NMOS transistor MN5 is connected to the source of the first cascade NMOS transistor MN7, and the source of the fifth NMOS transistor MN5 is grounded; the drain of the sixth NMOS transistor MN6 is connected to the source of the second cascade NMOS transistor MN8, the gate of the sixth NMOS transistor MN6 is connected to the gate of the fifth NMOS transistor MN5, and the source of the sixth NMOS transistor MN6 is grounded.

[0012] In some embodiments of the present disclosure, the first input module S01 further includes: a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first NMOS transistor MN1, a second NMOS transistor MN2, a variable resistor R S and variable capacitor C S .

[0013] A third NMOS transistor MN3 has a gate connected to the first INN input terminal INN1, and a drain connected to the source of the first cascade PMOS transistor MP7; a fourth NMOS transistor MN4 has a gate connected to the first INP input terminal INP1, and a drain connected to the source of the second cascade PMOS transistor MP8; a first NMOS transistor MN1 has a source connected to ground, and a drain connected to the source of the third NMOS transistor MN3; a second NMOS transistor MN2 has a source connected to ground, and a drain connected to the source of the fourth NMOS transistor MN4, and a gate connected to the gate of the first NMOS transistor MN1; a variable resistor R S, one end is connected to the source of the third NMOS tube MN3, and the other end is connected to the source of the fourth NMOS tube MN4; a variable capacitor C S , one end is connected to the source of the third NMOS tube MN3, and the other end is connected to the source of the fourth NMOS tube MN4; the variable resistor R S and the variable capacitor C S Used to adjust the first current signal provided to the output module S03.

[0014] In some embodiments of the present disclosure, the second input module S02 further includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first PMOS transistor MP1, a second PMOS transistor MP2, a variable resistor R S and variable capacitor C S .

[0015] The third PMOS transistor MP3 has a gate connected to the second INP input terminal INP2, and a drain of the third PMOS transistor MP3 is connected to the source of the second cascade NMOS transistor MN8; the fourth PMOS transistor MP4 has a gate connected to the second INN input terminal INN2, and a drain of the fourth NMOS transistor MP4 is connected to the source of the first cascade NMOS transistor MN7; the first PMOS transistor MP1 has a source connected to the second external power supply, and a drain connected to the source of the third PMOS transistor MP3; the second PMOS transistor MP2 has a source connected to the second external power supply, and a drain connected to the source of the fourth PMOS transistor MP4, and the gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1; the variable resistor R S , one end is connected to the source of the third PMOS tube MP3, and the other end is connected to the source of the fourth PMOS tube MP4; a variable capacitor C S , one end is connected to the source of the third PMOS tube MP3, and the other end is connected to the source of the fourth PMOS tube MP4; the variable resistor R S and the variable capacitor C S Used to adjust the second current signal provided to the output module S03.

[0016] In some embodiments of the present disclosure, the output module S03 further includes: a load capacitor C L , two equal load resistors R L , P output terminal and N output terminal.

[0017] Load capacitance C L , one end is connected to the drain of the first cascade NMOS transistor MN7, and the other end is connected to the drain of the second cascade NMOS transistor MN8; two equal load resistors R L , the two equal load resistors RL One end of the series connection is connected to the drain of the first cascade NMOS transistor MN7, and the other end is connected to the drain of the second cascade NMOS transistor MN8; the P output end is connected to the drain of the first cascade NMOS transistor MN7; the N output end is connected to the drain of the second cascade NMOS transistor MN8.

[0018] In some embodiments of the present disclosure, the output module S03 further includes a common-mode feedback unit S031, which includes an operational amplifier U1 and a compensation capacitor C C .

[0019] The positive input terminal V+ of the operational amplifier U1 is connected to the two equal load resistors R L At the middle node between the operational amplifier U1, the negative input terminal V- is connected to the external reference voltage; the compensation capacitor C C , one end is connected to the output terminal OUT of the operational amplifier U1, and the other end is grounded; the common-mode feedback unit S031 is used to determine the common-mode voltage output by the analog equalizer.

[0020] In some embodiments of the present disclosure, wherein: the first common mode voltage V of the first external voltage signal inn，cm The range is: V gsn3，4 +V gsn1，2 -V thn1，2 <V inn，cm <V b2 +|V gsp7，8 |+V thn3，4 , wherein the V gsn3，4 is the gate-source voltage of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, and the V gsn1，2 is the gate-source voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2, the V thn1，2 is the threshold voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2, the V b2 is the gate bias voltage of the first cascade PMOS transistor MP7 and the second cascade PMOS transistor MP8, the V gsp7，8 is the gate-source voltage of the first cascade PMOS tube MP7 and the second cascade PMOS tube MP8, the V thn3，4 is the threshold voltage of the third NMOS transistor MN3 and the fourth NMOS transistor MN4.

[0021] In some embodiments of the present disclosure, the second common mode voltage V inp，cm The range is: V b1 -V gsn7，8 +V thp3，4 <V inp，cm<VDD-|V gsp1，2 |+|V thp1，2 |-|V gsp3，4 |, wherein the V b1 is the gate bias voltage of the first cascade NMOS transistor MN7 and the second cascade NMOS transistor MN8, the V gsn7，8 is the gate-source voltage of the first cascade NMOS transistor MN7 and the second cascade NMOS transistor MN8, the V thp3，4 is the threshold voltage of the third PMOS transistor MP3 and the fourth PMOS transistor MP4, and the V gsp1，2 is the gate-source voltage of the first PMOS transistor MP1 and the second PMOS transistor MP2, the V thp1，2 is the threshold voltage of the first PMOS transistor MP1 and the second PMOS transistor MP2, the V gsp3，4 is the gate-source voltage of the third PMOS transistor MP3 and the fourth PMOS transistor MP4; the common-mode input range V in，cm =0≤V in，cm <VDD.

[0022] In some embodiments of the present disclosure, the voltage signal output by the analog equalizer includes two extremes. and A zero point where g m is the transconductance of the input pair transistors: the third NMOS transistor MN3, the fourth NMOS transistor MN4, the third PMOS transistor MP3, and the fourth PMOS transistor MP4.

[0023] (3) Beneficial effects

[0024] Based on the above technical solution, the analog equalizer disclosed in the present invention has at least one or part of the following beneficial effects compared to the prior art:

[0025] (1) The present disclosure can achieve rail-to-rail common-mode input, solving the problem that the threshold voltage increases significantly at extremely low temperatures, causing the input common-mode range of a general analog equalizer to become narrower and thus making it unable to work normally; and also solving the problem that the common-mode voltage cannot be determined at extremely low temperatures.

[0026] (2) This disclosure addresses the situation where general circuits cannot operate normally in extremely low temperature environments. The process used in the analog equalizer has passed testing, characterization, and modeling at extremely low temperatures, allowing the analog equalizer to operate normally in extremely low temperature environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of the composition of an analog equalizer according to an embodiment of the present disclosure;

[0028] Figure 2 is a schematic diagram of an operational amplifier according to an embodiment of the present disclosure;

[0029] Figure 3 : is a frequency response curve of the input common mode voltage from 0 to VDD according to an embodiment of the present disclosure;

[0030] Figure 4 is an eye diagram of a signal after passing through a channel according to an embodiment of the present disclosure;

[0031] Figure 5 1 is an eye diagram after passing through the analog equalizer according to an embodiment of the present disclosure.

[0032] [Description of Reference Numerals]

[0033] S01: First input module

[0034] S02: Second input module

[0035] S03: Output module

[0036] INN1: First INN input terminal

[0037] INN2: Second INN input terminal

[0038] INP1: first INP input terminal

[0039] INP2: Second INP input terminal

[0040] MN1: first NMOS tube

[0041] MN2: Second NMOS tube

[0042] MN3: The third NMOS tube

[0043] MN4: the fourth NMOS tube

[0044] MN5: fifth NMOS tube

[0045] MN6: Sixth NMOS tube

[0046] MN7: First cascade NMOS tube

[0047] MN8: Second cascade NMOS tube

[0048] MP1: first PMOS tube

[0049] MP2: second PMOS tube

[0050] MP3: The third PMOS tube

[0051] MP4: the fourth PMOS tube

[0052] MP5: fifth PMOS tube

[0053] MP6: sixth PMOS tube

[0054] MP7: First cascade PMOS tube

[0055] MP8: Second cascade PMOS tube

[0056] R S :Variable resistor

[0057] C S :Variable capacitor

[0058] C L : Load capacitance

[0059] R L : Load resistance

[0060] S031: Common mode feedback unit

[0061] U1: Operational amplifier

[0062] CC: compensation capacitor

[0063] V+: positive input of the operational amplifier

[0064] V-: negative input of the operational amplifier

[0065] OUT: output of the operational amplifier

[0066] MP11: First load PMOS tube

[0067] MP21: Second load PMOS tube

[0068] MN21: First input NMOS tube

[0069] MN31: Second input NMOS tube

[0070] MN11: NMOS tail current tube DETAILED DESCRIPTION

[0071] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0072] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0073] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0074] Certain embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings, some, but not all, of which embodiments are shown. Indeed, the various embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.

[0075] The present disclosure provides an analog equalizer, Figure 1 The figure schematically shows the composition of the analog equalizer according to the embodiment of the present disclosure.

[0076] like Figure 1 As shown, the analog equalizer includes a first input module S01, a second input module S02 and an output module S03.

[0077] The first input module S01 includes a first input unit and a first output unit, the first input unit is connected to the first external voltage signal, and the first output unit is used to provide a first current signal;

[0078] The second input module S02 includes a second input unit and a second output unit, the second input unit is connected to the second external voltage signal, and the second output unit is used to provide a second current signal;

[0079] The output module S03 is connected to the first input module S01 and the second input module S02 and is configured to convert the first current signal and / or the second current signal into a common mode voltage.

[0080] The first input unit includes a first INN input terminal INN1 and a first INP input terminal INP1;

[0081] The second input unit includes a second INN input terminal INN2 and a second INP input terminal INP2.

[0082] According to an embodiment of the present disclosure, after the first INN input terminal INN1 and the second INN input terminal INN2 are connected, the INN input terminal of the analog equalizer is formed, and after the first INP input terminal INP1 and the second INP input terminal INP2 are connected, the INP input terminal of the analog equalizer is formed, and the external voltage signal is connected to the INN input terminal and the INP input terminal.

[0083] The first input module S01 and the second input module S02 receive an external voltage signal. When the common-mode voltage of the received external voltage signal is within a first common-mode voltage range, the first input module S01 is in an operating state; when the common-mode voltage of the received external voltage signal is within a second common-mode voltage range, the second input module S02 is in an operating state; when the common-mode voltage of the received external voltage signal is within both the first common-mode voltage range and the second common-mode voltage range, the first input module S01 and the second input module S02 are in an operating state at the same time; the first input module S01 and the second input module S02 respectively convert the received voltage signals into current signals and transmit them to the output module S03; the output module S03 converts the current signal into a voltage signal for output.

[0084] According to the embodiment of the present disclosure, the first input module S01 further includes: a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first NMOS transistor MN1, a second NMOS transistor MN2, a variable resistor R S and variable capacitor C S .

[0085] The gate of the third NMOS transistor MN3 is connected to the first INN input terminal INN1, and the drain of the third NMOS transistor MN3 is connected to the output module S03;

[0086] The gate of the fourth NMOS transistor MN4 is connected to the first INP input terminal INP1, and the drain of the fourth NMOS transistor MN4 is connected to the output module S03;

[0087] The source of the first NMOS transistor MN1 is grounded, and the drain is connected to the source of the third NMOS transistor MN3;

[0088] The source of the second NMOS transistor MN2 is grounded, the drain is connected to the source of the fourth NMOS transistor MN4, and the gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1;

[0089] Variable resistor R S One end is connected to the source of the third NMOS transistor MN3, and the other end is connected to the source of the fourth NMOS transistor MN4;

[0090] Variable capacitor C S One end is connected to the source of the third NMOS transistor MN3, and the other end is connected to the source of the fourth NMOS transistor MN4;

[0091] Variable resistor R S and variable capacitor C S Used to adjust the first current signal provided to the output module S03.

[0092] The third NMOS transistor MN3 and the fourth NMOS transistor MN4 receive voltage signals from the outside through their gates, convert the voltage signals into current signals and output them to the output module S03 through their drains. S and variable capacitor C S The size of the input stage frequency domain zero and pole distribution is adjusted, and the current signal provided to the output module S03 is adjusted. The first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to the bias voltage Vs1. The first NMOS transistor MN1 and the second NMOS transistor MN2 provide current bias for the third NMOS transistor MN3 and the fourth NMOS transistor MN4. The variable resistor R S and variable capacitor C S This can be achieved by using a MOS tube operating in the linear region, and by adding different bias voltages to the gate of the MOS tube to adjust the resistance and capacitance values.

[0093] According to the embodiment of the present disclosure, the second input module S02 further includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first PMOS transistor MP1, a second PMOS transistor MP2, a variable resistor R S and variable capacitor C S .

[0094] The gate of the third PMOS transistor MP3 is connected to the second INP input terminal INP2, and the drain of the third PMOS transistor MP3 is connected to the output module S03;

[0095] The gate of the fourth PMOS transistor MP4 is connected to the second INN input terminal INN2, and the drain of the fourth NMOS transistor MP4 is connected to the output module S03;

[0096] The source of the first PMOS transistor MP1 is connected to the second external power supply, and the drain is connected to the source of the third PMOS transistor MP3;

[0097] The source of the second PMOS transistor MP2 is connected to the second external power supply, the drain is connected to the source of the fourth PMOS transistor MP4, and the gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1;

[0098] Variable resistor R S One end is connected to the source of the third PMOS transistor MP3, and the other end is connected to the source of the fourth PMOS transistor MP4;

[0099] Variable capacitor C S One end is connected to the source of the third PMOS transistor MP3, and the other end is connected to the source of the fourth PMOS transistor MP4;

[0100] Variable resistor R S and variable capacitor C SUsed to adjust the second current signal provided to the output module S03.

[0101] The third PMOS transistor MP3 and the fourth PMOS transistor MP4 receive external voltage signals through their gates, convert the voltage signals into current signals and output them to the output module S03 through their drains. S and variable capacitor C S The size of the input stage frequency domain zero and pole distribution is adjusted, and the current signal provided to the output module S03 is adjusted. The first PMOS tube MP1 and the second PMOS tube MP2 are connected to the bias voltage Vs2. The first PMOS tube MP1 and the second PMOS tube MP2 provide current bias for the third PMOS tube MP3 and the fourth PMOS tube MP4. The variable resistor R S and variable capacitor C S This can be achieved by using a MOS tube operating in the linear region, and by adding different bias voltages to the gate of the MOS tube to adjust the resistance and capacitance values.

[0102] According to an embodiment of the present disclosure, the output module S03 includes: a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first cascade PMOS transistor MP7, a second cascade PMOS transistor MP8, a first cascade NMOS transistor MN7, a second cascade NMOS transistor MN8, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6.

[0103] The source of the fifth PMOS transistor MP5 is connected to the first external power supply;

[0104] The source of the sixth PMOS transistor MP6 is connected to the first external power supply, and the gate of the sixth PMOS transistor MP6 is connected to the gate of the fifth PMOS transistor MP5;

[0105] The source of the first cascade PMOS transistor MP7 is connected to the drain of the fifth PMOS transistor MP5;

[0106] The source of the second cascade PMOS transistor MP8 is connected to the drain of the sixth PMOS transistor MP6, and the gate of the second cascade PMOS transistor MP8 is connected to the gate of the first cascade PMOS transistor MP7;

[0107] The drain of the first cascade NMOS transistor MN7 is connected to the drain of the first cascade PMOS transistor MP7;

[0108] The drain of the second cascade NMOS transistor MN8 is connected to the drain of the second cascade PMOS transistor MP8, and the gate of the second cascade NMOS transistor MN8 is connected to the first cascade NMOS transistor MN7;

[0109] The drain of the fifth NMOS transistor MN5 is connected to the source of the first cascade NMOS transistor MN7, and the source of the fifth NMOS transistor MN5 is grounded;

[0110] The drain of the sixth NMOS transistor MN6 is connected to the source of the second cascade NMOS transistor MN8 , the gate of the sixth NMOS transistor MN6 is connected to the gate of the fifth NMOS transistor MN5 , and the source of the sixth NMOS transistor MN6 is grounded.

[0111] According to the embodiment of the present disclosure, the output module S03 further includes: a load capacitor C L and two equal load resistors R L .

[0112] Load capacitance C L One end is connected to the drain of the first cascade NMOS transistor MN7, and the other end is connected to the drain of the second cascade NMOS transistor MN8;

[0113] Two equal load resistors R L After the series connection, one end is connected to the drain of the first cascade NMOS transistor MN7, and the other end is connected to the drain of the second cascade NMOS transistor MN8;

[0114] The P output terminal is connected to the drain of the first cascade NMOS transistor MN7;

[0115] The N output terminal is connected to the drain of the second cascade NMOS transistor MN8.

[0116] The gates of the first cascade NMOS transistor MN7 and the second cascade NMOS transistor MN8 are connected to the same bias voltage Vb1, the gates of the first cascade PMOS transistor MP7 and the second cascade PMOS transistor MP8 are connected to the same bias voltage Vb2, and the gates of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to the same bias voltage Vb3. The fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6 provide current bias for the output module S03.

[0117] The drain of the third NMOS transistor MN3 in the first input module S01 is connected to the source of the first cascade PMOS transistor MP7, and the drain of the fourth NMOS transistor MN4 is connected to the source of the second cascade PMOS transistor MP8; the drain of the third PMOS transistor MP3 in the second input module S02 is connected to the source of the second cascade NMOS transistor MP8, and the drain of the fourth NMOS transistor MP4 is connected to the source of the first cascade NMOS transistor MP7.

[0118] When the first input module S01 is in working state, the output module S03 receives the first current signal from the first input module S01, and the current flows to the load capacitor C through the first cascade PMOS transistor MP7 and the second cascade PMOS transistor MP8. L and two equal load resistors R L, forming a voltage, which is output by the P output terminal and the N output terminal; when the second input module S02 is in the working state, the output module S03 receives the second current signal from the second input module S02, and the current flows to the load capacitor C through the first cascade NMOS transistor MN7 and the second cascade NMOS transistor MN8. L and two equal load resistors R L A voltage is formed and outputted from the P output terminal and the N output terminal; when the first input module S01 and the second input module S02 are both in working state, the current flows to the load capacitor C through the first cascade PMOS transistor MP7, the second cascade PMOS transistor MP8, the first cascade NMOS transistor MN7 and the second cascade NMOS transistor MN8. L and two equal load resistors R L A voltage is formed and output from the P output terminal and the N output terminal.

[0119] According to the embodiment of the present disclosure, the output module S03 further includes a common-mode feedback unit S031, including: an operational amplifier U1 and a compensation capacitor C C .

[0120] Figure 2 is a schematic diagram of an operational amplifier U1 according to an embodiment of the present disclosure;

[0121] like Figure 2 As shown, the operational amplifier U1 includes: a first load PMOS transistor MP11, a second load PMOS transistor MP21, a first input NMOS transistor MN21, a second input NMOS transistor MN31, an NMOS tail current transistor MN11, a positive input terminal V+, a negative input terminal V- and an output terminal OUT.

[0122] The source of the NMOS tail current transistor MN11 is grounded, and the drain is connected to the sources of the first input NMOS transistor MN21 and the second input NMOS transistor MN31. The drain of the first input NMOS transistor MN21 is connected to the drain of the first load PMOS transistor MP11, and the drain of the second input NMOS transistor MN31 is connected to the drain of the second load PMOS transistor MP21. The sources of the first load PMOS transistor MP11 and the second load PMOS transistor MP21 are connected to a power supply, the gates of the first load PMOS transistor MP11 and the second load PMOS transistor MP21 are connected, and the gates of the first load PMOS transistor MP11 and the second load PMOS transistor MP21 are connected to the drain of the first input NMOS transistor MN21. The gate of the NMOS tail current transistor MN11 is connected to a bias voltage. The gate of the first input NMOS transistor MN21 constitutes the positive input terminal V+ of the operational amplifier U1, the gate of the second input NMOS transistor MN31 constitutes the negative input terminal V- of the operational amplifier U1, and the drain of the second load PMOS transistor MP21 serves as the output terminal OUT of the operational amplifier U1.

[0123] Combine Figure 1 and Figure 2 As shown, the positive input terminal V+ of the operational amplifier U1 in the output module S03 is connected to two load resistors R L At the middle node between, the negative input terminal V- of the operational amplifier U1 is connected to a reference voltage VREF, and the output terminal OUT of the operational amplifier U1 is connected to the gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6;

[0124] Compensation capacitor C C , one end is connected to the output terminal OUT of the operational amplifier U1, and the other end is grounded;

[0125] The common-mode feedback unit S031 is used to determine the common-mode voltage output by the analog equalizer.

[0126] Since the output stage uses cascade transistor output, the common mode voltage of the analog equalizer output cannot be determined, so a common mode feedback unit is added to determine the common mode voltage of the analog equalizer output so that the output common mode voltage is equal to VREF. By using the virtual short circuit characteristic of the op amp, the voltages at the two input points of the op amp are basically the same, that is, the common mode voltage of the analog equalizer output is equal to the load resistance R L The voltage at the midpoint is equal to VREF.

[0127] According to an embodiment of the present disclosure, the first common mode voltage V inn，cm The range is V gsn3，4 +V gsn1，2 -V thn1，2 <V inn，cm <V b2 +|V gsp7，8 |+V thn3，4 , where V gsn3，4 is the gate-source voltage of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, V gsn1，2 is the gate-source voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2, V thn1，2 is the threshold voltage of the first NMOS transistor MN1 and the second NMOS transistor MN2, V b2 is the gate bias voltage of the first cascade PMOS transistor MP7 and the second cascade PMOS transistor MP8, V gsp7，8 is the gate-source voltage of the first cascade PMOS transistor MP7 and the second cascade PMOS transistor MP8, V thn3，4 is the threshold voltage of the third NMOS transistor MN3 and the fourth NMOS transistor MN4. thn3，4 Higher, such as when the temperature is 4K (-269 degrees Celsius) V thn3，4It is about 550mV, which is easily larger than the V dsp5，6 |, so the first common mode voltage Vinn,cm range is V gsn3，4 +V gsn1，2 -V thn1，2 <V inn，cm <VDD, where |V dsp5，6 | is the absolute value of the drain-source voltage of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6.

[0128] According to an embodiment of the present disclosure, the second common mode voltage V inn，cm The range is V b1 -V gsn7，8 +V thp3，4 <V inp，cm <VDD-|V gsp1，2 |+|V thp1，2 |-|V gsp3，4 |, where V b1 is the gate bias voltage of the first cascade NMOS transistor MN7 and the second cascade NMOS transistor MN8, V gsn7，8 is the gate-source voltage of the first cascade NMOS transistor MN7 and the second cascade NMOS transistor MN8, V thp3，4 is the threshold voltage of the third PMOS transistor MP3 and the fourth PMOS transistor MP4, V gsp1，2 is the gate-source voltage of the first PMOS transistor MP1 and the second PMOS transistor MP2, V thp1，2 is the threshold voltage of the first PMOS transistor MP1 and the second PMOS transistor MP2, V gsp3，4 is the gate-source voltage of the third PMOS transistor MP3 and the fourth PMOS transistor MP4. thp3，4 Higher, such as when the temperature is 4K (-269 degrees Celsius) V thp3，4 It is about 750mV, which is easily greater than the V of the fifth NMOS tube MN5 and the sixth NMOS tube MN6. dsn5，6 , so the second common mode voltage V inp，cm The range is 0<V inp，cm <VDD-|V gs p 1，2 |+|V thp1，2 |-|V gsp3，4 |, where V dsn5，6 is the drain-source voltage of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6.

[0129] Therefore, the common-mode input range of the analog equalizer is V in，cm 0≤V in，cm <VDD.

[0130] According to an embodiment of the present disclosure, the analog equalizer transfer function is: Therefore, the voltage signal output by the analog equalizer includes two poles and A zero point where g m For the transconductance of the input pair of the third NMOS transistor MN3, the fourth NMOS transistor MN4, the third PMOS transistor MP3 and the fourth PMOS transistor MP4, selecting the zero point smaller than the two poles can achieve a larger gain at high frequencies, thereby realizing the analog equalizer function.

[0131] According to the embodiment of the present disclosure, the NMOS and PMOS transistors used are characterized by testing at an extremely low temperature of 4K (-269 degrees Celsius), and a BSIM model that can be used in commercial EDA tools is established for the design of the analog equalizer.

[0132] Figure 3 : is a frequency response curve of the input common mode voltage from 0 to VDD according to an embodiment of the present disclosure;

[0133] like Figure 3 As shown in FIG. 1 , the analog equalizer can provide high gain at high frequencies from 0 to VDD (1.8V), thereby compensating for the attenuation of high frequencies in the channel, thereby realizing the equalizer function.

[0134] Figure 4 is an eye diagram of a signal after passing through a channel according to an embodiment of the present disclosure; Figure 5 1 is an eye diagram after passing through the analog equalizer according to an embodiment of the present disclosure.

[0135] Figure 4 This shows that the eye diagram deteriorates after passing through the non-ideal channel, which means that the signal quality deteriorates. However, after compensation by the analog equalizer, both the eye height and eye width increase (e.g. Figure 5 As shown in Figure 2, the signal noise and jitter are reduced, and the signal quality is improved.

[0136] According to the above description, those skilled in the art should have a clear understanding of the analog equalizer disclosed in the present invention.

[0137] In summary, the present disclosure provides an analog equalizer that addresses the challenges of operating conventional circuits in extremely low-temperature environments. The process used in this analog equalizer has been tested, characterized, and modeled at these temperatures, enabling the analog equalizer to operate normally in these environments. This analog equalizer, capable of achieving rail-to-rail common-mode input, effectively addresses the situations where threshold voltage increases significantly at extremely low temperatures, narrowing the input common-mode range of conventional analog equalizers and preventing them from operating normally, or where the common-mode level cannot be determined at extremely low temperatures.

[0138] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

[0139] It should also be noted that directional terms such as "upper," "lower," "front," "back," "left," and "right" mentioned in the embodiments are merely references to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure.

[0140] Furthermore, the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but are merely illustrative of the contents of the embodiments of the present disclosure. In addition, in the claims, any reference signs placed between brackets should not be construed as limiting the claims.

[0141] Unless otherwise indicated, the numerical parameters in this specification and the appended claims are approximate and can vary depending on the desired properties obtained through the content of the present disclosure. Specifically, all numbers used in the specification and claims to express composition amounts, reaction conditions, etc., should be understood to be modified by the term "about" in all cases. Generally, the meaning of the expression is to include variations of ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments from the specific quantity.

[0142] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0143] The use of ordinal numbers such as "first," "second," and "third" in the specification and claims to modify corresponding elements does not in itself mean that the elements have any ordinal number, nor does it represent the order of one element relative to another or the order in the manufacturing method. The use of such ordinal numbers is only used to clearly distinguish one element with a certain name from another element with the same name.

[0144] Furthermore, unless specifically described or required to occur sequentially, the order of the steps is not limited to the order listed above and may be varied or rearranged based on desired design requirements. Furthermore, the above embodiments may be mixed and matched with each other or with other embodiments based on design and reliability considerations. That is, the technical features of different embodiments may be freely combined to form more embodiments.

[0145] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstract and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose. Furthermore, in a unit claim enumerating a number of devices, several of these devices may be embodied by the same item of hardware.

[0146] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed approach should not be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, the disclosed aspects consist of fewer than all the features of the individual embodiments disclosed above. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate embodiment of the present disclosure.

[0147] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. An analog equalizer, comprising: A first input module includes a first input unit and a first output unit, the first input unit is used to receive a first external voltage signal, the first output unit is used to provide a first current signal, and the first input unit includes a first INN input terminal and a first INP input terminal; A second input module includes a second input unit and a second output unit, the second input unit is used to receive a second external voltage signal, the second output unit is used to provide a second current signal, and the second input unit includes a second INN input terminal and a second INP input terminal; as well as The output module is connected to the first input module and the second input module, and is used to convert the first current signal and / or the second current signal into a voltage signal and output the voltage signal. The output module includes: a fifth PMOS transistor, whose source is connected to the first external power supply; a sixth PMOS transistor, wherein the source is connected to the first external power supply, and the gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor; The first cascade PMOS tube has a source connected to the drain of the fifth PMOS tube; A second cascade PMOS transistor, whose source is connected to the drain of the sixth PMOS transistor, and whose gate is connected to the gate of the first cascade PMOS transistor; The drain of the first cascade NMOS tube is connected to the drain of the first cascade PMOS tube; The drain of the second cascade NMOS tube is connected to the drain of the second cascade PMOS tube, and the gate of the second cascade NMOS tube is connected to the first cascade NMOS tube; a fifth NMOS transistor, wherein the drain is connected to the source of the first cascade NMOS transistor, and the source of the fifth NMOS transistor is grounded; a sixth NMOS transistor, wherein the drain is connected to the source of the second cascade NMOS transistor, the gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, and the source of the sixth NMOS transistor is grounded; A load capacitor, one end of which is connected to the drain of the first cascade NMOS transistor, and the other end of which is connected to the drain of the second cascade NMOS transistor; Two equal load resistors, one end of the two equal load resistors connected in series is connected to the drain of the first cascade NMOS transistor, and the other end is connected to the drain of the second cascade NMOS transistor; A P output terminal connected to the drain of the first cascade NMOS tube; and The N output terminal is connected to the drain of the second cascade NMOS tube.

2. The analog equalizer according to claim 1, wherein The first input module (S01) further includes: a third NMOS transistor (MN3), the gate of which is connected to the first INN input terminal (INN1), and the drain of which is connected to the source of the first cascade PMOS transistor (MP7); a fourth NMOS transistor (MN4), the gate of which is connected to the first INP input terminal (INP1), and the drain of which is connected to the source of the second cascade PMOS transistor (MP8); A first NMOS transistor (MN1), the source of which is grounded, and the drain of which is connected to the source of the third NMOS transistor (MN3); A second NMOS transistor (MN2), the source of which is grounded, the drain of which is connected to the source of the fourth NMOS transistor (MN4), and the gate of which is connected to the gate of the first NMOS transistor (MN1); Variable resistor (R S ), one end of which is connected to the source of the third NMOS transistor (MN3), and the other end of which is connected to the source of the fourth NMOS transistor (MN4); and Variable Capacitor (C S ), one end of which is connected to the source of the third NMOS transistor (MN3), and the other end of which is connected to the source of the fourth NMOS transistor (MN4); The variable resistor (R S ) and the variable capacitance (C S ) is used to adjust the first current signal provided to the output module (S03).

3. The analog equalizer according to claim 2, wherein: The second input module (S02) further includes: a third PMOS transistor (MP3), the gate of which is connected to the second INP input terminal (INP2), and the drain of which is connected to the source of the second cascade NMOS transistor (MN8); a fourth PMOS transistor (MP4), the gate of which is connected to the second INN input terminal (INN2), and the drain of which is connected to the source of the first cascade NMOS transistor (MN7); a first PMOS transistor (MP1), a source connected to a second external power supply, and a drain connected to a source of the third PMOS transistor (MP3); a second PMOS transistor (MP2), wherein the source is connected to the second external power supply, the drain is connected to the source of the fourth PMOS transistor (MP4), and the gate of the second PMOS transistor (MP2) is connected to the gate of the first PMOS transistor (MP1); Variable resistor (R S ), one end of which is connected to the source of the third PMOS transistor (MP3), and the other end of which is connected to the source of the fourth PMOS transistor (MP4); and Variable Capacitor (C S ), one end of which is connected to the source of the third PMOS transistor (MP3), and the other end of which is connected to the source of the fourth PMOS transistor (MP4); The variable resistor (R S ) and the variable capacitance (C S ) is used to adjust the second current signal provided to the output module (S03).

4. The analog equalizer according to claim 1, wherein The output module (S03) further includes a common mode feedback unit (S031), including: The positive input (V+) of the operational amplifier (U1) is connected to the two equal load resistors (R L ), the negative input terminal (V-) of the operational amplifier (U1) is connected to an external reference voltage; and Compensation capacitor (C C ), one end of which is connected to the output terminal (OUT) of the operational amplifier (U1), and the other end of which is grounded; The common-mode feedback unit (S031) is used to determine the common-mode voltage output by the analog equalizer.

5. The analog equalizer according to claim 2, wherein: a first common mode voltage of the first external voltage signal The range is , wherein is the gate-source voltage of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4), is the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), is the threshold voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), is the gate bias voltage of the first cascade PMOS tube (MP7) and the second cascade PMOS tube (MP8), is the gate-source voltage of the first cascade PMOS tube (MP7) and the second cascade PMOS tube (MP8), is the threshold voltage of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4).

6. The analog equalizer according to claim 3, wherein: a second common mode voltage of the second external voltage signal The range is , wherein is the gate bias voltage of the first cascade NMOS tube (MN7) and the second cascade NMOS tube (MN8), is the gate-source voltage of the first cascade NMOS tube (MN7) and the second cascade NMOS tube (MN8), is the threshold voltage of the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4), is the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), is the threshold voltage of the first PMOS tube (MP1) and the second PMOS tube (MP2), is the gate-source voltage of the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4); The common-mode input range of the analog equalizer for: .

7. The analog equalizer according to claim 3, wherein: The voltage signal output by the analog equalizer includes two poles and , a zero point ,in It is the transconductance of the third NMOS transistor (MN3), the fourth NMOS transistor (MN4), the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4) of the input pair transistors.

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