Amplification circuit, related chip and electronic device

Abstract

The application discloses an amplification circuit, a related chip and an electronic device. The amplification circuit comprises a current balancing unit, a biasing unit, an output unit, and a P-type transistor differential amplification unit, an N-type transistor replica differential input unit, a P-type transistor replica differential input unit and an N-type transistor differential amplification unit which respectively receive first and second input voltage signals. The current balancing unit balances the currents generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit. The biasing unit outputs a first biasing current to the P-type transistor differential amplification unit and the N-type transistor replica differential input unit, and provides a second biasing current to the P-type transistor replica differential input unit and the N-type transistor differential amplification unit. The output unit generates an output terminal current according to a plurality of current signals generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit.

Description

TECHNICAL FIELD

[0001] The present application relates to an amplification circuit, in particular to an amplification circuit with stable output current. BACKGROUND

[0002] Due to the low noise and high stability of the clock signal generated by the phase-locked loop, the phase-locked loop is widely used in various chips and gradually develops in the direction of low power consumption and high integration. In the charge pump phase-locked loop, the performance of the charge pump plays an important role in suppressing the reference spur of the phase-locked loop. In the prior art, in order to reduce the current mismatch caused by the charging and discharging effect of the parasitic capacitance in the charge pump and the voltage jitter at the output end of the charge pump, an amplifier is often used for feedback to clamp the output end of the charge pump, thereby enhancing the current matching accuracy of the charge pump.

[0003] Due to the small static current and fast switching speed required by the charge pump, the amplifier used to provide feedback also has higher requirements, for example, the amplifier needs to have a larger common-mode input range, higher driving capability, lower power consumption and larger bandwidth, etc. characteristics, so as to suppress the influence of the amplifier on the working point of the charge pump. That is, how to provide a suitable amplifier to reduce the influence on the working point of the charge pump has become a problem to be solved. SUMMARY

[0004] One of the purposes of the present application is to disclose an amplification circuit, a related chip and an electronic device to solve the above problems.

[0005] An embodiment of the present application provides an amplification circuit. The amplification circuit comprises a P-type transistor differential amplification unit, an N-type transistor replica differential input unit, a P-type transistor replica differential input unit, an N-type transistor differential amplification unit, a current balance unit, a bias unit and an output unit. The P-type transistor differential amplification unit is configured to receive a first input voltage signal and a second input voltage signal. The N-type transistor replica differential input unit is configured to receive the first input voltage signal and the second input voltage signal. The P-type transistor replica differential input unit is configured to receive the first input voltage signal and the second input voltage signal. The N-type transistor differential amplification unit is configured to receive the first input voltage signal and the second input voltage signal. The current balance unit is configured to balance currents generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit. The bias unit is configured to provide a first bias current to the P-type transistor differential amplification unit and the N-type transistor replica differential input unit, and to provide a second bias current to the P-type transistor replica differential input unit and the N-type transistor differential amplification unit. The output unit is configured to generate an output terminal current according to currents generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit.

[0006] The first bias current has the same current value as the second bias current. When a common mode voltage of the first input voltage signal and the second input voltage signal changes, a current change corresponding to the P-type transistor differential amplification unit and the P-type transistor replica differential input unit has the same change amount and opposite change direction as a current change corresponding to the N-type transistor replica differential input unit and the N-type transistor differential amplification unit, so that the output terminal current generated by the output unit remains stable.

[0007] Another embodiment of the present application provides a chip comprising an amplification circuit and a power supply circuit. The power supply circuit is connected to the amplification circuit and supplies power to the amplification circuit, for example, provides a stable power supply voltage VDD to the amplification circuit.

[0008] Another embodiment of the present application provides an electronic device comprising the chip and a housing. The chip is arranged inside the housing.

[0009] The amplification circuit, the related chip and the electronic device provided by the embodiments of the present application can use complementary single-stage input common-source amplifier groups to provide gain, and use a current branch circuit connected in parallel with the common-source amplifier and a current balance unit to balance the currents of the common-source amplifier groups, so that the output terminal current remains stable, thereby reducing the influence on the working point of the charge pump. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a schematic diagram of an amplification circuit according to an embodiment of the present application.

[0011] Figure 2 is Figure 1 a circuit diagram of the amplification circuit of

[0012] Figure 3 is a current schematic diagram of the amplification circuit of Figure 1

[0013] Figure 4 is a current schematic diagram of the amplification circuit of Figure 1

[0014] Figure 5 is a schematic diagram of an amplification circuit according to another embodiment of the present application.

[0015] Figure 6 is a circuit diagram of a P-type transistor differential amplification unit according to an embodiment of the present application.

[0016] Figure 7 is a circuit diagram of an N-type transistor replica differential input unit according to an embodiment of the present application. DETAILED DESCRIPTION

[0017] The following disclosure provides various implementations or examples, which can be used to implement different features of the present disclosure. Specific examples of components and configurations are given herein to illustrate the various features of the present disclosure. It is contemplated that these descriptions are not intended to limit the disclosure. For example, in the following description, a first feature is formed over or on a second feature can include some embodiments in which the first and second features are directly in contact with each other; and can also include some embodiments in which there are additional components formed between the first and second features such that the first and second features can not be directly in contact with each other. In addition, the present disclosure can use component numbers and / or reference numerals repeatedly throughout various embodiments. Such repeated use of the component numbers and / or reference numerals is based on the desire to simplify the drawings and is not intended to indicate that the different embodiments and / or configurations discussed are related.

[0018] ​​Notwithstanding that the numerical ranges and parameters setting forth the broadest scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to be

[0019] Figure 1 FIG. 1 is a schematic diagram of an amplification circuit 100 according to an embodiment of the present application. The amplification circuit 100 includes a bias unit 110, a P-type transistor differential amplification unit 120, an N-type transistor replica differential input unit 130, a P-type transistor replica differential input unit 140, an N-type transistor differential amplification unit 150, a current balancing unit 160, and an output unit 170. In this embodiment, the amplification circuit 100 can be designed as a chip and can be disposed in an electronic device according to system requirements.

[0020] In some embodiments, in order to enable the amplifier to provide a smaller current consumption and a larger bandwidth, a single-stage common-source amplifier is used. However, the output current of the single-stage common-source amplifier is easily affected by the load, such as when the load is large, which can cause the single-stage common-source amplifier to be turned off and unable to operate normally. To solve this problem, in the present embodiment, the amplification circuit 100 can use a single-stage input-stage common-source amplifier to provide gain, and add a current branch through a replica pair of transistors, so that the amplification circuit 100 can provide a more stable output current. For example, in the present embodiment, the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150 are complementary input-stage common-source amplifiers, and the P-type transistor replica differential input unit 140 and the N-type transistor replica differential input unit 130 are current branch circuits connected in parallel with the input-stage common-source amplifiers, and the P-type transistor replica differential input unit 140 can use a transistor of the same type and width-length ratio as the P-type transistor differential amplification unit 120, and the N-type transistor replica differential input unit 130 can use a transistor of the same type and width-length ratio as the N-type transistor differential amplification unit 150, so that the N-type transistor replica differential input unit 130 can generate a current change corresponding to and complementary to the P-type transistor differential amplification unit 120, and the P-type transistor replica differential input unit 140 can generate a current change corresponding to and complementary to the N-type transistor differential amplification unit 150. In this way, the amplification circuit 100 can have the advantages of less current consumption and a wider frequency band. Furthermore, since the current branches provided by the P-type transistor replica differential input unit 140 and the N-type transistor replica differential input unit 130 can compensate and balance the current generated by the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150, the output current of the amplification circuit 100 can be maintained in a more stable state, and the working state of the input pair of transistors, such as the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150, is not affected.

[0021] In this embodiment, the P-type transistor differential amplification unit 120, the N-type transistor replica differential input unit 130, the P-type transistor replica differential input unit 140, and the N-type transistor differential amplification unit 150 can each receive the first input voltage signal VP and the second input voltage signal VN, and can each convert the first input voltage signal VP and the second input voltage signal VN into amplified currents. In addition, in the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150, in addition to the input pair transistors, there are load pair transistors required to provide gain. However, since the main function of the N-type transistor replica differential input unit 130 and the P-type transistor replica differential input unit 140 is only to replicate branch currents, they can only include input pair transistors, and the load pair transistors can be omitted. The specific circuit structure of the P-type transistor differential amplification unit 120, the N-type transistor replica differential input unit 130, the P-type transistor replica differential input unit 140, and the N-type transistor differential amplification unit 150 will be described in detail in the following paragraphs.

[0022] The bias unit 110 can provide the bias currents required by the P-type transistor differential amplification unit 120, the N-type transistor replica differential input unit 130, the P-type transistor replica differential input unit 140, and the N-type transistor differential amplification unit 150. For example, the bias unit 110 can provide a first bias current IB1 and a second bias current IB2, where the first bias current IB1 is the total current flowing into the P-type transistor differential amplification unit 120 and the N-type transistor replica differential input unit 130, and the second bias current IB2 is the total current flowing out of the P-type transistor replica differential input unit 140 and the N-type transistor differential amplification unit 150. In this embodiment, the current value of the first bias current IB1 and the second bias current IB2 can have the same current value.

[0023] The current balancing unit 160 can balance the currents generated by the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150, and the output unit 170 can generate a stable output terminal current according to the current signal integrated by the current balancing unit 160, so that when providing an output voltage through the output terminal OUT of the amplification circuit 100, it is not easy for the amplification circuit 100 to be turned off due to excessive load current.

[0024] As previously described, in the present embodiment, the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150 are complementary common-source amplifier sets, and the N-type transistor replica differential input unit 130 and the P-type transistor replica differential input unit 140 are current branch circuits connected in parallel with the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150, respectively. In this case, when the common-mode voltage of the first input voltage signal VP and the second input voltage signal VN changes, the current changes generated by the P-type transistor differential amplification unit 120 and the P-type transistor replica differential input unit 140 have the same change amount and opposite change directions as the current changes generated by the N-type transistor replica differential input unit 130 and the N-type transistor differential amplification unit 150, and the current balancing unit 160 can further balance the currents generated by the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150, so that the output terminal current generated by the output unit 170 can remain stable and will not change with the change of the common-mode voltage. In addition, since the amplification circuit 100 does not use additional feedback circuits, the required area is small, the bandwidth is large, and the power consumption is low. In some embodiments, the amplification circuit 100 can be applied in a phase-locked loop and used to provide feedback required by a charge pump.

[0025] Figure 2 is a circuit diagram of the amplification circuit 100. In Figure 2 , the bias unit 110 can include a first current mirror 112, a second current mirror 114, and a third current mirror 116. The first current mirror 112 can generate a first replica current IP1 according to a received reference current IB0. The second current mirror 114 can include a plurality of P-type transistors and can generate a first bias current IB1 according to the first replica current IP1. The third current mirror 116 can include a plurality of N-type transistors and can generate a second bias current IB2 according to the first replica current IP1.

[0026] For example, the first current mirror 112 can include a first N-type transistor MN1 and a second N-type transistor MN2, the second current mirror can include a first P-type transistor MP1, a second P-type transistor MP2, and a third P-type transistor MP3, and the third current mirror 116 can include a third N-type transistor MN3 and a fourth N-type transistor MN4.

[0027] The first N-type transistor MN1 has a first terminal, a second terminal and a control terminal. The first terminal of the first N-type transistor MN1 is configured to receive a reference current IBO. The second terminal of the first N-type transistor MN1 is coupled to a ground voltage GND. The control terminal of the first N-type transistor MN1 is coupled to the first terminal of the first N-type transistor MN1. In this embodiment, the reference current IBO can be provided by a current source CS1. The second N-type transistor MN2 has a first terminal, a second terminal and a control terminal. The second terminal of the second N-type transistor MN2 is coupled to the ground voltage GND. The control terminal of the second N-type transistor MN2 is coupled to the control terminal of the first N-type transistor MN1.

[0028] The first P-type transistor MP1 has a first terminal, a second terminal and a control terminal. The first terminal of the first P-type transistor MP1 is coupled to a power supply voltage VDD. The second terminal of the first P-type transistor MP1 is coupled to the first terminal of the second N-type transistor MN2. The control terminal of the first P-type transistor MP1 is coupled to the second terminal of the first P-type transistor MP1. The second P-type transistor MP2 has a first terminal, a second terminal and a control terminal. The first terminal of the second P-type transistor MP2 is coupled to the power supply voltage VDD. The control terminal of the second P-type transistor MP2 is coupled to the control terminal of the first P-type transistor MP1. The third N-type transistor MN3 has a first terminal, a second terminal and a control terminal. The first terminal of the third N-type transistor MN3 is coupled to the second terminal of the second P-type transistor MP2. The second terminal of the third N-type transistor MN3 is coupled to the ground voltage GND. The control terminal of the third N-type transistor MN3 is coupled to the first terminal of the third N-type transistor MN3.

[0029] In this embodiment, the second N-type transistor MN2 in the first current mirror 112 can replicate the reference current IBO received by the first N-type transistor MN1 to generate a first replicated current IP1. The second P-type transistor MP2 in the second current mirror 114 can replicate the current IP1 flowing through the first P-type transistor MP1. Since the third N-type transistor MN3 and the second P-type transistor MP2 are connected in series, the third N-type transistor MN3 and the second P-type transistor MP2 will flow the same current, for example, the same current equal to the current IP1, and can be used to provide bias voltages VB1 and VB2 required by the third P-type transistor MP3 and the fourth N-type transistor MN4, respectively. As shown in FIG. 1, the bias voltage VB1 is coupled to the control terminal of the third P-type transistor MP3. The bias voltage VB2 is coupled to the control terminal of the fourth N-type transistor MN4. Figure 2As shown, the third P-type transistor MP3 has a first terminal, a second terminal and a control terminal. The first terminal of the third P-type transistor MP3 is coupled to the power supply voltage VDD. The second terminal of the third P-type transistor MP3 is configured to provide the first bias current IB1. The control terminal of the third P-type transistor MP3 is coupled to the control terminal of the second P-type transistor MP2 to receive the bias voltage VB1. That is, in the second current mirror 114, the control terminals of the third P-type transistor MP3 and the second P-type transistor MP2 receive the same voltage. Therefore, the third P-type transistor MP3 and the second P-type transistor MP2 can replicate the current flowing through the first P-type transistor MP1 to generate the first bias current IB1.

[0030] The fourth N-type transistor MN4 has a first terminal, a second terminal and a control terminal. The first terminal of the fourth N-type transistor MN4 is configured to provide the second bias current IB2. The second terminal of the fourth N-type transistor MN4 is coupled to the ground voltage GND. The control terminal of the fourth N-type transistor MN4 is coupled to the control terminal of the third N-type transistor MN3 to receive the bias voltage VB2. That is, in the third current mirror 116, the control terminals of the fourth N-type transistor MN4 and the third N-type transistor MN3 receive the same voltage. Therefore, the fourth N-type transistor MN4 can replicate the current flowing through the third N-type transistor MN3 to generate the second bias current IB2.

[0031] In addition, the P-type transistor differential amplification unit 120 can include a fourth P-type transistor MP4, a fifth P-type transistor MP5, a sixth N-type transistor MN6 and a seventh N-type transistor MN7. The fourth P-type transistor MP4 and the fifth P-type transistor MP5 can receive the first input voltage signal VP and the second input voltage signal VN, respectively, and generate a transconductance amplification current to the sixth N-type transistor MN6 and the seventh N-type transistor MN7 according to the first input voltage signal VP and the second input voltage signal VN.

[0032] As shown, the third P-type transistor MP3 has a first terminal, a second terminal and a control terminal. The first terminal of the third P-type transistor MP3 is coupled to the power supply voltage VDD. The second terminal of the third P-type transistor MP3 is configured to provide the first bias current IB1. The control terminal of the third P-type transistor MP3 is coupled to the control terminal of the second P-type transistor MP2 to receive the bias voltage VB1. That is, in the second current mirror 114, the control terminals of the third P-type transistor MP3 and the second P-type transistor MP2 receive the same voltage. Therefore, the third P-type transistor MP3 and the second P-type transistor MP2 can replicate the current flowing through the first P-type transistor MP1 to generate the first bias current IB1. Figure 2As shown, the fourth P-type transistor MP4 has a first terminal, a second terminal and a control terminal, the first terminal of the fourth P-type transistor MP4 is coupled to the second terminal of the third P-type transistor MP3, and the control terminal of the fourth P-type transistor MP4 can receive the first input voltage signal VP. The fifth P-type transistor MP5 has a first terminal, a second terminal and a control terminal, the first terminal of the fifth P-type transistor MP5 is coupled to the second terminal of the third P-type transistor MP3, and the control terminal of the fifth P-type transistor MP5 can receive the second input voltage signal VN. The sixth N-type transistor MN6 has a first terminal, a second terminal and a control terminal, the first terminal of the sixth N-type transistor MN6 is coupled to the second terminal of the fourth P-type transistor MP4, the second terminal of the sixth N-type transistor MN6 is coupled to the ground voltage GND, and the control terminal of the sixth N-type transistor MN6 is coupled to the first terminal of the sixth N-type transistor MN6. The seventh N-type transistor MN7 has a first terminal, a second terminal and a control terminal, the first terminal of the seventh N-type transistor MN7 is coupled to the second terminal of the fifth P-type transistor MP5, the second terminal of the seventh N-type transistor MN7 is coupled to the ground voltage GND, and the control terminal of the seventh N-type transistor MN7 is coupled to the first terminal of the seventh N-type transistor MN7.

[0033] In this embodiment, the P-type transistor differential amplification unit 120 and the N-type transistor replica differential input unit 130 have input pair transistors of complementary types, so that when the common-mode voltage of the first input voltage signal VP and the second input voltage signal VN changes, the current change generated by the P-type transistor differential amplification unit 120 has an opposite change direction to the current change generated by the N-type transistor replica differential input unit 130. For example, when the current generated by the P-type transistor differential amplification unit 120 increases, the current generated by the N-type transistor replica differential input unit 130 decreases, and vice versa. Furthermore, since the P-type transistor differential amplification unit 120 and the N-type transistor replica differential input unit 130 can be commonly biased by the first bias current IB1, even if the currents generated by the P-type transistor differential amplification unit 120 and the N-type transistor replica differential input unit 130 respectively change due to the common-mode voltage change of the first input voltage signal VP and the second input voltage signal VN, the sum of the currents generated by the P-type transistor differential amplification unit 120 and the N-type transistor replica differential input unit 130 can remain unchanged.

[0034] As Figure 2As shown, the N-type transistor replication differential input unit 130 may include a tenth N-type transistor MN10 and an eleventh N-type transistor MN11. The tenth N-type transistor MN10 has a first terminal, a second terminal, and a control terminal. The first terminal of the tenth N-type transistor MN10 is coupled to the second terminal of the third P-type transistor MP3, and the control terminal of the tenth N-type transistor MN10 can receive a first input voltage signal VP. The eleventh N-type transistor MN11 has a first terminal, a second terminal, and a control terminal. The first terminal of the eleventh N-type transistor MN11 is coupled to the second terminal of the third P-type transistor MP3, and the second terminal of the eleventh N-type transistor MN11 is coupled to the second terminal of the tenth N-type transistor MN10. The control terminal of the eleventh P-type transistor MN11 can receive a second input voltage signal VN.

[0035] In this embodiment, the third current mirror 116 of the bias unit 110 may further include a fifth N-type transistor MN5 to provide a bias current IB3 to the N-type transistor replica differential input unit 130, so that the N-type transistor replica differential input unit 130 generates and outputs a bias current IB3 accordingly. The fifth N-type transistor MN5 has a first terminal, a second terminal, and a control terminal. The first terminal of the fifth N-type transistor MN5 is coupled to the second terminal of the eighth N-type transistor MN8 to provide the bias current IB3, the second terminal of the fifth N-type transistor MN5 is coupled to the ground voltage GND, and the control terminal of the fifth N-type transistor MN5 is coupled to the control terminal of the third N-type transistor MN3 to receive the bias voltage VB2.

[0036] Furthermore, in this embodiment, the bias unit 110 can provide a second bias current IB2 to the P-type transistor replica differential input unit 140 and the N-type transistor differential amplifier unit 150 through the fourth N-type transistor MN4, so that the total output current of the P-type transistor replica differential input unit 140 and the N-type transistor differential amplifier unit 150 is the second bias current IB2.

[0037] like Figure 2 As shown, the P-type transistor replication differential input unit 140 includes a sixth P-type transistor MP6 and a seventh P-type transistor MP7. The sixth P-type transistor MP6 has a first terminal, a second terminal, and a control terminal. The second terminal of the sixth P-type transistor MP6 is coupled to the first terminal of the fourth N-type transistor MN4, and the control terminal of the sixth P-type transistor MP6 can receive a first input voltage signal VP. The seventh P-type transistor MP7 has a first terminal, a second terminal, and a control terminal. The first terminal of the seventh P-type transistor MP7 is coupled to the first terminal of the sixth P-type transistor MP6, and the second terminal of the seventh P-type transistor MP7 is coupled to the first terminal of the fourth N-type transistor MN4. The control terminal of the seventh P-type transistor MN7 can receive a second input voltage signal VN.

[0038] In addition, in the present embodiment, the second current mirror 114 of the biasing unit 110 can further include an eighth P-type transistor MP8 to provide a bias current IB4 required by the P-type transistor replica differential input unit 140. The eighth P-type transistor MP8 has a first terminal, a second terminal and a control terminal, the first terminal of the eighth P-type transistor MP8 is coupled to the power supply voltage VPP, the second terminal of the eighth P-type transistor MP8 is coupled to the first terminal of the sixth P-type transistor MP6 to provide the bias current IB4, and the control terminal of the eighth P-type transistor MP8 is coupled to the control terminal of the second P-type transistor MP2 to receive the bias voltage VB1.

[0039] The N-type transistor differential amplification unit 150 can include a ninth P-type transistor MP9, a tenth P-type transistor MP10, an eighth N-type transistor MN8 and a ninth N-type transistor MN9. The ninth P-type transistor MP9 has a first terminal, a second terminal and a control terminal, the first terminal of the ninth P-type transistor MP9 is coupled to the power supply voltage VPP, and the control terminal of the ninth P-type transistor MP9 is coupled to the second terminal of the ninth P-type transistor MP9. The tenth P-type transistor MP10 has a first terminal, a second terminal and a control terminal, the first terminal of the tenth P-type transistor MP10 is coupled to the power supply voltage VPP, and the control terminal of the tenth P-type transistor MP10 is coupled to the second terminal of the tenth P-type transistor MP10. The eighth N-type transistor MN8 has a first terminal, a second terminal and a control terminal, the first terminal of the eighth N-type transistor MN8 is coupled to the second terminal of the ninth P-type transistor MP9, the second terminal of the eighth N-type transistor MN8 is coupled to the first terminal of the fourth N-type transistor MN4, and the control terminal of the eighth N-type transistor MN8 can receive the first input voltage signal VP. The ninth N-type transistor MN9 has a first terminal, a second terminal and a control terminal, the first terminal of the ninth N-type transistor MN9 is coupled to the second terminal of the tenth P-type transistor MP10, the second terminal of the ninth N-type transistor MN9 is coupled to the first terminal of the fourth N-type transistor MN4, and the control terminal of the ninth N-type transistor MN9 can receive the second input voltage signal VN.

[0040] The current balancing unit 160 includes an eleventh P-type transistor MP11 and a twelfth N-type transistor MN12. The eleventh P-type transistor MP11 has a first terminal, a second terminal and a control terminal. The first terminal of the eleventh P-type transistor MP11 is coupled to the power supply voltage VPP. The second terminal of the eleventh P-type transistor MP11 is coupled to the first terminal of the seventh N-type transistor MN7. The control terminal of the eleventh P-type transistor MP11 is coupled to the control terminal of the tenth P-type transistor MP10. The twelfth N-type transistor MN12 has a first terminal, a second terminal and a control terminal. The first terminal of the twelfth N-type transistor MN12 is coupled to the second terminal of the ninth P-type transistor MP9. The second terminal of the twelfth N-type transistor MN12 is coupled to the ground voltage GND. The control terminal of the twelfth N-type transistor MN12 is coupled to the control terminal of the sixth N-type transistor MN6. In this embodiment, the eleventh P-type transistor MP11 can copy the current generated by the tenth P-type transistor MP10 to the seventh N-type transistor MN7. The twelfth N-type transistor MN12 can copy the current generated by the sixth N-type transistor MN6 to the ninth P-type transistor MP9, so as to balance the currents generated by the P-type transistor differential amplifying unit 120 and the N-type transistor differential amplifying unit 150.

[0041] The output unit 170 includes a twelfth P-type transistor MP12 and a thirteenth N-type transistor MN13. The twelfth P-type transistor MP12 has a first terminal, a second terminal and a control terminal. The first terminal of the twelfth P-type transistor MP12 is coupled to the power supply voltage VPP. The second terminal of the twelfth P-type transistor MP12 is coupled to the output terminal OUT of the amplifying circuit 100. The control terminal of the twelfth P-type transistor MP12 is coupled to the control terminal of the ninth P-type transistor MP9. The thirteenth N-type transistor MN13 has a first terminal, a second terminal and a control terminal. The first terminal of the thirteenth N-type transistor MN13 is coupled to the output terminal OUT. The second terminal of the thirteenth N-type transistor MN13 is coupled to the ground voltage GND. The control terminal of the thirteenth N-type transistor MN13 is coupled to the control terminal of the seventh N-type transistor MN7.

[0042] Figure 3is the current schematic of the amplification circuit 100 when the first input voltage signal VP and the second input voltage signal VN are equal and the common-mode voltage of both is half of the power supply voltage VDD. In this embodiment, the width-to-length ratio of the third P-type transistor MP3 can be a certain multiple of the width-to-length ratio of the first P-type transistor MP1, such as twice, so that the first bias current IB1 flowing through the third P-type transistor MP3 is twice the current flowing through the first P-type transistor MP1. In addition, to achieve that the replica pair current flowing through the N-type transistor replica differential input unit 130 can occupy one half of the first bias current IB1 at this common-mode voltage, the width-to-length ratio of the fifth N-type transistor MN5 can be set to be equal to the width-to-length ratio of the third N-type transistor MN3. In addition, the width-to-length ratio of the fourth N-type transistor MN4 can also be the same certain multiple of the width-to-length ratio of the third N-type transistor MN3, such as twice, so that the second bias current IB2 flowing through the fourth N-type transistor MN4 is twice the current flowing through the third N-type transistor MN3. Similarly, to achieve that the replica pair current flowing through the P-type transistor replica differential input unit 140 can occupy one half of the second bias current IB2 at this common-mode voltage, the width-to-length ratio of the eighth P-type transistor MP8 can be set to be equal to the width-to-length ratio of the first P-type transistor MP1. In this case, the current value of the first bias current IB1 is twice the current value of the bias current IB3, and the current value of the second bias current IB2 is twice the current value of the bias current IB4, and the first bias current IB1 and the second bias current IB2 can have the same current value.

[0043] In this embodiment, since the P-type transistor differential amplification unit 120 and the N-type transistor replica differential input unit 130 will jointly receive the first bias current IB1, and the current value of the bias current IB3 provided by the fifth N-type transistor MN5 is one half of the current value of the first bias current IB1, the P-type transistor differential amplification unit 120 will also flow a current that is one half of the first bias current IB1. In addition, in the case that the first input voltage signal VP and the second input voltage signal VN are the same, in the P-type transistor differential amplification unit 120, the fourth P-type transistor MP4 and the fifth P-type transistor MP5 will flow the same size of current, and in the N-type transistor replica differential input unit 130, the tenth N-type transistor MN10 and the eleventh N-type transistor MN11 will also flow the same size of current. That is, the fourth P-type transistor MP4, the fifth P-type transistor MP5, the tenth N-type transistor MN10 and the eleventh N-type transistor MN11 will all flow one quarter of the first bias current IB1, that is

[0044] Similarly, since the sum of the currents output by the P-type transistor replicating differential input unit 140 and the N-type transistor differential amplifier unit 150 should be the second bias current IB2, and the bias current IB4 provided by the eighth P-type transistor MP8 is half of the bias current IB2 provided by the fourth N-type transistor MN4, the P-type transistor replicating differential input unit 140 and the N-type transistor differential amplifier unit 150 will each output a current of half the bias current IB2. When the first input voltage signal VP and the second input voltage signal VN are the same, in the P-type transistor replicating differential input unit 140, the sixth P-type transistor MP6 and the seventh P-type transistor MP7 will flow with the same amount of current, and in the N-type transistor differential amplifier unit 150, the eighth N-type transistor MN8 and the ninth N-type transistor MN9 will also flow with the same amount of current. That is, the sixth P-type transistor MP6, the seventh P-type transistor MP7, the eighth N-type transistor MN8, and the ninth N-type transistor MN9 will all flow through one-quarter of the second bias current IB2, i.e.

[0045] Furthermore, in this embodiment, the aspect ratio of the eleventh P-type transistor MP11 is equal to that of the tenth P-type transistor MP10, and the aspect ratio of the twelfth N-type transistor MN12 is equal to that of the sixth N-type transistor MN6. In this case, the eleventh P-type transistor MP11 can adjust according to the current flowing through the tenth P-type transistor MP10. Generation and current An equal amount of replicated current is sent to the seventh N-type transistor MN7, while the twelfth N-type transistor MN12 can be based on the current flowing through the sixth N-type transistor MN6. Generation and current An equal amount of replicated current is applied, causing the ninth P-type transistor MP9 to output the current replicated by the twelfth N-type transistor MN12. In other words, as... Figure 3 As shown, the total current flowing through the ninth P-type transistor MP9 is Equivalent to half the second bias current The total current flowing through the seventh N-type transistor MN7 is Equivalent to half the first bias current

[0046] In this embodiment, the width-to-length ratio of the twelfth P-type transistor MP12 can be four times that of the ninth P-type transistor MP9, and the width-to-length ratio of the thirteenth N-type transistor MN13 can be four times that of the seventh N-type transistor MN7. In this case, the twelfth P-type transistor MP12 will generate twice the second bias current IB2, i.e., 2IB2, in accordance with the current flowing through the ninth P-type transistor MP9, and the thirteenth N-type transistor MN13 will generate twice the first bias current IB1, i.e., 2IB1, in accordance with the current flowing through the seventh N-type transistor MN7. Since the first bias current IB1 and the second bias current IB2 have substantially the same current value, the output current generated by the output unit 170 is substantially twice the first bias current IB1.

[0047] In addition, since the amplification circuit 100 uses the complementary pair of P-type and N-type transistors and the current branch circuit connected in parallel thereto, and balances the currents generated by the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150 through the current balancing unit 160, the output current of the output unit 170 can be maintained constant when the common-mode voltage of the first input voltage signal VP and the second input voltage signal VN changes.

[0048] Figure 4 is the case where the first input voltage signal VP and the second input voltage signal VN are equal and the common-mode voltage of both is the power supply voltage VDD, the current diagram of the amplification circuit 100 is shown. As shown in Figure 4 When the common-mode voltage of the first input voltage signal VP and the second input voltage signal VN becomes the power supply voltage VDD, the P-type transistors MP4 and MP5 in the P-type transistor differential amplification unit 120 will be turned off. Similarly, the P-type transistors MP6 and MP7 in the P-type transistor replica differential input unit 140 will be turned off

[0049] In this case, since the fourth P-type transistor MP4 is turned off, the sixth N-type transistor MN6 will not generate current, and the twelfth N-type transistor MN12 in the current balancing unit 160 will not generate current, and the ninth P-type transistor MP9 will not output extra current to the twelfth N-type transistor MN12, so the ninth P-type transistor MP9 and the eighth N-type transistor MN8 will flow the same current On the contrary, the eleventh P-type transistor MP11 will replicate the current generated by the tenth P-type transistor MP10 to the seventh N-type transistor MN7, so the seventh N-type transistor MN7 will still flow the current In this way, the twelfth P-type transistor MP12 generates a doubled second bias current IB2, i.e., 2IB2, according to the current flowing through the ninth P-type transistor MP9, and the thirteenth N-type transistor MN13 generates a doubled second bias current IB2, i.e., 2IB2, according to the current flowing through the seventh N-type transistor MN7. Since the first bias current IB1 and the second bias current IB2 have substantially the same current value, the output current generated by the output unit 170 is still substantially the doubled first bias current IB1.

[0050] In addition, when the first input voltage signal VP and the second input voltage signal VN are equal and the common-mode voltage of both is the ground voltage GND, the amplification circuit 100 can also balance the currents generated by the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150 through the current balancing unit 160 according to similar principles, so that the output current generated by the output unit 170 remains stable and unchanged. Since the amplification circuit 100 can maintain the output current constant, when the amplification circuit 100 is applied in a charge pump, it is less likely to affect the operating point of the charge pump, making the operation of the charge pump more accurate.

[0051] Since the amplification circuit 100 can use complementary single-stage input common-source amplifier groups, such as the P-type transistor differential amplification unit 120 and the N-type transistor differential amplification unit 150, to provide gain without using additional feedback circuits, the required circuit area is smaller, the bandwidth is larger, and the power consumption is lower. In addition, the amplification circuit 100 can also balance the currents of the common-source amplifier groups through the current branch circuits connected in parallel with the common-source amplifiers, such as the P-type transistor replica differential input unit 140 and the N-type transistor replica differential input unit 130, and the current balancing unit 160, so that the output current can also remain stable and unchanged, thereby reducing the impact on the operating point of the charge pump. However, the present application is not limited thereto, and in some embodiments, a buffer feedback unit can also be added to the amplification circuit to improve the gain of the amplification circuit.

[0052] Figure 5 FIG. 2 is a schematic diagram of an amplification circuit 200 according to another embodiment of the present application. The amplification circuit 200 has a similar structure to the amplification circuit 100 and can operate according to similar principles, but the amplification circuit 200 can further include a buffer feedback unit 280. The buffer feedback unit 280 can be coupled to the P-type transistor differential amplification unit 220, the N-type transistor differential amplification unit 250, the current balancing unit 260, and the output unit 270, and can stabilize the currents generated by the P-type transistor differential amplification unit 220 and the N-type transistor differential amplification unit 250 and / or improve the gain of the amplification circuit 200.

[0053] Furthermore, in some embodiments, the P-type transistor differential amplification unit 220, the P-type transistor replica differential input unit 240, the N-type transistor replica differential input unit 230, and the N-type transistor differential amplification unit 250 can use the same structure as the P-type transistor differential amplification unit 120, the P-type transistor replica differential input unit 140, the N-type transistor replica differential input unit 130, and the N-type transistor differential amplification unit 150 shown in FIG. 1, although the present application is not limited thereto. In some embodiments, any of the P-type transistor differential amplification unit 220, the P-type transistor replica differential input unit 240, the N-type transistor replica differential input unit 230, and the N-type transistor differential amplification unit 250 can also be implemented using the structure of a Cascode Amplifier to achieve larger input and output impedances. Figure 2 Furthermore, in some embodiments, the P-type transistor differential amplification unit 220, the P-type transistor replica differential input unit 240, the N-type transistor replica differential input unit 230, and the N-type transistor differential amplification unit 250 can use the same structure as the P-type transistor differential amplification unit 120, the P-type transistor replica differential input unit 140, the N-type transistor replica differential input unit 130, and the N-type transistor differential amplification unit 150 shown in FIG. 1, although the present application is not limited thereto. In some embodiments, any of the P-type transistor differential amplification unit 220, the P-type transistor replica differential input unit 240, the N-type transistor replica differential input unit 230, and the N-type transistor differential amplification unit 250 can also be implemented using the structure of a Cascode Amplifier to achieve larger input and output impedances.

[0054] Figure 6 FIG. 2 is a circuit diagram of the P-type transistor differential amplification unit 220 according to an embodiment of the present application. As shown in FIG. 2, the P-type transistor differential amplification unit 220 can include P-type transistors MP1A, MP2A, MP3A, and MP4A, and N-type transistors MN1A, MN2A, MN3A, and MN4A. The control terminals of the P-type transistors MP1A and MP2A can receive a first input voltage signal VP and a second input voltage signal VN, respectively, while the control terminals of the P-type transistors MP3A and MP4A and the N-type transistors MN1A, MN2A, MN3A, and MN4A can receive corresponding bias voltages VB1A, VB2A, and VB3A, respectively. In some embodiments, the bias voltages VB1A, VB2A, and VB3A can be provided, for example, by the bias unit 210. Figure 6

[0055] Furthermore, in some embodiments, any of the P-type transistor differential amplification unit 220, the P-type transistor replica differential input unit 240, the N-type transistor replica differential input unit 230, and the N-type transistor differential amplification unit 250 can also be implemented using the structure of a folded differential pair to achieve larger gain. Figure 7 FIG. 3 is a circuit diagram of the N-type transistor differential input unit 250 according to an embodiment of the present application.

[0056] ​In this embodiment, the biasing unit 210 can include a P-type transistor MP1B, which can receive a bias voltage VB1B and can provide a bias current IB2B to the P-type transistor replica differential input unit 240 and the N-type transistor differential amplification unit 250. In this embodiment, the biasing unit 210 can also include an N-type transistor MN1B, which can receive a bias voltage VB2B and can provide another bias current IB4B to the P-type transistor replica differential input unit 240, so that the P-type transistor replica differential input unit 240 can correspondingly generate and output the bias current IB4B. In addition, the bias current IB4B can have a current value that is half of the bias current IB2B, in which case, when the common-mode voltage of the first input voltage signal VP and the second input voltage signal VN is half of the power supply voltage VDD, the current flowing into the P-type transistor replica differential input unit 240 will be the same as the current flowing into the N-type transistor differential amplification unit 250, both of which are half of the bias current IB2B. In some embodiments, the P-type transistor differential amplification unit 220 is also implemented in a folded cascode circuit structure, and the bias current and bias voltage required by the N-type transistor replica differential input unit 230 can be correspondingly set according to similar principles.

[0057] The N-type transistor differential amplification unit 250 can include P-type transistors MP2B, MP3B, MP4B, MP5B, MP6B and MP7B, and N-type transistors MN2B, MN3B, MN4B and MN5B. In this embodiment, to implement a folded structure, the N-type transistor differential amplification unit 250 and the N-type transistor differential amplification unit 150 of Figure 2 The N-type transistor differential amplification unit 250 can include P-type transistors MP2B, MP3B, MP4B, MP5B, MP6B and MP7B, and N-type transistors MN2B, MN3B, MN4B and MN5B. In this embodiment, to implement a folded structure, the N-type transistor differential amplification unit 250 and the N-type transistor differential amplification unit 150 of Figure 7 As shown, the control terminals of the P-type transistors MP2B and MP3B of the N-type transistor differential amplification unit 250 can receive the first input voltage signal VP and the second input voltage signal VN, respectively. The P-type transistors MP4B and MP5B can receive a bias voltage VB3B, and the P-type transistors MP6B and MP7B can receive a bias voltage VB4B. In addition, the N-type transistors MN2B and MN3B can receive a bias voltage VB5B, and the N-type transistors MN4B and MN5B can receive a bias voltage VB6B. In some embodiments, the bias voltages VB3B, VB4B, VB5B and VB6B can be provided by the biasing unit 210, for example.

[0058] In this embodiment, the width-length ratios of the input pair transistors, such as P-type transistors MP2B and MP3B, in the N-type transistor differential amplification unit 250 can be equal to those of the input pair transistors of the same type, so as to reflect the current changes of the input pair transistors of the same type by copying the input pair transistors. For example, when the first input voltage signal VP and the second input voltage signal VN are equal and the common-mode voltage of both is half of the power supply voltage VDD, the N-type transistor differential amplification unit 250 and the P-type transistor copy differential input unit 240 will flow the same current, such as one-half of the first bias current IB1, that is, and the P-type transistors MP2B and MP3B will each flow one-quarter of the first bias current IB1, that is,

[0059] Since the N-type transistor differential amplification unit 250 has a folded cascode circuit structure, a large gain can be achieved, but because there are more stacked transistors, a larger power consumption and a larger power supply voltage can also be required. That is, the designer can implement the P-type transistor differential amplification unit 220, the P-type transistor copy differential input unit 240, the N-type transistor copy differential input unit 230, and the N-type transistor differential amplification unit 250 in a suitable structure according to actual needs.

[0060] In summary, the amplification circuit, the related chip, and the electronic device provided by the embodiments of the present application can use complementary single-stage input cascode amplifier groups to provide gain, and balance the currents of the cascode amplifier groups through the current branch circuit and the current balancing unit connected in parallel with the cascode amplifier, so that the output end current can be kept stable, thereby reducing the influence on the working point of the charge pump.

[0061] The above description briefly presents the features of some embodiments of the present application, so that those skilled in the art can more fully understand various aspects of the present disclosure. Those skilled in the art can easily use the present disclosure as a basis to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages as described herein. Those skilled in the art should understand that these equivalent embodiments still belong to the spirit and scope of the present disclosure, and they can be variously changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. An amplification circuit, characterized by, comprises: a P-type transistor differential amplification unit configured to receive a first input voltage signal and a second input voltage signal; an N-type transistor differential amplification unit configured to receive the first input voltage signal and the second input voltage signal; a P-type transistor replica differential input unit configured to receive the first input voltage signal and the second input voltage signal; an N-type transistor replica differential input unit configured to receive the first input voltage signal and the second input voltage signal; a current balancing unit configured to balance currents generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit; a biasing unit configured to provide a first biasing current to the P-type transistor differential amplification unit and the N-type transistor replica differential input unit together, and to provide a second biasing current to the P-type transistor replica differential input unit and the N-type transistor differential amplification unit together; and an output unit configured to generate an output terminal current according to currents generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit; wherein: the first biasing current has a same current value as the second biasing current; and when a common mode voltage of the first input voltage signal and the second input voltage signal changes, a current change corresponding to the P-type transistor differential amplification unit and the P-type transistor replica differential input unit has a same change amount and an opposite change direction as a current change corresponding to the N-type transistor replica differential input unit and the N-type transistor differential amplification unit, so that the output terminal current generated by the output unit remains stable.

2. The amplification circuit of claim 1, wherein the biasing unit comprises: a first current mirror configured to generate a first replica current according to a received reference current; and a second current mirror comprising a plurality of P-type transistors configured to generate the first biasing current according to the first replica current; and a third current mirror comprising a plurality of N-type transistors configured to generate the second biasing current according to the first replica current.

3. The amplification circuit of claim 2, wherein: the first current mirror comprises: a first N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first N-type transistor being configured to receive the reference current, the second terminal of the first N-type transistor being coupled to a ground voltage, and the control terminal of the first N-type transistor being coupled to the first terminal of the first N-type transistor; and a second N-type transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the second N-type transistor being coupled to the ground voltage and outputting the first replica current, and the control terminal of the second N-type transistor being coupled to the control terminal of the first N-type transistor; the second current mirror comprises: a first P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first P-type transistor being coupled to the first terminal of the first N-type transistor, the second terminal of the first P-type transistor being coupled to the control terminal of the first N-type transistor, and the control terminal of the first P-type transistor being coupled to the control terminal of the second N-type transistor; and a second P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second P-type transistor being coupled to the first terminal of the first N-type transistor, the second terminal of the second P-type transistor being coupled to the control terminal of the second N-type transistor, and the control terminal of the second P-type transistor being coupled to the control terminal of the second N-type transistor. ​ ​ a first P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first P-type transistor coupled to a power supply voltage, the second terminal of the first P-type transistor coupled to the first terminal of the second N-type transistor, and the control terminal of the first P-type transistor coupled to the second terminal of the first P-type transistor; a second P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second P-type transistor coupled to the power supply voltage, and the control terminal of the second P-type transistor coupled to the control terminal of the first P-type transistor; and a third P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third P-type transistor coupled to the power supply voltage, the second terminal of the third P-type transistor to output the first bias current, and the control terminal of the third P-type transistor coupled to the control terminal of the second P-type transistor; and the third current mirror includes: a third N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third N-type transistor coupled to the second terminal of the second P-type transistor, the second terminal of the third N-type transistor coupled to a ground voltage, and the control terminal of the third N-type transistor coupled to the first terminal of the third N-type transistor; and a fourth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth N-type transistor to provide the second bias current, the second terminal of the fourth N-type transistor coupled to the ground voltage, and the control terminal of the fourth N-type transistor coupled to the control terminal of the third N-type transistor.

4. The amplification circuit of claim 3, wherein the P-type transistor differential amplification unit includes: a fourth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth P-type transistor coupled to the second terminal of the third P-type transistor, and the control terminal of the fourth P-type transistor to receive the first input voltage signal; a fifth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth P-type transistor coupled to the second terminal of the third P-type transistor, and the control terminal of the fifth P-type transistor to receive the second input voltage signal; a sixth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth N-type transistor coupled to the second terminal of the fourth P-type transistor, the second terminal of the sixth N-type transistor coupled to the ground voltage, and the control terminal of the sixth N-type transistor coupled to the first terminal of the sixth N-type transistor; and a seventh N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh N-type transistor coupled to the second terminal of the fifth P-type transistor, the second terminal of the seventh N-type transistor coupled to the ground voltage, and the control terminal of the seventh N-type transistor coupled to the first terminal of the seventh N-type transistor.

5. The amplification circuit of claim 4, wherein the P-type transistor replica differential input cell comprises: a sixth P-type transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the sixth P-type transistor coupled to the first terminal of the fourth N-type transistor, and the control terminal of the sixth P-type transistor to receive the first input voltage signal; and a seventh P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh P-type transistor coupled to the first terminal of the sixth P-type transistor, the second terminal of the seventh P-type transistor coupled to the first terminal of the fourth N-type transistor, and the control terminal of the seventh P-type transistor to receive the second input voltage signal.

6. The amplification circuit of claim 5, wherein: the second current mirror further comprises an eighth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth P-type transistor coupled to the supply voltage, the second terminal of the eighth P-type transistor coupled to the first terminal of the sixth P-type transistor, and the control terminal of the eighth P-type transistor coupled to the control terminal of the second P-type transistor; and a width-to-length ratio of the third P-type transistor is twice a width-to-length ratio of the first P-type transistor, and a channel width-to-length of the eighth P-type transistor is equal to the width-to-length ratio of the first P-type transistor.

7. The amplification circuit of claim 4, wherein the N-type transistor differential amplification cell comprises: a ninth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the ninth P-type transistor coupled to the supply voltage, and the control terminal of the ninth P-type transistor coupled to the second terminal of the ninth P-type transistor; a tenth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the tenth P-type transistor coupled to the supply voltage, and the control terminal of the tenth P-type transistor coupled to the second terminal of the tenth P-type transistor; an eighth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth N-type transistor coupled to the second terminal of the ninth P-type transistor, the second terminal of the eighth N-type transistor coupled to the first terminal of the fourth N-type transistor, and the control terminal of the eighth N-type transistor to receive the first input voltage signal; and a ninth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the ninth N-type transistor coupled to the second terminal of the tenth P-type transistor, the second terminal of the ninth N-type transistor coupled to the first terminal of the fourth N-type transistor, and the control terminal of the ninth N-type transistor to receive the second input voltage signal.

8. The amplification circuit of claim 7, wherein the N-type transistor replica differential input cell comprises: a tenth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the tenth N-type transistor coupled to the second terminal of the third P-type transistor, and the control terminal of the tenth N-type transistor configured to receive the first input voltage signal; and an eleventh N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eleventh N-type transistor coupled to the second terminal of the third P-type transistor, the second terminal of the eleventh N-type transistor coupled to the second terminal of the tenth N-type transistor, and the control terminal of the eleventh N-type transistor configured to receive the second input voltage signal.

9. The amplification circuit of claim 8, wherein: the third current mirror further comprises a fifth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth N-type transistor coupled to the second terminal of the tenth N-type transistor, the second terminal of the fifth N-type transistor coupled to a ground voltage, and the control terminal of the fifth N-type transistor coupled to the control terminal of the third N-type transistor; and a width-to-length ratio of the fourth N-type transistor is twice a width-to-length ratio of the third N-type transistor, and a width-to-length ratio of the fifth N-type transistor is equal to the width-to-length ratio of the third N-type transistor.

10. The amplification circuit of claim 7, wherein the current balancing unit comprises: an eleventh P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eleventh P-type transistor coupled to the power voltage, the second terminal of the eleventh P-type transistor coupled to the first terminal of the seventh N-type transistor, and the control terminal of the eleventh P-type transistor coupled to the control terminal of the tenth P-type transistor; and a twelfth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the twelfth N-type transistor coupled to the second terminal of the ninth P-type transistor, the second terminal of the twelfth N-type transistor coupled to the ground voltage, and the control terminal of the twelfth N-type transistor coupled to the control terminal of the sixth N-type transistor.

11. The amplification circuit of claim 10, wherein: a width-to-length ratio of the eleventh P-type transistor is equal to a width-to-length ratio of the tenth P-type transistor; and a width-to-length ratio of the twelfth N-type transistor is equal to a width-to-length ratio of the sixth N-type transistor.

12. The amplification circuit of claim 7, wherein the output unit comprises: a twelfth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the twelfth P-type transistor coupled to the power voltage, the second terminal of the twelfth P-type transistor coupled to an output terminal of the amplification circuit, and the control terminal of the twelfth P-type transistor coupled to the control terminal of the ninth P-type transistor; and a twelfth P-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the twelfth P-type transistor coupled to the power voltage, the second terminal of the twelfth P-type transistor coupled to an output terminal of the amplification circuit, and the control terminal of the twelfth P-type transistor coupled to the control terminal of the ninth P-type transistor; and a thirteenth N-type transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the thirteenth N-type transistor coupled to the output terminal, the second terminal of the thirteenth N-type transistor coupled to the ground voltage, and the control terminal of the thirteenth N-type transistor coupled to the control terminal of the seventh N-type transistor.

13. The amplification circuit of claim 12, wherein: a width-to-length ratio of the twelfth P-type transistor is four times a width-to-length ratio of the ninth P-type transistor; and a width-to-length ratio of the thirteenth N-type transistor is four times a width-to-length ratio of the seventh N-type transistor.

14. The amplification circuit of claim 1, wherein at least one of the P-type transistor differential amplification unit, the P-type transistor replica differential input unit, the N-type transistor replica differential input unit, and the N-type transistor differential amplification unit comprises a folded differential pair structure.

15. The amplification circuit of claim 1, wherein at least one of the P-type transistor differential amplification unit and the N-type transistor differential amplification unit comprises a common-source common-gate amplifier.

16. The amplification circuit of claim 1, further comprising a buffer feedback unit coupled to the P-type transistor differential amplification unit, the N-type transistor differential amplification unit, and the current balancing unit to stabilize currents generated by the P-type transistor differential amplification unit and the N-type transistor differential amplification unit and / or to boost a gain of the amplification circuit.

17. A chip, characterized by including: the amplification circuit and the power supply circuit of any one of claims 1 to 16, the power supply circuit connected to the amplification circuit, the power supply circuit powering the amplification circuit.

18. An electronic device, comprising: including: the chip and the housing of claim 17, the chip disposed inside the housing.

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