A single-pulse high-level signal synchronization circuit

Abstract

The present invention discloses a single-pulse high-level signal synchronization circuit, specifically including: a single-pulse high-level signal synchronization module for synchronously converting the input single-pulse high-level synchronization signal from the first clock domain to the second clock domain and transmitting it to the first AND gate; a single-pulse high-level signal compensation module for providing a compensation and correction signal for the abnormal single-pulse high-level synchronization signal; the first AND gate for performing an AND logic selection on the single-pulse high-level synchronization signal output by the single-pulse high-level signal synchronization module using the compensation and correction signal provided by the single-pulse high-level signal compensation module, and outputting the normal single-pulse high-level synchronization signal in the second clock domain. The present invention not only satisfies the transfer of the synchronization signal from the fast clock domain to the slow clock domain, but also satisfies the transfer of the signal from the slow clock domain to the fast clock domain. At the same time, the problem of abnormal signals appearing during the cross-clock domain transfer is solved through the compensation and correction signal, realizing the final cross-clock domain output of the single-pulse high-level synchronization signal.

Description

Technical Field

[0001] The present invention relates to the field of signal circuit design, and particularly to a single-pulse high-level signal synchronization circuit. Background Art

[0002] During the chip design process, there are usually signals in multiple clock domains. When there are signals in multiple clock domains, the chip design needs to involve the transfer of signals between different clock domains. Currently, the most commonly used method for processing the transfer of signals across clock domains in the prior art is to use register pipelining. Although this method is simple, it has obvious limitations. In particular, for a single-pulse high-level signal synchronization circuit, the single-pulse high-level signal synchronization circuit is mainly used to synchronize the high level of the signal in the first time domain of a single clock cycle of the input to the second time domain. However, the current single-pulse high-level signal synchronization circuit has the problem that it cannot handle the synchronization transfer of signals from a fast clock domain to a slow clock domain, and there is also a problem that abnormal signals are easily caused during the signal transfer across clock domains due to the abnormal level state of the reset signal. Summary of the Invention

[0003] To solve the above problems, the present invention provides a single-pulse high-level signal synchronization circuit, which realizes the transfer of signals of a single clock cycle from the first clock domain to the second clock domain, not only satisfies the synchronization of signals from a fast clock domain to a slow clock domain, but also satisfies the transfer of signals from a slow clock domain to a fast clock domain. At the same time, by setting a compensation and correction signal, the problem of abnormal signals during the transfer across clock domains is solved, and the final single-pulse high-level signal output across clock domains is realized. The specific technical solution of the present invention is as follows:

[0004] A single-pulse high-level signal synchronization circuit specifically includes: a single-pulse high-level signal synchronization module, connected to a first AND gate, for synchronously converting a signal from the first clock domain to the second clock domain; a single-pulse high-level signal compensation module, connected to the first AND gate, for providing a compensation and correction signal for an abnormal high-level signal output by the signal synchronization circuit module; a first AND gate, for outputting a signal that is compensated and corrected by the single-pulse high-level signal compensation module and synchronously converted from the first clock domain to the second clock domain by the signal synchronization circuit module.

[0005] Further, the single-pulse high-level signal synchronization module specifically includes: a second AND gate, a third AND gate, a first register, a second register, a third register, a first inverter, and a second inverter; wherein, the output end of the first inverter is connected to the first input end of the second AND gate, the output end of the second AND gate is connected to the reset signal input end of the first register, the output end of the third register is connected to the input end of the second inverter, and the output end of the second inverter is connected to the first input end of the third AND gate.

[0006] Further, the input terminal of the first inverter in the single-pulse high-level signal synchronization module serves as the input terminal of the single-pulse high-level signal synchronization module, and is used to receive the signal that needs to be converted from the first clock domain to the second clock domain.

[0007] Further, the first register, the second register, and the third register in the single-pulse high-level signal synchronization module are connected in series; wherein, the output terminal of the first register is connected to the first input terminal of the second register, and the output terminal of the second register is connected to the first input terminal of the third register.

[0008] Further, the output terminal of the second register in the single-pulse high-level signal synchronization module is also connected to the second input terminal of the third AND gate.

[0009] Further, the single-pulse high-level signal compensation module specifically includes: a fourth AND gate, a fourth register, a fifth register, a sixth register, a third inverter, and a fourth inverter; wherein, the output terminal of the fourth register is connected to the first input terminal of the fifth register, the output terminal of the fifth register is connected to the first input terminal of the sixth register, the output terminal of the sixth register is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the fourth AND gate, and the output terminal of the fourth AND gate is connected to the input terminal of the fourth inverter.

[0010] Further, the output terminal of the fifth register in the single-pulse high-level signal compensation module is also connected to the second input terminal of the fourth AND gate.

[0011] Further, the output terminal of the third AND gate in the single-pulse high-level signal synchronization module serves as the output terminal of the single-pulse high-level signal synchronization module and is connected to the first input terminal of the first AND gate; the output terminal of the fourth inverter in the single-pulse high-level signal compensation module serves as the output terminal of the single-pulse high-level signal compensation module and is connected to the second input terminal of the first AND gate; the output terminal of the first AND gate serves as the output terminal of the single-pulse high-level signal synchronization circuit, and is used to output the signal converted from the first clock domain to the second clock domain.

[0012] Further, the reset signal input terminals of the second register, the third register, the fourth register, the fifth register, the sixth register, and the second input terminal of the second AND gate are respectively used to receive the inverted reset signal.

[0013] Further, the clock signal input terminals of the first register, the second register, the third register, the fourth register, the fifth register, and the sixth register are respectively used to receive the clock signal of the second clock domain.

[0014] The present invention realizes the synchronous transmission of the synchronous signal of a single clock cycle from the first clock domain to the second clock domain through the single-pulse high-level signal synchronization module, and realizes the compensation and correction when the single-pulse high-level signal synchronization module outputs an abnormal single-pulse low-level signal based on the single-pulse high-level signal compensation module, ensuring that the single-pulse high-level signal synchronization circuit outputs a normal single-pulse high-level synchronization signal transmitted from the first clock domain to the second clock domain. Description of the Drawings

[0015] Figure 1 It is a schematic diagram of the modules of the single-pulse high-level signal synchronization circuit according to the first embodiment of the present invention.

[0016] Figure 2 It is a schematic circuit diagram of the single-pulse high-level signal synchronization module according to the second embodiment of the present invention.

[0017] Figure 3 It is a schematic circuit diagram of the single-pulse high-level signal compensation module according to the third embodiment of the present invention.

[0018] Figure 4 It is a schematic circuit diagram of the single-pulse high-level signal synchronization circuit according to the fourth embodiment of the present invention.

[0019] Figure 5 It is a waveform schematic diagram of the output terminals of the single-pulse high-level signal synchronization circuit according to an embodiment of the present invention.

[0020] Figure 6 It is a waveform schematic diagram after compensation and correction in the single-pulse high-level signal synchronization circuit according to an embodiment of the present invention. Detailed Embodiments

[0021] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described and explained below with reference to the drawings and embodiments. It should be understood that the specific embodiments described below are only used to explain the present invention and are not used to limit the present invention. In addition, it can also be understood that for those of ordinary skill in the art, making some design, manufacturing or production changes to the technical content disclosed in the present invention is only a conventional technical means and should not be understood that the content disclosed in this application is insufficient.

[0022] Unless otherwise defined, the technical terms or scientific terms involved in the present invention shall have the ordinary meanings understood by those of ordinary skill in the technical field to which this application belongs. The words "a", "an", "one", "the", etc. involved in this application do not indicate a limitation in quantity and may represent a singular or plural number. The terms "comprising", "including", "having" and any variations thereof involved in this application are intended to cover non-exclusive inclusion. For example, a process, method, system product or device that includes a series of steps or modules is not limited to the listed steps or units, but may further include steps or modules not listed, or may further include other steps or units inherent to these processes, methods, products or devices. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar counterparts and do not represent a specific order for the objects.

[0023] As a preferred embodiment of the present invention, a single-pulse high-level signal synchronization circuit is provided in the first embodiment of the present invention, as Figure 1 shown. The single-pulse high-level signal synchronization circuit specifically includes: a single-pulse high-level signal synchronization module, a single-pulse high-level signal compensation module, and a first AND gate. Among them, the single-pulse high-level signal synchronization module is used to receive a signal that needs to be synchronously converted from the first clock domain to the second clock domain, synchronously convert the signal from the first clock domain to the second clock domain, and then transmit it to the first AND gate. The single-pulse high-level signal compensation circuit is used to provide a compensation and correction signal for compensation and correction when the single-pulse high-level signal synchronization module outputs an abnormal high-level signal. The first AND gate is respectively connected to the single-pulse high-level signal synchronization module and the single-pulse high-level signal compensation module, and is used to perform an AND logic selection on the signal output from the first clock domain to the second clock domain by the single-pulse high-level signal synchronization module according to the compensation and correction signal provided by the single-pulse high-level signal compensation circuit, and output a signal that realizes the synchronous conversion from the first clock domain to the second clock domain.

[0024] It should be noted that in the current prior art, usually only a part of the above-mentioned single-pulse high-level synchronization module is used as the single-pulse high-level signal synchronization circuit. This circuit has the problem of outputting an abnormal high-level signal. The reason for the generation of the abnormal high-level signal may be that when the synchronization signal in the first time domain received by the single-pulse high-level signal synchronization module is at a low level, due to the abnormal low level of the inverted reset signal input to the single-pulse high-level signal synchronization module, the single-pulse high-level signal synchronization module erroneously believes that the synchronization signal received in the first time domain is at a high level. Therefore, the single-pulse high-level synchronization circuit outputs an abnormal high-level signal. In this embodiment, by setting a single-pulse high-level signal compensation module in the single-pulse high-level signal synchronization circuit, when the single-pulse high-level signal synchronization module outputs an abnormal high-level signal, the AND logic of the first AND gate is used to select and compensate and correct the abnormal high-level signal, so as to enable the single-pulse high-level signal synchronization circuit to output a normal signal that is synchronized and converted from the first clock domain to the second clock domain, and avoid the output of conversion abnormal signals.

[0025] Based on the above first embodiment, as a preferred embodiment of the present invention, as Figure 2 shown, in the second embodiment of the present invention, the single-pulse high-level signal synchronization module specifically includes: a second AND gate, a third AND gate, a first register, a second register, a third register, a first inverter, and a second inverter; wherein, the output end of the first inverter is connected to the first input end of the second AND gate, the output end of the second AND gate is connected to the reset signal input end of the first register, the output end of the third register is connected to the input end of the second inverter, and the input end of the second inverter is connected to the first input end of the third AND gate.

[0026] Preferably, the input end of the first inverter in the single-pulse high-level signal synchronization module serves as the input end of the single-pulse high-level signal synchronization module, and is used to receive the signal that needs to be converted from the first clock domain to the second clock domain.

[0027] Preferably, the first register, the second register, and the third register in the single-pulse high-level signal synchronization module are connected in series; wherein, the output end of the first register is connected to the first input end of the second register, and the output end of the second register is connected to the first input end of the third register.

[0028] Preferably, the output end of the second register in the single-pulse high-level signal synchronization module in the single-pulse high-level signal synchronization module is also connected to the second input end of the third AND gate.

[0029] Based on the above embodiments, as a preferred embodiment of the present invention, as Figure 3As shown in the figure, in the third embodiment of the present invention, the single-pulse high-level signal compensation module specifically includes: a fourth AND gate, a fourth register, a fifth register, a sixth register, a third inverter, and a fourth inverter; wherein, the output end of the fourth register is connected to the first input end of the fifth register, the output end of the fifth register is connected to the first input end of the sixth register, the output end of the sixth register is connected to the input end of the third inverter, the output end of the third inverter is connected to the first input end of the fourth AND gate, and the output end of the fourth AND gate is connected to the input end of the fourth inverter.

[0030] Preferably, the output end of the fifth register in the single-pulse high-level signal compensation module is further connected to the second input end of the fourth AND gate.

[0031] Preferably, the output end of the third AND gate in the single-pulse high-level signal synchronization module is used as the output end of the single-pulse high-level signal synchronization module and is connected to the first input end of the first AND gate; the output end of the fourth inverter in the single-pulse high-level signal compensation module is used as the output end of the single-pulse high-level signal compensation module and is connected to the second input end of the first AND gate; the output end of the first AND gate is used as the output end of the single-pulse high-level signal synchronization circuit for outputting a signal converted from the first clock domain to the second clock domain.

[0032] Based on the above embodiments, as a preferred embodiment of the present invention, as Figure 4 shown, in the fourth embodiment of the present invention, the reset signal input ends of the second register, the third register, the fourth register, the fifth register, the sixth register, and the second input end of the second AND gate in the single-pulse high-level synchronization circuit are respectively used to receive inverted reset signals. At the same time, the clock signal input ends of the first register, the second register, the third register, the fourth register, the fifth register, and the sixth register are respectively used to receive clock signals of the second clock domain.

[0033] It should be noted that the reset values of the first register and the fourth register are high-level signals, and the reset values of the second register, the third register, the fifth register, and the sixth register are low-level signals.

[0034] As Figure 5 shown, Figure 5It is a waveform diagram of each output signal when the compensation module in the single-pulse high-level signal synchronization circuit does not produce a compensation effect. In the figure, signal_in refers to the synchronization signal in the first time domain input to the single-pulse high-level synchronization module, and signal_out in the figure refers to the synchronization signal in the second time domain output by the single-pulse high-level synchronization circuit. It can be seen from the figure that at this time, the first time domain is a slow clock domain compared to the second time domain, which belongs to synchronously transmitting the signal from the slow clock domain to the fast clock domain.

[0035] As Figure 6 shown, Figure 6 It is a waveform diagram of the output signals of each output terminal when the compensation module in the single-pulse high-level signal synchronization circuit produces a compensation effect. In the figure, signal_in refers to the synchronization signal in the first time domain input to the single-pulse high-level synchronization module, and signal_out in the figure refers to the synchronization signal in the second time domain output by the single-pulse high-level synchronization circuit. When the single-pulse high-level signal synchronization module outputs an abnormal synchronization signal, the compensation correction module output by the single-pulse high-level signal compensation module compensates and corrects the abnormal synchronization signal to ensure the normal synchronization signal output in the final second clock domain. As Figure 6 shown, the inverting reset signal outputs an abnormal low-level signal, resulting in the output signal of the second AND gate being affected by the abnormal low-level signal output by the inverting reset signal and outputting an abnormal low-level signal. The beating of the first register, the second register, and the third register is not affected. The output signal of the third AND gate is affected by the abnormal low-level signal output by the second AND gate and outputs an abnormal high-level signal. Under the compensation of the output signal of the fourth inverter in the single-pulse high-level signal compensation module, the single-pulse high-level synchronization circuit is not affected by the abnormal low-level signal, ensuring the accuracy of the synchronization signal output by the single-pulse high-level signal synchronization circuit.

[0036] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single-pulse high-level signal synchronization circuit, characterized in that, The single-pulse high-level signal synchronization circuit specifically includes: A single-pulse high-level signal synchronization module, connected to the first AND gate, for synchronously converting the input single-pulse high-level synchronization signal from the first clock domain to the second clock domain; A single-pulse high-level signal compensation module, connected to the first AND gate, for providing a compensation and correction signal for the abnormal single-pulse high-level synchronization signal output by the single-pulse high-level signal synchronization module; The first AND gate, for performing an AND logic selection on the single-pulse high-level synchronization signal output by the single-pulse high-level signal synchronization module using the compensation and correction signal provided by the single-pulse high-level signal compensation module, and outputting the normal single-pulse high-level synchronization signal in the second clock domain; Among them, the single-pulse high-level signal synchronization module specifically includes: a second AND gate, a third AND gate, a first register, a second register, a third register, a first inverter, and a second inverter; among them, the output end of the first inverter is connected to the first input end of the second AND gate, the output end of the second AND gate is connected to the reset signal input end of the first register, the output end of the third register is connected to the input end of the second inverter, and the output end of the second inverter is connected to the first input end of the third AND gate; Among them, the first register, the second register, and the third register in the single-pulse high-level signal synchronization module are connected in series, the output end of the first register is connected to the first input end of the second register, and the output end of the second register is connected to the first input end of the third register; Among them, the output end of the second register in the single-pulse high-level signal synchronization module is also connected to the second input end of the third AND gate; Among them, the reset signal input end of the second register, the reset signal input end of the third register, and the second input end of the second AND gate are respectively used to receive the inverted reset signal; Among them, the clock signal input ends of the first register, the second register, and the third register are respectively used to receive the clock signal in the second clock domain; Among them, the input end of the first inverter in the single-pulse high-level signal synchronization module serves as the input end of the single-pulse high-level signal synchronization module, for receiving the single-pulse high-level synchronization signal that needs to be converted from the first clock domain to the second clock domain; Among them, the output end of the third AND gate in the single-pulse high-level signal synchronization module serves as the output end of the single-pulse high-level signal synchronization module and is connected to the first input end of the first AND gate; Among them, the output end of the first AND gate serves as the output end of the single-pulse high-level signal synchronization circuit, for outputting the single-pulse high-level synchronization signal converted from the first clock domain to the second clock domain.

2. The single-pulse high-level signal synchronization circuit according to claim 1, characterized in that The single-pulse high-level signal compensation module specifically includes: a fourth AND gate, a fourth register, a fifth register, a sixth register, a third inverter, and a fourth inverter; wherein, the output end of the fourth register is connected to the first input end of the fifth register, the output end of the fifth register is connected to the first input end of the sixth register, the output end of the sixth register is connected to the input end of the third inverter, the output end of the third inverter is connected to the first input end of the fourth AND gate, and the output end of the fourth AND gate is connected to the input end of the fourth inverter; Wherein, the output end of the fifth register in the single-pulse high-level signal compensation module is further connected to the second input end of the fourth AND gate; Wherein, the reset signal input ends of the fourth register, the fifth register, and the sixth register are respectively used for receiving an inverted reset signal; Wherein, the clock signal input ends of the fourth register, the fifth register, and the sixth register are respectively used for receiving the clock signal of the second clock domain; Wherein, the output end of the fourth inverter in the single-pulse high-level signal compensation module is used as the output end of the single-pulse high-level signal compensation module and is connected to the second input end of the first AND gate.

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