Wafer-Level Three-Dimensional Packaging Method and Structure of MEMS Gas Sensors

Abstract

The present invention provides a wafer-level three-dimensional packaging method and structure for a MEMS gas sensor. The method includes the steps of: providing a semiconductor substrate with an ASIC chip and a plurality of spaced-through silicon vias formed therein; back-thinning the semiconductor substrate; etching the back surface of the semiconductor substrate to make the surface of the silicon vias protrude from the back surface of the semiconductor substrate; forming an insulating layer on the back surface of the semiconductor substrate; performing chemical mechanical polishing on the back surface of the semiconductor substrate to expose the silicon vias; performing photolithography and dry etching to form a cavity on the back surface of the semiconductor substrate; eutectically bonding the MEMS micro-heating plate with the MEMS device formed thereon and a pre-bonding structure, with the MEMS device facing the cavity, bonding the silicon vias with the pads of the MEMS micro-heating plate, and bonding the insulating layer with the insulating surface of the MEMS micro-heating plate; forming silicon via solder balls on the surfaces of the silicon vias on the front side of the ASIC chip; and dicing to form single MEMS gas sensor chips. The present invention helps to improve the bonding performance and the manufacturing process efficiency.

Description

Technical Field

[0001] The present invention relates to the field of MEMS technology, and particularly to a wafer-level three-dimensional packaging method and structure for a MEMS gas sensor. Background Art

[0002] Micro-Electro-Mechanical System (MEMS), also known as microelectronic mechanical system, microsystem, micromachine, etc., is a micro device or system integrating micro sensors, micro actuators, micro mechanical structures, micro power supplies, micro energy sources, signal processing and control circuits, high-performance electronic integrated devices, interfaces, communications, etc. Due to its advantages such as miniaturization, intelligence, multi-function, high integration, and suitability for mass production, it has been increasingly widely used in national defense and national economic fields such as electronics, medicine, industry, automobiles, and aerospace.

[0003] During the manufacturing process of MEMS products, the packaging process is both a key point and a difficult point, and the packaging cost accounts for more than 50% of the MEMS manufacturing cost. The existing MEMS packaging processes include three-dimensional stacked packaging and wafer-level packaging processes. Three-dimensional stacked packaging is to stack multiple functional chips in sequence and assemble them into a three-dimensional packaging structure through conductive vias or wire bonding, etc. This packaging method is prone to damage the functional chips, and the volume of the packaged device is relatively large; wafer-level packaging is to fabricate external functional chips and MEMS devices on the same wafer or different wafers, and then bond them together to form a silicon package. However, in the prior art, high-temperature bonding is usually used, which is prone to damage the device, and there are problems such as poor heat dissipation in the packaged device, resulting in a decline in device performance. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a wafer-level three-dimensional packaging method and structure for a MEMS gas sensor, which is used to solve the problems that the volume of the device packaged by the existing MEMS packaging technology is relatively large, the chips are prone to damage during the packaging process, and / or the heat dissipation of the packaged device is poor, resulting in a decline in device performance.

[0005] To achieve the above purpose and other related purposes, the present invention provides a wafer-level three-dimensional packaging method for a MEMS gas sensor, including the steps of:

[0006] Provide a semiconductor substrate, in which an ASIC chip and a plurality of spaced silicon vias are formed, and one end of each silicon via is exposed on the front surface of the semiconductor substrate;

[0007] Perform back thinning on the semiconductor substrate so that the other end of the silicon via is flush with the back surface of the semiconductor substrate, and the front surface and the back surface are two opposite surfaces;

[0008] Etch the back surface of the semiconductor substrate to make the surface of the through-silicon via protrude from the back surface of the semiconductor substrate;

[0009] Form an insulating layer on the back surface of the semiconductor substrate;

[0010] Perform chemical mechanical polishing on the back surface of the semiconductor substrate to expose the through-silicon via;

[0011] Perform photolithography and dry etching to form a cavity on the back surface of the semiconductor substrate, the cavity penetrates the insulating layer and extends into the semiconductor substrate, thereby obtaining a pre-bonding structure;

[0012] Eutectically bond the MEMS micro-heating plate with the MEMS device formed thereon and the pre-bonding structure. The back surface of the semiconductor substrate and the surface where the MEMS device is located are bonding surfaces. The MEMS device faces the cavity. The through-silicon via is bonded to the pad of the MEMS micro-heating plate, and the insulating layer is bonded to the insulating surface of the MEMS micro-heating plate;

[0013] Form through-silicon via solder balls on the surface of the through-silicon via on the front surface of the ASIC chip;

[0014] Cut to form single MEMS gas sensor chips.

[0015] Optionally, the through-silicon via includes a copper pillar and an aluminum layer on the surface of the copper pillar.

[0016] Optionally, the process of back thinning the semiconductor substrate includes CMP.

[0017] Optionally, the method of forming the insulating layer is:

[0018] Use chemical vapor deposition process to form the insulating layer on the back surface of the semiconductor substrate and the surface of the through-silicon via;

[0019] Perform chemical mechanical polishing to remove the insulating layer on the surface of the through-silicon via, and at the same time make the surface of the through-silicon via and the surface of the insulating layer flush.

[0020] Optionally, the semiconductor substrate includes a silicon wafer, and the insulating layer includes a silicon dioxide layer.

[0021] Optionally, the method of forming a cavity on the back surface of the semiconductor substrate includes:

[0022] Form a photoresist layer on the surface of the insulating layer and the through-silicon via;

[0023] Perform patterning on the photoresist layer to define a cavity pattern;

[0024] Dry-etch the insulating layer according to the photoresist layer to form a first part of the cavity in the insulating layer;

[0025] Dry-etch the semiconductor substrate corresponding to the first part to form the cavity with the required depth.

[0026] Optionally, after forming the solder balls, it further includes a step of cutting the obtained structure to separate it into multiple independent devices.

[0027] Optionally, the MEMS micro-heating plate includes a silicon substrate, a silicon oxide layer, and a silicon nitride layer from bottom to top. The solder pads are formed in the silicon nitride layer, and the MEMS device is formed on the silicon oxide layer. During the bonding process, the silicon nitride layer is bonded to the insulating layer on the surface of the semiconductor substrate.

[0028] Optionally, the solder pad includes a bonding metal layer and a solder metal layer located on the surface of the bonding metal layer, and the solder metal layer is bonded to the silicon through-hole.

[0029] More optionally, the bonding metal layer includes a titanium layer and / or a titanium nitride layer, and the solder metal layer includes a chromium layer and / or a gold layer.

[0030] The present invention also provides a wafer-level three-dimensional packaging structure of a MEMS gas sensor. The wafer-level three-dimensional packaging structure of the MEMS gas sensor includes a semiconductor substrate and a MEMS micro-heating plate bonded to each other. An ASIC chip, a cavity, and a plurality of spaced silicon through-holes are formed in the semiconductor substrate. An insulating layer is formed on the surface of the semiconductor substrate. The cavity penetrates the insulating layer and extends into the semiconductor substrate. The silicon through-holes are exposed on the surface of the insulating layer. A MEMS device and solder pads are formed in the MEMS micro-heating plate. The MEMS device faces the cavity. The insulating layer is bonded to the insulating surface of the MEMS micro-heating plate, and the silicon through-holes are bonded and connected to the solder pads.

[0031] As described above, the wafer-level three-dimensional packaging method and structure of the MEMS gas sensor provided by the present invention have the following beneficial effects: The present invention uses a three-dimensional packaging technology of silicon through-holes and backside copper exposure process to prepare a MEMS gas sensor, and uses a eutectic bonding method for wafer-level bonding and packaging of the ASIC and the MEMS micro-heating plate, which helps to improve the bonding performance and manufacturing process efficiency. Description of the Drawings

[0032] Figures 1-10 It shows an exemplary cross-sectional structural schematic diagram presented in each step of the wafer-level three-dimensional packaging method of the MEMS gas sensor provided by the present invention for preparing the wafer-level three-dimensional packaging structure of the MEMS gas sensor.

[0033] Description of Component Labels

[0034] 11 Semiconductor substrate

[0035] 12 Copper pillar

[0036] 13 Aluminum layer

[0037] 14 Insulating layer

[0038] 15 Cavity

[0039] 161 MEMS device

[0040] 163 Silicon substrate

[0041] 164 Silicon oxide layer

[0042] 165 Silicon nitride layer

[0043] 166 Bonding metal layer

[0044] 167 Solder metal layer Detailed implementation manners

[0045] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0046] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers.

[0047] In the context of the present application, the structure in which the first feature is "above" the second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex. To make the illustrations as concise as possible, not all structures are marked in each drawing.

[0049] Please refer to Figures 1 to 10

[0050] As Figures 1 to 10 shown, the present invention provides a wafer-level three-dimensional packaging method for a MEMS gas sensor, including the steps:

[0051] Provide a semiconductor substrate 11, in which an ASIC (Application Specific Integrated Circuit) chip and a plurality of spaced silicon vias are formed. One end of the silicon via is exposed on the front surface of the semiconductor substrate 11. The structure of this step is as Figure 1 shown. The silicon via can be formed by deep silicon etching process. The semiconductor substrate 11 is, for example, a silicon wafer, but is not limited thereto, and can also be a germanium wafer, a germanium-silicon wafer, an SOI wafer, etc. When the semiconductor substrate 11 is a 200 mm or 300 mm wafer, there are usually multiple ASIC chips, which are arrayed in the semiconductor substrate 11, and the number of silicon vias matches the number of ASIC chips.

[0052] Use a process including but not limited to chemical mechanical polishing process, that is, CMP process (for example, rough grinding first and then fine grinding) to perform back thinning on the semiconductor substrate 11, so that the other end of the silicon via is flush with the back surface of the semiconductor substrate 11. The front surface and the back surface are two opposite surfaces. It is also possible to define the silicon via as including the opposite front surface and back surface. After grinding, the front surface of the silicon via is flush with the front surface of the semiconductor substrate 11, and the back surface is flush with the back surface of the semiconductor substrate 11. The structure obtained after this step is as Figure 2 shown. The back surface refers to Figure 2 the bottom surface in Figure 2 and the front surface refers to

[0053] Etch the back surface of the semiconductor substrate 11, for example, perform back etching on the semiconductor substrate 11, so that the surface of the silicon via protrudes from the back surface of the semiconductor substrate 11, that is, from Figure 3 it can be seen that the lower surface of the silicon via is lower than the lower surface of the semiconductor substrate 11.

[0054] An insulating layer 14 is formed on the back surface of the semiconductor substrate 11 such that the back surface of the through-silicon via remains exposed. The structure obtained after this step is as shown in Figure 5 ; This process may include chemical mechanical polishing of the back surface of the semiconductor substrate 11 after forming the insulating layer 14 to expose the through-silicon via.

[0055] Lithography and dry etching are performed to form a cavity 15 on the back surface of the semiconductor substrate 11. The cavity 15 penetrates the insulating layer 14 and extends into the semiconductor substrate 11, thereby obtaining a pre-bonding structure. This process can be referred to Figures 6 to 8 ;

[0056] The MEMS micro-heating plate formed with the MEMS device 161 and the pre-bonding structure are eutectically bonded. The MEMS device 161 faces the cavity 15. The electrical connection structure between the through-silicon via and the MEMS micro-heating plate, that is, the pad bonding, and the insulating surface of the insulating layer 14 and the MEMS micro-heating plate are bonded. The structure obtained after this step is as shown in Figure 9 ;

[0057] A solder ball 17 is formed on the surface of the exposed through-silicon via, that is, the front surface of the through-silicon via, that is, on the surface of the through-silicon via on the front surface of the ASIC chip, by using a process including but not limited to ball mount. The structure obtained is as shown in Figure 10 ;

[0058] Since multiple MEMS devices 161 are usually formed on the MEMS micro-heating plate, after forming the solder ball 17, it is usually necessary to perform die saw on the obtained structure to separate the multiple devices on the wafer from each other to form single MEMS gas sensor chips.

[0059] The wafer-level three-dimensional packaging method of the MEMS gas sensor provided by the present invention first pre-treats the semiconductor substrate formed with the ASIC chip alone, and then eutectically bonds it with the MEMS micro-heating plate formed with the MEMS device, which can minimize the damage to the chip during the packaging process and help improve the packaging efficiency; the bonding structure can be customized in batches, which helps reduce the packaging cost and device miniaturization; by using the advantages of the eutectic bonding process, such as low bonding temperature, little influence by surface roughness, suitable for batch hermetic packaging, good physical properties, good thermal conductivity, high strength, no need for flux, and low viscosity, etc., the bonding consistency can be improved, avoiding interface voids caused by contamination, and helping to improve the bonding quality; the MEMS device is placed in the cavity, which helps improve the device heat dissipation and device reliability, and the cavity can be used for gas introduction, which helps improve the performance of the packaged device. At the same time, the present invention uses the three-dimensional packaging technology of the through-silicon via and backside copper exposure process to prepare the MEMS gas sensor, and combines the eutectic bonding method for wafer-level bonding packaging of the ASIC and the MEMS micro-heating plate, which helps improve the bonding performance and manufacturing process efficiency.

[0060] In one example, the MEMS micro-heating plate from bottom to top (taking Figure 9 and 10 as an example) includes a silicon substrate 163, a silicon oxide layer 164, and a silicon nitride layer 165. The bonding pads are formed in the silicon nitride layer 165. The MEMS device 161 is formed on the silicon oxide layer 164 and preferably has a spacing from the silicon nitride layer 165, that is, the MEMS device 161 is formed in a space surrounded by the silicon nitride layer 165. During the bonding process, the silicon nitride layer 165 is bonded to the insulating layer 14 on the surface of the semiconductor substrate 11, and the bonding pads are bonded to the through-silicon vias. Of course, the structure of the MEMS micro-heating plate is not limited to this. Importantly, it is matched with the semiconductor substrate 11. In a preferred example, the bonding pads include a bonding metal layer 166 and a solder metal layer 167 located on the surface of the bonding metal layer 166. The solder metal layer 167 is bonded to the through-silicon vias. The bonding metal layer 166 includes but is not limited to a titanium layer and / or a titanium nitride layer. The solder metal layer 167 includes but is not limited to a chromium layer and / or a gold layer. For example, it is a stack of a chromium metal layer and a gold layer. Chromium has good hardness, while gold has good flexibility and conductivity, which can reduce the requirement for surface flatness in the eutectic bonding process and improve the bonding quality.

[0061] In a preferred example, the through-silicon via includes a copper pillar 12 and an aluminum layer 13 on the surface of the copper pillar 12. The through-silicon via can be formed in the semiconductor substrate 11 by a through-silicon via (TSV) process. For example, a via is first formed in the semiconductor substrate 11 by deep silicon etching, and then a metal is deposited in the via to form the through-silicon via. The copper pillar 12 has good electrical conductivity, while the aluminum layer 13 has advantages such as a low melting point. Therefore, it is easy to soften and mutually fuse with the pads of the MEMS micro-heating plate during the subsequent eutectic bonding process. In particular, the eutectic bonding speed between the copper pillar 12 and gold is relatively fast.

[0062] In a preferred example, the method for forming the insulating layer 14 is as follows:

[0063] The insulating layer 14 is formed on the back surface of the semiconductor substrate 11 and the surface of the through-silicon via by chemical vapor deposition. When the semiconductor substrate 11 is a silicon wafer, the insulating layer 14 is preferably a silicon dioxide layer, which helps to reduce interlayer stress and improve interface uniformity. The structure obtained in this step is as Figure 4 shown; of course, the insulating layer 14 can also be made of other insulating materials, such as a silicon oxynitride layer, etc. However, using a silicon dioxide layer not only helps to improve interlayer stress but also helps to simplify the subsequent etching process;

[0064] Chemical mechanical polishing is performed to remove the insulating layer 14 on the surface of the through-silicon via and make the surface of the through-silicon via and the surface of the insulating layer 14 flush. The structure obtained in this step is as Figure 5 shown. Through this step, the interface flatness can be further improved, which helps to improve the subsequent bonding quality.

[0065] In a preferred example, the method for forming a cavity 15 on the back surface of the semiconductor substrate 11 includes:

[0066] A photoresist layer 18 is formed on the insulating layer 14 and the surface of the through-silicon via by using a coating process including but not limited to this. The thickness of the photoresist layer 18 is, for example, 3000 μm - 7000 μm;

[0067] The photoresist layer 18 is patterned to define the cavity 15 pattern. The structure obtained in this step is as Figure 6 shown;

[0068] The insulating layer 14 is dry-etched according to the photoresist layer 18 to form a first part of the cavity 15 in the insulating layer 14. The structure obtained in this step is as Figure 7 shown;

[0069] The corresponding part of the semiconductor substrate 11 is dry-etched to form the cavity 15 with the required depth. The structure obtained in this step is as Figure 8As shown, the depth of the cavity 15 in the semiconductor substrate 11 is preferably 1 / 4 - 3 / 4 of the thickness of the semiconductor substrate 11.

[0070] In a preferred example, before eutectic bonding, the pre-bonding structure and the MEMS micro-heating plate can be cleaned first, for example, cleaned with nitrogen. This can not only effectively remove inorganic and organic pollutants, improve the cleanliness of the bonding surface, but also significantly improve the surface properties of the metal on the bonding surface, enhance the wettability of the solder, reduce the formation of interface voids, and improve the bonding quality.

[0071] The present invention also provides a wafer-level three-dimensional packaging structure for a MEMS gas sensor. The wafer-level three-dimensional packaging structure of the MEMS gas sensor can be prepared based on the packaging method described in any of the foregoing solutions, so the foregoing content can be fully incorporated herein by reference. The wafer-level three-dimensional packaging structure of the MEMS gas sensor is as Figure 10 shown, and includes a semiconductor substrate 11 and a MEMS micro-heating plate bonded to each other. An ASIC chip, a cavity 15, and a plurality of spaced silicon vias are formed in the semiconductor substrate 11. An insulating layer 14 is formed on the surface of the semiconductor substrate 11. The cavity 15 penetrates through the insulating layer 14 and extends into the semiconductor substrate 11. The silicon vias are exposed on the surface of the insulating layer 14. A MEMS device 161 and bonding pads are formed in the MEMS micro-heating plate. The MEMS device 161 faces the cavity 15. The silicon vias are bonded to the electrical connection structure of the MEMS micro-heating plate, such as bonded to the bonding pads composed of a bonding metal layer 166 and a solder metal layer 167. The insulating layer 14 is bonded to the insulating surface of the MEMS micro-heating plate. And in a further example, the bonding pads include a bonding metal layer and a solder metal layer located on the surface of the bonding metal layer. The solder metal layer is bonded to the silicon vias. The bonding metal layer includes a titanium layer and / or a titanium nitride layer. The solder metal layer includes a chromium layer and / or a gold layer.

[0072] For more introduction to the wafer-level three-dimensional packaging structure of the MEMS gas sensor, please refer to the foregoing content. For the sake of brevity, it will not be elaborated. Since it is packaged by the foregoing method, the wafer-level three-dimensional packaging structure of the MEMS gas sensor provided by the present invention has advantages such as high bonding quality and good heat dissipation performance.

[0073] In summary, the present invention provides a wafer-level three-dimensional packaging method and structure for a MEMS gas sensor. The packaging method includes the steps of: providing a semiconductor substrate, in which an ASIC chip and a plurality of spaced silicon vias are formed, and one end of each silicon via is exposed on the front surface of the semiconductor substrate; thinning the back surface of the semiconductor substrate so that the other end of the silicon via is flush with the back surface of the semiconductor substrate, and the front surface and the back surface are two opposite surfaces; etching the back surface of the semiconductor substrate so that the surface of the silicon via protrudes from the back surface of the semiconductor substrate; forming an insulating layer on the back surface of the semiconductor substrate; performing chemical mechanical polishing on the back surface of the semiconductor substrate to expose the silicon via; performing photolithography and dry etching to form a cavity on the back surface of the semiconductor substrate, the cavity penetrating the insulating layer and extending into the semiconductor substrate, thereby obtaining a pre-bonding structure; eutectically bonding a MEMS micro-heating plate formed with a MEMS device and the pre-bonding structure, the back surface of the semiconductor substrate and the surface where the MEMS device is located being the bonding surfaces, the MEMS device facing the cavity, the silicon via being bonded to the bonding pad of the MEMS micro-heating plate, and the insulating layer being bonded to the insulating surface of the MEMS micro-heating plate; forming silicon via solder balls on the surface of the silicon via on the front surface of the ASIC chip; and dicing to form single MEMS gas sensor chips. The present invention prepares a MEMS gas sensor by using a three-dimensional packaging technology of silicon vias and a backside copper exposure process, and combines an eutectic bonding method for wafer-level bonding and packaging of the ASIC and the MEMS micro-heating plate, which helps to improve the bonding performance and the manufacturing process efficiency. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0074] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer-level three-dimensional packaging method for a MEMS gas sensor, characterized in that, Including the steps: Providing a semiconductor substrate, in which an ASIC chip and a plurality of silicon vias arranged at intervals are formed, and one end of each silicon via is exposed on the front surface of the semiconductor substrate; Performing back thinning on the semiconductor substrate so that the other end of the silicon via is flush with the back surface of the semiconductor substrate, and the front surface and the back surface are two opposite surfaces; Etching the back surface of the semiconductor substrate so that the surface of the silicon via protrudes from the back surface of the semiconductor substrate; Forming an insulating layer on the back surface of the semiconductor substrate; Performing chemical mechanical polishing on the back surface of the semiconductor substrate to expose the silicon via; Performing photolithography and dry etching to form a cavity on the back surface of the semiconductor substrate, the cavity penetrating the insulating layer and extending into the semiconductor substrate, and the depth of the cavity in the semiconductor substrate being 1 / 4 to 3 / 4 of the thickness of the semiconductor substrate, thereby obtaining a pre-bonding structure; Performing eutectic bonding on the MEMS micro-heating plate formed with MEMS devices and the pre-bonding structure, the MEMS device facing the cavity, the silicon via being bonded to the solder pad of the MEMS micro-heating plate, and the insulating layer being bonded to the insulating surface of the MEMS micro-heating plate; Forming silicon via solder balls on the surface of the silicon via on the front surface of the ASIC chip; Cutting to form single MEMS gas sensor chips.

2. The wafer-level three-dimensional packaging method for a MEMS gas sensor according to claim 1, characterized in that, The silicon via includes a copper pillar and an aluminum layer on the surface of the copper pillar.

3. The wafer-level three-dimensional packaging method for a MEMS gas sensor according to claim 1, characterized in that, The process of performing back thinning on the semiconductor substrate includes CMP.

4. The wafer-level three-dimensional packaging method for a MEMS gas sensor according to claim 1, characterized in that, The method for forming the insulating layer is: Using chemical vapor deposition process to form the insulating layer on the back surface of the semiconductor substrate and the surface of the silicon via; Performing chemical mechanical polishing to remove the insulating layer on the surface of the silicon via, and at the same time making the surface of the silicon via flush with the surface of the insulating layer.

5. The wafer-level three-dimensional packaging method for a MEMS gas sensor according to claim 1, characterized in that, The semiconductor substrate includes a silicon wafer, and the insulating layer includes a silicon dioxide layer.

6. The wafer-level three-dimensional packaging method for a MEMS gas sensor according to claim 5, characterized in that, The method for forming a cavity on the back surface of the semiconductor substrate includes: Forming a photoresist layer on the insulating layer and the surface of the silicon via; Performing patterning on the photoresist layer to define a cavity pattern; Dry etching the insulating layer according to the photoresist layer to form a first part of the cavity in the insulating layer; Dry etching the corresponding part of the semiconductor substrate to form the cavity with a required depth.

7. The wafer-level three-dimensional packaging method for a MEMS gas sensor according to claim 1, characterized in that, The MEMS micro-heating plate includes a silicon substrate, a silicon oxide layer, and a silicon nitride layer from bottom to top, the solder pad is formed in the silicon nitride layer, the MEMS device is formed on the silicon oxide layer, and during the bonding process, the silicon nitride layer is bonded to the insulating layer on the surface of the semiconductor substrate.

8. The wafer-level three-dimensional packaging method for a MEMS gas sensor according to claim 7, characterized in that, The solder pad includes a bonding metal layer and a solder metal layer on the surface of the bonding metal layer, the solder metal layer is bonded to the silicon via, the bonding metal layer includes a titanium layer and / or a titanium nitride layer, and the solder metal layer includes a chromium layer and / or a gold layer.

9. A wafer-level three-dimensional packaging structure for a MEMS gas sensor, characterized in that, The wafer-level three-dimensional packaging structure of the MEMS gas sensor is prepared by using the wafer-level three-dimensional packaging method of the MEMS gas sensor described in any one of claims 1 to 8. The wafer-level three-dimensional packaging structure of the MEMS gas sensor includes a semiconductor substrate and a MEMS micro-heating plate bonded to each other. An ASIC chip, a cavity, and a plurality of silicon vias spaced apart are formed in the semiconductor substrate. An insulating layer is formed on the surface of the semiconductor substrate. The cavity penetrates through the insulating layer and extends into the semiconductor substrate. The silicon vias are exposed on the surface of the insulating layer. A MEMS device and bonding pads are formed in the MEMS micro-heating plate. The MEMS device faces the cavity. The insulating layer and the insulating surface of the MEMS micro-heating plate are bonded. The silicon vias and the bonding pads are bonded by eutectic bonding.

10. The wafer-level three-dimensional packaging structure for a MEMS gas sensor according to claim 9, characterized in that,The bonding pads include a bonding metal layer and a solder metal layer located on the surface of the bonding metal layer. The solder metal layer is bonded to the silicon vias. The bonding metal layer includes a titanium layer and / or a titanium nitride layer. The solder metal layer includes a chromium layer and / or a gold layer.

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