A fault detection apparatus, method, device and electronic device

Abstract

The application discloses a kind of fault detection equipment, method, device and electronic equipment, comprising: PID controller component, digital-analog converter, debugging digital-analog converter, analog-digital converter and electric driver, digital-analog converter, debugging digital-analog converter, analog-digital converter are connected with PID controller component respectively, and analog-digital converter and electric driver are used to be connected with measured device;Processor is used to indicate the test parameter for being used to test measured device to PID controller component and obtains the test data generated after testing from PID controller component, and digital-analog converter is used to input measured device by electric driver after the conversion of test parameter;Analog-digital converter is used to input PID controller component after the conversion of obtained test data, and debugging digital-analog converter is used to carry out digital-analog conversion to the test data input to PID controller component;External measuring instrument is used to display analog signal corresponding to test data.

Description

Technical Field

[0001] This invention relates to the field of testing technology, and specifically to a fault detection device, method, apparatus, and electronic equipment. Background Technology

[0002] A Device Under Test (DUT) is a manufactured product that is tested during initial manufacturing or later in its lifecycle. Existing technologies typically use Automatic Test Equipment (ATE) to test the DUT. However, since the ATE used for testing is usually controlled by a Field Programmable Gate Array (FPGA) of a Source Unit (SMU), and the SMU also includes components such as digital-to-analog converters (DACs), analog-to-digital converters (ADCs), and electrical drivers, when a fault occurs during ATE testing, the cause may originate from these components within the ATE itself. In related technologies, probes are generally used to probe the ATE components; however, due to the load effect of the probes, the probe results are inaccurate. Therefore, there is an urgent need to propose a new fault detection method to accurately locate the cause of faults when using ATE to test the DUT. Summary of the Invention

[0003] Therefore, the technical problem to be solved by the present invention is to overcome the defect of inaccurate detection results of existing fault cause detection methods when using ATE to test DUT, thereby providing a fault detection device, method, apparatus and electronic device.

[0004] According to a first aspect, embodiments of the present invention disclose a fault detection device, comprising: a field-programmable gate array (FPGA), the FPGA including a PID controller component; a source table unit, the source table unit including a digital-to-analog converter (DAC), a debugging DAC, an analog-to-digital converter (ADC), and an electrical driver, the DAC, the debugging DAC, and the ADC being respectively connected to the PID controller component in the FPGA, the ADC and the electrical driver being used to connect to a device under test (DUT); and a processor, respectively connected to the PID controller component and the debugging DAC, used to instruct the PID controller component to perform fault detection on the device under test (DUT). The system includes test parameters for testing the device under test (DUT) and test data generated after testing the DUT using the test parameters, obtained from the PID controller component; a digital-to-analog converter (DAC) for converting the test parameters from digital to analog and inputting them to the DUT via the electric driver; an analog-to-digital converter (ADC) for converting the acquired DUT test data from analog to digital and inputting it to the PID controller component; a debugging DAC for converting the test data input to the PID controller component from digital to analog; and an external measuring instrument, connected on one side to the debugging DAC and on the other side to the processor, for displaying the analog signal corresponding to the test data of the DUT.

[0005] Optionally, the external measuring instrument includes: a digital instrument and / or an oscilloscope.

[0006] According to a second aspect, embodiments of the present invention disclose a fault detection method for use with the fault detection device described in the first aspect or any optional embodiment of the first aspect; the method includes: reading an analog signal from an external measuring instrument after testing a DUT (Distributed Under Test) using test parameters; comparing the analog signal with the test parameters to obtain a test result; when the test result is abnormal, testing a reference DUT using the same test parameters, wherein the reference DUT represents a DUT that has been tested and whose test result is normal; when the test result of the reference DUT is normal, determining that the DUT to be tested has a fault.

[0007] Optionally, the method further includes: if the test result of the reference DUT is still abnormal, then the cause of the fault is determined to be a fault in the reference DUT or a fault in a component of the fault detection device.

[0008] Optionally, comparing the analog signal with the test parameters to obtain the test result includes: determining the correlation between the analog signal and the indicated test parameters for testing the device under test; if the analog signal is not correlated with the indicated test parameters for testing the device under test, the test result is determined to be abnormal.

[0009] According to a third aspect, embodiments of the present invention also disclose a fault detection device for use with the fault detection equipment described in the first aspect or any optional embodiment of the first aspect; the device includes: a reading module, used to read analog signals from an external measuring instrument after testing a DUT under test using test parameters; a comparison module, used to compare the analog signals with the test parameters to obtain a test result; a testing module, used to test a reference DUT using the same test parameters when the test result is abnormal, wherein the reference DUT represents a DUT that has been tested and whose test result is normal; and a first determination module, used to determine that the DUT under test has a fault when the test result of the reference DUT is normal.

[0010] Optionally, the device further includes a second determination module, configured to determine that the fault is caused by a fault in the reference DUT or a fault in a component of the fault detection device when the test result of the reference DUT is still abnormal.

[0011] Optionally, the comparison module includes: a determination submodule, used to determine the correlation between the analog signal and the indicated test parameters for testing the device under test; and a judgment submodule, used to determine that the test result is abnormal when the analog signal and the indicated test parameters for testing the device under test are not correlated.

[0012] According to a fourth aspect, embodiments of the present invention also disclose an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the steps of the fault detection method as described in the second aspect or any optional embodiment of the second aspect.

[0013] According to a fifth aspect, embodiments of the present invention also disclose a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the fault detection method as described in the second aspect or any optional embodiment of the second aspect.

[0014] The technical solution of this invention has the following advantages:

[0015] The fault detection device provided by this invention includes: a PID controller component, a digital-to-analog converter (DAC), a debugging DAC, an analog-to-digital converter (ADC), and an electric driver. The DAC, debugging DAC, and ADC are respectively connected to the PID controller component. The ADC and the electric driver are used to connect to the device under test (DUT). A processor is used to instruct the PID controller component on test parameters for testing the DUT and to acquire test data generated after testing from the PID controller component. The DAC converts the test parameters and inputs them to the DUT through the electric driver. The ADC converts the acquired test data and inputs it to the PID controller component. The debugging DAC converts the test data input to the PID controller component. An external measuring instrument is used to display the analog signal corresponding to the test data, so that the processor can compare the indicated test parameters with the analog signal corresponding to the read test data to locate the fault. Compared with the prior art of directly using probes for fault detection, this method can further improve the accuracy of fault location during DUT testing.

[0016] The fault detection method / apparatus provided by this invention involves reading analog signals from an external measuring instrument after testing a Device Under Test (DUT) using test parameters. The analog signals are then compared with the indicated test parameters used to test the DUT to obtain the test result. If the test result is abnormal, a reference DUT is tested using the same test parameters. If the test result for the reference DUT is normal, the DUT under test is determined to be faulty. When an abnormal test result is determined by comparing the read analog signals with the indicated test parameters, a previously tested DUT with normal test results is tested again using the same test parameters. If the test result is normal, the cause of the abnormality is determined to be a fault in the DUT itself. If the test result for the reference DUT is still abnormal, the cause of the fault is determined to be a fault in the reference DUT or a fault in a component of the fault detection device. Compared to the prior art method of directly using probes for fault detection, the method provided by this invention can further improve the accuracy of fault location during DUT testing. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a specific example of a fault detection device in an embodiment of the present invention;

[0019] Figure 2 This is a flowchart illustrating a specific example of the fault detection method in an embodiment of the present invention;

[0020] Figure 3 This is a schematic block diagram of a specific example of a fault detection device in an embodiment of the present invention;

[0021] Figure 4 This is a specific example diagram of an electronic device in an embodiment of the present invention. Detailed Implementation

[0022] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] In the description of this invention, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0025] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] This invention discloses a fault detection device, such as... Figure 1 As shown, it includes:

[0027] A field-programmable gate array (FPGA) 101 includes a PID controller component 1011;

[0028] Source meter unit 102 includes a digital-to-analog converter (DAC) 1021, a debug DAC 1022, an analog-to-digital converter (ADC) 1023, and an electrical driver 1024. The DAC 1021, debug DAC 1022, and ADC 1023 are respectively connected to the PID controller component 1011 in the field-programmable gate array 101. The ADC 1023 and the electrical driver 1024 are used to connect to the device under test 104.

[0029] The processor 103 is connected to the PID controller component 1011 and the debugging digital-to-analog converter 1022, respectively, and is used to indicate to the PID controller component 1011 test parameters for testing the device under test 104 and to obtain from the PID controller component 1011 test data generated after testing the device under test 104 using the test parameters.

[0030] The digital-to-analog converter 1021 is used to convert the test parameters from digital to analog and then input them to the device under test 104 via the electric driver 1024; the analog-to-digital converter 1023 is used to convert the acquired test data from the device under test 104 from analog to digital and then input it to the PID controller component 1011; the debugging digital-to-analog converter 1022 is used to convert the test data input to the PID controller component 1011 from digital to analog.

[0031] An external measuring instrument 105, connected on one side to the debugging digital-to-analog converter 1022 and on the other side to the processor 103, is used to display the analog signal corresponding to the test data of the device under test 104. Exemplarily, the external measuring instrument can be used to display the real-time analog signal corresponding to the test data of the debugging DAC driver. This application embodiment does not limit the type of external measuring instrument; those skilled in the art can determine it according to actual needs. In this application embodiment, the external measuring instrument can be a digital instrument and / or an oscilloscope. By setting an external measuring instrument, users can easily view the analog signal corresponding to the test data.

[0032] When an ATE (Automatic Test Equipment) malfunctions, it is usually due to electrical drift that occurs over time due to frequent use. While this defect can be caused by any component within the ATE, it is typically caused by the output of the PID controller component. Therefore, the output of the PID controller component is siphoned to a debug DAC to monitor output faults in the PID controller component. In this embodiment, a debug digital-to-analog converter is used as an example. When it is necessary to acquire the outputs of multiple components, multiple debug digital-to-analog converters can be set up to acquire test data from the corresponding component outputs.

[0033] The fault detection device provided in this application includes: a PID controller component, a digital-to-analog converter (DAC), a debugging DAC, an analog-to-digital converter (ADC), and an electric driver. The DAC, debugging DAC, and ADC are connected to the PID controller component, and the ADC and electric driver are used to connect to the device under test (DUT). A processor is used to instruct the PID controller component on test parameters for testing the DUT and to acquire test data generated after testing from the PID controller component. The DAC converts the test parameters and inputs them to the DUT through the electric driver. The ADC converts the acquired test data and inputs it to the PID controller component. The debugging DAC converts the test data input to the PID controller component and sends it to the processor. An external measuring instrument is used to display the analog signal corresponding to the test data, so that the processor can compare the indicated test parameters with the analog signal corresponding to the read test data to locate the fault. Compared with the prior art, which directly uses probes for fault detection, this method can further improve the accuracy of fault location during DUT testing.

[0034] This invention discloses a fault detection method for use with the fault detection device described in the above embodiments. For example... Figure 2 As shown, the method includes the following steps:

[0035] Step 201: After testing the DUT using the test parameters, read the analog signal from an external measuring instrument. For example, the test parameters for testing the DUT can be pre-programmed into the processor's test program. The processor instructs the test parameters to the DUT to perform the test, and can acquire the test data of the DUT in real time. The processor can also read the corresponding analog signal from an external measuring instrument. Specifically, the PID controller component instructs the SMU to provide the required voltage or current to the DUT according to the test requirements. The ADC measures the voltage and current provided to the DUT by the SMU, and then sends the test data to the FPGA and then to the PID controller component, which in turn transmits it to the processor.

[0036] The analog signal can be the analog signal corresponding to all test data received by the PID controller component, or it can be the analog signal of the test data output from the PID controller component to the debug DAC controlled by the test program in the processor, so that the external measuring instrument displays the corresponding type of test data. This application does not limit the type of analog signal displayed by the external measuring instrument; those skilled in the art can determine it according to actual needs, as long as the displayed analog signal can be used to determine whether a test fault has occurred.

[0037] Step 202: Compare the analog signal with the test parameters to obtain the test result;

[0038] As an optional embodiment of the present invention, step 202 includes: determining the correlation between the analog signal and the indicated test parameters for testing the device under test; when the analog signal and the indicated test parameters for testing the device under test are not correlated, the test result is determined to be abnormal.

[0039] For example, the comparison method of correlation may include determining whether the test parameters are the same as or correlated with the waveform parameters of the read analog signal. If they are the same or correlated, it indicates that no fault has occurred in the test process. If the analog signal is not correlated with the test parameters indicated for testing the device under test, the test result is determined to be abnormal.

[0040] Step 203: When the test result is abnormal, the same test parameters are used to test the reference DUT, wherein the reference DUT represents the DUT that has been tested and the test result is normal.

[0041] Step 204: When the test result of the reference DUT is normal, it is determined that the DUT under test has failed. As an optional embodiment of the present invention, the method further includes: when the test result of the reference DUT is still abnormal, it is determined that the cause of the failure is a failure of the reference DUT or a failure of a component in the fault detection device.

[0042] For example, a problem in mass production of DUTs is that even if a DUT has previously passed inspection by a fault detection device, it may still be detected as faulty upon retesting. This may be due to variations in testing accuracy or DUT manufacturing precision. Therefore, when a fault detection device is used to retest a DUT that has already been tested and whose test results are normal, and the test result is still abnormal, it indicates that the cause of the abnormality is either a fault in a component of the fault detection device itself, or a defect in the DUT produced during mass production. To further confirm the cause of the abnormality, other testing methods can be used to inspect the components in the fault detection device or a reference DUT. If it is determined that the fault in the fault detection device itself is faulty, the fault detection device should be removed from the production line. If it is determined that the fault is in a reference DUT, it may be necessary to halt production and inspect the entire DUT production line.

[0043] The fault detection method provided by this invention determines that when an abnormal test result is found by comparing the read analog signal with the indicated test parameters, the same test parameters are used to retest the DUT that has already been tested and whose test result is normal. If the test result is normal, the abnormality can be attributed to a fault in the DUT itself. If the test result for the reference DUT is still abnormal, the fault is determined to be a fault in the reference DUT or a fault in a component of the fault detection device. Compared with the prior art, which directly uses probes for fault detection, the method provided by this invention can further improve the accuracy of fault location during DUT testing.

[0044] This invention also discloses a fault detection device for use with the fault detection equipment described in the above embodiments. For example... Figure 3 As shown, the device includes:

[0045] The reading module 301 is used to read analog signals from an external measuring instrument after testing the DUT using test parameters;

[0046] The comparison module 302 is used to compare the analog signal with the test parameters to obtain the test result;

[0047] Test module 303 is used to test a reference DUT using the same test parameters when the test result is abnormal, wherein the reference DUT represents a DUT that has been tested and the test result is normal;

[0048] The first determination module 304 is used to determine that the DUT under test has a fault when the test result of the reference DUT is normal.

[0049] The fault detection device provided by this invention determines that when an abnormal test result is found by comparing the read analog signal with the indicated test parameters, it retests the DUT that has already been tested and whose test result is normal using the same test parameters. If the test result is normal, the cause of the abnormality is that the DUT itself is faulty. If the test result of the reference DUT is still abnormal, the cause of the fault is determined to be a fault in the reference DUT or a fault in a component of the fault detection device. Compared with the prior art of directly using probes for fault detection, the method provided by this invention can further improve the accuracy of fault location during the DUT testing process.

[0050] As an optional embodiment of the present invention, the device further includes: a second determination module, used to determine that the fault is caused by a fault in the reference DUT or a fault in a component of the fault detection device when the test result of the reference DUT is still abnormal.

[0051] As an optional embodiment of the present invention, the comparison module includes: a determination submodule, used to determine the correlation between the analog signal and the indicated test parameters for testing the device under test; and a judgment submodule, used to determine that the test result is abnormal when the analog signal and the indicated test parameters for testing the device under test are not correlated.

[0052] This invention also provides an electronic device, such as... Figure 4 As shown, the electronic device may include a processor 401 and a memory 402, wherein the processor 401 and the memory 402 may be connected via a bus or other means. Figure 4 Taking the example of a connection between China and Israel via a bus.

[0053] Processor 401 can be a central processing unit (CPU). Processor 401 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other field-programmable logic gate arrays, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0054] The memory 402, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the fault detection method in the embodiments of the present invention. The processor 401 executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions, and modules stored in the memory 402, thereby implementing the fault detection method in the above method embodiments.

[0055] The memory 402 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor 401, etc. Furthermore, the memory 402 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 402 may optionally include memory remotely located relative to the processor 401, and these remote memories may be connected to the processor 401 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0056] The one or more modules are stored in the memory 402, and when executed by the processor 401, they perform actions such as... Figure 2 The fault detection method in the illustrated embodiment.

[0057] For specific details regarding the aforementioned electronic devices, please refer to the relevant documentation. Figure 2 The relevant descriptions and effects in the illustrated embodiments are for understanding purposes only and will not be repeated here.

[0058] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0059] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A fault detection device, characterized by, The method comprises: a field programmable logic gate array, wherein a PID controller component is contained; a source table unit, wherein a digital-to-analog converter, a debugging digital-to-analog converter, an analog-to-digital converter and an electric driver are contained, the digital-to-analog converter, the debugging digital-to-analog converter and the analog-to-digital converter are connected with the PID controller component in the field programmable logic gate array respectively, and the analog-to-digital converter and the electric driver are used to be connected with a device under test; a processor connected with the PID controller component and the debugging digital-to-analog converter respectively, used to indicate test parameters for testing the device under test to the PID controller component and acquire test data generated after the device under test is tested by using the test parameters from the PID controller component; the digital-to-analog converter is used to convert the test parameters into analog signals and input the analog signals into the device under test through the electric driver; the analog-to-digital converter is used to convert the acquired test data of the device under test into digital signals and input the digital signals into the PID controller component, and the debugging digital-to-analog converter is used to convert the test data input into the PID controller component into analog signals; an external measuring instrument connected with the debugging digital-to-analog converter on one side and connected with the processor on the other side, used to display analog signals corresponding to the test data of the device under test; the processor is further used to compare the analog signals with the test parameters, when an abnormal test result is obtained by comparison, test a reference DUT by using the same test parameters, wherein the reference DUT represents a DUT that has been tested and has a normal test result, and when a normal test result is obtained by testing the reference DUT, it is determined that the DUT to be tested is faulty.

2. The fault detection device of claim 1, wherein, The external measuring instrument comprises a digital instrument and / or an oscilloscope.

3. A failure detection method for the failure detection device according to claim 1 or 2, characterized by, The method comprises: reading analog signals from an external measuring instrument after a device under test is tested by using test parameters; comparing the analog signals with the test parameters to obtain a test result; when the test result is abnormal, testing a reference DUT by using the same test parameters, wherein the reference DUT represents a DUT that has been tested and has a normal test result; when a normal test result is obtained by testing the reference DUT, it is determined that the DUT to be tested is faulty. The method further comprises:

4. The method of claim 3, wherein, when the test result of the reference DUT is still abnormal, it is determined that the fault reason is that the reference DUT is faulty or a component in the fault detection device is faulty. The comparison of the analog signals with the test parameters to obtain a test result comprises:

5. The method of claim 3, wherein, determining a correlation between the analog signals and the indicated test parameters for testing the device under test; when the analog signals are not correlated with the indicated test parameters for testing the device under test, it is determined that the test result is abnormal.

6. A fault detection device for the fault detection apparatus in claim 1 or 2; The device comprises: characterized in that a reading module used to read analog signals from an external measuring instrument after a device under test is tested by using test parameters; ​ a comparison module, configured to compare the analog signal with the test parameter to obtain a test result; a test module, configured to test a reference DUT with the same test parameter when the test result is abnormal, wherein the reference DUT represents a DUT that has been tested and has a normal test result; a first determination module, configured to determine that the DUT to be tested is faulty when a test result of the reference DUT is normal.

7. The apparatus of claim 6, wherein, The apparatus further comprises: a second determination module, configured to determine that the fault is caused by the reference DUT being faulty or a component in the fault detection device being faulty when the test result of the reference DUT is still abnormal.

8. The apparatus of claim 6, wherein, The comparison module comprises: a determination sub-module, configured to determine a correlation between the analog signal and the test parameter indicated for testing the DUT; a determination sub-module, configured to determine that the test result is abnormal when the analog signal is not correlated with the test parameter indicated for testing the DUT. comprise:

9. An electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to cause the at least one processor to perform steps of the fault detection method according to any one of claims 3-5. The computer program is executed by the processor to implement steps of the fault detection method according to any one of claims 3-5.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, ​

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