A method for identifying intermittent states of electronic products and preventing false alarms using BIT

Abstract

The present invention belongs to the technical field of electronic product testability design, and specifically relates to a method for identifying intermittent states of electronic products and preventing BIT false alarms. The method transforms the electronic equipment system state from the traditional two-state assumption ("normal" and "hard fault") to a three-state assumption ("normal," "intermittent," and "hard fault"), wherein the "intermittent" state further includes two sub-states: "intermittent fault" and "intermittent recovery." The method of the present invention is used to determine the system state based on the embedded test (BIT) sequence of the electronic product. While achieving electronic product state assessment, the intermittent state can be identified, effectively improving the electronic product state assessment performance and reducing the BIT false alarm rate during use.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic product testability design, and in particular relates to an electronic product intermittent state recognition and BIT false alarm prevention method. Background Art

[0002] Testability refers to a design feature that enables a product to accurately and promptly determine its status (operating, inoperable, or degraded) and isolate internal faults. Built-in testing (BIT) is a key component of product testability design. BIT (electronics embedded testing) refers to the automated testing capability provided within a system or device to detect and isolate faults. It can significantly improve system test performance and fault diagnosis capabilities, and is gaining increasing attention in the testability design of various electronic devices. However, high false alarm rates remain a major issue plaguing BIT technology research and application. BIT false alarms are a significant factor contributing to low availability and high maintenance costs for electronic products.

[0003] Data from the US military and the electronics industry indicates that intermittent faults are a major cause of false BIT alarms in electronic systems, accounting for 30% to 40% of false BIT alarms. Intermittent faults are characterized by their random appearance and disappearance, with their occurrence occurring at random times, impacting the system within a limited, unpredictable timeframe.

[0004] The uncertainty of intermittent faults causes uncertainties such as cannot be reproduced (CND) and retest to be acceptable (RTOK), which will lead to BIT false alarms.

[0005] Commonly used BIT false alarm mitigation techniques include repetitive testing and voting testing. The repetitive testing method requires that after a BIT detects a fault, it will only report the fault after it has been detected multiple times (e.g., three times) in a row. The voting testing method requires that the fault is not reported until m (n>m>n / 2) of n tests have been detected. The problem with both methods is that m and n are predetermined and may not represent specific fault conditions. For example, if either m or n is low, a certain number (possibly all) of the false alarms will be attributed solely to the selection of m or n, rather than to any hardware fault. Furthermore, neither method can identify intermittent faults. Summary of the Invention

[0006] In light of this, to reduce BIT false alarms in electronic products under complex mission profiles and environmental conditions, a method for identifying intermittent states and preventing BIT false alarms for electronic products was proposed. This method can simultaneously assess the status of electronic products and identify intermittent states, effectively improving the performance of electronic product status assessment and reducing the BIT false alarm rate during use.

[0007] In order to achieve the above technical objectives, the specific technical solutions adopted by the present invention are:

[0008] A method for identifying intermittent states of electronic products and preventing BIT false alarms, comprising the following steps:

[0009] S101 establishes a state transition model of the unit under test; the states of the model include: normal state, intermittent state and hard fault state; the intermittent state includes intermittent fault state and intermittent recovery state;

[0010] S102 Intermittent state identification of the unit under test:

[0011] S102.1 assumes that the unit under test is initially in a normal state. Continuous electronic product embedded testing (BIT) monitoring is performed on the unit under test to obtain a judgment result, which is a time series under a normal state: X Norm =[x1,x2,L,x N ];

[0012] S102.2: Obtain P0 and P1 based on the time series; if P1 decreases to a set threshold, the unit under test enters an intermittent state;

[0013] S103 Status evaluation and false alarm suppression of the unit under test:

[0014] S103.1 When the unit under test enters the intermittent state, obtain multiple embedded test samples of the electronic product and obtain more accurate estimates of P0 and P1 after multiple evaluations;

[0015] S103.2 Continue to record K0 or K1 times of electronic product embedded test, and obtain the time series X in the intermittent state. intm =[x1,x2,L,x N ], using the time series X intm Estimate and correct P0 and P1;

[0016] S103.3 Perform state assessment based on the definition of the state transition model;

[0017] S103.4 When switching between intermittent fault state and intermittent recovery state, the current K 0i or K 1j Sub-electronic product embedded test data is added to the time series X intm , and using the supplemented X intm Re-estimate P0 and P1;

[0018] S103.5 Repeat S103.3 and S103.4 until the UUT exits the intermittent state or the UUT task execution is completed;

[0019] in:

[0020] P0: The probability of transition from intermittent recovery state to intermittent fault state;

[0021] P1: The probability of transition from intermittent fault state to intermittent recovery state;

[0022] P K : confidence of state transition;

[0023] K0: Between probability P0 and confidence P K Under this condition, determine the number of embedded tests of electronic products required to transfer from intermittent fault state to intermittent recovery state;

[0024] K1: Between probability P1 and confidence P K Under this condition, the number of embedded tests of electronic products required to determine the transition from intermittent fault state to intermittent recovery state is determined.

[0025] Furthermore, the set threshold is a large value close to 1.

[0026] Furthermore, in S103.3, the method for status assessment includes the following steps:

[0027] S103.31 Set the initial state to normal by default;

[0028] S103.32 Continue to run the embedded test of the electronic product until a fault is reported;

[0029] S103.33 Dynamically evaluate P0 and P1 until P1 < 0.9;

[0030] S103.34 performs N electronic product embedded test samplings and dynamically estimates P0 and P1 based on the samples;

[0031] S103.34: Select whether the current electronic product embedded test reports a fault. If so, the system state switches to an intermittent fault state and performs K0 = f(P0) electronic product embedded test sampling times. If not, the system state switches to an intermittent recovery state and performs K1 = f(P1) electronic product embedded test sampling times.

[0032] If there are faults in all K1 electronic product embedded test samples, the system switches to a hard fault state. If not, reselect whether to report a fault in the current electronic product embedded test;

[0033] If K0 electronic product embedded test samples are all normal, then enter S103.31, if not, then reselect whether the current electronic product embedded test reports a fault.

[0034] Furthermore, the state of the model also includes a recovery state; in S101, the transition between the states is as follows:

[0035] The unit under test starts from the normal state and switches to the intermittent fault state when the intermittent state identification conditions are met;

[0036] In the intermittent fault state, if the electronic product embedded test passes once, it will be converted to intermittent recovery. Otherwise, if it fails K1 times continuously, it will be converted to hard fault state;

[0037] In the intermittent recovery state, if the electronic product embedded test fails once, it will be converted to the intermittent fault state. Otherwise, if it succeeds K0 times continuously, it will be converted to normal;

[0038] In the hard fault state, if the electronic product passes the embedded test once, it will be converted to the recovery state.

[0039] Furthermore, the calculation method of each parameter is:

[0040] Let the time series X=[x1,x2,L,x N ], x i =0 means the i-th BIT test passed, x i =1 means the i-th BIT test failed;

[0041] If there are S 0s in X, and x i =0,x i+1 =1 i There are s in total, then P0=s / S;

[0042] If there are F 1s in X, and x j =1,x j+1 =0 j There are f in total, then P1=f / F;

[0043] Suppose the probability of a random event is P. According to Bernoulli's random variable theory, the probability of an event occurring in no more than K trials is:

[0044] P K =1-(1-P) K

[0045] Given P, satisfy the confidence level P K The K value is:

[0046] K≥ceil(log(1-P K ) / log(1-P))

[0047] Where ceil(·) means rounding up, then:

[0048] K0=ceil(log(1-P K) / log(1-P0)), K1=ceil(log(1-P K ) / log(1-P1)).

[0049] Furthermore, between S103.3 and S103.4, the following steps are included:

[0050] S201: When in an intermittent state, the occurrence probabilities P0 and P1 of intermittent failure and intermittent recovery are recorded for the user of the unit under test to assess the risk of continued use.

[0051] Furthermore, the S103.5 is also used to repeat the S201.

[0052] By adopting the above technical solution, the present invention addresses the BIT false alarm problem of electronic products under complex mission profiles and environmental conditions and proposes a method for identifying intermittent faults and preventing BIT false alarms in electronic products. This method involves state transition process modeling, intermittent state identification, and BIT data processing technology. Compared with existing repeated BIT false alarm reduction technologies or voting BIT false alarm reduction technologies, it has the following advantages:

[0053] 1. The present invention can identify intermittent status while implementing electronic product status assessment and automatically adjust the status assessment method;

[0054] 2. The present invention can greatly reduce the false alarm rate of electronic products in intermittent state;

[0055] 3. The present invention only requires improvements in BIT data processing technology and does not require modification of hardware circuits, making engineering implementation simple.

[0056] The present invention is applicable to the field of electronic product testability design, can effectively improve the electronic product status assessment performance and availability, and reduce the BIT false alarm rate during use. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0058] Figure 1 This is a state transition model diagram of an electronic product intermittent state recognition and BIT false alarm prevention method in a specific embodiment of the present invention;

[0059] Figure 2 This is a flow chart of a state assessment method for electronic product intermittent state recognition and BIT false alarm prevention in a specific embodiment of the present invention;

[0060] Figure 3 A graph of BIT time series data based on an electronic product intermittent state identification and BIT false alarm prevention method in a specific embodiment of the present invention;

[0061] Figure 4 In a specific embodiment of the present invention, a state determination result of a unit under test in an electronic product intermittent state identification and BIT false alarm prevention method;

[0062] Figure 5 This is a comparison diagram of the effects of an electronic product intermittent state recognition and BIT false alarm prevention method according to a specific embodiment of the present invention and a traditional method. DETAILED DESCRIPTION

[0063] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0064] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0065] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0066] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0067] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0068] In one embodiment of the present invention, a method for identifying intermittent states of electronic products and preventing BIT false alarms is proposed, comprising the following steps:

[0069] S101 establishes a state transition model of the unit under test; the states of the model include: normal state, intermittent state and hard fault state; the intermittent state includes intermittent fault state and intermittent recovery state;

[0070] S102 Intermittent state identification of the unit under test:

[0071] S102.1 assumes that the unit under test is initially in a normal state. Continuous electronic product embedded testing (BIT) monitoring is performed on the unit under test to obtain a judgment result, which is a time series under a normal state: X Norm =[x1,x2,L,x N ];

[0072] S102.2: Obtain P0 and P1 based on the time series; if P1 decreases to a set threshold, the unit under test enters an intermittent state;

[0073] S103 Status evaluation and false alarm suppression of the unit under test:

[0074] S103.1 When the unit under test enters the intermittent state, obtain multiple embedded test samples of the electronic product and obtain more accurate estimates of P0 and P1 after multiple evaluations;

[0075] S103.2 Continue to record K0 or K1 times of electronic product embedded test, and obtain the time series X in the intermittent state. intm =[x1,x2,L,x N ], using the time series X intm Estimate and correct P0 and P1;

[0076] S103.3 Perform state assessment based on the definition of the state transition model;

[0077] S103.4 When switching between intermittent fault state and intermittent recovery state, the current K 0i or K 1j Sub-electronic product embedded test data is added to the time series X intm , and using the supplemented X intm Re-estimate P0 and P1;

[0078] S103.5 Repeat S103.3 and S103.4 until the UUT exits the intermittent state or the UUT task execution is completed;

[0079] in:

[0080] P0: The probability of transition from intermittent recovery state to intermittent fault state;

[0081] P1: The probability of transition from intermittent fault state to intermittent recovery state;

[0082] P K : confidence of state transition;

[0083] K0: Between probability P0 and confidence P K Under this condition, determine the number of embedded tests of electronic products required to transfer from intermittent fault state to intermittent recovery state;

[0084] K1: Between probability P1 and confidence P K Under this condition, the number of embedded tests of electronic products required to determine the transition from intermittent fault state to intermittent recovery state is determined.

[0085] In one embodiment, the set threshold is a large value close to 1.

[0086] In S103.3, the method for condition assessment includes the following steps:

[0087] S103.31 Set the initial state to normal by default;

[0088] S103.32 Continue to run the embedded test of the electronic product until a fault is reported;

[0089] S103.33 Dynamically evaluate P0 and P1 until P1 < 0.9;

[0090] S103.34 performs N electronic product embedded test samplings and dynamically estimates P0 and P1 based on the samples;

[0091] S103.34: Select whether the current electronic product embedded test reports a fault. If so, the system state switches to an intermittent fault state and performs K0 = f(P0) electronic product embedded test sampling times. If not, the system state switches to an intermittent recovery state and performs K1 = f(P1) electronic product embedded test sampling times.

[0092] If there are faults in all K1 electronic product embedded test samples, the system switches to hard fault state. If not, reselect whether to report faults in the current electronic product embedded test;

[0093] If K0 electronic product embedded test samples are all normal, then enter S103.31, if not, then reselect whether the current electronic product embedded test reports a fault.

[0094] In one embodiment, the state of the model further includes a recovery state; in S101, the transition between the states is as follows:

[0095] The unit under test starts from the normal state and switches to the intermittent fault state when the intermittent state identification conditions are met;

[0096] In the intermittent fault state, if the electronic product embedded test passes once, it will be converted to intermittent recovery. Otherwise, if it fails K1 times continuously, it will be converted to hard fault state;

[0097] In the intermittent recovery state, if the electronic product embedded test fails once, it will be converted to the intermittent fault state. Otherwise, if it succeeds K0 times continuously, it will be converted to normal;

[0098] In the hard fault state, if the electronic product passes the embedded test once, it will be converted to the recovery state.

[0099] In one embodiment, the parameters are calculated as follows:

[0100] Let the time series X=[x1,x2,L,x N ], x i =0 means the i-th BIT test passed, x i =1 means the i-th BIT test failed;

[0101] If there are S 0s in X, and x i =0,x i+1 =1 i There are s in total, then P0=s / S;

[0102] If there are F 1s in X, and x j =1,x j+1 =0 j There are f in total, then P1=f / F;

[0103] Suppose the probability of a random event is P. According to Bernoulli's random variable theory, the probability of an event occurring in no more than K trials is:

[0104] P K =1-(1-P) K

[0105] Given P, satisfy the confidence level P K The K value is:

[0106] K≥ceil(log(1-PK ) / log(1-P))

[0107] Where ceil(·) means rounding up, then:

[0108] K0=ceil(log(1-P K ) / log(1-P0)), K1=ceil(log(1-P K ) / log(1-P1)).

[0109] In one embodiment, between S103.3 and S103.4, the following steps are further included:

[0110] In S201, when in the intermittent state, the occurrence probabilities P0 and P1 of intermittent failure and intermittent recovery are recorded for the user of the unit under test to assess the risk of continued use. In one embodiment, S103.5 is further used to repeat S201.

[0111] The following is further described with reference to the accompanying drawings:

[0112] Step 1: Establish the state transition model of the unit under test (UUT):

[0113] 1.1、Establish Figure 1 The UUT state transition model shown;

[0114] 1.2. Definition of state transition behavior:

[0115] Normal: The system starts from the "Normal" state and transitions to the "Intermittent Fault" state when the intermittent state recognition conditions are met;

[0116] Intermittent fault: If one BIT test passes, the system switches to the "intermittent recovery" state. Otherwise, if it fails K1 times in a row, it switches to the "hard fault" state.

[0117] Intermittent recovery: If a BIT test fails, the system switches to the "intermittent fault" state. Otherwise, if it succeeds K0 times in a row, it switches to the "normal" state.

[0118] Hard fault: If one BIT test passes, it transitions to the "Recovery" state.

[0119] 1.3 Model parameter definition and calculation

[0120] The parameters are defined as follows:

[0121] (1) P0: The probability of “intermittent recovery” transitioning to “intermittent failure”;

[0122] (2) P1: The probability of “intermittent failure” transferring to “intermittent recovery”;

[0123] (3)P K : confidence of state transition;

[0124] (4) K0: Between probability P0 and confidence P K Under this condition, determine the number of BITs required to transfer from "intermittent failure" to "intermittent recovery";

[0125] (5) K1: Between probability P1 and confidence P K Under this condition, determine the number of BITs required to transfer from "intermittent failure" to "intermittent recovery";

[0126] The parameters are calculated as follows:

[0127] Assume that there is a BIT time series X=[x1,x2,L,x N ], x i =0 means the i-th BIT test passed, x i =1 means the i-th BIT test failed;

[0128] If there are S 0s in X, and x i =0,x i+1 =1 i There are s in total, then P0=s / S;

[0129] If there are F 1s in X, and x j =1,x j+1 =0 j There are f in total, then P1=f / F;

[0130] Assume that the probability of a random event is P. According to Bernoulli's random variable theory, the probability of the event occurring in no more than K trials is:

[0131] P K =1-(1-P) K

[0132] Therefore, given P, the confidence level P is satisfied. K The K value is:

[0133] K≥ceil(log(1-P K ) / log(1-P))

[0134] Where ceil(·) means rounding up.

[0135] Therefore, K0 = ceil(log(1-P K ) / log(1-P0)), K1=ceil(log(1-P K) / log(1-P1)).

[0136] Step 2: Identify the intermittent state of the unit under test (UUT):

[0137] 2.1. The default initial state of the unit under test (UUT) is "normal". The UUT is continuously monitored by BIT to obtain the time series X Norm =[x1,x2,L,x N ], in this case, BIT test failure is allowed to occur, but the possibility of conversion to BIT test passing is very high, that is, P1 should be a large value close to 1;

[0138] 2.2. Dynamically estimate P0 and P1. If P1 decreases to the set threshold, the UUT enters the intermittent state;

[0139] Step 3: Status evaluation and false alarm suppression of the unit under test (UUT):

[0140] 3.1. After the unit under test (UUT) enters the "intermittent state", more BIT samples are required to re-evaluate P0 and P1;

[0141] 3.2. Based on the estimated P0 obtained in step 2.2, continue to record K0 or K1 BITs to obtain the time series X intm =[x1,x2,L,x N ], use the time series X to estimate and correct P0 and P1;

[0142] 3.3, according to the state transition behavior defined in step 1.2, Figure 2 The process shown is used to evaluate the UUT status;

[0143] 3.4. When the system state is "intermittent failure", the occurrence probabilities P0 and P1 of the two sub-states "intermittent failure" and "intermittent recovery" are given;

[0144] 3.5. To improve the utilization of historical data, each time the UUT status switches between "intermittent fault" and "intermittent recovery", the current K 0i or K 1j BIT data is added to the BIT time series X intm , and using the supplemented X intm Re-estimate P0 and P1;

[0145] 3.6. Repeat steps 3.3, 3.4 and 3.5 until the UUT exits the intermittent state or the task execution is completed. In this embodiment, the BIT time series X = [x1, x2, L, x N], N=700; in this BIT sequence, '0' represents that the current BIT detection result is normal, and '1' represents that the current BIT detection result is abnormal. Figure 3 As shown, the horizontal axis is the BIT sampling sequence number, and the vertical axis is the BIT test result ("normal" or "abnormal"); the black solid line is the BIT data plot; among them, sequence numbers 1 to 200 indicate that the UUT is in the "normal" state, and sequence numbers 201 to 700 indicate that the UUT is in the "intermittent" state. The UUT status evaluation process is as follows:

[0146] Step 1: Establish the state transition model of the unit under test (UUT):

[0147] 1.1、Establish Figure 1 The UUT state transition model shown;

[0148] 1.2. Definition of state transition behavior:

[0149] The definitions of normal state, intermittent state, and hard fault state are described in Section 5 "State Transition Behavior Definition".

[0150] 1.3 Model parameter calculation

[0151] Confidence P K Take 0.98 and calculate P0i and P according to the method described in Section 5 "Model Parameter Definition and Calculation" 1j , K 0i , K 1j ;

[0152] Step 2: Identify the intermittent state of the unit under test (UUT):

[0153] 2.1、The default initial state of the unit under test (UUT) is "normal", such as Figure 4 As shown in (d), for the sequence X Norm =[x1,x2,L,x 231 ], P1 is close to 1, Figure 4 (b) The UUT status is determined to be normal;

[0154] 2.2. When the BIT sequence number is 231, P1 = 0.875 < 0.9, which exceeds the set threshold, and the UUT is judged to have entered the intermittent state;

[0155] Step 3: Status evaluation and false alarm suppression of the unit under test (UUT):

[0156] 3.1. After the unit under test (UUT) enters the "intermittent state", according to the P0 and P1 estimated in step 2.2, K0 or K1 BIT records are continuously performed to obtain the time series X intm =[x1,x2,L,x M], use the time series X to estimate and correct P0 and P1;

[0157] 3.3, according to the state transition behavior defined in step 1.2, Figure 2 The process shown is used to evaluate the UUT status;

[0158] 3.3. The UUT status is evaluated using the method of the present invention and the conventional method (repeated BIT and voting BIT). The results are as follows: Figure 4 and Figure 5 As shown in Table 1, the number of times the UUT status is judged as a "hard fault" by different false alarm suppression methods is shown. It can be seen that the number of times of this method is lower than that of the conventional method, indicating that the method of the present invention has a strong inhibitory effect on false alarms caused by intermittent faults;

[0159] Table 1 Comparison of the effects of different false alarm suppression methods

[0160]

[0161] 3.4, P 0i and P 1j The calculation results are as follows Figure 4 (c) and (d);

[0162] 3.5, P 0i and P 1j Dynamic updates of Figure 4 (c) and (d);

[0163] 3.6. Repeat steps 3.3, 3.4 and 3.5 until the UUT exits the intermittent state or the task execution is completed.

[0164] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for identifying intermittent states of electronic products and preventing BIT false alarms, characterized in that: The following steps are involved: S101 establishes a state transition model of the unit under test; the states of the model include: normal state, intermittent state and hard fault state; the intermittent state includes intermittent fault state and intermittent recovery state; S102 Intermittent state identification of the unit under test: S102.1 assumes that the unit under test is initially in a normal state. The unit under test is continuously monitored by the embedded electronic product test (BIT) to obtain the judgment result. The judgment result is the time series under the normal state: X Norm =[x1,x2,…,x N ]; S102.2: Obtain P0 and P1 based on the time series; if P1 decreases to a set threshold, the unit under test enters an intermittent state; S103 Status evaluation and false alarm suppression of the unit under test: S103.1 When the unit under test enters the intermittent state, obtain multiple embedded test samples of the electronic product and obtain more accurate estimates of P0 and P1 after multiple evaluations; S103.2 Continue to record K0 or K1 times of electronic product embedded test, and obtain the time series X in the intermittent state. intm =[x1,x2,…,x N ], using the time series X intm Estimate and correct P0 and P1; S103.3 Perform state assessment based on the definition of the state transition model; S103.4 When switching between intermittent fault state and intermittent recovery state, the current K 0i or K 1j Sub-electronic product embedded test data is added to the time series X intm , and using the supplemented X intm Re-estimate P0 and P1; S103.5 Repeat S103.3 and S103.4 until the UUT exits the intermittent state or the UUT task execution is completed; in: P0: The probability of transition from intermittent recovery state to intermittent fault state; P1: The probability of transition from intermittent fault state to intermittent recovery state; P K : confidence of state transition; K0: Between probability P0 and confidence P K Under this condition, determine the number of embedded tests of electronic products required to transfer from intermittent fault state to intermittent recovery state; K1: Between probability P1 and confidence P K Under this condition, determine the number of embedded tests of electronic products required to transfer from intermittent fault state to intermittent recovery state; Also included between S103.3 and S103.4: S201: When in an intermittent state, the occurrence probabilities P0 and P1 of intermittent failure and intermittent recovery are recorded for the user of the unit under test to assess the risk of continued use; The S103.5 is also used to repeat the S201.

2. The electronic product intermittent state identification and BIT false alarm prevention method according to claim 1, characterized in that: The set threshold is a large value close to 1.

3. The electronic product intermittent state identification and BIT false alarm prevention method according to claim 2, characterized in that: In S103.3, the method for condition assessment includes the following steps: S103.31 Set the initial state to normal by default; S103.32 Continue to run the embedded test of the electronic product until a fault is reported; S103.33 Dynamically evaluate P0 and P1 until P1 < 0.9; S103.34 performs N electronic product embedded test samplings and dynamically estimates P0 and P1 based on the samples; S103.34: Select whether the current electronic product embedded test reports a fault. If so, the system state switches to an intermittent fault state and performs K0 = f(P0) electronic product embedded test sampling times. If not, the system state switches to an intermittent recovery state and performs K1 = f(P1) electronic product embedded test sampling times. If there are faults in all K1 electronic product embedded test samples, the system switches to a hard fault state. If not, reselect whether to report a fault in the current electronic product embedded test; If K0 electronic product embedded test samples are all normal, then enter S103.31, if not, then reselect whether the current electronic product embedded test reports a fault.

4. The electronic product intermittent state identification and BIT false alarm prevention method according to claim 3, characterized in that: The state of the model also includes a recovery state; in S101, the transition between the states is as follows: The unit under test starts from the normal state and switches to the intermittent fault state when the intermittent state identification conditions are met; In the intermittent fault state, if the electronic product embedded test passes once, it will be converted to intermittent recovery. Otherwise, if it fails K1 times continuously, it will be converted to hard fault state; In the intermittent recovery state, if the electronic product embedded test fails once, it will be converted to the intermittent fault state. Otherwise, if it succeeds K0 times continuously, it will be converted to normal; In the hard fault state, if the electronic product passes the embedded test once, it will be converted to the recovery state.

5. The electronic product intermittent state identification and BIT false alarm prevention method according to claim 4, characterized in that: The calculation method of each parameter is: Let the time series X=[x1,x2,…,x N ], x i =0 means the i-th BIT test passed, x i =1 means the i-th BIT test failed; If there are S 0s in X, and x i =0,x i+1 =1 i There are s in total, then P0=s / S; If there are F 1s in X, and x j =1,x j+1 =0 j There are f in total, then P1=f / F; Suppose the probability of a random event is P. According to Bernoulli's random variable theory, the probability of an event occurring in no more than K trials is: P K =1-(1-P) K Given P, satisfy the confidence level P K The K value is: K≥ceil(log(1-P K ) / log(1-P)) Where ceil(·) means rounding up, then: K0=ceil(log(1-P K ) / log(1-P0)),K1=ceil(log(1-P K ) / log(1-P1))。

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