Adjustable column address scrambling using fuses

Abstract

The subject matter relates to adjustable column address scrambling using fuses. A test device can detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The test device can identify, based on detecting the first error and the second error, a first column address of the first column plane and a second column address of the second column plane associated with the first error. The test device can determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the test device can perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Description

[0001] This application is a divisional application of Chinese Invention Patent Application No. 202011301401.2, titled “ADJUSTABLE COLUMN ADDRESS SCRAMBLE USING FUSES,” filed on November 19, 2020, having the same filing date and priority date of December 19, 2019.

[0002] Cross reference

[0003] This patent application claims priority to U.S. Patent Application No. 16 / 723,532, titled “ADJUSTABLE COLUMN ADDRESS SCRAMBLE USING FUSES,” filed on December 20, 2019, for Rehmeyer et al., assigned to the assignee hereof, and expressly incorporated herein in its entirety by reference thereto. TECHNICAL FIELD

[0004] The technical field relates to adjustable column address scramble using fuses. BACKGROUND

[0005] The following relates generally to one or more memory systems and more specifically to adjustable column address scramble using fuses.

[0006] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, individual memory cells can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state in the memory device.

[0007] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, sulfide memory technology, and the like. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power source. SUMMARY

[0008] A method is described. The method can include detecting a first error in a first column plane of a memory array and a second error in a second column plane of the memory array, identifying a first column address of the first column plane and a second column address of the second column plane associated with the first error based at least in part on detecting the first error and the second error, determining, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane based at least in part on identifying the first column address and the second column address, and performing a fuse blow of a fuse associated with the first column plane based at least in part on determining the configuration to implement the determined configuration.

[0009] An apparatus is described. The apparatus can include a memory array comprising one or more column planes each comprising a plurality of columns, a column address decoder configured to access a column of a column plane during an access operation based at least in part on an address input into the column address decoder, and one or more fuses coupled with an input of the column address decoder and used to implement a configuration to scramble column addresses of the column plane to different column addresses of the column plane when at least one of the one or more fuses is blown.

[0010] A method is described. The method can include receiving a command comprising a first column address of a first column plane, scrambling the first column address based at least in part on a state of a fuse associated with scrambling column addresses of the first column plane, and accessing a second column address of the first column plane different from the first column address based at least in part on scrambling the first column address. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 An example of a system supporting adjustable column address scrambling using fuses is described in accordance with examples as disclosed herein.

[0012] Figure 2 An example of a test setup supporting adjustable column address scrambling using fuses is described in accordance with examples as disclosed herein.

[0013] Figure 3 An example of a column repair region supporting adjustable column address scrambling using fuses is described in accordance with examples as disclosed herein.

[0014] Figure 4 An example of a block diagram supporting adjustable column address scrambling using fuses is described in accordance with examples as disclosed herein.

[0015] Figure 5 An example of a system supporting adjustable column address scrambling using fuses is described in accordance with examples as disclosed herein.

[0016] Figure 6 A block diagram showing a memory device supporting adjustable column address scrambling using fuses according to examples as disclosed herein is shown.

[0017] Figure 7 and 8 A flow diagram showing one or more methods supporting adjustable column address scrambling using fuses according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0018] In some memory systems, global column repair techniques can be implemented to repair column planes of a memory array. Global column repair can repair a single column plane at a time per prefetch. For example, when using global column repair, a memory device can repair one column of a group of column planes. That is, if two column planes encounter a failure on the same prefetch address (e.g., column index), global column repair can not be able to repair both failures. In such cases, the two column planes can encounter an address conflict. For memory devices that encounter column failures on the same column index, local column repair can be added to each column plane, thereby increasing the size of the memory die, reducing the efficiency of the memory die operation, and causing additional errors on the memory device. To improve yield loss due to repeated column failures on the same address, a memory device can implement adjustable column address scrambling using fuses in a column decoder.

[0019] The functionality of a memory device can be improved by performing a fuse blow of a fuse to scramble at least one of the addresses (e.g., column addresses) that encounter an address conflict. When an address conflict occurs, the column address mapping of one of the column planes can be scrambled to avoid the conflict, thereby allowing the memory device to increase the efficiency of the memory array resources. For example, a memory device can detect that an error occurs on the same index in at least two different column planes in a repair zone. In such cases, the memory device can identify the column address of at least one of the column planes that encounter the error and determine a configuration for scrambling the column address to a different column address in the same column plane.

[0020] Fuses (or a fuse array) in a column decoder can be used to scramble column addresses. For example, a memory device can blow a fuse associated with a column address that encounters an error to scramble the column address to a different column address in the same column plane. Using such scrambling techniques can reduce the likelihood that a memory device can not be able to repair using global repair techniques and reduce yield loss caused by repeated column address failures on the same address.

[0021] The features of the present disclosure are first described in the context of a memory system as described with reference to Figure 1 The features of the present disclosure are described in the context of a test setup and a memory array as described with reference to Figures 2 to 5 The features of the present disclosure are described in the context of a test setup and a memory array as described with reference toFigures 6 to 8 The described device diagrams and flowcharts related to adjustable column address scrambling using fuses further illustrate and describe these and other features of the disclosure.

[0022] Figure 1 An example of a system 100 that supports adjustable column address scrambling using fuses is described in accordance with examples as disclosed herein. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 and the memory device 110. The system 100 can include one or more memory devices 110, but aspects of the one or more memory devices 110 can be described in the context of a single memory device, such as the memory device 110.

[0023] The system 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 can illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular telephone, a wearable device, an internet-connected device, a vehicle controller, and the like. The memory device 110 can be a component of the system that is operable to store data for one or more other components of the system 100.

[0024] At least portions of the system 100 can be an example of the host device 105. The host device 105 can be an example of a processor or other circuitry within a device that uses memory to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular telephone, a wearable device, an internet-connected device, a vehicle controller, or some other stationary or portable electronic device, among other examples. In some examples, the host device 105 can refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 120. In some examples, the external memory controller 120 can be referred to as a host or host device 105.

[0025] The memory device 110 can be a standalone device or a component that is operable to provide physical memory addresses / space that can be used or referenced by the system 100. In some examples, the memory device 110 can be configurable to work with one or more different types of host devices. Signaling between the host device 105 and the memory device 110 can be operable to support one or more of: modulation schemes for modulating signals; various pin configurations for communicating signals; various form factors for physical packaging of the host device 105 and the memory device 110; clock signaling and synchronization between the host device 105 and the memory device 110; timing conventions, or other factors.

[0026] Memory device 110 can be operable to store data for components of host device 105. In some examples, memory device 110 can act as a slave-type device to host device 105 (e.g., responsive to and executing commands provided by host device 105 through external memory controller 120). Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0027] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components (e.g., one or more peripheral components or one or more input / output controllers). Components of the host device can be coupled with each other using bus 135.

[0028] Processor 125 can be operable to provide control or other functionality for at least portions of system 100 or at least portions of host device 105. Processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 can be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a system on a chip (SoC), among other examples. In some examples, external memory controller 120 can be implemented by processor 125 or be part of processor 125.

[0029] BIOS component 130 can be a software component that includes a BIOS that operates as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 can also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 can include a program or software stored in one or more of read-only memory (ROM), flash memory, or other nonvolatile storage.

[0030] Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 can be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more blocks, one or more sections) where each memory cell is operable to store at least one data bit. A memory device 110 including two or more memory dies can be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package. In some cases, memory array 170 can include one or more repair regions, which can include one or more column planes. Each of the one or more column planes can include a plurality of columns. In some cases, the plurality of column planes can be in the same memory bank. In some examples, there can be a plurality of memory banks.

[0031] Device memory controller 155 can include circuitry, logic, or components operable to control operations of memory device 110. Device memory controller 155 can include hardware, firmware, or instructions that enable memory device 110 to perform various operations and can be operable to receive, transmit, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 can be operable to communicate with one or more of external memory controller 120, one or more memory dies 160, or processor 125. In some examples, device memory controller 155 can control operations of memory device 110 described herein in conjunction with local memory controllers 165 of memory dies 160.

[0032] The local memory controller 165 (e.g., local to the memory die 160) can be operable to control operations of the memory die 160. In some examples, the local memory controller 165 can be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller 155. In some examples, the memory device 110 can not include the device memory controller 155 and the local memory controller 165, or the external memory controller 120 can perform various functions described herein. As such, the local memory controller 165 can be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that can be included in the device memory controller 155 or the local memory controller 165, or both, can include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0033] The external memory controller 120 can be operable to enable one or more of information, data, or commands to be communicated between components of the system 100 or the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 can translate or interpret communications exchanged between the host device 105 and components of the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or the host device 105, or functions thereof described herein, can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software implemented by the processor 125 or by other components of the system 100 or the host device 105, or some combination thereof. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or functions thereof described herein can be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0034] The components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 can be operable to support communications between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path can be an example of an electrically conductive path that is operable to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin can be an example of an electrically conductive input or output point of a device of the system 100, and a pin can be operable to act as part of a channel.

[0035] The channels 115 (and associated signal paths and terminals) can be dedicated to communicating one or more types of information. For example, the channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, information can be communicated over the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., a signal level) of a signal can be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0036] In a global column repair scheme, a column plane in a single repair column plane can be repaired or replaced by a column repair in the repair column plane. In some such configurations, a single prefetch column address in a repair region can be repaired or replaced using a repair column plane at a time. Thus, if a same column address in multiple column planes in a repair region fails, it can not be repairable using a single repair column plane. In some examples, the memory device 110 can detect an error in a first column plane of a memory array 170 and an error in a second column plane that is different from the first column plane of the same memory array 170. A column address associated with each error in the first and second column planes can be identified. In some cases, the memory device 110 can determine a first column plane scrambling configuration for scrambling the column address of the first column plane to a different column address of the first column plane. For example, to implement the scrambling configuration, the memory device 110 can blow a fuse associated with the first column plane.

[0037] Memory device 110 can receive a command from host device 105. The command can include a column address of a column plane of memory array 170. Memory device 110 can scramble the column address of the column plane based on a state (e.g., blown or unblown) of a fuse of memory array 170. In some cases, the memory device can access a different column address of the column plane based on the scrambled column address.

[0038] Figure 2 An example of a test setup 200 that supports adjustable column address scrambling using fuses is described in accordance with examples as disclosed herein is described.

[0039] Test setup 200 can involve a memory die 205 coupled with a tester 210. Memory die 205 can be an example of memory die 160 as described with reference to Figure 1 In some cases, a method as described herein can be performed if an error is detected in both a first column plane and a second column plane of a memory array. Additionally or alternatively, a method as described herein can be performed if an address conflict is detected between an address of the first column plane and an address of the second column plane. In some examples, memory die 205 can be replaced by a more general logic circuit without departing from the scope of the disclosure.

[0040] Memory die 205 can include one or more memory arrays. Each memory array can contain a different subset of memory cells contained in the one or more memory arrays. Additionally, each memory array can include one or more access lines (e.g., word lines or bit lines), where each access line is coupled with at least one of the memory cells of the respective subset. Additionally, each access line of a memory array can be coupled with a corresponding via. In some cases, memory die 205 can include column planes 215 and 220.

[0041] A test column plane can be a column plane used by tester 210 to perform testing on memory die 205 and a non-test column plane can be a column plane not used by tester 210 to perform testing on memory die 205. In some cases, a via coupled with each access line of column planes 215 and 220 can be coupled with a substrate on which memory die 205 is resting. The substrate can include one or more circuits configured to activate or deactivate the access lines of the test column plane and column plane via the vias.

[0042] Memory die 205 can use a global column repair technique. For example, when using global column repair, memory die 205 can repair one column index in a column plane group that forms a repair zone. The repair zone can include a single repair column plane and multiple column planes that are repaired using that single repair column plane. However, in some cases, the same column address in different column planes of the repair zone can fail. In some examples, memory die 205 can be configured to repair only a single column at a single column address in a repair zone when using a global column repair technique, thereby rendering memory die 205 unable to repair because the column address failure is occurring at the same or similar address in the repair zone.

[0043] Tester 210 can be configured to test the performance of memory die 205. For example, tester 210 can detect a first error in column plane 215 and a second error in column plane 220 to test column plane 215 and column plane 220, respectively. Tester 210 can identify the column addresses of each column plane 215 and column plane 220. Based on whether there is an address conflict between column plane 215 and column plane 220, tester 210 can perform a fuse blow of memory die 205 to implement a configuration for scrambling the column addresses of column plane 215 or the column addresses of column plane 220. In some cases, the communication between tester 210 and memory die 205 can operate with increased latency. In such cases, the memory of tester 210 can overflow to retain information stored in tester 210. Tester 210 can be configured to analyze information according to test performance during a test phase of a manufacturing process. Reference can be made to Figure 3 More details are described regarding how tester 210 performs a test procedure.

[0044] Figure 3 An example of a column repair zone 300 that supports adjustable column address scrambling using fuses according to examples as disclosed herein is illustrated. Column repair zone 300 can include one or more column planes 305 (only two column planes are explicitly numbered in Figure 3

[0045] Column repair zone 300 can include one or more column planes 305. For example, column repair zone 300 can include 18 column planes, 34 column planes, or 64 column planes. In some memory systems, each column plane 305 can include a number of redundant columns that can only be used in column repair zone 300 to repair column plane 305. For example, if a first column of a repair column plane 305 is repaired, the first column of each column plane 305 in column repair zone 300 can be repaired. The set of column planes 305 can be in the same memory bank. In some cases, there can be multiple memory banks. In some examples, each column plane can include multiple columns.

[0046] ​In memory systems that use global column repair, the column repair region 300 can include a global column plane 310 configured to repair the column planes 305 in the column repair region 300. The global column plane 310 can be associated with each column plane in the column repair region 300.

[0047] The global column plane 310 can repair any of the column planes 305 in the column repair region 300. However, the global column plane 310 can be configured to repair one column in one column plane 305 at a time per prefetch. For example, the column repair region 300 can include a repair component. The repair component can be configured to receive an external command (e.g., from a tester) to perform a blow on one or more fuses to repair a column plane 305. In such cases, if two or more column planes 305 encounter a column failure on the same prefetch address (e.g., column address), the global column plane 310 can not be able to repair both columns using the global column plane 310, which can result in a non-repairable memory die.

[0048] For example, a single column of the first column plane 305-a can be repaired, while a column of the second column plane 305-b that encounters a failure on the same address can not be repairable by the global column plane 310, or vice versa. The global column plane 310 can exchange data on a single input / output (I / O) line external to the memory array. The columns in the same prefetch can be accessed simultaneously. However, the logic for determining which column plane 305 to repair can be sequential or prioritized for the same result. For example, when defects occur on multiple column planes 305 at the same address, the column planes 305 can be accessed sequentially (e.g., one at a time). In such cases, the global column plane 310 can exchange data on the I / O line for a single column plane 305. When columns in multiple column planes 305 are out of order, the amount of data on the I / O line can be exceeded, thereby preventing the global column plane 310 from repairing each column plane 305 that encounters a failure.

[0049] In some examples, the column repair region 300 can support local column repair in addition to the global column plane 310. For example, if the column repair region 300 encounters failures at a repeating address (e.g., the same column address in different column planes 305), the column repair region 300 can use local column repair for one failure and the global column plane for the other failure. In other examples, the column repair region 300 can use local column repair because local column repair repairs the same column address in multiple column planes 305 (e.g., local column repair addresses the deficiency of global column repair; however, local column repair can increase cost). However, the addition of local column repair can increase the size of the memory die, thereby decreasing the efficiency of the column repair region 300.

[0050] Memory arrays can experience yield loss due to repeated column address failures (e.g., address collisions). In some cases, a memory array can experience an increased failure rate at column addresses on the edge of a column plane 305. For example, column addresses 0 to 3 can experience a higher failure rate than column addresses 3 to 12 of a column repair region 300. In such cases, an increased likelihood of repeated address failures can occur on the edge of a column plane 305. In some cases, the yield loss can be associated with random failures occurring on the same column address in different column planes 305 in the same column repair region 300. In some examples, the size of a column repair region 300 can increase the likelihood of address collisions. For example, the larger the size of a column repair region 300, the higher the chance of an address collision occurring.

[0051] In some cases, a tester can perform a test to determine whether a column repair can be needed. The tester can be an example of the tester 210 as described with reference to Figure 2 For example, the tester can identify a collision between a column address of a first error in a first column plane 305-a associated with a column repair region 300 and a different column address of a second error in a second column plane 305-b associated with the column repair region 300. In such cases, the tester can identify that the index of the column addresses is the same. Based on identifying the collision between the column addresses, the tester can determine that scrambling one or both of the column addresses of the first column plane 305-a and the second column plane 305-b can allow for repairing both column errors using a single global column plane 310. The memory device and the host device can communicate to perform the test to determine whether a column repair can be needed.

[0052] Figure 4 An example of a block diagram 400 supporting adjustable column address scrambling using fuses according to examples as disclosed herein is illustrated. The block diagram can include a first address configuration 425-a of a column plane 405, a fuse blow 420, and a second address configuration 425-b of the column plane 405. The first address configuration 425-a can include a first column address 410-a and a second column address 415-a. The second address configuration 425-b can include a first column address 410-b and a second column address 415-b.

[0053] To reduce or eliminate yield loss due to a duplicate column failure in a repair region, a memory device can program a fuse to scramble a column address of one of the column planes involved in a duplicate column failure. For example, if a column failure of column plane 405 conflicts with a column failure in another column plane, the memory device can blow a fuse to adjust the logical / physical scrambling of column plane 405, thereby avoiding a duplicate address failure. In such cases, the memory device can move a column plane failure from one logical address to a different logical address in the same column plane, thereby eliminating a conflict (e.g., two failures occurring at the same prefetch) and enabling the repair column plane to repair both column failures.

[0054] The first address configuration 425-a can include logical / physical addresses ranging from 0 to 63. The first column address 410-a can include logical / physical address 0. The second column address 415-a can include logical / physical address 63. In some examples, a column failure can occur at logical address 0. When a tester determines that an error occurs at logical / physical address 0 (e.g., first column address 410-a) of column plane 405 and an error occurs on logical / physical address 0 of a different column plane, the tester can perform a fuse blow 420.

[0055] The fuse blow 420 can invert the column addresses of column plane 405 to move a column failure to a different address. In such cases, in the second address configuration 425-b, the column failure can be moved to logical address 63. The first column address 410-b can include logical address 63 and physical address 0, and the second column address 415-b can include logical address 0 and physical address 63. The fuse blow 420 can activate an inverter to scramble the column addresses of column plane 405 to a different address of column plane 405.

[0056] In some cases, the fuse blow 420 can reorder the address scrambling in multiple permutations to eliminate yield loss. For example, the fuse blow 420 can switch the column addresses from a minimum-maximum column address order to a maximum-minimum column address order (e.g., inversion). One or more fuses can be added to the column decoder of the memory device to invert any one or more bits of the column addresses. In some cases, the fuse blow 420 of one or more fuses can reorder the column addresses 0 to 63 on column plane 405 to 31 to 0 and 63 to 32. In some cases, the fuse blow 420 of one or more fuses can reorder the column addresses 0 to 63 on column plane 405 to 15 to 0, 31 to 16, 47 to 21, and 63 to 48. The memory device can include any number of fuses to enable any column address scrambling. For example, the memory device can include one, two, three, four, five, six, seven, or eight fuses to enable column address scrambling.

[0057] To reduce the number of fuses implemented in a memory device, each column plane 405 group can implement a single set of inversion fuses. In some cases, reordering of column addresses can be supported on a per column plane basis or a per column plane group basis. For example, a memory device can scramble the column addresses of every column plane in a memory die, every 8 column planes in a memory die, or a predetermined amount of alternating column planes in a memory die. In some examples, address scrambling can be implemented on a per section basis, a per section group basis, or a per memory bank basis. For example, a memory device can invert the column addresses of half of the column planes of each memory bank.

[0058] Figure 5 An example of a system 500 that supports adjustable column address scrambling using fuses is described in accordance with examples as disclosed herein. The system 500 can include a memory device 505, latches 510, a controller 525, a column address decoder 530, and a memory array 535. The memory device 505, the controller 525, and the memory array 535 can be examples of a memory device, a controller, and a memory array as described with reference to Figures 1 to 4 The memory array 535 can include one or more column planes each including a plurality of columns.

[0059] The memory device 505 can receive a command including a column address of a column plane of the memory array 535. The command can be an example of a read command or a write command. In some cases, the memory device 505 can include latches 510 configured to select the column address included in the command. The latches 510 can be in electronic communication with the column address decoder 530 via column address bits 515-a, 515-b, 515-c, and 515-d. The column address bit 515-a can be an example of a first column address bit, and the column address bit 515-b can be an example of a complementary first column address bit. The column address bit 515-c can be an example of a second column address bit, and the column address bit 515-d can be an example of a complementary second column address bit.

[0060] The column address bit 515-a and the column address bit 515-b can be configured to pass a value selected to access the column address (e.g., a column address value). In some cases, the column address bit 515-c and the column address bit 515-d can be configured to pass a value selected to access the column address depending on a state of the fuse 520. In some cases, the state of the fuse 520 can be determined based on the command. If the fuse 520 can be in a default state (e.g., unblown), the value selected to access the column address can be passed via the column address bit 515-c and the column address bit 515-d.

[0061] In some cases, the memory device 505 can detect an error in a first column plane of the memory array 535 and an error in a second column plane of the memory array 535. The memory device 505 can then identify an address of the error in the first column plane and an address of the error in the second column plane. In some cases, the memory device 505 (or a tester, as the case can be) can identify an address conflict between the address of the first column plane and the address of the second column plane that encountered the error. In such cases, the memory device 505 can identify that the index of the address of the first column plane is the same as the index of the address of the second column plane, indicating the address conflict.

[0062] The memory device 505 (or a tester, as the case can be) can determine a configuration for scrambling the address of the first column plane based on identifying the conflict and identifying the index. To implement the configuration for scrambling the address of the first column plane, the memory device 505 can perform a fuse blow on the fuse 520. The address of the first column plane can be scrambled to a different address of the first column plane based on performing the fuse blow on the fuse 520.

[0063] In such cases, the fuse 520 can be configured to scramble the column address to a different column address of the plane based on the configuration when the fuse 520 is blown. For example, the fuse 520 can invert one or more bits of an address input into the column address decoder 530 when the fuse 520 is blown. In some examples, a voltage source can be coupled with the fuse 520 to apply a voltage to perform the fuse blow. In such cases, the voltage source can apply a voltage to the fuse 520 based on the configuration, where the voltage meets a voltage threshold of the fuse 520 to which the voltage is applied. The fuse blow can occur based on the applied voltage.

[0064] In some examples, the fuse 520 can be positioned elsewhere on the memory device 505 (i.e., a fuse array). The state of the fuse 520 can be broadcast to a local latch (e.g., the latch 510) associated with the memory device 505 during initialization and for use during operation. The local latch (e.g., the latch 510) can be positioned near the column address decoder 530 and used for scrambling addressing.

[0065] The fuse can be coupled with the multiplexer 540-a and the multiplexer 540-b via the controller 525. In some examples, the fuse 520 can be an example of an antifuse. In some examples, the multiplexer 540-a and the multiplexer 540-b can each be an example of an inverter or a multiplexer. The fuse 520 can latch a signal that controls the multiplexer 540-a and the multiplexer 540-b. In some examples, when the fuse 520 is in a low state, the multiplexer 540-a can be configured to invert a first value on the column address bit 515-c (e.g., at least one bit of an address of the first column plane) and transmit the first value to the column address decoder 530 via the column address bit 515-d. The low state can represent that the fuse 520 receives a voltage that is below a voltage threshold of the fuse 520. In such cases, the first value can be output after the multiplexer 540-a onto the column address decoder 530 via the column address bit 515-d. In other examples, the multiplexer 540-b can be configured to invert a second value on the column address bit 515-d (e.g., at least one bit of an address of the first column plane) and transmit the second value to the column address decoder 530 via the column address bit 515-c when the fuse is in the low state. In such cases, the second value can be output after the multiplexer 540-b onto the column address decoder 530 via the column address bit 515-c.

[0066] In other examples, if the fuse 520 is in a high state, the multiplexer 540-a can be configured to pass the first value on the column address bit 515-c (e.g., at least one bit of an address of the first column plane) and transmit the first value to the column address decoder 530 via the column address bit 515-c. In such cases, the multiplexer 540-a can avoid inverting the first value, and the first value can be output after the multiplexer 540-a onto the column address decoder 530 via the column address bit 515-c. The high state can represent that the fuse 520 receives a voltage that meets or is above a voltage threshold of the fuse 520. In other examples, when the fuse is in the high state, the multiplexer 540-b can be configured to pass the second value on the column address bit 515-d (e.g., at least one bit of an address of the first column plane) and transmit the second value to the column address decoder 530 via the column address bit 515-d. In such cases, the second value can be output after the multiplexer 540-b onto the column address decoder 530 via the column address bit 515-d, thereby avoiding inverting the second value.

[0067] In one example, if a fuse 520 is activated (e.g., blown), the value of a column address selected to access can be scrambled or inverted. In such cases, the memory device 505 can scramble the column address based on the state of the fuse 520. After the fuse 520 is blown, the controller 525 can determine whether an error (e.g., an address conflict) occurs in the memory array 535. Different scrambling patterns are possible based on which bit of the column address is inverted using the fuse(s). For more complex scrambling, one or more fuses can be positioned to invert two or more bits of the column address of a column plane.

[0068] The controller 525 (or a tester, as appropriate) can determine a configuration for scrambling the column address of one or more column planes. In such cases, the controller 525 can be an example of a fuse programmable scrambler. In some examples, the controller 525 can be configured to modify the column address based on an output received from the fuse 520. For example, the controller 525 can perform a fuse blow on the fuse 520 to scramble the column address according to a configuration. The fuse 520 can output the scrambled column address, and the controller 525 can transmit the output received from the fuse 520 to the multiplexer 540-a and the multiplexer 540-b. In such cases, the controller 525 can instruct the multiplexer 540-a and the multiplexer 540-b to switch the output of the multiplexer 540-a and the multiplexer 540-b according to the configuration (e.g., the scrambled column address). In some cases, the fuse 520 can be directly coupled with the multiplexer 540-a and the multiplexer 540-b. In such cases, the multiplexer 540-a and the multiplexer 540-b can receive the output from the fuse 520 and switch the output of the multiplexer 540-a and the multiplexer 540-b according to the output received from the fuse 520.

[0069] The column address can be manipulated via a configuration determined by the controller 525. For example, the controller 525 can determine a configuration for inverting one or more bits of the column address of a column plane. In some cases, the configuration can be an example of an address configuration as described with reference to Figure 4 The system 500 can be an example of an implementation; however, any number of latches 510, column address bits 515, fuses 520, controllers 525, column address decoders 530, or memory arrays 535 can be implemented into the system 500.

[0070] In some cases, an additional fuse can be implemented after fuse 520. For example, an additional fuse implemented after fuse 520 can operate as a level 2 fuse. For example, a first fuse (e.g., fuse 520) can operate according to a configuration provided by controller 525. If fuse 520 fails to operate according to the configuration, then controller 525 can route instructions to an additional fuse to implement the configuration. In some cases, fuse 520 can include control logic to verify whether fuse 520 is failing or completing the configuration.

[0071] Column address decoders 530 can be configured to access columns of a column plane during an access operation based on an address input into column address decoders 530. The address input into column address decoders 530 can be supplied via column address bits 515-a, 515-b, 515-c, and 515-d. In some cases, column address decoders 530 can change the internal of memory device 505 and the internal of memory banks based on the configuration. In some cases, column address decoders 530 can be unique to each memory bank, each column repair region, or each memory array 535. When fuse 520 performs a fuse blow, fuse 520 can change the structure of column address decoders 530, thereby sending commands to a new logical address (e.g., via column address bit 515-d) instead of sending commands to a previous logical address (e.g., via column address bit 515-c).

[0072] Controller 525 can configure address scrambling prior to performing a fuse blow. In some cases, controller 525 can be coupled with more than one fuse 520. In such cases, controller 525 can determine (e.g., identify) which fuse to perform a fuse blow based on the configuration. In some cases, controller 525 can determine which column plane of memory array 535 to perform a fuse blow. In such cases, fuse 520 can directly affect addressing in column address decoders 530. Incorporating fuse-based address scrambling can maximize the yield of memory device 505, thereby enabling memory device 505 to resolve scrambling based on yield and defects. In some cases, memory device 505 can access a different column address of a column plane than originally received based on the scrambling. The accessed column address can be determined based on receiving a command and the state of fuse 520.

[0073] In some cases, controller 525 may determine whether a defect in memory array 535 is repairable. For example, controller 525 may generate a defect map associated with a repair area and determine the column address of the defect based on the map. The defect map may be generated based on the detection of address conflicts in memory array 535. In some cases, controller 525 may determine a configuration (e.g., address scrambling configuration) based on the defect map. For example, different column planes or groups of column planes may be given different address scrambling to ensure that a fault in the repair area can be repaired using the global repair column plane of the repair area. Controller 525 may determine whether a defect associated with a column address can be repaired by global column repair. If the defect can be repaired by global column repair, then fuse 520 may redirect the column address to the global column repair component to repair the column plane. In such cases, the global column repair component may activate a different set of fuses than fuse 520 to repair the column plane. The set of fuses may contain seven to eight fuses for resolving the defect and enabling repair.

[0074] If a defect cannot be corrected by global column repair, controller 525 may configure address scrambling and perform fuse blowing according to the configuration. In some cases, controller 525 may determine whether a defect (e.g., an error occurring in an address conflict) can be corrected by error correction code (ECC). If the defect can be corrected by global column repair or ECC, controller 525 may avoid configuring address scrambling and performing fuse blowing. Defects that cannot be corrected by ECC may be instances of ECC conflicts. If a defect cannot be corrected by ECC, controller 525 may determine the configuration for scrambling the address. In some cases, the address scrambling configuration may be based on when the defect occurs, how many defects occur, or the order of both. In some instances, ECC conflicts may occur independently of global column repair address conflicts. For example, ECC conflicts and local column repair can benefit from scrambling the address because rescrambling the column plane to avoid ECC conflicts prevents the memory die from using repair techniques (i.e., correcting faulty bits after scrambling instead of ECC logic).

[0075] Figure 6 A block diagram 600 illustrates a memory device 605 supporting adjustable column address scrambling using fuses, according to an example disclosed herein. The memory device 605 may be as described in the references... Figures 1 to 5 Examples of aspects of the described memory device. Memory device 605 may include an error component 610, an address recognizer 615, a configuration component 620, a fuse component 625, a command component 630, a scrambling component 635, and an access component 640. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0076] Error component 610 can detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. In some examples, error component 610 can identify a conflict between a first column address associated with the first error and a second column address of the second error, where determining the configuration is based on identifying the conflict.

[0077] In some examples, error component 610 can determine that the first error or the second error cannot be repaired by ECC, where determining the configuration is based on determining that the first error or the second error cannot be repaired by ECC. In some examples, error component 610 can generate an error map in the memory array based on detecting the first error in the first column plane and the second error in the second column plane, where determining the configuration is based on generating the error map.

[0078] Address identifier 615 can identify a first column address of the first column plane and a second column address of the second column plane associated with the first error based on detecting the first error and the second error. In some examples, address identifier 615 can identify that an index of the first column address in the first column plane is the same as an index of the second column address in the second column plane, where identifying the conflict is based on identifying that the indices are the same.

[0079] Configuration component 620 can determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane based on identifying the first column address and the second column address. In some examples, configuration component 620 can scramble the column addresses of the first column plane to the different column addresses of the first column plane based on performing a fuse blow, where accessing the columns of the first column plane is based on the scrambled column addresses.

[0080] Fuse component 625 can perform a fuse blow associated with the first column plane to implement the determined configuration based on determining the configuration. In some examples, fuse component 625 can invert at least one bit of the first column address of the first column plane based on performing the fuse blow, where accessing the columns of the first column plane is based on inverting the at least one bit of the first column address.

[0081] In some examples, fuse component 625 can activate a set of fuses using a global column repair component to repair the first column plane of the memory array or the second column plane of the memory array based on performing the fuse blow, where the set of fuses are different than the fuse. In some examples, fuse component 625 can identify a fuse to perform the fuse blow based on determining the configuration, where performing the fuse blow is based on identifying the fuse. In some examples, fuse component 625 can apply a voltage to the fuse that satisfies a voltage threshold of the fuse based on determining the configuration, where performing the fuse blow is based on applying the voltage.

[0082] The command component 630 can receive a command that includes a first column address of a first column plane. In some cases, the command is a read command or a write command.

[0083] The scrambling component 635 can scramble the first column address based on a state of a fuse associated with scrambling column addresses of the first column plane. In some examples, the scrambling component 635 can scramble the first column address to indicate a first error in the first column plane and a second error in the second column plane, where scrambling the first column address is based on the first error and the second error.

[0084] The accessing component 640 can access a second column address of the first column plane that is different from the first column address based on scrambling the first column address. In some examples, the accessing component 640 can determine the second column address of the first column plane based on receiving the command and the state of the fuse, where accessing the second column address is based on determining the second column address. In some examples, the accessing component 640 can determine the state of the fuse based on receiving the command, where accessing the second column address is based on determining the state of the fuse.

[0085] Figure 7 A flow diagram illustrating one or more methods 700 that support adjustable column address scrambling using fuses as disclosed herein is shown. The operations of method 700 can be implemented by a memory device or its components as described herein. For example, the operations of method 700 can be performed by a memory device as described with reference to Figure 6 FIGS. 1-6. In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0086] At 705, the memory device can detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The operations of 705 can be performed according to the methods described herein. In some examples, aspects of the operations of 705 can be performed by an error component as described with reference to Figure 6 FIGS. 1-6. In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0087] At 710, the memory device can identify a first column address of the first column plane and a second column address of the second column plane associated with the first error based on detecting the first error and the second error. The operations of 710 can be performed according to the methods described herein. In some examples, aspects of the operations of 710 can be performed by an address identifier as described with reference to Figure 6 FIGS. 1-6. In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0088] At 715, the memory device can determine, for a first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane based on identifying the first column address and the second column address. The operations 715 can be performed according to the methods described herein. In some examples, aspects of the operations 715 can be performed by a configuration component as described with reference to Figure 6

[0089] At 720, the memory device can perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration based on determining the configuration. The operations 720 can be performed according to the methods described herein. In some examples, aspects of the operations 720 can be performed by a fuse component as described with reference to Figure 6

[0090] In some examples, an apparatus as described herein can perform one or more methods, such as method 700. The apparatus can include features, means, or instructions for detecting a first error in a first column plane of a memory array and a second error in a second column plane of the memory array, identifying a first column address of the first column plane and a second column address of the second column plane associated with the first error based on detecting the first error and the second error, determining, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane based on identifying the first column address and the second column address, and performing a fuse blow of a fuse associated with the first column plane to implement the determined configuration based on determining the configuration.

[0091] Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for scrambling the column addresses of the first column plane to the different column addresses of the first column plane based on performing the fuse blow, where accessing columns of the first column plane can be based on scrambling the column addresses. Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for inverting at least one bit of the first column address of the first column plane based on performing the fuse blow, where accessing columns of the first column plane can be based on inverting the at least one bit of the first column plane. Some examples of the method 700 and apparatus described herein can further include operations, features, means, or instructions for identifying a conflict between the first column address associated with the first error and the second column address of the second error, where determining the configuration can be based on identifying the conflict.

[0092] ​​Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for identifying that an index of the first column address in the first column plane can be the same as an index of the second column address in the second column plane, where identifying the conflict can be based on identifying that the index can be the same. Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for determining that the first error or the second error can not be repairable by an error correction code (ECC), where determining the configuration can be based on determining that the first error or the second error can not be repairable by the ECC.

[0093] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for activating a set of fuses to repair the first column plane of the memory array or the second column plane of the memory array based on performing the fuse blowing, where the set of fuses is different than the fuse. Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for generating an error map in the memory array based on detecting the first error in the first column plane and the second error in the second column plane, where determining the configuration can be based on generating the error map.

[0094] Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for identifying the fuse to perform the fuse blowing based on determining the configuration, where performing the fuse blowing can be based on identifying the fuse. Some examples of the method 700 and the apparatus described herein can further include operations, features, means, or instructions for applying a voltage to the fuse that satisfies a voltage threshold of the fuse based on determining the configuration, where performing the fuse blowing can be based on applying the voltage.

[0095] Figure 8 A flow diagram illustrating one or more methods 800 that support adjustable column address scrambling using fuses in accordance with examples as disclosed herein is shown. The operations of method 800 can be implemented by a memory device or its components as described herein. For example, the operations of method 800 can be performed by a memory device as described with reference to FIGS. 1-6 by a memory device as described with reference to FIGS. 7-8, by a memory device as described with reference to FIG. 9, by a memory device as described with reference to FIG. 10, or by a memory device as described with reference to FIG. 11. In some examples, a memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware. Figure 6

[0096] ​At 805, the memory device can receive a command that includes a first column address of a first column plane. The operations 805 can be performed according to the methods described herein. In some examples, aspects of the operations 805 can be performed by a command component as described with reference to Figure 6

[0097] At 810, the memory device can scramble the first column address based on a state of a fuse associated with scrambling column addresses of the first column plane. The operations 810 can be performed according to the methods described herein. In some examples, aspects of the operations 810 can be performed by a scrambling component as described with reference to Figure 6

[0098] At 815, the memory device can access a second column address of the first column plane that is different from the first column address based on scrambling the first column address. The operations 815 can be performed according to the methods described herein. In some examples, aspects of the operations 815 can be performed by an access component as described with reference to Figure 6

[0099] In some examples, an apparatus as described herein can perform one or more methods, such as the method 800. The apparatus can include features, means, or instructions for the actions, e.g., a non-transitory computer-readable medium storing instructions executable by a processor to: receive a command that includes a first column address of a first column plane; scramble the first column address based on a state of a fuse associated with scrambling column addresses of the first column plane; and access a second column address of the first column plane that is different from the first column address based on scrambling the first column address.

[0100] Some examples of the method 800 and apparatus described herein can further include operations, features, means, or instructions for determining the second column address of the first column plane based on receiving the command and the state of the fuse, where accessing the second column address can be based on determining the second column address. Some examples of the method 800 and apparatus described herein can further include operations, features, means, or instructions for determining the state of the fuse based on receiving the command, where accessing the second column address can be based on determining the state of the fuse.

[0101] Some examples of the method 800 and apparatus described herein can further include operations, features, means, or instructions for scrambling the first column address to indicate a first error in the first column plane and a second error in a second column plane, where scrambling the first column address can be based on the first error and the second error. In some examples of the method 800 and apparatus described herein, the command can be a read command or a write command. ​​​

[0102] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more methods can be combined.

[0103] An apparatus is described. The apparatus can include a memory array including one or more column planes each including a set of columns, a column address decoder configured to access a column of a column plane during an access operation based on an address input into the column address decoder, and one or more fuses coupled with an input of the column address decoder and used to implement a configuration to scramble a column address of the column plane to a different column address of the column plane when at least one of the one or more fuses is blown.

[0104] Some examples of the apparatus can include a fuse programmable scrambler configured to determine the configuration for scrambling the column address of the column plane to the different column address of the column plane. In some examples, the one or more fuses can be configured to scramble one or more bits of the address input into the column address decoder when at least one of the one or more fuses can be blown. Some examples of the apparatus can include a first column plane of the one or more column planes associated with a first error and a second column plane of the one or more column planes associated with a second error. In some examples, a voltage source is coupled with a fuse of the one or more fuses and configured to apply a voltage to the fuse to perform a fuse blow.

[0105] Some examples of the apparatus can include a repair component configured to perform a fuse blow on one or more fuses to repair one or more column planes. In some examples, the one or more fuses can be configured to redirect column addresses of the one or more column planes to a global column repair component to repair the one or more column planes. In some examples, the one or more fuses include one or more antifuses. Some examples of the apparatus can include a latch coupled with the one or more column planes. In some examples, the configuration to scramble column addresses is implemented on a per column plane basis, a per column plane group basis, a per section basis, or a per section group basis.

[0106] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields, or particles, or any combination thereof. Some drawings can convey information in a single format; however, a person of ordinary skill in the art will understand that signals can be represented using a bus, which can have a variety of bit widths.

[0107] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which signals can be passed between the components. Components are considered to be in electronic communication with each other (or in conductive contact or connected or coupled with each other) if there exists any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled with each other) at any given time can be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components or the conductive path between connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0108] The term "coupled" refers to a condition of an open circuit relationship between components (where signals cannot currently pass between the components through a conductive path) moving to a closed circuit relationship between the components (where signals can pass between the components through a conductive path). When a component (e.g., a controller) is coupled with other components, the component initiates a change to allow signals to flow between the other components through a conductive path where signals were not previously allowed to flow.

[0109] The term "isolated" refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, two components that are separated by a switch positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller initiates a change that prevents signals from flowing between the components using a conductive path where signals were previously allowed to flow.

[0110] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate by ion implantation or by any other doping method.

[0111] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials (e.g., metals). The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" when a voltage is applied to the gate of the transistor that is greater than or equal to the threshold voltage of the transistor. A transistor can be "turned off' or "deactivated" when a voltage is applied to the gate of the transistor that is less than the threshold voltage of the transistor.

[0112] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the instances that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0113] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by adding a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the detail can be applicable to any one of the similar components with the same first reference label irrespective of the second reference label.

[0114] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields, or particles, or any combination thereof.

[0115] The various illustrative blocks and modules described in connection with the present disclosure can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein, using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0116] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items prefaced by "at least one of indicates a disjunctive list such that, for example, a list of "at least one of A, B, or C" means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as "based on condition A" can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on."

[0117] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0118] The description is presented to enable one of ordinary skill in the art to make and use the application. Various modifications to the application will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the application. Therefore, the application is not to be limited to the examples and designs described herein, but to the broadest scope consistent with the principles and novel features disclosed.

Claims

1. A method of a memory device, comprising: blowing a fuse associated with a column plane to implement a configuration to scramble a column address of the column plane to a different column address of the column plane; based at least in part on performing the fuse blowing, using one or more multiplexers to invert at least one bit of a column address of the column plane; and based at least in part on inverting the at least one bit of the column address, accessing a column of the column plane.

2. The method of claim 1, further comprising: based at least in part on performing the fuse blowing, determining that a resistance associated with the fuse satisfies a threshold, wherein inverting the at least one bit of the column address is based at least in part on determining that the resistance satisfies the threshold.

3. The method of claim 2, further comprising: based at least in part on determining that the resistance satisfies the threshold, transmitting a value associated with the at least one bit to a column address decoder.

4. The method of claim 2, further comprising: based at least in part on performing the fuse blowing, inverting at least one other bit of the column address of the column plane; and based at least in part on determining that the resistance satisfies the threshold, transmitting a value associated with the at least one other bit to a column address decoder.

5. The method of claim 1, further comprising: based at least in part on performing the fuse blowing, determining that a resistance of the fuse does not satisfy a threshold.

6. The method of claim 5, further comprising: based at least in part on determining that the resistance does not satisfy the threshold, refraining from inverting at least one other bit of the column address of the column plane.

7. The method of claim 1, further comprising: based at least in part on inverting the at least one bit of the column address of the column plane, scrambling the column address of the column plane to the different column address of the column plane, wherein accessing the column of the column plane is based at least in part on scrambling the column address.

8. The method of claim 1, further comprising: based at least in part on performing the fuse blowing, determining whether an error occurred in a memory array, wherein the configuration is based at least in part on determining that the error occurred in the memory array.

9. A memory device, comprising: a memory array comprising one or more column planes; a column address decoder configured to access a column of a column plane during an access operation; one or more fuses coupled with the column address decoder and used to implement a configuration to scramble a column address of the column plane to a different column address of the column plane; and one or more multiplexers coupled with one or more fuses and used to invert at least one bit of a column address of the column plane.

10. The memory device of claim 9, wherein the one or more multiplexers comprise a first multiplexer configured to invert a first value of a first column address bit when the one or more fuses are in a first state, wherein the first value comprises the at least one bit of the column address of the column plane.

11. The memory device of claim 10, wherein the first multiplexer is configured to transmit the first value to the column address decoder when the one or more fuses are in the first state.

12. The memory device of claim 10, wherein the one or more multiplexers comprise a second multiplexer configured to invert a second value of a second column address bit when the one or more fuses are in the first state, wherein the second value comprises at least one other bit of the column address of the column plane.

13. The memory device of claim 12, wherein the second multiplexer is configured to transmit the second value to the column address decoder when the one or more fuses are in the first state.

14. The memory device of claim 9, wherein the one or more multiplexers are configured to scramble one or more address bits input to the column address decoder when at least one of the one or more fuses is blown.

15. The memory device of claim 9, wherein the one or more multiplexers are configured to switch one or more address bits input to the column address decoder according to the configuration.

16. The memory device of claim 9, further comprising: a voltage source coupled with a fuse of the one or more fuses and configured to apply a voltage to the fuse to perform a fuse blow.

17. A memory device, comprising: a memory array comprising a column plane; a fuse coupled with the memory array; and a multiplexer coupled with the fuse; and a controller coupled with the multiplexer and configured to cause the device to: blow a fuse of the fuse associated with the column plane to implement a configuration to scramble a column address of the column plane to a different column address of the column plane; based at least in part on performing the fuse blow, invert at least one bit of a column address of the column plane using the multiplexer; and access a column of the column plane based at least in part on inverting the at least one bit of the column address.

18. The memory device of claim 17, wherein the controller is further configured to cause the device to: determine a state of the fuse after performing the fuse blow, wherein inverting the at least one bit is based at least in part on determining the state.

19. The memory device of claim 18, wherein the controller is further configured to cause the device to: scramble the column address based at least in part on the state of the fuse associated with scrambling the column address of the column plane.

20. The memory device of claim 17, wherein the controller is further configured to cause the device to: apply a voltage to the fuse to perform the fuse blow, wherein inverting the at least one bit is based at least in part on applying the voltage.

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