Smart power module containing IGBT and super junction MOSFET

Abstract

An intelligent power module (IPM) includes first, second, third, and fourth chip support elements, a first set of insulated gate bipolar transistors (IGBTs), a second set of IGBTs, a first set of super junction metal-oxide-semiconductor field effect transistors (MOSFETs), a second set of super junction MOSFETs, a fifth chip support element, a low voltage integrated circuit, a high voltage integrated circuit, and a molded package. The low voltage and high voltage integrated circuits are connected to the fifth chip support element. The molded package encapsulates the first, second, third, and fourth chip support elements, the first set of IGBTs, the second set of IGBTs, the first set of super junction MOSFETs, the second set of super junction MOSFETs, the fifth chip support element, the low voltage IC, and the high voltage IC.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application is a continuation-in-part of pending patent application 16 / 585,388, filed September 27, 2019. This patent application is a continuation-in-part of pending patent application 16 / 585,437, filed September 27, 2019. The disclosure in patent application 16 / 585,388 and the disclosure in patent application 16 / 585,437 are hereby incorporated by reference. TECHNICAL FIELD

[0003] The present invention relates generally to a molded intelligent power module (IPM) for driving electric machines. More specifically, the present invention relates to a molded IPM containing insulated gate bipolar transistors (IGBTs) and super junction metal oxide semiconductor field effect transistors (MOSFETs). BACKGROUND

[0004] Pending patent application 16 / 585,388 and pending patent application 16 / 585,437 disclose a device comprising electrically coupled IGBPs and MOSFETs. It is advantageous to facilitate an IGBT package that has high conductivity at low temperatures and has excellent reverse current conduction characteristics.

[0005] Conventional IPMs include fast recovery diodes (FRDs). In the present invention, the FRDs are replaced by super junction MOSFETs. Advantages of the IPM of the present invention include higher efficiency to meet higher energy efficiency label requirements, wide operating power capability in high temperature environments, improved reliability performance, and efficient package design and configuration. SUMMARY

[0006] An IPM is disclosed having a plurality of separate chip support elements, a first set of IGBTs, a second set of IGBTs, a first set of super junction MOSFETs, a second set of super junction MOSFETs, a low voltage IC, and a high voltage IC. The low voltage IC is connected to the first set of IGBTs and the first set of super junction MOSFETs. The high voltage IC is connected to the second set of IGBTs and the second set of super junction MOSFETs. A molded package encapsulates the plurality of separate chip support elements, the first set of IGBTs, the second set of IGBTs, the first set of super junction MOSFETs, the second set of super junction MOSFETs, the low voltage IC, and the high voltage IC.

[0007] In one example, the wires are joined by a ball on stitch on ball (BSOB) method. In another example, the wires are joined by a bridge bond method. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1A top view of an intelligent power module (IPM) is shown in an example of the present invention.

[0009] Figure 2 A top view of another IPM is shown in an example of the present invention.

[0010] Figure 3 A top view of an IPM for driving a motor is shown in an example of the present invention. Figure 1 A circuit diagram of the IPM shown.

[0011] Figure 4 A top view of another IPM is shown in an example of the present invention.

[0012] Figure 5 A top view of another IPM is shown in an example of the present invention.

[0013] Figure 6 A top view of an IPM for driving a motor is shown in an example of the present invention. Figure 4 A circuit diagram of the IPM shown.

[0014] Figure 7 A top view of a method for ball on stitch (BSOB) wire bonding is shown in an example of the present invention.

[0015] Figure 8 A side view of a bridge bonding method for wire bonding is shown in an example of the present invention. DETAILED DESCRIPTION

[0016] Figure 1 A top view of an intelligent power module (IPM) 100 is shown in an example of the present invention. The IPM 100 has a die support element 102A, a die support element 102B, a die support element 102D, a die support element 110, a first set of insulated gate bipolar transistors (IGBTs) 141, a second set of IGBTs 151, a first set of super junction metal oxide semiconductor field effect transistors (MOSFETs) 161, a second set of super junction MOSFETs 171, a low voltage integrated circuit (IC) 120, a high voltage IC 122, and a molded package 198 (transparent as shown by the dashed lines).

[0017] The die support elements 102A, 102B, and 102D are separated from each other and aligned in a line one edge (the upper edge) of each die support element. The die support element 110 is separated from the die support elements 102A, 102B, and 102D. A majority of the die support element 110 extends along the aligned edges of the die support elements 102A, 102B, and 102D.

[0018] The first set of IGBTs 141 includes a first IGBT 142 and a second IGBT 144, the bottom collector of the first IGBT 142 is conductively connected to the die support element 102A, and the bottom collector of the second IGBT 144 is conductively connected to the die support element 102B. The second set of IGBTs 151 includes a first IGBT 152 and a second IGBT 154, the bottom collector of the first IGBT 152 is conductively connected to the die support element 102D, and the bottom collector of the second IGBT 154 is conductively connected to the die support element 102D.

[0019] The first set of super junction MOSFETs 161 includes a first super junction MOSFET 162 and a second super junction MOSFET 164, the bottom drain of the first super junction MOSFET 162 is conductively connected to the die support element 102A, and the bottom drain of the second super junction MOSFET 164 is conductively connected to the die support element 102B. The second set of super junction MOSFETs 171 includes a first super junction MOSFET 172 and a second super junction MOSFET 174, the bottom drain of the first super junction MOSFET 172 is conductively connected to the die support element 102D, and the bottom drain of the second super junction MOSFET 174 is conductively connected to the die support element 102D. In a preferred embodiment of the present invention, the first super junction MOSFET 162 and the second super junction MOSFET 164 of the first set of super junction MOSFETs 161 are connected in parallel with the first IGBT 142 and the second IGBT 144 of the first set of IGBTs 141, respectively. In another preferred embodiment of the present invention, the first super junction MOSFET 172 and the second super junction MOSFET 174 of the second set of super junction MOSFETs 171 are connected in parallel with the first IGBT 152 and the second IGBT 154 of the first set of IGBTs 151, respectively. The super junction MOSFET connected in parallel with the IGBT means that the gate of the super junction MOSFET is connected to the gate, the source and the drain of the super junction MOSFET are connected to the gate, the emitter and the collector of the IGBT, respectively. In Figure 1 In the example shown, the gate of each super junction MOSFET is connected to the gate of the corresponding IGBT arranged on the same die support element by a bond wire 101 having a size between 0.7 mil and 3 mil (17.8 microns and 76.2 microns). The source of each super junction MOSFET is connected to the emitter of the corresponding IGBT arranged on the same die support element by a connection member 103 (e.g., a bond wire, a ribbon, or a conductive clip). The connection member 103 has a size between 5 mil and 20 mil (127 microns and 508 microns). Preferably, the connection member 103 has a size at least 5 times larger than the bond wire 101.

[0020] The low voltage IC 120 is electrically connected to the gate of the first IGBT 142 of the first set of IGBTs 141 and the gate of the second IGBT 144 of the first set of IGBTs 141. The high voltage IC 122 is electrically connected to the gate of the first IGBT 152 of the second set of IGBTs 151 and the gate of the second IGBT 154 of the second set of IGBTs 151.

[0021] The molded package 198 encloses the die support elements 102A, 102B, and 102D, the first set of IGBTs 141, the second set of IGBTs 151, the first set of super junction MOSFETs 161, the second set of super junction MOSFETs 171, the die support element 110, the low voltage IC 120, and the high voltage IC 122.

[0022] The die support elements can be die attach pad (DAP) type or direct bond copper (DBC) type. In the example of the present invention, the die support element 102A is a die attach pad (DAP). The die support element 102B is a DAP. The die support element 102D is a DAP.

[0023] The low voltage IC 120 is disposed on the die support element 110 adjacent to the die support elements 102A and 102B, and the high voltage IC 122 is disposed on the die support element 110 adjacent to the die support element 102D. In the example of the present invention, the low voltage IC 120 and the high voltage IC 122 are directly connected to the die support element 110.

[0024] Figure 2 is a top view of an IPM 200 in the example of the present invention. The IPM 200 has a die support element 202A, a die support element 202B, a die support element 202C, a die support element 202D, a die support element 210, a first set of IGBTs 241, a second set of IGBTs 251, a first set of super junction MOSFETs 261, a second set of super junction MOSFETs 271, a low voltage IC 220, and a high voltage IC 222.

[0025] The first set of IGBTs 241 includes a first IGBT 242 connected to the die support element 202A and a second IGBT 244 connected to the die support element 202B. The second set of IGBTs 251 includes a first IGBT 252 connected to the die support element 202D and a second IGBT 254 connected to the die support element 202D.

[0026] The first group of superjunction MOSFETs 261 includes a first superjunction MOSFET 262 connected to die support element 202A and a second superjunction MOSFET 264 connected to die support element 202B. The second group of superjunction MOSFETs 271 includes a first superjunction MOSFET 272 connected to die support element 202D and a second superjunction MOSFET 274 connected to die support element 202D.

[0027] The low-voltage IC 220 is electrically connected to the gate of the first IGBT 242 and the gate of the second IGBT 244 of the first IGBT 241. The high-voltage IC 222 is electrically connected to the gate of the first IGBT 252 and the gate of the second IGBT 254 of the second IGBT 251.

[0028] A low-voltage IC 220 is disposed on a chip support element 210 adjacent to chip support elements 202A, 202B, and 202C, and a high-voltage IC 222 is disposed on a chip support element 210 adjacent to chip support element 202D. In this example of the invention, the low-voltage IC 220 and the high-voltage IC 222 are directly connected to the chip support element 210. Except... Figure 2 The IPM200 shown includes an optional die support element 202C, and no IGBT or superjunction MOSFET is connected outside of the die support element 202C; all others are connected to it. Figure 1 The IPM100 shown is similar. Alternatively, one of the die support elements 202A or 202B can be used as an optional die support element, in which no IGBT or superjunction MOSFET is connected. This provides flexibility and cost savings for IPM modules with different lead configurations sharing the same lead frame.

[0029] Figure 3 In the example of this invention, the motor is used for driving the motor. Figure 1 The IPM 100 shown and Figure 2 The circuit diagram 300 for the IPM200 is shown. It is a two-phase, bootstrap, full-bridge inverter IPM, comprising eight active devices with four gate driver channels. The low-voltage IC 320 controls the first IGBT 342 and the second IGBT 344 of the first IGBT group. The high-voltage IC 322 controls the first IGBT 352 and the second IGBT 354 of the second IGBT group.

[0030] The drain of the first super junction MOSFET 362 is electrically connected to the source of the first super junction MOSFET 372 of the second set of super junction MOSFETs. The drain of the second super junction MOSFET 364 of the first set of super junction MOSFETs is electrically connected to the source of the fourth super junction MOSFET 374 of the second set of super junction MOSFETs. In Figure 1 , Figure 2 and Figure 3 In the example shown in FIGS. 36-37, the source of the first super junction MOSFET 362 of the first set of super junction MOSFETs and the source of the second super junction MOSFET 364 are electrically isolated. In an alternative example, the source of the first super junction MOSFET 362 of the first set of super junction MOSFETs and the source of the second super junction MOSFET 364 are electrically connected (not shown).

[0031] Figure 4 is a top view of an IPM 400 in an example of the present application. The IPM 400 has a die support element 402A, a die support element 402B, a die support element 402C, a die support element 402D, a die support element 410, a first set of IGBTs 441, a second set of IGBTs 451, a first set of super junction MOSFETs 461, a second set of super junction MOSFETs 471, a low voltage integrated circuit (IC) 420, a high voltage IC 422, and a molded package 498 (transparent where indicated by dashed lines).

[0032] The die support elements 402A, 402B, 402C, and 402D are separated from each other and arranged in a line with one edge (the upper edge) of each die support element substantially aligned. The die support element 410 is separated from the die support elements 402A, 402B, 402C, and 402D. Most of the die support element 410 extends along the aligned edges of the die support elements 402A, 402B, 402C, and 402D.

[0033] The first set of IGBTs 441 includes a first IGBT 442 and a second IGBT 444, the bottom collector of the first IGBT 442 is conductively connected to the die support element 402A, the bottom collector of the second IGBT 444 is conductively connected to the die support element 402B, and a third IGBT 446 having a bottom collector conductively connected to the die support element 402C. The second set of IGBTs 451 includes a first IGBT 452 and a second IGBT 454, the bottom collector of the first IGBT 452 is conductively connected to the die support element 402D, the bottom collector of the second IGBT 454 is conductively connected to the die support element 402D, and a third IGBT 456 having a bottom collector conductively connected to the die support element 402D.

[0034] The first set of super-junction MOSFETs 461 includes a first super-junction MOSFET 462 and a second super-junction MOSFET 464, the bottom drain of the first super-junction MOSFET 462 is conductively connected to the die support element 402A, the bottom drain of the second super-junction MOSFET 464 is conductively connected to the die support element 402B, and a third super-junction MOSFET 466 having a bottom drain conductively connected to the die support element 402C. The second set of super-junction MOSFETs 471 includes a first super-junction MOSFET 472 and a second super-junction MOSFET 474, the bottom drain of the first super-junction MOSFET 472 is conductively connected to the die support element 402D, the bottom drain of the second super-junction MOSFET 474 is conductively connected to the die support element 402D, and a third super-junction MOSFET 476 having a bottom drain conductively connected to the die support element 402D. In a preferred example of the invention, each super-junction MOSFET of the first set of super-junction MOSFETs 461 is connected in parallel with a corresponding IGBT of the first set of IGBTs 441 arranged on the same die support element. In another optional example of the invention, each super-junction MOSFET of the second set of super-junction MOSFETs 471 is connected in parallel with a corresponding IGBT of the second set of IGBTs 451 arranged on the same die support element.

[0035] The low voltage IC 420 is electrically connected to the gate of the first IGBT 442 of the first set of IGBTs 441, the gate of the second IGBT 444 of the first set of IGBTs 441, and the gate of the third IGBT 446 of the first set of IGBTs 441. The high voltage IC 422 is electrically connected to the gate of the first IGBT 452 of the second set of IGBTs 451, the gate of the second IGBT 454 of the second set of IGBTs 451, and the gate of the third IGBT 456 of the second set of IGBTs 451.

[0036] The molded package 498 encapsulates the die support elements 402A, 402B, 402C, and 402D, the first set of IGBTs 441, the second set of IGBTs 451, the first set of super junction MOSFETs 461, the second set of super junction MOSFETs 471, the die support element 410, the low voltage IC 420, and the high voltage IC 422.

[0037] The chip support elements can be die attach pad (DAP) type or direct bond copper (DBC) type. In the example of the present application, the first chip support element 402A is a first die attach pad (DAP). The second chip support element 402B is a second DAP. The third chip support element 402C is a third DAP. The fourth chip support element 402D is a fourth DAP.

[0038] The low voltage IC 420 is disposed on the die support element 410 adjacent to the chip support elements 402A, 402B, and 402C, and the high voltage IC 422 is disposed on the die support element 410 adjacent to the chip support element 402D. In the example of the present application, the low voltage IC 420 and the high voltage IC 422 are directly connected to the die support element 410.

[0039] In the example of the present application, a single gate pad is used. The first IGBT 442 of the first set of IGBTs 441 includes one single gate pad 481A. The second IGBT 444 of the first set of IGBTs 441 includes one single gate pad 481B. The third IGBT 446 of the first set of IGBTs 441 includes one single gate pad 481C. The first IGBT 452 of the second set of IGBTs 451 includes one single gate pad 483A. The second IGBT 454 of the second set of IGBTs 451 includes one single gate pad 483B. The third IGBT 456 of the second set of IGBTs 451 includes one single gate pad 483C.

[0040] The first super junction MOSFET 462 of the first group of super junction MOSFETs 461 includes a single gate pad 491A. The second super junction MOSFET 464 of the first group of super junction MOSFETs 461 includes a single gate pad 491B. The third super junction MOSFET 466 of the first group of super junction MOSFETs 461 includes a single gate pad 491C. The first super junction MOSFET 472 of the second group of super junction MOSFETs 471 includes a single gate pad 493A. The second super junction MOSFET 474 of the second group of super junction MOSFETs 471 includes a single gate pad 493B. The third super junction MOSFET 476 of the second group of super junction MOSFETs 471 includes a single gate pad 493C.

[0041] The IPM 400 includes a first group of wires 401, a second group of wires 403, a third group of wires 411, and a fourth group of wires 413. Each wire in the groups of wires 401, 403, 411, and 413 can include a bond wire having a size between 0.7 mil to 3 mil (17.8 microns to 76.2 microns), preferably made of gold, copper, or aluminum oxide.

[0042] The first group of wires 401 includes a first wire 409A, a second wire 409B, and a third wire 409C. The first wire 409A connects a first pad of the low voltage IC 420 to the single gate pad 481A of the first IGBT 442 of the first group of IGBTs 441. The second wire 409B connects a second pad of the low voltage IC 420 to the single gate pad 481B of the second IGBT 444 of the first group of IGBTs 441. The third wire 409C connects a third pad 481B of the low voltage IC 420 to the single gate pad 481C of the third IGBT 446 of the first group of IGBTs 441.

[0043] The second group of wires 403 includes a first wire 404A, a second wire 404B, and a third wire 404C. The first wire 404A connects a first pad of the high voltage IC 422 to the single gate pad 483A of the first IGBT 452 of the second group of IGBTs 451. The second wire 404B connects a second pad of the high voltage IC 422 to the single gate pad 483B of the second IGBT 454 of the second group of IGBTs 451. The third wire 404C connects a third pad of the high voltage IC 422 to the single gate pad 483C of the third IGBT 456 of the second group of IGBTs 451.

[0044] The third set of wires 411 includes a first wire 412A, a second wire 412B, and a third wire 412C. The first wire 412A connects the individual gate pad 481 A of the first IGBT 442 of the first set of IGBTs 441 to the individual gate pad 491 A of the first super junction MOSFET 462 of the first set of super junction MOSFETs 461. The second wire 412B connects the individual gate pad 481 B of the second IGBT 444 of the first set of IGBTs 441 to the individual gate pad 491 B of the second super junction MOSFET 464 of the first set of super junction MOSFETs 461. The third wire 412C connects the individual gate pad 481 C of the third IGBT 446 of the first set of IGBTs 441 to the individual gate pad 491 C of the third super junction MOSFET 466 of the first set of super junction MOSFETs 461.

[0045] The fourth set of wires 413 includes a first wire 414A, a second wire 414B, and a third wire 414C. The first wire 414A connects the individual gate pad 483 A of the first IGBT 452 of the second set of IGBTs 451 to the individual gate pad 493 A of the first super junction MOSFET 472 of the second set of super junction MOSFETs 471. The second wire 414B connects the individual gate pad 483B of the second IGBT 454 of the second set of IGBTs 451 to the individual gate pad 493B of the second super junction MOSFET 474 of the second set of super junction MOSFETs 471. The third wire 414C connects the individual gate pad 483C of the third IGBT 456 of the second set of IGBTs 451 to the individual gate pad 493C of the third super junction MOSFET 476 of the second set of super junction MOSFETs 471.

[0046] The IPM 400 also includes a plurality of connection members 415, each of which respectively connects a top emitter electrode of each IGBT to a top source electrode of a corresponding super junction MOSFET arranged on the same die support element. The connection members 415 are sized between 5 mils to 20 mils (127 microns to 508 microns). Preferably, the connection members 415 are at least 5 times larger in size than the bonding leads in the sets of wires 401, 403, 411, and 413.

[0047] Figure 5represents a top view of IPM 500 in an example of the invention. IPM 500 has die support element 502A, die support element 502B, die support element 502C, die support element 502D, die support element 502E, die support element 510, first set of IGBTs 541, second set of IGBTs 551, first set of super junction MOSFETs 561, second set of super junction MOSFETs 571, low voltage integrated circuit (IC) 520, high voltage IC 522, and power factor correction (PFC) diode 599. Chip support elements 502A, 502B, 502C, 502D, 502E, and 510 are electrically insulated from each other.

[0048] The first set of IGBTs 541 includes first IGBT 542 connected to chip support element 502A, second IGBT 544 connected to chip support element 502B, and third IGBT 546 connected to chip support element 502C. The second set of IGBTs 551 includes first IGBT 552 connected to chip support element 502D, second IGBT 554 connected to chip support element 502D, and third IGBT 556 connected to chip support element 502D. Power factor correction (PFC) diode 599 is connected to chip support element 502E.

[0049] The first set of super junction MOSFETs 561 includes first super junction MOSFET 562 connected to die support element 502A, second super junction MOSFET 564 connected to die support element 502B, and third super junction MOSFET 566 connected to die support element 502C. The second set of super junction MOSFETs 571 includes first super junction MOSFET 572 connected to die support element 502D, second super junction MOSFET 574 connected to die support element 502D, and third super junction MOSFET 576 connected to die support element 502D. In a preferred example of the invention, each super junction MOSFET of the first set of super junction MOSFETs 561 is connected in parallel with a corresponding IGBT of the first set of IGBTs 541 arranged on the same die support element. In another preferred example of the invention, each super junction MOSFET of the second set of super junction MOSFETs 571 is connected in parallel with a corresponding IGBT of the second set of IGBTs 551 arranged on the same die support element.

[0050] The low-voltage IC 520 is electrically connected to the gate of the first IGBT 542, the gate of the second IGBT 544, and the gate of the third IGBT 546 of the first IGBT 541. The high-voltage IC 522 is electrically connected to the gate of the first IGBT 552, the gate of the second IGBT 554, and the gate of the third IGBT 556 of the second IGBT 551.

[0051] A low-voltage IC 520 is disposed on a chip support element 510 adjacent to chip support elements 502A, 502B, and 502C, and a high-voltage IC 522 is disposed on a chip support element 510 adjacent to chip support element 502D. In this example of the invention, the low-voltage IC 520 and the high-voltage IC 522 are directly connected to the chip support element 510. The IPM 500 is similar to the IPM 400, except that the IPM 500 includes an optional chip support element 502E on which a power factor correction (PFC) diode 599 is disposed. The electrodes of the power factor correction (PFC) diode 599 may be electrically insulated from the first and second groups of IGBTs, as well as the low-voltage IC 520 and the high-voltage IC 522.

[0052] Figure 6 In the example of this invention, the motor is used for driving the motor. Figure 4 The circuit diagram 600 for the IPM 400 is shown. It is a three-phase, bootstrap inverter IPM comprising 12 active devices with six gate driver channels. The low-voltage IC 620 controls the first IGBT 642, the second IGBT 644, and the third IGBT 646 of the first IGBT group 641. The high-voltage IC 622 controls the first IGBT 652, the second IGBT 654, and the third IGBT 656 of the second IGBT group 651.

[0053] The drain D of the first super junction MOSFET 672 of the second group of super junction MOSFETs 671, the drain of the second super junction MOSFET 674 of the second group of super junction MOSFETs 671, and the drain of the third super junction MOSFET 676 of the second group of super junction MOSFETs 671 are electrically connected. The drain of the first super junction MOSFET 662 of the first group of super junction MOSFETs 661 is electrically connected to the source of the first super junction MOSFET 672 of the second group of super junction MOSFETs 671. The drain of the second super junction MOSFET 664 of the first group of super junction MOSFETs 661 is electrically connected to the source of the second super junction MOSFET 674 of the second group of super junction MOSFETs 671. The drain of the third super junction MOSFET 666 of the first group of super junction MOSFETs 661 is electrically connected to the source of the third super junction MOSFET 676 of the second group of super junction MOSFETs 671.

[0054] The collector of the first IGBT 642 of the first group of IGBTs 641 is electrically connected to the drain of the first super junction MOSFET 662 of the first group of super junction MOSFETs 661. The collector of the second IGBT 644 of the first group of IGBTs 641 is electrically connected to the drain of the second super junction MOSFET 664 of the first group of super junction MOSFETs 661. The collector of the third IGBT 646 of the first group of IGBTs 641 is electrically connected to the drain of the third super junction MOSFET 666 of the first group of super junction MOSFETs 661.

[0055] The collector of the first IGBT 652 of the second group of IGBTs 651 is electrically connected to the drain of the first super junction MOSFET 672 of the second group of super junction MOSFETs 671. The collector of the second IGBT 654 of the second group of IGBTs 651 is electrically connected to the drain of the second super junction MOSFET 674 of the second group of super junction MOSFETs 671. The collector of the third IGBT 656 of the second group of IGBTs 651 is electrically connected to the drain of the third super junction MOSFET 676 of the second group of super junction MOSFETs 671.

[0056] The emitter of the first IGBT 642 in the first IGBT group 641 is electrically connected to the source of the first superjunction MOSFET 662 in the first superjunction MOSFET group 661. The emitter of the second IGBT 644 in the first IGBT group 641 is electrically connected to the source of the second IGBT, the superjunction MOSFET 664 in the first superjunction MOSFET group 661. The emitter of the third IGBT 646 in the first IGBT group 641 is electrically connected to the source of the third superjunction MOSFET 666 in the first superjunction MOSFET group 661.

[0057] The emitter of the first IGBT 652 in the second IGBT group 651 is electrically connected to the source of the first superjunction MOSFET 672 in the second superjunction MOSFET group 671. The emitter of the second IGBT 654 in the second IGBT group 651 is electrically connected to the source of the second superjunction MOSFET 674 in the second superjunction MOSFET group 671. The emitter of the third IGBT 656 in the second IGBT group 651 is electrically connected to the source of the third superjunction MOSFET 676 in the second superjunction MOSFET group 671.

[0058] Figure 7 A represents a top view of the stitch-on-ball (BSOB) method for wire bonding in an embodiment of the present invention. A first conductor 750 electrically and mechanically connects a first device 730 to a second device 740. A second conductor 770 electrically and mechanically connects the second device 740 to conductor 760.

[0059] In the example of this invention, the connection is made via the BSOB method. Figure 4 Each wire of the first group of wires 401 and Figure 4 The corresponding conductor of the third group of conductors 411. Figure 4 The second group of conductors 403, each conductor and Figure 4 The corresponding wires of the fourth group of wires 413 are connected by the BSOB method.

[0060] Figure 8 This is a side view illustrating a bridging bonding method for wire bonding in an embodiment of the present invention. A second solder ball 820 is directly stacked on top of a first solder ball 810. A first conductor 870 electrically connects a first device 840 to a conductor 860. A second conductor 850 electrically connects a second device 830 to a first device 840.

[0061] In an example of the present invention, Figure 4 Each wire of the first group of wires 401 and Figure 4 The corresponding wires of the third group of wires 411 are connected by a bridging method. Figure 4each wire of the second set of wires 403 and Figure 4 corresponding wires of the fourth set of wires 413 are connected by a bridge method.

[0062] One of ordinary skill in the art will recognize that modifications to the embodiments disclosed herein are possible. For example, the total number of IGBTs connected to the fourth die support element can vary. Other modifications can be made by one of ordinary skill in the art and all such modifications are considered to be within the scope of the invention as defined by the claims.

Claims

1. An intelligent power module (IPM) for driving a motor, the IPM comprising: The first, second, third, and fourth chip support elements are separated from each other; The first group of insulated gate bipolar transistors (IGBTs) includes: The first IGBT is connected to the third chip support element; and The second IGBT is connected to the fourth chip support element; The second group of IGBTs includes: The first IGBT is connected to the second chip support element; and The second IGBT is connected to the second chip support element; The first group of superjunction metal-oxide-semiconductor field-effect transistors (MOSFETs) includes: The first superjunction MOSFET is connected to the third chip support element; and The second superjunction MOSFET is connected to the fourth chip support element; The second group of superjunction MOSFETs includes: The first superjunction MOSFET is connected to the second chip support element; The second superjunction MOSFET is connected to the second chip support element; A low-voltage integrated circuit (IC) is connected to a first chip support element; the low-voltage IC is electrically connected to the first IGBT of the first group of IGBTs and the second IGBT of the first group of IGBTs. A high-voltage IC is connected to the first chip support element, and the high-voltage IC is electrically connected to the first IGBT of the second IGBT group and the second IGBT of the second IGBT group; and A molded package encapsulates the first, second, third, and fourth chip support elements, the first group of IGBTs, the second group of IGBTs, the first group of superjunction MOSFETs, the second group of superjunction MOSFETs, a low-voltage IC, and a high-voltage IC. Each IGBT in the first and second groups of IGBTs includes a separate gate pad; and each superjunction MOSFET in the first and second groups of superjunction MOSFETs includes a separate gate pad; It also includes the first set of leads, the second set of leads, the third set of leads, and the fourth set of leads; Each lead in the first group of leads connects the corresponding pad of the low-voltage IC to the individual gate pad of the corresponding IGBT in the first group of IGBTs. Each lead in the second group of leads connects the corresponding pad of the high-voltage IC to the individual gate pad of the corresponding IGBT in the second group of IGBTs. Each lead in the third set of leads connects the individual gate pad of the corresponding IGBT of the first set of IGBTs to the individual gate pad of the corresponding superjunction MOSFET of the first set of superjunction MOSFETs, wherein the corresponding IGBT and the corresponding superjunction MOSFET are disposed on the same die support element; and Each lead in the fourth group connects the individual gate pad of the corresponding IGBT in the second group of IGBTs to the individual gate pad of the corresponding superjunction MOSFET in the second group of superjunction MOSFETs; It also includes a fifth chip support element, which is adjacent to the third and fourth chip support elements, and the fifth chip support element is not connected to an IGBT or a superjunction MOSFET.

2. The IPM of claim 1, wherein each IGBT in the first group of IGBTs includes a bottom collector electrically connected to a corresponding chip support element; Each IGBT in the second group includes a bottom collector that is electrically connected to the second chip support element; Each of the superjunction MOSFETs in the first group includes a bottom drain electrode that is electrically connected to the corresponding chip support element. as well as Each of the superjunction MOSFETs in the second group includes a bottom drain electrode that is electrically connected to the second chip support element.

3. The IPM of claim 2 further includes an additional chip support element separate from the first, second, third and fourth chip support elements; wherein no IGBT or superjunction MOSFET is connected to this additional chip support element.

4. The IPM of claim 2 further includes a fifth chip support element separate from the first, second, third and fourth chip support elements; The molded package encapsulates the fifth chip support element; The first group of IGBTs also includes a third IGBT connected to the fifth chip support element; The second group of IGBTs also includes a third IGBT connected to the second chip support element; The first group of superjunction MOSFETs also includes a third superjunction MOSFET connected to the fifth chip support element; and The second group of superjunction MOSFETs also includes a third superjunction MOSFET connected to the second chip support element.

5. The IPM of claim 4, wherein the low-voltage IC is electrically connected to the third IGBT of the first group of IGBTs; and The high-voltage IC is electrically connected to the third IGBT of the second IGBT group.

6. The IPM of claim 4, wherein a power factor correction diode is arranged on a sixth chip support element, and the first chip support element, the second chip support element, the third chip support element, the fourth chip support element, the fifth chip support element and the sixth chip support element are electrically insulated from each other.

7. The IPM of claim 1, wherein each lead in the first set of leads and the corresponding lead in the third set of leads are joined by a ball-on-ball (BSOB) method; and Each lead in the second group of leads and each lead in the fourth group of leads are connected using the BSOB method.

8. The IPM of claim 1, wherein each lead of the first set of leads and the corresponding lead of the third set of leads are connected by a bridging method, such that the second bonding ball is directly stacked on top of the first bonding ball; and Each lead in the second group of leads and the corresponding lead in the fourth group of leads are connected by a bridging method, so that the fourth bonding ball is directly stacked on top of the third bonding ball.

9. The IPM of claim 1, wherein each of the first, second, third and fourth sets of leads comprises a bonding lead with a size between 17.8 micrometers and 76.2 micrometers.

10. The IPM of claim 9, wherein the emitter electrode of each IGBT in the first group of IGBTs is electrically connected to the source electrode of the corresponding superjunction MOSFET in the first group of superjunction MOSFETs via a corresponding connection element, and the first group of superjunction MOSFETs are located on the same chip support element; and In the second group of IGBTs, the emitter electrode of each IGBT is electrically connected to the source electrode of the corresponding superjunction MOSFET in the second group of superjunction MOSFETs through a corresponding connection element.

11. The IPM of claim 10, wherein the dimensions of the corresponding connecting element are at least five times larger than the bonding lead.

12. The IPM of claim 11, wherein the bottom drain electrode of the first superjunction MOSFET of the first group of superjunction MOSFETs is electrically connected to the emitter electrode of the first IGBT of the second group of IGBTs; The bottom drain electrode of the second superjunction MOSFET in the first group of superjunction MOSFETs is electrically connected to the emitter electrode of the second IGBT in the second group of IGBTs; The bottom drain electrode of the third superjunction MOSFET in the first group of superjunction MOSFETs is electrically connected to the emitter electrode of the third IGBT in the second group of IGBTs.

13. An intelligent power module (IPM) for driving a motor, the IPM comprising: Multiple separate chip support components; The first group of insulated gate bipolar transistors (IGBTs) includes two or more IGBTs, each connected to a different chip support element among multiple chip support elements; The second group of IGBTs includes two or more IGBTs, each of which is connected to the same chip support element among multiple chip support elements. The first group of superjunction metal-oxide-semiconductor field-effect transistors (MOSFETs) includes two or more superjunction MOSFETs, each of which is connected in parallel to the respective IGBT of the first group of IGBTs; The second group of superjunction metal-oxide-semiconductor field-effect transistors (MOSFETs) includes two or more superjunction MOSFETs, each of which is connected in parallel to the respective IGBT of the second group of IGBTs; A low-voltage integrated circuit (IC) is electrically connected to each of the IGBTs in the first group of IGBTs; A high-voltage integrated circuit (IC) is electrically connected to each of the IGBTs in the second group of IGBTs; as well as A molded package encapsulates multiple chip support components, a first group of IGBTs, a second group of IGBTs, a first group of superjunction MOSFETs, a second group of superjunction MOSFETs, a low-voltage IC, and a high-voltage IC. Each IGBT in the first and second groups of IGBTs includes a separate gate pad; and each superjunction MOSFET in the first and second groups of superjunction MOSFETs includes a separate gate pad; It also includes the first set of leads, the second set of leads, the third set of leads, and the fourth set of leads; Each lead in the first group of leads connects the corresponding pad of the low-voltage IC to the individual gate pad of the corresponding IGBT in the first group of IGBTs. Each lead in the second group of leads connects the corresponding pad of the high-voltage IC to the individual gate pad of the corresponding IGBT in the second group of IGBTs. Each lead in the third set of leads connects the individual gate pad of the corresponding IGBT of the first set of IGBTs to the individual gate pad of the corresponding superjunction MOSFET of the first set of superjunction MOSFETs, wherein the corresponding IGBT and the corresponding superjunction MOSFET are disposed on the same die support element; and Each lead in the fourth group of leads connects the individual gate pad of the corresponding IGBT of the second group of IGBTs to the individual gate pad of the corresponding superjunction MOSFET of the second group of superjunction MOSFETs. An optional chip support element is adjacent to a different chip support element connected to the first group of IGBTs, and the optional chip support element is not connected to any IGBT or superjunction MOSFET.

14. The IPM of claim 13, wherein each IGBT in the first group of IGBTs includes a bottom collector electrically connected to a corresponding chip support element; Each IGBT in the second group of IGBTs includes a bottom collector that is electrically connected to the same chip support element. Each of the superjunction MOSFETs in the first group includes a bottom drain electrode that is electrically connected to the corresponding chip support element; and Each of the superjunction MOSFETs in the second group includes a bottom drain electrode that is electrically connected to the same chip support element.

15. The IPM of claim 13, wherein each IGBT in the first and second groups of IGBTs includes a separate gate pad; and wherein each superjunction MOSFET in the first and second groups of superjunction MOSFETs includes a separate gate pad.

16. The IPM of claim 15, wherein the individual gate pad of each IGBT is electrically connected via a lead to the individual gate pad of a corresponding superjunction MOSFET connected in parallel with each IGBT.

17. The IPM of claim 16, wherein the lead comprises a bonding lead with a size ranging from 17.8 micrometers to 76.2 micrometers.

18. The IPM of claim 17, wherein the emitter gate of each IGBT in the first and second groups of IGBTs is electrically connected, through a corresponding connection element, to the source electrode of the corresponding superjunction MOSFET in the first and second groups of superjunction MOSFETs connected in parallel with each IGBT.

19. The IPM of claim 18, wherein the dimensions of the corresponding connecting element are at least five times larger than the bonding lead.

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