Semiconductor structure

Abstract

The present invention provides a semiconductor structure. An insulating pattern at least covers the sidewall of a first opening of a spacer node contact structure, and the upper surface of the insulating pattern is also recessed into the first opening to form a recessed portion, so that a single film layer can replace the existing insulating pattern composed of two film layers, thereby omitting the steps of grinding and removing a portion of the thickness of the insulating material layer and re-forming the mask material layer in the prior art, simplifying the preparation process of the memory, and improving the preparation efficiency. Moreover, since multiple grinding processes are usually used to flatten the surface of the substrate when forming a capacitor structure, even if the surface of the insulating pattern is uneven, it will not affect the performance of the memory.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure. Background Art

[0002] A memory, such as a dynamic random access memory (DRAM), generally has a memory cell array, wherein the memory cell array includes a plurality of memory cells arranged in an array. The memory has a plurality of word line structures and bit line structures, wherein the word line structures are embedded in a substrate, the bit line structures are formed on the substrate and are electrically connected to corresponding memory cells, and the memory further includes a capacitor structure, wherein the capacitor structure is used to store charges representing stored information, and the memory cell can be electrically connected to the capacitor structure through a node contact structure, thereby realizing the storage function of each memory cell.

[0003] Figure 1a to Figure 1e The structure diagram of a conventional memory formation method is shown in FIG. Figure 1a to Figure 1d Some memory formation methods include: Figure 1a As shown, after the bit line structure 200' is formed on the substrate 100', a conductive material layer 300' is formed to cover the substrate 100' and the bit line structure 200'. Figure 1b As shown, the conductive material layer 300' and a portion of the bit line structure 200' are etched to form a first opening 300a', wherein the first opening 300a' separates the remaining conductive material layer 300' into a plurality of node contact structures 300b'. Figure 1c As shown, an insulating material layer 410' is formed on the plurality of node contact structures 300b', and the insulating material layer 410' also fills the first opening 300a'. At this time, since the upper surface of the insulating material layer 410' may be uneven, as shown in FIG. Figure 1d As shown, the insulating material layer 410' needs to be ground first until the insulating material layer 410' on the upper surface of the node contact structure 300b' is removed to make the insulating material layer 410' and the upper surface of the node contact structure 300b' flat. Figure 1eAs shown, a mask material layer 420' and a stacked material layer 500' are sequentially formed on the insulating material layer 410', and finally the stacked material layer 500' and the mask material layer 420' are etched to form a second opening 501a', so that the second opening 501a' exposes the node contact structure 300b', and the lower electrode of the capacitor structure can be formed in the second opening 501a' in the subsequent steps. At this time, the remaining insulating material layer 410' and the mask material layer 420' constitute a plurality of insulating patterns 400'. Each insulating pattern 400' here includes two film layers (stacked insulating material layer 410' and mask material layer 420'), and the roles played by the two film layers in the subsequent steps are actually the same, so the use of two film layers to form the insulating pattern 400' increases the difficulty and complexity of the preparation process of the memory and reduces the preparation efficiency. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor structure which simplifies the formation process of a memory without affecting the performance of the memory.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a memory, comprising: a substrate; a plurality of node contact structures extending upward from the substrate; a plurality of first openings located between adjacent node contact structures; an insulating pattern located in the first opening, the insulating pattern at least covering the sidewalls of the first opening and extending upward, the upper surface of the insulating pattern also being recessed into the first opening to form a recessed portion; and a capacitor structure comprising a lower electrode, a metal oxide layer and an upper electrode, wherein the lower electrode is in direct contact with the node contact structure, the metal oxide layer is at least partially located on the insulating pattern and covers the recessed portion to form an air gap.

[0006] Optionally, the metal oxide layer fills a portion of the depth of the recess to form an air gap.

[0007] Optionally, the insulating pattern extends upward and covers the top of the node contact structure.

[0008] Optionally, the sidewalls of the insulation pattern contact the sidewalls of the node contact structure and the lower electrode simultaneously.

[0009] Optionally, the topmost portion of the insulating pattern is higher than the topmost portion of the node contact structure.

[0010] Optionally, the node contact structure is divided into an upper node contact portion and a lower node contact portion with the height position of the bottom of the first opening as a boundary, and the maximum width dimension of the upper node contact portion is greater than the maximum width dimension of the lower node contact portion.

[0011] The present invention also provides another semiconductor structure, comprising: a substrate; a plurality of node contact structures extending upward from the substrate; a plurality of first openings located between adjacent node contact structures; an insulating pattern located in the first opening, the insulating pattern at least covering the side walls of the first opening and extending upward, the upper surface of the insulating pattern also being recessed into the first opening to form a recess; and a capacitor structure comprising a lower electrode, a metal oxide layer and an upper electrode, wherein the lower electrode is in direct contact with the node contact structure, the metal oxide layer is at least partially located on the insulating pattern and completely fills the recess.

[0012] The present invention also provides another semiconductor structure, comprising: a substrate; a plurality of node contact structures extending upward from the substrate; a plurality of first openings located between adjacent node contact structures; an insulating pattern located in the first opening, the insulating pattern at least covering the side walls of the first opening and extending upward, the upper surface of the insulating pattern also being recessed into the first opening to form a recessed portion; and a capacitor structure comprising a lower electrode, a metal oxide layer and an upper electrode, wherein the bottom of the metal oxide layer is lower than the top of the node contact structure.

[0013] Optionally, the metal oxide layer is at least partially located on the insulating pattern and fills the recess.

[0014] In the semiconductor structure provided by the present invention, the insulating pattern at least covers the side wall of the first opening of the spacer node contact structure, and the upper surface of the insulating pattern is also recessed into the first opening to form a recessed portion, so that the insulating pattern composed of the existing two film layers can be replaced by a single film layer, thereby omitting the steps of grinding and removing a portion of the thickness of the insulating material layer and re-forming the mask material layer in the prior art, simplifying the preparation process of the memory and improving the preparation efficiency. Moreover, since multiple grinding processes are usually used to flatten the surface of the substrate when forming the capacitor structure, even if the surface of the insulating pattern is uneven, it will not affect the performance of the memory; further, by forming an air gap in the first opening, the parasitic capacitance between the node contact structures is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1a to Figure 1e A schematic diagram of a structure formed by a method for forming an existing memory;

[0016] Figure 2 A flowchart of a method for forming a memory provided in Embodiment 1 of the present invention;

[0017] Figure 3a to Figure 4g A schematic diagram of a structure formed by a method for forming a memory provided in Embodiment 1 of the present invention;

[0018] Figure 5aA schematic diagram of a portion of the structure of a memory provided in Embodiment 2 of the present invention;

[0019] Figure 5b A partial structural diagram of another memory provided in Embodiment 2 of the present invention;

[0020] Figure 6a A schematic diagram of a portion of the structure of a memory provided in Embodiment 3 of the present invention;

[0021] Figure 6b A partial structural diagram of another memory provided in Embodiment 3 of the present invention;

[0022] Wherein, the accompanying drawings are marked as follows:

[0023] 100'-substrate; 200'-bit line structure; 300'-conductive material layer; 300b'-node contact structure; 300a'-first opening; 410'-insulating material layer; 420'-mask material layer; 500'-stacked material layer; 501a'-second opening; 400'-insulating pattern;

[0024] 100-substrate; STI-trench isolation structure; 200-bit line structure; 200a-node contact window; 300-conductive material layer; 300a-first opening; 300b-node contact structure; 400-insulating material layer; 400a-insulating pattern; 500-stacked material layer; 500a-first oxide layer; 500b-first supporting layer; 500c-second oxide layer; 500d-second supporting layer; 500e-second opening; 500f-third opening; 510a-first supporting structure; 510b-second supporting structure; 600a-cylindrical lower electrode; 600b-metal oxide layer; 600c-upper electrode; 600-capacitor structure;

[0025] G1, G2-air gap;

[0026] X1-the maximum width dimension of the upper node contact portion;

[0027] X2-the maximum width dimension of the lower node contact;

[0028] X3-The width dimension of the second opening in the direction perpendicular to the height. DETAILED DESCRIPTION

[0029] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0030] Figure 4b or Figure 4g FIG. 1 is a schematic diagram of a partial structure of the memory in this embodiment. Figure 4b or Figure 4g As shown, the memory is, for example, a memory device such as a dynamic random access memory (DRAM) element, but is not limited thereto. In detail, the memory first includes a substrate 100, and the substrate 100 is, for example, a silicon substrate, a silicon containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, etc. A memory cell region and a peripheral region are also defined in the substrate 100, and the memory cell region is only schematically shown in the drawings of this embodiment.

[0031] At least one shallow trench isolation STI is formed on the substrate 100 to define an active area (not shown) in the substrate 100. The manufacturing process of the shallow trench isolation STI is, for example, to first form at least one trench in the substrate 100 by etching, and then fill the trench with an insulating material (such as silicon oxide or silicon oxynitride, etc.), but is not limited thereto. In addition, a plurality of buried gates (not shown) may be formed in the active area of ​​the substrate 100, and the buried gates extend in parallel along the same direction and cross the active area, and serve as buried word lines (not shown) of the memory.

[0032] Furthermore, the active region is used to form a storage transistor, for example, and a source / drain region may be formed in the active region, the source / drain region includes a first source / drain region and a second source / drain region, the first source / drain region and the second source / drain region are respectively located on both sides of the buried gate to form the storage transistor together. It can be understood that the bottom of the first source / drain region and the second source / drain region is lower than the top of the buried gate, so that the first source / drain region and the second source / drain region have an overlapping area with the buried gate.

[0033] Furthermore, a plurality of bit line structures 200 may be formed on the substrate 100, which extend in parallel with each other along another direction perpendicular to the buried gate so as to simultaneously cross the active area and the buried gate in the substrate 100. The bit line structure 200 includes a first bit line conductive layer, a second bit line conductive layer and a third bit line conductive layer stacked sequentially from bottom to top. The material of the first bit line conductive layer includes, for example, doped polysilicon, the material of the second bit line conductive layer includes, for example, titanium nitride, and the material of the third bit line conductive layer includes, for example, tungsten. Furthermore, the bit line structure 200 may also include a bit line shielding layer and an isolation sidewall. The bit line shielding layer is formed above the sequentially stacked bit line conductive layers, and the isolation sidewall at least covers the sidewalls of the sequentially stacked bit line conductive layers and the sidewalls of the bit line shielding layer.

[0034] The bit line structure 200 may define a node contact window 200a, and the node contact window 200a is used to accommodate the node contact structure 300b. The bottom of at least part of the node contact window 200a may further extend into the substrate 100. The defined multiple node contact windows 200a are aligned in the direction in which the bit line structure 200 and the buried gate extend. The multiple node contact windows 200a are, for example, arranged in an array to form an array of node contact windows 200a. At this point, it can be considered that the multiple node contact windows 200a are arranged in multiple rows in the direction in which the bit line structure 200 and the buried gate extend.

[0035] Continue to refer Figure 4b or Figure 4g As shown, the node contact structures 300 b fill the node contact windows 200 a and are arranged in multiple rows accordingly, and the node contact structures 300 b are electrically connected to the corresponding active regions.

[0036] In this embodiment, the node contact structure 300b fills the node contact window 200a, and the top position of each node contact structure 300b is further higher than the top position of the node contact window 200a. Further, in this embodiment, the node contact structure 300b is located on the substrate 100. As an optional embodiment, the node contact structure 300b can also extend into the active area of ​​the substrate 100 and be electrically connected to the active area.

[0037] As an optional embodiment, the node contact structure 300b includes a conductive contact layer, which fills the node contact window 200a to be electrically connected to the active area. Further, the node contact structure 300b also includes an electrically conductive layer, which fills the node contact window 200a and is formed on the conductive contact layer to be electrically connected to the conductive contact layer.

[0038] Continue to refer Figure 4b or Figure 4g As shown, the node contact structures 300b are separated by first openings 300a. In this embodiment, the first openings 300a extend from a position flush with the top of the node contact structures 300b to the bit line structure 200 (and a portion of the bit line shielding layer on the top of the bit line structure 200 is removed), so that the adjacent node contact structures 300b can be electrically insulated.

[0039] Continue to refer Figure 4b or Figure 4g As shown, in this embodiment, the first opening 300a is located on the bit line structure 200, but in the direction perpendicular to the height, the position of the bit line structure 200 is not directly opposite to the position of the first opening 300a, but is offset to the right by a certain distance relative to the bit line structure 200, thereby saving area and reducing the size of the device. Of course, in other embodiments, in the direction perpendicular to the height, the position of the bit line structure 200 may also be directly opposite to the position of the first opening 300a, and the present invention is not limited thereto.

[0040] In this embodiment, the node contact structure 300b includes an upper node contact portion and a lower node contact portion, wherein the upper node contact portion is located above the height position of the bottom of the first opening 300a, and the lower node contact portion is located below the height position of the bottom of the first opening 300a. It can also be understood that the node contact structure 300b is divided into an upper node contact portion and a lower node contact portion with the height position of the bottom of the first opening 300a as the boundary, and in the direction perpendicular to the height, the maximum width dimension X1 of the upper node contact portion is greater than the maximum width dimension X2 of the lower node contact portion, and the width dimension of the upper node contact portion is larger, so the manufacturing difficulty of the node contact structure 300b can be reduced.

[0041] Further, an insulating pattern 400a is formed in each of the first openings 300a, and the insulating pattern 400a at least covers the sidewalls of the first openings 300a and extends upward to be higher than the node contact structure 300b. Specifically, the top of the insulating pattern 400a is located at a first height position, and the top of the node contact structure 300b is located at a second height position, and the first height position is higher than the second height position.

[0042] Continue to refer Figure 4b or Figure 4gAs shown, in this embodiment, the insulating pattern 400a is a single layer of nitride, such as silicon nitride, etc. As an optional embodiment, the insulating pattern 400a can also be a single layer of carbon-doped nitride (such as carbon-doped silicon nitride), carbide (such as silicon carbide) or oxide (such as tantalum oxide, titanium oxide), etc., which is not limited by the present invention. Of course, the insulating pattern 400a can also be a combination of at least two film layers, such as a composite film layer of oxide and nitride, which is not limited by the present invention.

[0043] Furthermore, the insulating pattern 400a in the present invention has a portion filling the first opening 300a and a portion extending upward to be higher than the node contact structure 300b. Therefore, compared with the insulating pattern 400a formed by two film layers in the prior art, the present invention is equivalent to using one film layer to replace two film layers with the same function. The structure is simpler, the preparation process is simplified, and it will not have any impact on the performance of the memory.

[0044] Continue to refer Figure 4b or Figure 4g As shown, the upper surface of the insulating pattern 400a is also recessed into the first opening 300a to form a recessed portion. In this embodiment, the insulating pattern 400a only covers the inner wall of the first opening 300a, and the insulating pattern 400a between the side walls of the first opening 300a has a gap, which can be regarded as a recessed portion formed by the upper surface of the insulating pattern 400a recessed into the first opening 300a. At this time, the recessed portion is linear as a whole. As an optional embodiment, the insulating pattern 400a can also fill the first opening 300a, and the upper surface of the insulating pattern 400a is still recessed into the first opening 300a, but the bottom of the recessed portion is higher than the top of the first opening 300a, so that the recessed portion is only located in the portion of the insulating pattern 400a that is higher than the top of the first opening 300a. At this time, the recessed portion is in the shape of a trumpet with a large top and a small bottom. It can be understood that the recessed portion is not limited to being linear or trumpet-shaped, but can also be other shapes such as rectangles, trapezoids, etc., and the present invention is not limited thereto.

[0045] Continue to refer Figure 4b or Figure 4gAs shown, the width dimension of the insulating pattern 400a in the direction perpendicular to the height is also greater than the width dimension of the first opening 300a, so that the top of the insulating pattern 400a also extends laterally to cover the partial top of the node contact structure 300b on both sides of the first opening 300a. Of course, as an optional embodiment, the width dimension of the insulating pattern 400a in the direction perpendicular to the height can also be less than or equal to the width dimension of the first opening 300a, so that the insulating pattern 400a only covers the partial top of the node contact structure 300b on either side of the first opening 300a, or the insulating pattern 400a is only located in the first opening 300a.

[0046] refer to Figure 4b As shown, a stacked structure is formed on the insulating pattern 400a, and the stacked structure is separated by a second opening 500e, one of the second openings 500e is located above one of the node contact structures 300b, and the second opening 500e exposes at least a portion of the top of the node contact structure 300b. The sidewalls of the second opening 500e are formed by the sidewalls of the insulating pattern 400a and the sidewalls of the stacked structure, and the sidewalls of the insulating pattern 400a are flush with the sidewalls of the stacked structure, so that the second opening 500e is a straight groove structure. Of course, as an optional embodiment, the sidewalls of the insulating pattern 400a and the sidewalls of the stacked structure may not be flush, so that the second opening 500e is a stepped groove structure.

[0047] Continue to refer Figure 4b As shown, the air gap G1 may be located between the insulating pattern 400a and the stacked structure. Specifically, the stacked structure is sequentially composed of a first oxide layer 500a, a first supporting layer 500b, a second oxide layer 500c and a second supporting layer 500d from bottom to top, wherein the first oxide layer 500a covers the opening of the recessed portion, and the first supporting layer 500b, the second oxide layer 500c and the second supporting layer 500d are sequentially stacked on top of the first oxide layer 500a. It should be understood that since the stacked structure is separated by the second opening 500e, at this time, the first oxide layer 500a, the first supporting layer 500b, the second oxide layer 500c and the second supporting layer 500d are also patterned film layers.

[0048] refer to Figure 4g As shown, a tubular lower electrode 600a may be further formed on the node contact structure 300b, and a metal oxide layer 600b covers the plurality of insulating patterns 400a and conformally covers the surface of the tubular lower electrode 600a.

[0049] Specifically, the bottom of the tubular lower electrode 600a contacts and is electrically connected to the node contact structure 300b, and the tubular lower electrode 600a extends upward through the second opening 500e. Each or at least one of the tubular lower electrodes 600a has a cylindrical shape with a closed bottom.

[0050] The side wall of the cylindrical lower electrode 600a has a first supporting structure 510a and a second supporting structure 510b separated from each other in the height direction. The first supporting structure 510a is used to support the side wall of the lower end of the cylindrical lower electrode 600a, and the second supporting structure 510b is used to support the side wall of the upper end of the cylindrical lower electrode 600a, so as to prevent the cylindrical lower electrode 600a from tilting. The upper end can be the end of the cylindrical lower electrode 600a away from the surface of the substrate 100.

[0051] Continue to refer Figure 4g As shown, one side wall of a part of the tubular lower electrode 600a does not have the first support structure 510a and the second support structure 510b, so that a third opening 500f is formed between adjacent tubular lower electrodes 600a, and the third opening 500f exposes the insulating pattern 400a. The metal oxide layer 600b can conformally cover the first support structure 510a, the second support structure 510b and the tubular lower electrode 600a. In other words, the metal oxide layer 600b covers the exposed surfaces of the tubular lower electrode 600a, the first support structure 510a and the second support structure 510b, and at the same time, the metal oxide layer 600b also needs to cover the insulating pattern 400a.

[0052] Further, if Figure 4g As shown, the metal oxide layer 600b covers part of the insulating pattern 400a and covers the recessed portion to form an air gap G1. Of course, the metal oxide layer 600b can also extend into the recessed portion so that the upper portion of the recessed portion is filled. In this case, the recessed portion is not filled and the air gap G1 is preserved.

[0053] Continue to refer Figure 4g As shown, an upper electrode 600c is also formed on the metal oxide layer 600b, and the upper electrode 600c partially faces the tubular lower electrode 600a, and the metal oxide layer 600b is sandwiched between the two. The upper electrode 600c also extends to cover the top of the second support structure 510b and fill the second opening 500e and the third opening 500f. The tubular lower electrode 600a, the metal oxide layer 600b and the upper electrode 600c together constitute a capacitor structure 600.

[0054] In this embodiment, there are two node contact structures 300 b on both sides of the air gap G1 , so the air gap G1 with a low dielectric constant can reduce the parasitic capacitance between adjacent node contact structures 300 b and improve the performance of the memory.

[0055] In this embodiment, the width dimension X3 of the second opening 500e in the direction perpendicular to the height is smaller than the maximum width dimension X1 of the upper node contact portion, and in this case, the second opening 500e only exposes a portion of the top of the node contact structure 300b. However, it should be understood that the width dimension X3 of the second opening 500e in the direction perpendicular to the height can actually be smaller than or equal to the maximum width dimension X1 of the upper node contact portion, and in this case, the second opening 500e completely exposes the top of the node contact structure 300b, and the insulating pattern 400a is also only located in the first opening 300a or only covers a portion of the top of the node contact structure 300b on one side of the first opening 300a.

[0056] The following is combined with Figure 2 and Figure 3a to Figure 4g The method for forming the memory as described above in this embodiment is described in detail. Figure 2 is a flow chart of a method for forming a memory in an embodiment of the present invention, Figure 3a to Figure 4g FIG. 4 is a schematic diagram of a semiconductor structure formed during the preparation process of the memory in an embodiment of the present invention.

[0057] like Figure 2 As shown, the method for forming the memory includes:

[0058] Step S100: providing a substrate 100;

[0059] Step S200: forming a plurality of node contact structures 300 b on the substrate 100 , wherein the node contact structures 300 b extend upward from the substrate 100 ;

[0060] Step S300: forming a plurality of first openings 300a between adjacent node contact structures 300b, wherein the first openings 300a electrically isolate adjacent node contact structures 300b;

[0061] Step S400: forming an insulating pattern 400a in the first opening 300a, wherein the insulating pattern 400a at least covers the sidewall of the first opening 300a and extends upward to be higher than the node contact structure 300b, and the upper surface of the insulating pattern 400a is also recessed into the first opening 300a to form a recessed portion; and

[0062] Step S500: forming a capacitor structure on the node contact structure, and electrically connecting the capacitor structure to the node contact structure.

[0063] Specifically, first refer to Figure 3a As shown, step S100 is performed to provide a substrate 100, in which a trench isolation structure STI is formed, and a plurality of active areas are defined by the trench isolation structure SIT. A plurality of buried gates are also formed in the active area as word line symbols, but this is not limited to this. In some embodiments, other types of word line structures can also be formed as needed. In addition, the material of the electrode of the buried gate may include aluminum (Al), tungsten (W), copper (Cu), titanium aluminum alloy (TiAl) or other suitable conductive materials, and the medium covering the electrode of the buried gate may include silicon nitride, silicon oxynitride, silicon carbide nitride or other suitable insulating materials.

[0064] Furthermore, a source / drain region is formed in the active region of the substrate 100, and the side edge boundary of the source / drain region extends to the side wall of the buried gate close to the top opening, and the bottom boundary of the source / drain region is lower than the top position of the buried gate, so that there is an overlapping area between the source / drain region and the buried gate. Specifically, the source / drain region includes a first source / drain region and a second source / drain region, and the first source / drain region and the second source / drain region are respectively located on both sides of the buried gate. In this embodiment, the side edge boundary of the first source / drain region also extends to the side wall of the trench isolation structure STI.

[0065] It should be noted that the source and drain regions may be prepared after the buried gate is formed, or the source and drain regions may be formed first and then the buried gate is prepared, which is not limited here.

[0066] A bit line structure 200 is also formed on the substrate 100, and the bit line structure 200 includes three layers of conductive material layers stacked in sequence. Based on this, the formed bit line structure 200 can include a first bit line conductive layer, a second bit line conductive layer and a third bit line conductive layer. Further, the bit line structure 200 also includes a bit line shielding layer, and the bit line shielding layer can be a patterned film layer and is formed above the three layers of conductive material layers. In an optional scheme, for example, the patterned bit line shielding layer is used to sequentially pattern the conductive material layers below it. In this embodiment, the method for forming the bit line structure 200 also includes: forming isolation sidewalls on the side walls of the first bit line conductive layer, the second bit line conductive layer, the third bit line conductive layer and the bit line shielding layer.

[0067] like Figure 3a As shown, a portion of the bit line structure 200 is located on the substrate 100 , and a portion extends from the substrate 100 to the active region of the substrate 100 . The bit line structure 200 defines a plurality of node contact windows 200 a located on the substrate 100 .

[0068] See also Figure 3b , perform step S200 and step S300 to form a conductive material layer 300 on the substrate 100, the conductive material layer 300 covers and fills the node contact window 200a and extends to cover the top of the bit line structure 200. The conductive material layer 300 is used to form a node contact structure, and its material may include silicon-containing conductive materials such as amorphous silicon, polycrystalline silicon and other conductive materials such as metal conductive materials. For example, the lower part of the conductive material layer 300 may be a silicon-containing conductive material, and the upper part of the conductive material layer 300 may be a metal conductive material with a lower resistivity such as tungsten, etc., but it is not limited to this. In addition, a metal silicide layer may be formed between the lower and upper parts of the conductive material layer 300 as needed to reduce the contact impedance between the silicon-containing conductive material and the metal conductive material, but it is not limited to this.

[0069] Please refer to Figure 3b and Figure 3c , etching the conductive material layer 300 and at least a portion of the height of the bit line structure 200 to form a plurality of first openings 300a, wherein the first openings 300a correspond to the bit line structures 200. As shown in FIG3 , the first openings 300a separate the remaining conductive material layer 300, and the remaining conductive material layer 300 can form a plurality of node contact structures 300b, and each of the node contact structures 300b is electrically isolated from each other.

[0070] In this embodiment, the node contact window 200a is located on the substrate 100, so that the formed node contact structure 300b is also located on the substrate 100. As an optional embodiment, before forming the conductive material layer 300, the bottom of the node contact window 200a may be etched so that the node contact window 200a extends to the active area of ​​the substrate 100, so that the node contact structure 300b can extend from the substrate 100 to the active area and be electrically connected to the active area.

[0071] Please continue reading Figure 3c In this embodiment, in the direction perpendicular to the height (i.e., the thickness direction of the substrate 100), the position of the bit line structure 200 and the first opening 300a is offset (offset to the right), so that the process window of the first opening 300a is widened and it is beneficial to save area. Of course, as an optional embodiment, the position of the bit line structure 200 and the first opening 300a can also be directly opposite, and the present invention is not limited thereto.

[0072] Please continue reading Figure 3cThe node contact structure 300b is divided into an upper node contact part and a lower node contact part with the height position of the bottom of the first opening 300a as the boundary. In the direction perpendicular to the height, the maximum width dimension X1 of the upper node contact part is greater than the maximum width dimension X2 of the lower node contact part. By increasing the width dimension of the node contact structure 300b close to the top of the first opening 300a, the manufacturing difficulty of the node contact structure 300b can be reduced.

[0073] See also Figure 3d , an insulating material layer 400 is formed on the node contact structure 300b, the insulating material layer 400 covers the node contact structure 300b and extends into the first opening 300a to cover the side walls of the first opening 300a, and the insulating material layer 400 has a gap between the side walls of the first opening 300a. The gap can also be regarded as a recessed portion formed by the portion of the upper surface of the insulating material layer 400 corresponding to the first opening 300a being recessed into the first opening 300a.

[0074] from Figure 3d As can be seen in FIG. 1 , the recessed portion extends from the highest position of the insulating material layer 400 in the height direction to the first opening 300a, so that the recessed portion is linear. However, it should be understood that Figure 3d When the thickness of the insulating material layer 400 is increased on the basis of the first opening 300a, the insulating material layer 400 can fill the first opening 300a, and the surface of the insulating material layer 400 is only recessed to the area above the first opening 300a, so that the bottom height of the recessed portion is higher than or equal to the top height of the first opening 300a. At this time, the recessed portion is in the shape of a trumpet with a large mouth and a small bottom.

[0075] In this embodiment, the insulating material layer 400 is a single layer of silicon nitride. As an optional embodiment, the insulating material layer 400 may also be made of carbon-doped nitride (such as carbon-doped silicon nitride) or carbide (such as silicon carbide), but is not limited to this.

[0076] It should be understood that after forming the insulating material layer 400 , the present embodiment does not perform a grinding process. At this time, the surface of the substrate 100 may be uneven, but has a bumpy profile.

[0077] See also Figure 4a, perform step S500, and form a first oxide layer 500a, a first supporting layer 500b, a second oxide layer 500c and a second supporting layer 500d in sequence from bottom to top on the insulating material layer 400, wherein the first oxide layer 500a, the first supporting layer 500b, the second oxide layer 500c and the second supporting layer 500d are stacked to form a stacked material layer 500. The thickness of the second supporting layer 500d is preferably greater than the thickness of the first supporting layer 500b, thereby preventing the overly thick first supporting layer 500b from affecting the size of the area where the capacitor structure can be formed, and the thicker second supporting layer 500d can ensure its supporting effect. In some embodiments, only the first oxide layer 500a and the first supporting layer 500b may be formed as needed without forming the second oxide layer 500c and the second supporting layer 500d. In addition, the first oxide layer 500a and the second oxide layer 500c may respectively include a single layer or multiple layers of oxide materials such as silicon oxide, tetraethyl orthosilicate (TEOS) or boro-phospho-silicate glass (BPSG), and the first supporting layer 500b and the second supporting layer 500d may respectively include a single layer or multiple layers of materials such as nitrides (such as silicon nitride), carbon-doped nitrides (such as carbon-doped silicon nitride), carbides (such as silicon carbide) or oxides (such as tantalum oxide, titanium oxide), etc., but are not limited thereto.

[0078] See also Figure 4b , step S400 is performed, and an etching process can be performed using a patterned mask layer (not shown) to pattern the stacked material layer 500 and the insulating material layer 400. Specifically, the second support layer 500d, the second oxide layer 500c, the first support layer 500b, the first oxide layer 500a and the insulating material layer 400 are sequentially etched using the patterned mask layer as a mask to form a plurality of second openings 500e. The position of one of the second openings 500e matches the position of one of the node contact structures 300b, and the second opening 500e exposes at least a portion of the top of the node contact structure 300b.

[0079] Please continue reading Figure 4bThe second opening 500e separates the remaining stacked material layers 500 to form a plurality of stacked structures. The second opening 500e also separates the remaining insulating material layers 400 to form a plurality of insulating patterns 400a. Each of the stacked structures is located directly above the corresponding insulating pattern 400a, and the width of the stacked structure is equal to the width of the insulating pattern 400a in the direction perpendicular to the height, that is, the sidewall of the second opening 500e is formed by the sidewall of the stacked structure and the sidewall of the insulating pattern 400a.

[0080] Please continue reading Figure 4b In this embodiment, a deposition process with poor trench filling capability is used when forming the first oxide layer 500a, so that the formed first oxide layer 500a only covers the opening of the recessed portion, so as to form an air gap G1 between the first oxide layer 500a and the insulating pattern 400a. Of course, a deposition process with better trench filling capability can also be used when forming the first oxide layer 500a, but the reaction speed is increased by controlling the process parameters, so that the formed first oxide layer 500a only covers the opening of the recessed portion. Furthermore, the first oxide layer 500a can extend into the recessed portion and fill the upper part of the recessed portion, and an air gap G1 will be formed as long as the recessed portion is not fully filled.

[0081] It should be understood that after the second opening 500 e is formed, the air gap G1 is located between each of the stacked structures and the corresponding insulating pattern 400 a .

[0082] Please continue reading Figure 4b In this embodiment, in the direction perpendicular to the height, the width dimension X3 of the second opening 500e is smaller than the maximum width dimension X1 of the upper node contact portion, so that the second opening 500e can only expose a portion of the top of the node contact structure 300b, and a portion of the insulating material layer 400 covering the top of the node contact structure 300b will be retained, so that the formed insulating pattern 400a will also extend from the first opening 300a to the portion of the node contact structure 300b covering both sides of the first opening 300a.

[0083] As an optional embodiment, the width dimension X3 of the second opening 500e may also be greater than or equal to the maximum width dimension X1 of the upper node contact portion, so that the portion of the insulating material layer 400 covering the top of the node contact structure 300b is completely removed, so that the formed insulating pattern 400a only exists in the first opening 300a and extends upward to be higher than the first opening 300a (naturally also higher than the node contact structure 300b). Further, by changing the position of the second opening 500e in the vertical direction to the height, the formed insulating pattern 400a can also be extended from the first opening 300a to the portion of the node contact structure 300b covering any side of the first opening 300a, which will not be described one by one here.

[0084] Furthermore, the method for forming the memory may further include the following steps:

[0085] See also Figure 4c After forming the second opening 500e, the patterned mask layer is removed, and a tubular lower electrode 600a is formed in half of the second opening 500e, and the tubular lower electrode 600a sequentially penetrates the second support layer 500d, the second oxide layer 500c, the first support layer 500b, the first oxide layer 500a, and part of the insulating pattern 400a, but is not limited thereto. In addition, the tubular lower electrode 600a is electrically connected to the corresponding node contact structure 300b. Figure 4c As shown, the second supporting layer 500d, the second oxide layer 500c, the first supporting layer 500b and the first oxide layer 500a are all located on the side of the first electrode 61.

[0086] See also Figure 4d , the second support layer 500d is patterned using a patterned mask layer, and a plurality of third openings 500f are formed on the second support layer 500d (only one third opening 500f is schematically shown in the figure). The planar shape of the third opening 500f can be a triangle or a rhombus, etc., and this third opening 500f defines the range of the second support layer 500d and the first support layer 500b to be removed later. It is worth noting that different shapes of the third openings 500f or different arrangements of the third openings 500f will affect the strength of the first support layer 500b and the second support layer 500d in supporting the tubular lower electrode 600a and the efficiency of removing the first oxide layer 500a and the second oxide layer 500c. Therefore, by adjusting the shapes of the different third openings 500f and the arrangements of the third openings 500f, a stronger effect of supporting the tubular lower electrode 600a and the efficiency of removing the oxide layer can be achieved.

[0087] Next, please refer to Figure 4e, the second oxide layer 500c at the bottom of the third opening 500f is etched, so that the third opening 500f extends downward and exposes a portion of the first support layer 500b. The etching process used in this step is preferably an isotropic etching process such as a wet etching process, so that the second oxide layer 500c can be completely removed (the second oxide layer 500c covered by the second support layer 500d can also be removed), but it is not limited thereto.

[0088] Please continue reading Figure 4e Then, the first support layer 500b at the bottom of the third opening 500f is removed by an etching process, so that the first support layer 500b is patterned, and the third opening 500f further extends downward to expose the first oxide layer 500a. The etching process in this step is preferably an anisotropic etching process such as a dry etching process, so that only a portion of the first support layer 500b at the bottom of the third opening 500f can be removed, and the first support layer 500b covered by the second support layer 500d is retained. It should be understood that since the lateral etching of the anisotropic etching process is less obvious, a protruding structure similar to a waistband will be left on the side wall of the tubular lower electrode 600a.

[0089] Finally, the first oxide layer 500a below the third opening 500f is completely removed by etching again, so that the third opening 500f extends to the insulating pattern 400a, and the sidewall of the third opening 500f exposes the sidewall of the tubular lower electrode 600a. The etching process used in this step is preferably an isotropic etching process such as a wet etching process, so that the first oxide layer 500a can be completely removed (the second oxide layer 500c covered by the second supporting layer 500d and the first supporting layer 500b can also be removed), but the present invention is not limited thereto.

[0090] In some embodiments, the first support layer 500b, the first oxide layer 500a, the second support layer 500d and the second oxide layer 500c may be etched continuously by a single etching step, or the first support layer 500b, the first oxide layer 500a, the second support layer 500d and the second oxide layer 500c may be etched respectively by a plurality of etching steps with different manufacturing process conditions as needed. For example, when the first support layer 500b and the second support layer 500d are nitride layers, a plasma etching may be used to etch the first support layer 500b and the second support layer 500d, and the reaction gas used in the plasma etching may include oxygen, nitrogen, hydrogen, nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6) or / and methane (CH4), but is not limited thereto. By adjusting the ratio of the components in the above-mentioned reaction gas, the etching selectivity of plasma etching for different materials can be controlled. For example, in some embodiments, the etching rate of plasma etching for the first support layer 500b and the second support layer 500d can be greater than the etching rate of the first oxide layer 500a and the second oxide layer 500c, but the invention is not limited thereto. In addition, the etching step for the first oxide layer 500a and the second oxide layer 500c can also have a higher etching selectivity for the first support layer 500b and the second support layer 500d, thereby improving the control of the etching process for the formed etching pattern.

[0091] Please continue reading Figure 4e After removing the first oxide layer 500a, the second oxide layer 500c, part of the first supporting layer 500b and part of the second supporting layer 500d, the surface of the insulating pattern 400a is exposed, and the remaining first supporting layer 500b constitutes a first supporting structure 510a and the remaining second supporting layer 500d constitutes a second supporting structure 510b. The first supporting structure 510a and the second supporting structure 510b can be used to support the top area and the middle area of ​​the tubular lower electrode 600a, respectively. When the height of the tubular lower electrode 600a is large, they can support the tubular lower electrode 600a and prevent the tubular lower electrode 600a from tilting.

[0092] See also Figure 4f , a metal oxide layer 600b is deposited on the substrate 100, and the metal oxide layer 600b covers the insulating pattern 400a and conformally covers the exposed surface of the tubular lower electrode 600a. Figure 4fAs shown, the metal oxide layer 600b covers the upper surface of the tubular lower electrode 600a in the second opening 500e, the upper surface of the insulating pattern 400a in the third opening 500f and extends to cover the upper surface of the second supporting structure 510b. At the same time, the metal oxide layer 600b also covers the lower surface of the second supporting structure 510b, the upper and lower surfaces of the first supporting structure 510a, and the surface of the insulating pattern 400a covered by the first supporting structure 510a and the second supporting structure 510b. Alternatively, it can be understood that the metal oxide layer 600b includes a first part similar to a square wave and a second part similar to a rectangle, the first part covers the inner surface of the tubular lower electrode 600a, the upper surface of the second supporting structure 510b and part of the upper surface of the insulating pattern 400a, and part of the second part covers the upper part of the outer surface of the tubular lower electrode 600a, the lower surface of the second supporting structure 510b and the upper surface of the first supporting structure 510a, and the remaining second part covers the lower part of the outer surface of the tubular lower electrode 600a, the lower surface of the first supporting structure 510a and part of the surface of the insulating pattern 400a.

[0093] Please continue reading Figure 4f In this embodiment, since the surface of the insulating pattern 400a has a recessed portion, a deposition process with poor groove filling capability is used when forming the metal oxide layer 600b, so that the formed metal oxide layer 600b only covers the opening of the recessed portion, so as to form an air gap G1 between the metal oxide layer 600b and the insulating pattern 400a. Of course, a deposition process with better groove filling capability can also be used when forming the metal oxide layer 600b, but the reaction speed is increased by controlling the process parameters, so that the formed metal oxide layer 600b only covers the opening of the recessed portion, thereby forming the air gap G1. Furthermore, the metal oxide layer 600b can also extend into the recessed portion to fill the upper part of the recessed portion, and an air gap will be formed as long as the recessed portion is not fully filled.

[0094] See also Figure 4g, an upper electrode 600c is formed on the metal oxide layer 600b, and the upper electrode 600c covers a portion of the upper surface of the metal oxide layer 600b and fills the second opening 500e and the third opening 500f, but the present invention is not limited thereto. At least a portion of the metal oxide layer 600b is located between the tubular lower electrode 600a and the upper electrode 600c to form a capacitor structure 600, and a portion of the capacitor structure 600 may be located on the node contact structure 300b, but the present invention is not limited thereto. In some embodiments, the tubular lower electrode 600a and the upper electrode 600c may be respectively regarded as the lower electrode and the upper electrode 600c in the above-mentioned capacitor structure 600, but the present invention is not limited thereto.

[0095] It can be understood that the material of the tubular lower electrode 600a may include impurity-doped silicon, metals such as tungsten or copper, and / or conductive metal compounds such as titanium nitride, and the material of the upper electrode 600c may include doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba, Sr)RuO), CRO (CaRuO), BaRuO, La (Sr, Co) O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN or a combination thereof, but is not limited thereto. The metal oxide layer 600b can be any suitable high dielectric constant dielectric layer, such as TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O or a combination thereof.

[0096] It is conceivable that a grinding process is inevitably used when forming the stacked material layer 500, the cylindrical lower electrode 600a and / or the upper electrode 600c. Figure 3d After the insulating material layer 400 is formed as shown, the surface of the substrate 100 has an uneven profile, and the surface of the substrate 100 can be completely flattened through the grinding process used in the subsequent process. Therefore, this embodiment omits the steps of grinding away a portion of the thickness of the insulating material layer 400 and reforming the mask material layer, which will not affect the performance of the memory at all, and also simplifies the preparation process of the memory and improves the preparation efficiency.

[0097] Embodiment 2

[0098] like Figure 5aAs shown in FIG. 5b, different from the first embodiment, in this embodiment, the metal oxide layer 600b fills a part of the depth of the recessed portion, thereby forming an air gap G2 between the metal oxide layer 600b and the insulating pattern 400a. That is, the bottom of the metal oxide layer 600b extends from the top of the insulating pattern 400a to the first opening, so that the bottom of the metal oxide layer 600b is lower than the top of the insulating pattern 400a.

[0099] For details, please refer to Figure 5a When the first oxide layer 500a is formed, the first oxide layer 500a not only covers the insulating pattern 400a, but also completely fills the recessed portion with a partial depth. Figure 5b When the metal oxide layer 600b is formed to cover the portion of the insulating pattern 400a, the metal oxide layer 600b not only covers the insulating pattern 400a, but also fills a portion of the depth of the recessed portion. In this way, the upper portion of the recessed portion is filled with a dielectric, and the remaining portion of the recessed portion constitutes an air gap G2.

[0100] The method for forming the memory in this embodiment can be the same as the method for forming the memory in embodiment one, with the only difference being that when forming the first oxide layer 500a and the metal oxide layer 600b, the first oxide layer 500a and the metal oxide layer 600b fill a partial depth of the recess.

[0101] In this embodiment, the process parameters for preparing the first oxide layer 500a and the metal oxide layer 600b are controlled so that the first oxide layer 500a and the metal oxide layer 600b fill the recessed portion. For example, a deposition process with better groove filling capability is used to form the first oxide layer 500a and the metal oxide layer 600b, or the speed of the deposition process for preparing the first oxide layer 500a and the metal oxide layer 600b is reduced. After the first oxide layer 500a and the metal oxide layer 600b fill the recessed portion to a certain depth, the reaction is stopped immediately, so that the recessed portion is not completely filled, and the remaining recessed portion constitutes the air gap G2.

[0102] It should be understood that this embodiment is not limited to the first oxide layer 500a and the metal oxide layer 600b both filling the recess. The first oxide layer 500a may also fill the recess or just cover the recess, and the metal oxide layer 600b fills a partial depth of the recess.

[0103] Embodiment 3

[0104] like Figure 6aAs shown in FIG6b, different from the first and second embodiments, in this embodiment, the metal oxide layer 600b completely fills the recessed portion, so that no air gap is formed between the metal oxide layer 600b and the insulating pattern 400a.

[0105] For details, please refer to Figure 6a When the first oxide layer 500a is formed, the first oxide layer 500a not only covers the insulating pattern 400a, but also completely fills the recessed portion. Figure 6b When the metal oxide layer 600b is formed to cover the portion of the insulating pattern 400a, the metal oxide layer 600b not only covers the insulating pattern 400a, but also completely fills the recessed portion. In this way, the recessed portion is completely filled with dielectric, so that no air gap exists.

[0106] The method for forming the memory in this embodiment may be the same as the method for forming the memory in the first embodiment, with the only difference being that when forming the first oxide layer 500a and the metal oxide layer 600b, the first oxide layer 500a and the metal oxide layer 600b are made to fill the recess.

[0107] In this embodiment, the process parameters for preparing the first oxide layer 500a and the metal oxide layer 600b are controlled so that the first oxide layer 500a and the metal oxide layer 600b fill the recessed portion. For example, a deposition process with better trench filling capability is used to form the first oxide layer 500a and the metal oxide layer 600b, or the speed of the deposition process for preparing the first oxide layer 500a and the metal oxide layer 600b is reduced, so that the first oxide layer 500a and the metal oxide layer 600b can better fill the recessed portion.

[0108] It should be understood that this embodiment is not limited to the first oxide layer 500a and the metal oxide layer 600b both filling the recess. The first oxide layer 500a may also fill a partial depth of the recess or only cover the recess, and the metal oxide layer 600b fills the recess.

[0109] In summary, in the memory and the formation method thereof provided by the present invention, the insulating pattern at least covers the side wall of the first opening of the spacing node contact structure and extends upward to be higher than the node contact structure, and the upper surface of the insulating pattern is also recessed into the first opening to form a recessed portion, so that a single film layer can replace the existing insulating pattern composed of two film layers, thereby omitting the steps of grinding away a portion of the thickness of the insulating material layer and re-forming the mask material layer, simplifying the preparation process of the memory and improving the preparation efficiency. In addition, since multiple grinding processes are usually used to flatten the surface of the substrate when forming the capacitor structure, the performance of the memory will not be affected.

[0110] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0111] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0112] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0113] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

[0114] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: substrate; a plurality of node contact structures extending upward from the substrate; A plurality of first openings located between adjacent node contact structures; an insulating pattern located in the first opening, the insulating pattern at least covering the sidewall of the first opening and extending upward, and the upper surface of the insulating pattern is also recessed into the first opening to form a recessed portion; and The capacitor structure comprises a lower electrode, a metal oxide layer and an upper electrode, wherein the lower electrode is in direct contact with the node contact structure, and the metal oxide layer is at least partially located on the insulating pattern and covers the recessed portion to form an air gap.

2. The semiconductor structure according to claim 1, wherein: The metal oxide layer fills a portion of the depth of the recess to form an air gap.

3. The semiconductor structure according to claim 1, wherein: The insulating pattern extends upward and covers the top of the node contact structure.

4. The semiconductor structure according to claim 1, wherein: A sidewall of the insulating pattern contacts sidewalls of the node contact structure and the lower electrode at the same time.

5. The semiconductor structure according to claim 1, wherein: The topmost portion of the insulating pattern is higher than the topmost portion of the node contact structure.

6. The semiconductor structure according to claim 1, wherein: The node contact structure is divided into an upper node contact portion and a lower node contact portion with the height position of the bottom of the first opening as a boundary, and the maximum width dimension of the upper node contact portion is greater than the maximum width dimension of the lower node contact portion.

7. A semiconductor structure, characterized in that: include: substrate; a plurality of node contact structures extending upward from the substrate; A plurality of first openings located between adjacent node contact structures; an insulating pattern located in the first opening, the insulating pattern at least covering the sidewall of the first opening and extending upward, and the upper surface of the insulating pattern is also recessed into the first opening to form a recessed portion; and The capacitor structure comprises a lower electrode, a metal oxide layer and an upper electrode, wherein the lower electrode is in direct contact with the node contact structure, and the metal oxide layer is at least partially located on the insulating pattern and completely fills the recessed portion.

8. A semiconductor structure, characterized in that: include: substrate; a plurality of node contact structures extending upward from the substrate; A plurality of first openings located between adjacent node contact structures; an insulating pattern located in the first opening, the insulating pattern at least covering the sidewall of the first opening and extending upward, and the upper surface of the insulating pattern is also recessed into the first opening to form a recessed portion; and The capacitor structure comprises a lower electrode, a metal oxide layer and an upper electrode, wherein the bottom of the metal oxide layer is lower than the top of the node contact structure.

9. The semiconductor structure according to claim 8, characterized in that The metal oxide layer is at least partially located on the insulating pattern and fills the recess.

Images