A dynamic comparator with differential charge compensation function

Abstract

The application discloses a dynamic comparator with differential charge compensation function. The dynamic comparator mainly comprises an input stage with compensation function and a digital output stage. The application proposes a differential charge compensation mechanism for the influence of input pair tube grid capacitance, which is used for eliminating the influence of input pair tube grid capacitance on signal sampling process. The dynamic comparator changes the input end load capacitance corresponding to the signal sampling process and the differential charge compensation process by the compensation input transistors M1 and M2 and the two-phase non-overlapping clock and introduced signal sampling process and differential charge compensation process, so that the differential equivalent charge on the input grid capacitance in the comparator reset stage after signal sampling is completely offset, the purpose of differential charge compensation is achieved, and the error caused by the existence of the comparator grid capacitance is eliminated. The dynamic comparator is suitable for successive approximation type digital-to-analog converter design of top plate sampling mechanism.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and specifically relates to a dynamic comparator with differential charge compensation function. Background Technology

[0002] Dynamic comparators are a common circuit module in mixed-signal systems, widely used in systems such as digital-to-analog conversion. The performance and non-ideal characteristics of dynamic comparators are factors that need to be considered when improving system performance. Improving the performance and non-ideal characteristics of dynamic comparators can significantly improve the overall system performance.

[0003] In successive approximation analog-to-digital converters (ADCs), the theoretical difference between the input analog signal and the analog signal corresponding to the output digital code value is within the ADC's accuracy range. However, when various non-ideals exist in the design, the analog signal corresponding to the output digital code value may differ from the input analog signal beyond the accuracy range. Dynamic comparator design is a critical task in successive approximation ADC design. Due to the non-ideals of the dynamic comparator, the gate of the input transistor pair at the input terminal has a parasitic capacitance to ground. This parasitic capacitance causes a certain degree of attenuation in the reference voltage generated for the next comparison at each bit. When the successive approximation ADC operates using a top-plate sampling mechanism, this parasitic capacitance to ground stores signal-related charge during the sample-and-hold process, meaning the signal does not attenuate. Therefore, the presence of this parasitic capacitance to ground affects the output of the successive approximation ADC using a top-plate sampling mechanism, causing a certain error in the analog signal corresponding to the output digital code value.

[0004] This invention proposes a dynamic comparator with differential charge compensation function for the design of successive approximation analog-to-digital converter systems with top plate sampling mechanism. It can achieve complete differential charge compensation and eliminate errors caused by parasitic input pair transistors of the comparator. Summary of the Invention

[0005] The purpose of this invention is to provide a highly practical dynamic comparator with differential charge compensation function.

[0006] The present invention provides a dynamic comparator with differential charge compensation function, which is used to achieve complete compensation of differential charge. Figure 1 The circuit schematic of a dynamic comparator with differential charge compensation is given, consisting of an input stage with compensation function and a digital output stage; wherein:

[0007] In the input stage with compensation function, the compensation input transistor pairs M1 and M2 and the input transistor pairs M3 and M4 are all the same size, and their sources are all connected to the drain of transistor M5. The source of transistor M5 is connected to the drain of transistor M6. The current source IREF is connected to transistor M7 through its drain and gate. The gate of transistor M6 is connected to the gate of M7. The sources of transistors M6 and M7 are both the power supply voltage. VDD The gates of transistors M1 and M2 are both fed by two non-overlapping clocks. and The control switch is connected to the gates of transistors M3 and M4, and the drains of transistors M1 and M2 are both connected to two non-overlapping clocks. and The control switch is connected to the drains of transistors M3 and M4; the gates of transistors M3 and M4 are respectively connected through... The control value is connected to the differential input signal. VIP and VIN The drains of transistors M3, M8, and M10 are connected to the gate of transistor M9; the drains of transistors M4, M9, and M11 are connected to the gate of transistor M8; the gates of transistors M5, M10, and M11 are all connected to the operating clock of the dynamic comparator. CLK The sources of transistors M8, M9, M10, and M11 are all grounded.

[0008] In the digital output stage, the sources of transistors M12 and M13 are connected to... VDD The sources of transistors M14 and M15 are grounded; the gates of both M12 and M14 are connected to the drain of M3, and their drains are both connected to the input of inverter I1; the gates of both transistors M13 and M15 are connected to the drain of transistor M4, and their drains are both connected to the input of inverter I2; the outputs of inverters I1 and I2 are connected to the inputs of inverters I3 and I4, respectively; the outputs of inverters I3 and I4 are the output signals of the comparator. VON , VOP The two inputs of the two-input NAND gate I5 are connected in sequence; the output of I5 is the valid output signal of the comparator. VALID .

[0009] In the input stage with compensation function, the two-phase non-overlapping clocks and The high-level signal controls the corresponding switches to turn on sequentially, introducing a differential charge compensation mechanism; High level When the signal level is low, the circuit is in the signal sampling process, and the differential input signal is active. VIP and VINTransistors M2 and M4 are connected to their respective gates, while transistors M2 and M3 are connected to all their terminals. Similarly, transistors M1 and M4 are connected to all their terminals, ensuring the parasitic gate capacitance of transistor M2 is minimized. Parasitic gate capacitance of transistor M3 Equal to the parasitic gate capacitance of transistor M1 Parasitic gate capacitance of M4 The charges stored at the differential input terminals during this process are equal, respectively. VIP (+ ), VIN ( + ); Change to low level After becoming high, the differential input signal VIP and VIN The gates of transistors M3 and M4 are disconnected respectively. Transistors M1 and M3 are connected at all terminals, and transistors M2 and M4 are connected at all terminals. After charge transfer and sharing, the charges stored at the differential input terminals are respectively... VIP + VIN * , VIP + VIN * Since the two are equal, the differential equivalent charge is zero, achieving the purpose of differential charge compensation and thus eliminating the error caused by the gate parasitic capacitance of the input transistor.

[0010] In the input stage with compensation function, the added compensation transistor pair exists as part of the input transistor, contributing half of the transconductance to the input transistor pair; during signal sampling, transistors M2 and M3 are connected in parallel, and transistors M1 and M4 are connected in parallel; during differential charge compensation, transistors M1 and M3 are connected in parallel, and transistors M2 and M4 are connected in parallel.

[0011] The differential charge compensation function of the dynamic comparator is completed during the comparator's reset phase, and the two-phase non-overlapping clock... and Corresponding to the signal sampling process and the differential charge compensation process respectively, the dynamic comparator's operating clock CLK is at a high level, and the circuit is in a reset state; and The absence of overlapping high-level states prevents additional charge sharing between the two differential inputs, thus ensuring the effectiveness of the differential charge compensation mechanism.

[0012] The present invention provides a dynamic comparator with differential charge compensation function, wherein the compensation input pair exists as part of the input pair, contributing half of the transconductance to the input pair; the differential charge compensation mechanism is realized by adding two-phase non-overlapping clocks and corresponding switches, providing a practical solution for reducing the error of the successive approximation analog-to-digital converter sampled by the top plate. Attached Figure Description

[0013] Figure 1 This is the circuit schematic of a dynamic comparator with differential charge compensation.

[0014] Figure 2 This is a timing diagram of two non-overlapping clocks.

[0015] Figure 3 This is a circuit diagram of the signal sampling process.

[0016] Figure 4 This is the circuit diagram of the differential charge compensation process. Detailed Implementation

[0017] This invention proposes a dynamic comparator with differential charge compensation function to address the error introduced by the comparator in a successive approximation analog-to-digital converter with top plate sampling.

[0018] Figure 2 Two-phase non-overlapping clocks are given and Timing diagram, or A high level indicates that the corresponding switch is on, and a low level indicates that the corresponding switch is off. High level When the signal level is low, the circuit is in the signal sampling process; Low level When the voltage level is high, the circuit is in the differential charge compensation process. and The two inputs are not simultaneously high to avoid additional charge sharing between them, thus ensuring the effectiveness of the differential charge compensation mechanism.

[0019] Figure 3 Given High level This is the circuit schematic for the low-level signal. At this time, the circuit is in the signal sampling process. The input signal is connected to the differential input of the comparator, causing input-related charges to accumulate on the gate parasitic capacitance of the input transistors. Transistors M2 and M3 are connected in parallel, and transistors M1 and M4 are connected in parallel. Transistors M1, M2, M3, and M4 have the same dimensions. Let the gate parasitic capacitances of transistors M1, M2, M3, and M4 be respectively... , , , The gate charge accumulation of transistors M1, M2, M3, and M4 are respectively VIN , VIP , VIP , VIN .

[0020] Figure 4 Given Low level This is the circuit schematic when the signal is high. At this time, the circuit is in the differential charge compensation process. The input signal is disconnected from the differential input of the comparator. Transistors M1 and M3 are connected in parallel, and the charge on their gates is... VIN + VIP Transistors M2 and M4 are connected in parallel, and the charge on their gates is... VIP + VIN .because and The transistor connections are highly symmetrical before and after clock switching, and transistors M1, M2, M3, and M4 are the same size, therefore... VIN + VIP and VIP + VIN They are equal; since they are located at the two inputs of the dynamic comparator, the differential charge is equivalent to zero, thus fully realizing differential charge compensation.

[0021] This invention provides a highly practical dynamic comparator design method by introducing a two-phase non-overlapping clock. , With corresponding switches and two pairs of identical input transistors, differential compensation for the charge accumulation due to parasitic capacitance in the input stage of the dynamic comparator is achieved, avoiding the error in the successive approximation of the digital-to-analog converter caused by the top plate sampling in the input stage of the dynamic comparator with relatively small component overhead.

Claims

1. A dynamic comparator having a differential charge compensation function, characterized by comprising: Comprise: The input stage with compensation function and digital output stage; wherein: In the input stage with compensation function, the first transistor M1 and the second transistor M2 are a pair of compensation input transistors, and the third transistor M3 and the fourth transistor M4 are a pair of input transistors. The compensation input transistor pairs are the same size as the input transistor pairs. Furthermore, their sources are all connected to the drain of the fifth transistor M5, and the source of the fifth transistor M5 is connected to the drain of the sixth transistor M6. The current source IREF is connected to the drain-gate of the seventh transistor M7, and the gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7. The sources of both the sixth transistor M6 and the seventh transistor M7 are the power supply voltage VDD. The gate of the first transistor M1 is connected to a two-phase non-overlapping clock. The control switch is connected to the gate of the third transistor M3, and is controlled by a two-phase non-overlapping clock. The control switch is connected to the gate of the fourth transistor M4; the gate of the second transistor M2 is connected to a two-phase non-overlapping clock. The control switch is connected to the gate of the fourth transistor M4, and is controlled by a two-phase non-overlapping clock. The control switch is connected to the gate of the third transistor M3; the drain of the first transistor M1 is connected to a two-phase non-overlapping clock. The control switch is connected to the drain of the fourth transistor M4, and is controlled by a two-phase non-overlapping clock. The control switch is connected to the drain of the third transistor M3; the drain of the second transistor M2 is connected to a two-phase non-overlapping clock. The control switch is connected to the drain of the third transistor M3, and is controlled by a two-phase non-overlapping clock. The control switch is connected to the drain of the fourth transistor M4; the gates of the third transistor M3 and the fourth transistor M4 are respectively connected through... The control value switch is connected to the differential input signals VIP and VIN; the drains of the third transistor M3, the eighth transistor M8, the tenth transistor M10, and the gate of the ninth transistor M9 are connected; the drains of the fourth transistor M4, the ninth transistor M9, the eleventh transistor M11, and the gate of the eighth transistor M8 are connected; the gates of the fifth transistor M5, the tenth transistor M10, and the eleventh transistor M11 are all the operating clock CLK of the dynamic comparator; the sources of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are all grounded; In the digital output stage, the source of the twelfth transistor M12 and the thirteenth transistor M13 is connected to VDD, the source of the fourteenth transistor M14 and the fifteenth transistor M15 is connected to ground; the gate of the twelfth transistor M12 and the fourteenth transistor M14 is connected to the drain of the thirteenth transistor M3, and their drains are connected to the input of the first inverter I1; the gate of the thirteenth transistor M13 and the fifteenth transistor M15 is connected to the drain of the fourth transistor M4, and their drains are connected to the input of the second inverter I2; the output of the first inverter I1 and the second inverter I2 is connected to the input of the third inverter I3 and the fourth inverter I4 respectively; the output of the third inverter I3 and the fourth inverter I4 is the output signal VON and VOP of the comparator respectively, and is connected to the two inputs of the two-input NAND gate I5 in turn; the output of the NAND gate I5 is the valid signal VALID of the comparator output.

2. The dynamic comparator with differential charge compensation function according to claim 1, wherein, The input stage with compensation function, two-phase non-overlapping clock And The corresponding switch is turned on by high level control in turn, and the differential charge compensation mechanism is introduced. High level, Low level, the circuit is in the signal sampling process, the differential input signal VIP and VIN are connected with the gate of the third transistor M3 and the fourth transistor M4 respectively, the second transistor M2 and the third transistor M3 are connected with each other, the first transistor M1 and the fourth transistor M4 are connected with each other, which ensures that the parasitic gate capacitance C2 of the second transistor M2 is equal to the parasitic gate capacitance C3 of the third transistor M3, and the parasitic gate capacitance C1 of the first transistor M1 is equal to the parasitic gate capacitance C4 of the fourth transistor M4, and the charge stored in the differential input terminal is VIP(C2+C3) and VIN(C1+C4) respectively in this process. Low level, After the high level, the differential input signal VIP and VIN are disconnected with the gate of the third transistor M3 and the fourth transistor M4 respectively, the first transistor M1 and the third transistor M3 are connected with each other, the second transistor M2 and the fourth transistor M4 are connected with each other, and the charge is transferred and shared, at this time the charge stored in the differential input terminal is VIP*C3+VIN*C1 and VIP*C2+VIN*C4 respectively, which are equal, so that the differential equivalent charge is zero, and the purpose of differential charge compensation is achieved, so as to eliminate the error caused by the parasitic gate capacitance of the input tube.

3. The dynamic comparator with differential charge compensation function according to claim 1, wherein, In the input stage with compensation function, the added compensation pair transistor exists as part of the input pair transistor, contributing half of the transconductance to the input pair transistor; during the signal sampling process, the second transistor M2 and the third transistor M3 are connected in parallel, and the first transistor M1 and the fourth transistor M4 are connected in parallel; during the differential charge compensation process, the first transistor M1 and the third transistor M3 are connected in parallel, and the second transistor M2 and the fourth transistor M4 are connected in parallel.

4. The dynamic comparator with differential charge compensation function according to claim 1, wherein, The two-phase non-overlapping clock And The dynamic comparator working clock CLK is at high level, and the circuit is in reset state in the signal sampling process and the differential charge compensation process. And There is no overlapping high level state, which avoids additional charge sharing between the two differential input terminals, thereby ensuring the effectiveness of the differential charge compensation mechanism.

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