Semiconductor devices

Abstract

The present invention relates to a semiconductor device, wherein a semiconductor substrate has an active region where a main current flows and an end region further outward than the active region, the semiconductor device having: a first main electrode, which is arranged on the active region; a second main electrode, which is arranged on the opposite side of the semiconductor substrate to the first main electrode; a protective film, which at least covers the end region; and a non-electrolytic plating layer, which is arranged on the first main electrode not covered by the protective film, the first main electrode having: a central electrode in a central portion; and a peripheral electrode, which is arranged along the central electrode at a distance from the central electrode, the protective film being arranged from the end region to the end edge of the peripheral electrode, the central electrode and the peripheral electrode having: a first metal layer; and a second metal layer, which is arranged on the first metal layer and contains aluminum, at least the peripheral electrode having a hole portion, the hole portion penetrating the second metal layer to reach the first metal layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an external electrode electrically connected to the outside and a main electrode of the semiconductor device are joined by soldering. Background Art

[0002] In conventional semiconductor devices, in order to reduce the on-resistance of the semiconductor device, for example, Patent Document 1 discloses a structure in which a surface electrode and an external electrode are soldered. In this structure, due to the thermal cycle when power is applied, tensile stress is generated on the surface electrode, and cracks may be generated from the electrode ends. In the case of cracks, the cracks develop from the electrode to the inside of the semiconductor device, and depending on the situation, the semiconductor device may be electrically damaged, which has become a problem for improving the thermal cycle resistance of the product.

[0003] In addition, since the solder and the surface electrode may alloy through heat cycles, the surface electrode needs to be thickened to ensure heat cycle resistance. Therefore, as disclosed in Patent Document 2, the electrode is usually formed by using nickel (Ni) electroless plating.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2008-182074

[0005] Patent Document 2: Japanese Patent Application Publication No. 2005-19798 Summary of the invention

[0006] Even when the surface electrode is thickened, cracks may occur at the ends of the surface electrode. If the cracks develop and reach the inside of the semiconductor device, the semiconductor device may be electrically damaged.

[0007] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device having improved thermal cycle resistance.

[0008] The present invention relates to a semiconductor device in which a main current flows in a thickness direction of a semiconductor substrate. In the semiconductor device, the semiconductor substrate has: an active region in which the main current flows; and an end region on the outer side of the active region. The semiconductor device has: a first main electrode arranged on the active region; a second main electrode arranged on the opposite side of the semiconductor substrate to the first main electrode; a protective film covering at least the end region; and an electroless plating layer arranged on the first main electrode not covered by the protective film. The first main electrode has: a central electrode in a central portion; and a peripheral electrode arranged along the central electrode at a distance from the central electrode, the protective film being arranged from the end region to the edge of the peripheral electrode, the central electrode and the peripheral electrode having: a first metal layer; and a second metal layer arranged on the first metal layer and containing aluminum, at least the peripheral electrode having a hole portion that penetrates the second metal layer and reaches the first metal layer.

[0009] Effects of the Invention

[0010] According to the semiconductor device involved in the present invention, there is a hole portion that penetrates the second metal layer of the peripheral electrode to reach the first metal layer, so that the contact area between the first metal layer and the second metal layer is reduced, and therefore peeling is likely to occur at the interface between the first metal layer and the second metal layer. Even if cracks are generated along the interface between the protective film and the electroless plating layer (interface peeling) due to thermal cycling, if the cracks reach the peripheral electrode, the peeling at the interface between the first metal layer and the second metal layer will also develop in the horizontal direction, thereby suppressing the development of the cracks in the vertical direction, that is, the thickness direction of the semiconductor device, and improving the thermal cycle resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a plan view showing the upper surface structure of the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a partial cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0013] Figure 3 This is a partial cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0014] Figure 4 This is a partially enlarged view showing the structure of the semiconductor device according to the first embodiment.

[0015] Figure 5 This is a cross-sectional view schematically showing cracks generated when a heat cycle caused by energization is applied to the semiconductor device according to the first embodiment.

[0016] Figure 6 This is a partial cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Figure 7 This is a partial cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Figure 8 This is a partial cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0019] Fig. 9 This is a partial cross-sectional view showing the structure of a semiconductor device according to a third embodiment.

[0020] Fig.10 This is a partial cross-sectional view for explaining a method for manufacturing a semiconductor device according to a third embodiment.

[0021] Fig.11 This is a partial cross-sectional view for explaining a method for manufacturing a semiconductor device according to a third embodiment.

[0022] Fig.12 It is a partial cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment.

[0023] Fig.13 This is a partial cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment.

[0024] Fig.14 This is a diagram for explaining the relationship between the distance between the emitter central electrode and the emitter peripheral electrode and the thickness of the plating layer. DETAILED DESCRIPTION

[0025] <Foreword>

[0026] In the following description, the "active region" refers to the region where the main current flows when the semiconductor device is in the on state. In addition, in the following, "outside" is the direction toward the periphery of the semiconductor device, and "inside" is the direction opposite to "outside". In addition, in the following description, regarding the conductivity type of the impurity, the N type is usually defined as the "first conductivity type", and the P type, which is the opposite conductivity type to the N type, is defined as the "second conductivity type", but the opposite definition may also be used.

[0027] In addition, the drawings are only schematically shown, and the mutual relationship between the size and position of the images shown in different drawings may not be accurately recorded and can be appropriately changed. In addition, in the following description, the same structural elements are marked with the same reference numerals and illustrated, and their names and functions are also the same. Therefore, their detailed descriptions are sometimes omitted. In addition, in this specification, in the case of "above" and "covering ~", inclusions between structural elements are not excluded. For example, in the case of "B set on A" or "A covers B", it may mean that other structural elements C are set between A and B, or it may mean that other structural elements C are not set. In addition, in the following description, terms such as "upper", "lower", "side", "bottom", "table" or "back" are sometimes used to indicate specific positions and directions. These terms are only for the convenience of understanding the contents of the implementation method, and have nothing to do with the direction during actual implementation.

[0028] In addition, the term "MOS" was previously used for the junction structure of metal-oxide-semiconductor, and the initials of Metal-Oxide-Semiconductor were used. However, in particular, in field effect transistors having a MOS structure (hereinafter, simply referred to as "MOS transistors"), the materials of gate insulating films and gate electrodes have been continuously improved from the perspectives of integration and improvement of manufacturing processes in recent years.

[0029] For example, in MOS transistors, polysilicon can be used as the material of the gate electrode instead of metal mainly from the viewpoint of forming the source and drain in a self-aligned manner. In addition, from the viewpoint of improving electrical characteristics, a material with a high dielectric constant is used as the material of the gate insulating film, but the material is not necessarily limited to oxides.

[0030] Therefore, the term "MOS" is not necessarily limited to the stacked structure of metal-oxide-semiconductor, and this specification is not based on such a limitation. That is, in view of common technical knowledge, here, "MOS" is not only an abbreviation derived from its etymology, but also has a broad meaning including the stacked structure of conductor-insulator-semiconductor.

[0031] Hereinafter, an embodiment of a semiconductor device according to the present invention will be described. In the following, an IGBT (Insulated Gate Bipolar Transistor) will be described as an example of a semiconductor device.

[0032] <Implementation Method 1>

[0033] <Device Structure>

[0034] Figure 1FIG. 1 is a top view schematically showing the upper surface structure of the IGBT 100 according to the first embodiment of the present invention. Figure 1 As shown, the IGBT 100 is provided on a semiconductor substrate 1 having a quadrangular shape in plan view, and a gate wiring 51 is provided along its periphery. In addition, a quadrangular gate electrode pad 5 is provided at one of the corners of the IGBT 100 and is surrounded by the gate wiring 51.

[0035] The emitter electrode 3 (first main electrode) is provided on most of the main surface of the IGBT 100 except for the portion where the gate electrode pad 5 and the gate wiring 51 are provided.

[0036] The emitter electrode 3 is provided on the active region AR of the IGBT 100 , and is divided into an emitter central electrode 3 a at the center and an emitter peripheral electrode 3 b arranged to surround the outer side of the emitter central electrode 3 a .

[0037] The region outside the periphery of the gate wiring 51 is defined as the termination region 2. An impurity region for maintaining a withstand voltage may be provided in the termination region 2, but this is not shown.

[0038] exist Figure 2 Shown in Figure 1 The arrow direction section view at line AA in the figure is Figure 3 The arrow direction cross-sectional view at line BB is shown in FIG. Figure 2 and Figure 3 As shown, the IGBT 100 has an N-type drift layer 15 disposed on an upper main surface of an N-type buffer layer 16 , and a P-type body layer 10 disposed on an upper layer portion of the N-type drift layer 15 .

[0039] In addition, a P-type collector layer 17 is provided on the lower main surface of the buffer layer 16, an AlSi (aluminum-silicon alloy) metal layer 18 is provided on the lower main surface of the collector layer 17, and a Ni metal layer 19 is provided on the lower main surface of the metal layer 18 to form a collector electrode (electrode) (second main electrode). In addition, the semiconductor substrate 1 includes the collector layer 17, the buffer layer 16, the drift layer 15 and the body layer 10.

[0040] A plurality of N-type emitter layers 12 are selectively provided on the upper layer portion of the body layer 10 , and a plurality of trench gate electrodes 11 are provided that penetrate the emitter layers 12 and the body layer 10 in the thickness direction and reach the inside of the drift layer 15 .

[0041] Furthermore, an interlayer insulating film 13 is provided on the drift layer 15 (on the body layer 10 ), and a plurality of contact electrodes 14 are provided on the interlayer insulating film 13 so as to penetrate the interlayer insulating film 13 in the thickness direction and reach the emitter layer 12 .

[0042] The emitter central electrode 3a and the emitter peripheral electrode 3b have a stacked structure of a metal layer 6 (first metal layer) and a metal layer 7 (second metal layer), wherein the metal layer 6 is provided on the interlayer insulating film 13 in contact with the plurality of contact electrodes 14, the metal layer 7 is provided on the metal layer 6, and a plating layer 8 is provided on the metal layer 7. Here, the metal layer 6 is, for example, a barrier metal (Ti / TiN) in which Ti (titanium) is stacked on TiN (titanium nitride), the metal layer 7 is, for example, an aluminum layer, and the plating layer 8 is, for example, an electroless nickel plating layer (electroless plating layer) of nickel (NiP) containing phosphorus.

[0043] The metal layer 7 has a hole 9 formed therein which penetrates the metal layer 7 in the thickness direction and reaches onto the metal layer 6 , and the hole 9 is filled with the plating layer 8 .

[0044] From Figure 1 The gate electrode pad 5 covers the outer edge of the emitter peripheral electrode 3b, and Figure 2 A protective film 4 made of, for example, polyimide is provided on the outer edge portion of the emitter peripheral electrode 3 b so as to cover the gate wiring 51 .

[0045] Here, in Figure 4 Shown in Figure 2 Magnified view of area "X" in FIG. Figure 4 1 is a diagram showing details of the trench gate electrode 11 and the contact electrode 14. Figure 4 As shown, with respect to the trench gate electrode 11 , a gate insulating film 111 is provided in a manner covering the inner surface of a gate trench 113 penetrating the emitter layer 12 and the body layer 10 in the thickness direction and reaching the drift layer 15 , and a gate electrode 112 is buried in the gate trench 113 covered by the gate insulating film 111 .

[0046] The trench gate electrode 11 is covered with an interlayer insulating film 13 , but is electrically connected to a gate line 51 via an opening of the interlayer insulating film 13 provided in a portion not shown in the figure, and is supplied with a gate voltage.

[0047] The contact electrode 14 is configured such that a metal layer 6 is embedded in an opening 131, and the opening 131 penetrates the interlayer insulating film 13 in the thickness direction and reaches the emitter layer 12. Furthermore, in the metal layer 6 embedded in the opening 131, a tungsten (W) layer 142 is embedded in the opening 141, and the metal layer 6 and the tungsten layer 142 constitute the contact electrode 14. The metal layer 6 is provided to reduce the contact resistance between the upper metal layer 7 and the tungsten layer 142 (contact electrode 14).

[0048] Figure 5 This is a cross-sectional view schematically showing a crack 21 generated when a solder layer 20 is bonded to a plating layer 8 and a heat cycle caused by energization is applied.

[0049] like Figure 5 As shown, the crack 21 generated by the heat cycle develops along the interface between the protective film 4 and the plating layer 8, and if it contacts the metal layer 7, first, interface peeling (crack) occurs at the interface between the plating layer 8 and the metal layer 7. After that, if the peeling reaches the metal layer 6, the contact area between the metal layer 6 and the metal layer 7 decreases due to the formation of the hole portion 9, so that peeling occurs at the interface between the metal layer 7 and the metal layer 6. As a result, the peeling develops in the horizontal direction, and the peeling is suppressed from developing in the vertical direction, that is, the thickness direction of the IGBT 100, so that the damage of the element structure of the IGBT 100 is suppressed, and the device life can be extended compared with the past.

[0050] Furthermore, although the delamination of the interface progresses on the emitter peripheral electrode 3 b , the emitter peripheral electrode 3 b and the emitter central electrode 3 a are separated, so that the crack is suppressed from reaching the emitter central electrode 3 a .

[0051] <Manufacturing method>

[0052] Next, a cross-sectional view showing the manufacturing process in sequence is used. Figure 6 and Figure 7 , a method for manufacturing the IGBT 100 will be described. The structure below the interlayer insulating film 13 is a known structure, and a known technique can be used for the manufacturing method, so the description thereof will be omitted.

[0053] After the structure below the interlayer insulating film 13 is formed using the conventional technology, Figure 6 In the process shown, contact electrode 14 is formed in interlayer insulating film 13, barrier metal such as Ti / TiN is formed as metal layer 6 on interlayer insulating film 13, and aluminum layer is formed as metal layer 7 on metal layer 6. Metal layer 7 may also be an aluminum alloy layer.

[0054] In addition, the metal layer 6 is formed on the active region, and is not formed in the region where the gate electrode pad 5 and the gate wiring 51 are formed, and the stacked structure of the metal layer 6 and the metal layer 7 is formed on the active region. In addition, the metal layer 6 may also be formed in the region where the gate electrode pad 5 and the gate wiring 51 are formed, and is set as a stacked structure with the metal layer 7.

[0055] Through a photolithography (photolithography) process and an etching process, the stacked structure of the metal layer 6 and the metal layer 7 and the metal layer 7 are patterned, and openings are opened in the region where the protective film 4 contacts the interlayer insulating film 13 and in the region where the emitter central electrode 3a and the emitter peripheral electrode 3b are separated. Then, the protective film 4 is selectively formed by, for example, polyimide. In addition, the etching of the metal layer 6 and the metal layer 7 can use a known etching process.

[0056] Next, before forming the plating layer 8 by electroless NiP plating on aluminum, zincate treatment is performed as a pre-treatment to cause Al pitting in the metal layer 7, as shown in FIG. Figure 7 As shown, a plurality of holes 9 are formed to penetrate the metal layer 7 in the thickness direction.

[0057] Here, the depth of Al pitting formed by zincate treatment is about 0.5 μm to 1 μm, so the thickness of the metal layer 7 is greater than or equal to 0.5 μm and less than or equal to 1 μm, and is more preferably about 0.5 μm, so that the hole 9 can reliably penetrate the metal layer 7. In addition, the thickness of the metal layer 6 is set to about 0.1 μm, and the thickness of the plating layer 8 is set to about 5 μm.

[0058] Then, the plated layer 8 is formed by electroless NiP plating to obtain a Figure 2 and Figure 3 1. The cross-sectional structure of the IGBT 100 is shown.

[0059] Since Al pitting formed by zincate treatment is used as hole portion 9, processing for forming hole portion 9 in the metal layer can be omitted, thereby reducing the number of steps and costs required for processing and suppressing a decrease in productivity caused by providing hole portion 9.

[0060] <Implementation Method 2>

[0061] Figure 8 is a cross-sectional view showing the structure of an IGBT 200 according to a second embodiment of the present invention, and Figure 1 The cross-sectional view along the arrow direction at the BB line in FIG. 2 corresponds to the cross-sectional view along the arrow direction at the BB line in FIG. Figure 1 The top view of the IGBT 100 shown is identical.

[0062] like Figure 8As shown, the hole 91 at the emitter peripheral electrode 3b of the IGBT 200 is formed larger than the hole 9 at the emitter central electrode 3a. By making the hole 91 at the emitter peripheral electrode 3b larger, cracks (interface peeling) generated when a heat cycle is applied to the IGBT 200 can be more reliably developed in the horizontal direction of the emitter peripheral electrode 3b, and the peeling can be suppressed from developing in the vertical direction, that is, the thickness direction of the IGBT 200, thereby suppressing the damage to the element structure of the IGBT 200 and extending the device life compared with the past.

[0063] In this way, in order to form the hole 91 at the emitter peripheral electrode 3b larger than the hole 9 at the emitter central electrode 3a, in the formation of the metal layer 7 composed of AlSi, the formation process of the part that will become the emitter central electrode 3a and the gate electrode pad 5 (not shown) and the formation process of the part that will become the emitter peripheral electrode 3b are separated, and the metal layer 7 that will become the emitter peripheral electrode 3b is formed from different film materials in such a way that the silicon concentration of the metal layer 7 that will become the emitter peripheral electrode 3b is higher than the silicon concentration of the metal layer 7 that will become the emitter central electrode 3a and the gate electrode pad 5.

[0064] Normally, the Si content of AlSi is about 1%, but by increasing it to about 10%, a large amount of silicon particles (silicon segregation) are formed in the metal layer 7. During the zincate treatment before forming the plating layer 8, the silicon particles are also separated from the metal layer 7, thereby forming a hole portion 91 larger than the hole portion 9 at the emitter central electrode 3a in the metal layer 7 that becomes the emitter peripheral electrode 3b.

[0065] The metal layer 7 is formed by sputtering, and by using sputtering targets with different Si composition ratios, it is possible to change the Si concentration between the portion that becomes the emitter central electrode 3a and the portion that becomes the emitter peripheral electrode 3b and the gate electrode pad 5. That is, when forming the metal layer 7 that becomes the emitter central electrode 3a and the gate electrode pad 5 (not shown), a sputtering target with a Si composition ratio of about 1% is used, and when forming the portion that becomes the emitter peripheral electrode 3b, a sputtering target with a Si composition ratio of about 10% is used.

[0066] <Implementation Method 3>

[0067] <Device Structure>

[0068] Fig. 9 is a cross-sectional view showing the structure of an IGBT 300 according to a third embodiment of the present invention, and Figure 1 The cross-sectional view along the AA line in FIG. 1 corresponds to the cross-sectional view along the AA line in FIG. 1. In addition, the upper surface structure of IGBT300 corresponds to Figure 1 The top view of the IGBT 100 shown is identical.

[0069] like Fig. 9 As shown, in the IGBT 300, the hole 92 at the emitter peripheral electrode 3b is formed to be deeper and larger than the hole 9 at the emitter central electrode 3a and the gate electrode pad 5. The hole 92 at the emitter peripheral electrode 3b penetrates the metal layer 7 and reaches the metal layer 6. In contrast, the hole 9 at the emitter central electrode 3a and the gate electrode pad 5 does not penetrate the metal layer 7.

[0070] By forming the hole portion 92 at the emitter peripheral electrode 3b in a manner that penetrates the metal layer 7 and reaches onto the metal layer 6, cracks (interface peeling) generated when a thermal cycle is applied to the IGBT 300 can be allowed to develop in the horizontal direction of the emitter peripheral electrode 3b, and the peeling can be suppressed from developing in the vertical direction, i.e., the thickness direction of the IGBT 300, thereby suppressing damage to the element structure of the IGBT 300 and extending the device life compared to the past.

[0071] Here, the hole 92 in the emitter peripheral electrode 3b is a hole selectively formed by etching, and the hole 9 in the emitter central electrode 3a and the gate electrode pad 5 are holes formed by Al pitting caused by zincate treatment before forming the plating layer 8, and are non-selectively formed.

[0072] <Manufacturing method>

[0073] Next, a cross-sectional view showing the manufacturing process in sequence is used. Fig.10 and Fig.11 , a method for manufacturing the IGBT 300 will be described. The structure below the interlayer insulating film 13 is a known structure, and a known technique can be used for the manufacturing method, so the description thereof will be omitted.

[0074] After the structure below the interlayer insulating film 13 is formed using the conventional technology, the contact electrode 14 is formed in the interlayer insulating film 13, and a barrier metal such as Ti / TiN is formed on the interlayer insulating film 13 as a metal layer 6, and an aluminum layer is formed on the metal layer 6 as a metal layer 7. In addition, the metal layer 6 is formed on the active region, and is not formed in the region where the gate electrode pad 5 and the gate wiring 51 are formed, and the stacked structure of the metal layer 6 and the metal layer 7 is formed on the active region. In addition, the metal layer 6 may also be formed in the region where the gate electrode pad 5 and the gate wiring 51 are formed, and it may be set as a stacked structure with the metal layer 7.

[0075] After the photolithography process and the etching process, the stacked structure of the metal layer 6 and the metal layer 7 and the metal layer 7 are patterned, and openings are opened in the area where the protective film 4 contacts the interlayer insulating film 13 and in the area separating the emitter central electrode 3a and the emitter peripheral electrode 3b. Then, the protective film 4 is selectively formed by, for example, polyimide.

[0076] After that, it goes through the photoengraving process again. Fig.10 In the process shown, a resist mask RM is provided on the metal layer 7 that becomes the emitter peripheral electrode 3b, and the portion that becomes the hole portion 92 is an opening portion OP. The resist mask RM does not have an opening portion other than the opening portion OP, and the metal layer 7 that becomes the emitter central electrode 3a and the gate electrode pad 5 is covered by the resist mask RM.

[0077] Thereafter, the stacked structure of the metal layer 6 and the metal layer 7 is etched through the opening OP by an etching step, thereby forming a hole 92 that penetrates the metal layer 7 and reaches onto the metal layer 6 .

[0078] After the resist mask RM is removed, zincate treatment is performed before forming the plating layer 8 by electroless NiP plating on aluminum. Fig.11 As shown, Al pitting occurs in the metal layer 7 at the portion that becomes the emitter central electrode 3 a and the gate electrode pad 5 , and a hole portion 9 is formed.

[0079] Here, by setting the thickness of the metal layer 7 to be greater than or equal to 1.5 μm, the hole 9 cannot penetrate the metal layer 7, and the hole 9 does not reach the metal layer 6 at the emitter central electrode 3a and the gate electrode pad 5. In addition, from the viewpoint of ensuring the flatness of the plating layer 8, it is preferred that the thickness of the metal layer 7 be greater than or equal to 1.5 μm and less than or equal to 2 μm.

[0080] Furthermore, Al pitting also occurs in the emitter peripheral electrode 3 b by the zincate treatment. However, since the thickness of the metal layer 7 is greater than or equal to 1.5 μm, the holes 9 formed by the Al pitting cannot penetrate the metal layer 7 and are therefore not shown.

[0081] Then, the plated layer 8 is formed by electroless NiP plating to obtain a Fig. 9 1 and 2. The cross-sectional structure of the IGBT 300 is shown.

[0082] In this way, by utilizing etching to form the hole portion 92 at the emitter peripheral electrode 3b, the size, shape, number and arrangement pattern of the hole portion 92 can be set arbitrarily, thereby enabling the development of interface peeling (cracks) at the interface between the metal layer 7 and the metal layer 6 at the emitter peripheral electrode 3b to be controlled, and enabling the cracks to reliably develop in the horizontal direction.

[0083] In addition, since the hole 9 of the emitter central electrode 3a and the gate electrode pad 5 cannot penetrate the metal layer 7, the contact between the metal layer 6 with a large contact resistance and the plating layer 8 can be avoided, the contact area between the metal layer 6 with a small contact resistance and the metal layer 7 is increased, the resistance when power is turned on is reduced, and the electrical performance of the IGBT 300 is improved.

[0084] <Implementation Method 4>

[0085] Fig.12 is a cross-sectional view showing the structure of an IGBT 400 according to a fourth embodiment of the present invention, and Figure 1 The cross-sectional view along the arrow direction at line BB in FIG. 4 corresponds to the cross-sectional view along the arrow direction at line BB in FIG. Figure 1 The top view of the IGBT 100 shown is identical.

[0086] like Fig.12 As shown, in the IGBT 400, the thickness of the metal layer 7 at the emitter central electrode 3a and the gate electrode pad 5 is formed thicker than the thickness of the metal layer 7 at the emitter peripheral electrode 3b, and the hole 9 of the emitter central electrode 3a does not penetrate the metal layer 7. On the other hand, the hole 9 at the emitter peripheral electrode 3b penetrates the metal layer 7 and reaches the metal layer 6.

[0087] In this way, in order to make the thickness of the metal layer 7 at the emitter central electrode 3a and the gate electrode pad 5 thicker than the thickness of the metal layer 7 at the emitter peripheral electrode 3b, in the formation of the metal layer 7, the formation process of the part that will become the emitter central electrode 3a and the gate electrode pad 5 and the formation process of the part that will become the emitter peripheral electrode 3b are separated.

[0088] Furthermore, the thickness of the metal layer 7 that will become the emitter central electrode 3a and the gate electrode pad 5 is set to be greater than or equal to 1.5 μm, and the thickness of the metal layer 7 that will become the emitter peripheral electrode 3b is set to be greater than or equal to 0.5 μm and less than or equal to 1 μm, and more preferably about 0.5 μm, so that the hole 9 can reliably penetrate the metal layer 7. In addition, from the viewpoint of ensuring the flatness of the plating layer 8, the thickness of the metal layer 7 that will become the emitter central electrode 3a and the gate electrode pad 5 is preferably set to be greater than or equal to 1.5 μm and less than or equal to 2 μm.

[0089] By setting such a structure, at the emitter peripheral electrode 3b, cracks (interface peeling) generated when a heat cycle is applied to the IGBT 400 can be allowed to develop in the horizontal direction of the emitter peripheral electrode 3b, and the peeling can be suppressed from developing in the vertical direction, that is, the thickness direction of the IGBT 400, thereby suppressing damage to the element structure of the IGBT 400, thereby extending the device life compared to the past.

[0090] In addition, since the hole 9 of the emitter central electrode 3a and the gate electrode pad 5 cannot penetrate the metal layer 7, the contact between the metal layer 6 with a large contact resistance and the plating layer 8 can be avoided, the contact area between the metal layer 6 with a small contact resistance and the metal layer 7 is increased, the resistance when power is turned on is reduced, and the electrical performance of the IGBT 400 is improved.

[0091] <Implementation method 5>

[0092] Fig.13 is a cross-sectional view showing the structure of an IGBT 500 according to a fifth embodiment of the present invention, and Figure 1 The cross-sectional view along the arrow direction at line BB in FIG. 1 corresponds to the cross-sectional view along the arrow direction at line BB in FIG. 1. In addition, the upper surface structure of IGBT500 corresponds to Figure 1 The top view of the IGBT 100 shown is identical.

[0093] like Fig.13 As shown, the IGBT 500 has a structure in which the trench gate electrode 11 is not provided below the emitter peripheral electrode 3 b , that is, it does not have a unit cell which is the minimum unit structure of the IGBT.

[0094] By adopting the above-mentioned structure, the flatness of the metal layer 6 of the emitter peripheral electrode 3b is improved, and the cracks (interface peeling) generated when the IGBT 500 is subjected to a thermal cycle are likely to develop in the horizontal direction at the interface between the metal layer 7 and the metal layer 6 at the emitter peripheral electrode 3b, and the peeling can be suppressed from developing in the vertical direction, that is, the thickness direction of the IGBT 500, thereby suppressing the damage to the component structure of the IGBT 500, thereby extending the device life compared with the past.

[0095] Furthermore, since the trench gate electrode 11 is not provided below the emitter peripheral electrode 3b, the number of unit cells in the IGBT 500 is reduced accordingly. Therefore, in order to suppress the reduction of unit cells, the horizontal length of the emitter peripheral electrode 3b is made as short as possible, for example, about 5 μm.

[0096] <Relationship between the distance between the emitter central electrode and the emitter peripheral electrode and the thickness of the plating layer>

[0097] Fig.14 This is a diagram illustrating the relationship between the distance between the emitter central electrode and the emitter peripheral electrode and the thickness of the plating layer. Figure 1 The figure is based on the cross-sectional view in the direction of the arrow at line BB in FIG. Fig.14 , the distance between the emitter central electrode 3a and the emitter peripheral electrode 3b is set to d, the thickness of the plating layer 8 is set to t, and the relationship between the distance d and the thickness t is shown as d>2t.

[0098] In this case, the interval between the emitter central electrode 3a and the emitter peripheral electrode 3b is too wide relative to the plating layer 8. When the solder layer 20 is joined to the plating layer 8, the solder layer 20 only wets and expands on the emitter central electrode 3a. When a thermal cycle is applied, cracks are generated on the emitter central electrode 3a, and the device life may be reduced.

[0099] On the other hand, by setting the interval between the emitter central electrode 3a and the emitter peripheral electrode 3b so that the relationship between the interval d and the thickness t is d≤2t, the plating layer 8 formed on the emitter central electrode 3a and the emitter peripheral electrode 3b is smoothly connected, and the solder layer 20 wets and spreads over the entire surface of the plating layer 8 above the emitter central electrode 3a and the emitter peripheral electrode 3b. Therefore, cracks are likely to occur on the emitter peripheral electrode 3b when a thermal cycle is applied.

[0100] In the IGBTs 100 to 500 in the first to fifth embodiments, since the relationship between the distance d and the thickness t is set to satisfy d≦2t, the crack develops in the horizontal direction of the emitter peripheral electrode 3 b.

[0101] <Other Application Examples>

[0102] In the above-described embodiments 1 to 5, the trench gate IGBT is used as an example, but the structures of the embodiments 1 to 5 can be applied to both the planar gate IGBT and the MOS transistor, and can also be applied to various diodes such as the PN junction diode. In particular, if it is a planar gate IGBT and MOS transistor, the structure of the embodiment 5 is particularly effective, and the flatness of the metal layer 6 of the emitter peripheral electrode 3b is greatly improved.

[0103] In the above-described embodiments 1 to 5, the material of the semiconductor substrate 1 is not particularly limited, but the semiconductor substrate 1 may be silicon or SiC (silicon carbide), or a wide bandgap semiconductor other than silicon carbide, such as GaN (gallium nitride).

[0104] In particular, SiC has a dielectric breakdown strength that is about 10 times that of Si, and the thickness of the semiconductor layer can be reduced to about 1 / 10 of that of Si. Therefore, SiC semiconductor devices can achieve low on-state voltage. In addition, they can operate even at high temperatures, so SiC semiconductor devices can be smaller and more efficient than Si semiconductor devices.

[0105] Although the present invention has been described in detail, the above invention is in all aspects illustrative and the present invention is not limited thereto. It should be understood that numerous modifications not shown here are conceivable without departing from the scope of the present invention.

[0106] Furthermore, the present invention can freely combine the various embodiments within the scope of the invention, and can appropriately modify or omit the various embodiments.

Claims

1. A semiconductor device having a main current flowing in a thickness direction of a semiconductor substrate, In the semiconductor device, The semiconductor substrate has: an active region, in which the main current flows; and a terminal region further outward than the active region, The semiconductor device has: a first main electrode disposed on the active area; a second main electrode disposed on the semiconductor substrate on the opposite side to the first main electrode; a protective film covering at least the terminal region; as well as an electroless plating layer provided on the first main electrode not covered by the protective film, The first main electrode comprises: a central electrode in the central part; as well as a peripheral electrode disposed along the central electrode at a distance from the central electrode, The protective film is provided from the terminal region to the edge of the peripheral electrode. The central electrode and the peripheral electrode have: A first metal layer; and a second metal layer disposed on the first metal layer and comprising aluminum, At least the peripheral electrode has a hole portion that penetrates the second metal layer and reaches the first metal layer.

2. The semiconductor device according to claim 1, wherein The holes are holes formed by pitting formed by pre-treatment before forming the electroless plating layer.

3. The semiconductor device according to claim 2, wherein: The second metal layer is composed of an aluminum-silicon alloy, The silicon concentration of the second metal layer of the peripheral electrode is higher than the silicon concentration of the second metal layer of the central electrode.

4. The semiconductor device according to claim 1, wherein The hole portion is a selectively formed hole.

5. The semiconductor device according to claim 2, wherein: The central electrode has the hole portion, The thickness of the second metal layer of the central electrode is set to be thicker than the thickness of the second metal layer of the peripheral electrode and to be thick enough that the hole does not penetrate the second metal layer.

6. The semiconductor device according to claim 1, wherein The active region does not have a unit cell, which is the minimum unit structure of the semiconductor device, below the peripheral electrode.

7. The semiconductor device according to claim 1, wherein The distance between the central electrode and the peripheral electrode is set to be smaller than the thickness of the electroless plating layer.

8. The semiconductor device according to claim 2, wherein: The thickness of the second metal layer is set to be greater than or equal to 0.5 μm.

9. The semiconductor device according to claim 4, wherein: The thickness of the second metal layer of the central electrode and the thickness of the second metal layer of the peripheral electrode are set to be greater than or equal to 1.5 μm.

10. The semiconductor device according to claim 5, wherein The thickness of the second metal layer of the central electrode is set to be greater than or equal to 1.5 μm. The thickness of the second metal layer of the peripheral electrode is set to be greater than or equal to 0.5 μm.

Images