Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device

Abstract

The standard cell (C1) comprises a gate wiring (52), a dummy gate wiring (56), a pad (46), a nanosheet (24) and a dummy nanosheet (34), wherein the dummy gate wiring (56) is formed to be adjacent to the gate wiring (52) on the right side of the drawing in the X direction, the pad (46) is arranged between the gate wiring (52) and the dummy gate wiring (56), the nanosheet (24) is formed to overlap with the gate wiring (52) when viewed from above and is connected to the pad (46), and the dummy nanosheet (34) is formed to overlap with the dummy gate wiring (56) when viewed from above and is connected to the pad (46).

Description

Technical Field

[0001] The present disclosure relates to a layout structure of a semiconductor integrated circuit device including a standard cell (hereinafter referred to as a cell depending on the situation) using a nanosheet FET (Field Effect Transistor) and a method for manufacturing the same. Background Art

[0002] The standard cell method is a known method for forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell method refers to the following method, that is, basic cells (such as inverters, latches, flip-flops, full adders, etc.) with specific logical functions are prepared in advance as standard cells, and then multiple standard cells are arranged on the semiconductor substrate, and these standard cells are connected by wiring to design an LSI chip.

[0003] Transistors, the basic components of LSI, have achieved increased integration, lower operating voltage, and higher operating speed by reducing gate length (scaling). However, in recent years, the problem has arisen that excessive scaling will cause cutoff current, which in turn will cause a significant increase in power consumption. To solve this problem, people have begun to actively study three-dimensional transistors, that is, to change the transistor structure from the existing planar type to a three-dimensional type. Nanosheet FET (nanowire FET) is one of them that has attracted much attention.

[0004] Patent Document 1 discloses a layout structure of a semiconductor integrated circuit device in which dummy pads that do not contribute to the logic function of the circuit are arranged in a standard cell using a nanosheet FET.

[0005] Patent Document 1: International Publication No. 2018 / 025580 Summary of the invention

[0006] -Technical problem to be solved by the invention-

[0007] Patent document 1 discloses a nanosheet forming a channel portion of a nanosheet FET and a pad connected to both ends of the nanosheet and forming a source portion or a drain portion. However, in Patent document 1, a layout structure for suppressing performance deviation of a transistor formed in a standard cell and a manufacturing method thereof are not studied in detail.

[0008] The present disclosure aims to provide a layout structure of a semiconductor integrated circuit device and a method for manufacturing the same, which are used to suppress performance variations of transistors formed in a standard cell in a layout structure of a standard cell using a nanosheet FET.

[0009] -Technical solutions to technical problems-

[0010] The first aspect discloses a semiconductor integrated circuit device, comprising a first standard cell and a second standard cell, wherein the first standard cell and the second standard cell are arranged in a first direction. The first standard cell comprises a first gate wiring, a first dummy gate wiring, a first pad, a first nanosheet, and a first dummy nanosheet, wherein the first dummy gate wiring is formed to be adjacent to the first gate wiring on the second standard cell side of the first gate wiring located in the first direction, the first pad is arranged between the first gate wiring and the first dummy gate wiring, the first nanosheet is formed to overlap with the first gate wiring when viewed from above and is connected to the first pad, and the first dummy nanosheet is formed to overlap with the first dummy gate wiring when viewed from above and is connected to the first pad. The second standard cell comprises a second gate wiring, a second dummy gate wiring, and a second pad, wherein the second dummy gate wiring is formed to be adjacent to the second gate wiring on the first standard cell side of the second gate wiring located in the first direction and is formed to be adjacent to the first dummy gate wiring, and the second pad is arranged between the second gate wiring and the second dummy gate wiring.

[0011] According to the present disclosure, a first pad is provided between a first gate wiring and a first dummy gate wiring, and the first dummy gate wiring is formed to be adjacent to the first gate wiring on a second standard cell side of the first gate wiring located in a first direction. The first pad is connected to a first nanosheet and a first dummy nanosheet, and the first nanosheet is formed to overlap with the first gate wiring when viewed from above, and the first dummy nanosheet is formed to overlap with the first dummy gate wiring when viewed from above.

[0012] That is, the first pad is formed between the first nanosheet that functions as a channel portion and the first dummy nanosheet that does not function as a channel portion. Therefore, the first pad is formed by epitaxially growing the stacked semiconductor portion that forms the first nanosheet and the first dummy nanosheet. In this way, the first pad is formed in the same manner as the pad that is formed between the nanosheets that function as the channel portion. Therefore, since the deviation in the manufacturing accuracy of the transistor and the performance deviation of the transistor can be suppressed, the reliability and yield rate of the semiconductor integrated circuit device can be improved.

[0013] The second aspect discloses a semiconductor integrated circuit device, including a first standard cell and a second standard cell, wherein the first standard cell and the second standard cell are arranged adjacent to each other along a first direction. A first dummy gate wiring is formed at the cell boundary between the first standard cell and the second standard cell. The first standard cell includes a first gate wiring, a first pad, a first nanosheet, and a first dummy nanosheet, wherein the first gate wiring is formed to be adjacent to the first dummy gate wiring along the first direction, the first pad is arranged between the first dummy gate wiring and the first gate wiring, the first nanosheet is formed to overlap with the first gate wiring when viewed from above and is connected to the first pad, and the first dummy nanosheet is formed to overlap with the first dummy gate wiring when viewed from above and is connected to the first pad. The second standard cell includes a second gate wiring, a second pad, a second nanosheet and a second dummy nanosheet, the second gate wiring is formed to be adjacent to the first dummy gate wiring along the first direction, the second pad is arranged between the first dummy gate wiring and the second gate wiring, the second nanosheet is formed to overlap with the second gate wiring when viewed from above and is connected to the second pad, the second dummy nanosheet is formed to overlap with the first dummy gate wiring when viewed from above and is connected to the second pad and is formed to be separated from the first dummy nanosheet.

[0014] According to the present disclosure, a first dummy gate wiring is formed at the cell boundary of the first standard cell and the second standard cell arranged adjacent to each other along the first direction. The first pad is arranged between the first dummy gate wiring and the first gate wiring, and the first gate wiring is formed to be adjacent to the first dummy gate wiring along the first direction. The first pad is connected to the first nanosheet and the first dummy nanosheet, and the first nanosheet is formed to overlap with the first gate wiring when viewed from above, and the first dummy nanosheet is formed to overlap with the first dummy gate wiring when viewed from above. The second pad is arranged between the first dummy gate wiring and the second gate wiring, and the second gate wiring is formed to be adjacent to the first dummy gate wiring along the first direction. The second pad is connected to the second nanosheet and the second dummy nanosheet, and the second nanosheet is formed to overlap with the second gate wiring when viewed from above, and the second dummy nanosheet is formed to overlap with the first dummy gate wiring when viewed from above and is formed to be separated from the first dummy nanosheet.

[0015] That is, the first pad is formed between the first nanosheet that functions as a channel portion and the first dummy nanosheet that does not function as a channel portion. The second pad is formed between the second nanosheet that functions as a channel portion and the second dummy nanosheet that is separated from the first dummy nanosheet and does not function as a channel portion. Therefore, the first pad is formed by epitaxially growing the stacked semiconductor portion that forms the first nanosheet and the first dummy nanosheet. The second pad is formed by epitaxially growing the stacked semiconductor portion that forms the second nanosheet and the second dummy nanosheet. In this way, the first pad and the second pad are respectively formed in the same manner as the following pads, which are formed between the nanosheets that function as channel portions. Therefore, since the deviation in the manufacturing accuracy of the transistor and the performance deviation of the transistor can be suppressed, the reliability and yield of the semiconductor integrated circuit device can be improved.

[0016] Since the first standard cell and the second standard cell are adjacently arranged along the first direction, it is possible to reduce the area of ​​the semiconductor integrated circuit device.

[0017] The third aspect discloses a method for manufacturing a semiconductor integrated circuit device, the semiconductor integrated circuit device comprising a first standard cell and a second standard cell, the first standard cell and the second standard cell being arranged adjacent to each other along a first direction, the method for manufacturing the semiconductor integrated circuit device comprising the following steps: alternately stacking two different semiconductors on a semiconductor substrate to form a stacked semiconductor; forming a first sacrificial gate structure at a cell boundary between the first standard cell and the second standard cell on the upper part of the stacked semiconductor, forming a second sacrificial gate structure at a formation position of the first standard cell, and forming a third sacrificial gate structure at a formation position of the second standard cell; excluding the sacrificial gate structure formed between the first sacrificial gate structure and the second sacrificial gate structure and between the first sacrificial gate structure and the third sacrificial gate structure when viewed from above The stacked semiconductor between the first sacrificial gate structure, thereby forming a first stacked semiconductor part, a second stacked semiconductor part and a third stacked semiconductor part at the lower parts of the first sacrificial gate structure, the second sacrificial gate structure and the third sacrificial gate structure respectively; by epitaxially growing the first stacked semiconductor part and the second stacked semiconductor part, a first welding pad is formed between the first stacked semiconductor part and the second stacked semiconductor part, and by epitaxially growing the first stacked semiconductor part and the third stacked semiconductor part, a second welding pad is formed between the first stacked semiconductor part and the third stacked semiconductor part; removing the first sacrificial gate structure, the second sacrificial gate structure and the third sacrificial gate structure; removing a part or all of the second stacked semiconductor part to prevent the first welding pad and the second welding pad from being electrically connected through the second stacked semiconductor part.

[0018] According to the present disclosure, a first stacked semiconductor portion and a second stacked semiconductor portion are formed to be adjacent to each other in a first direction. The first stacked semiconductor portion and the third stacked semiconductor portion are formed to be adjacent to each other in a first direction. The first pad is formed by epitaxially growing the first stacked semiconductor portion and the second stacked semiconductor portion. The second pad is formed by epitaxially growing the side surface of the first stacked semiconductor portion and the third stacked semiconductor portion. Furthermore, a part or all of the first stacked semiconductor portion is removed to prevent the first pad from being electrically connected to the second pad.

[0019] That is, the first pad and the second pad are formed by epitaxially growing the stacked semiconductor portions that are formed to be adjacent to each other in the first direction. Therefore, the first pad and the second pad are formed in the same manner as the pad formed between the stacked semiconductor portions including the semiconductor layer that functions as the channel portion. Therefore, since the deviation in the manufacturing accuracy of the transistor and the performance deviation of the transistor can be suppressed, the reliability and yield of the semiconductor integrated circuit device can be improved.

[0020] -Effects of the Invention-

[0021] According to the present disclosure, a layout structure and a manufacturing method thereof can be realized, which are used to suppress performance variation of transistors formed in a standard cell in a layout structure of a standard cell using a nanosheet FET. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a plan view showing an example of the layout structure of the semiconductor integrated circuit device involved in the first embodiment;

[0023] Figure 2 is a cross-sectional view showing an example of the layout structure of a standard cell according to the first embodiment;

[0024] Figure 3 yes Figure 1 The circuit diagram of the standard cell C1 shown;

[0025] Figure 4 A diagram for explaining a method for manufacturing a semiconductor integrated circuit device according to a first embodiment;

[0026] Figure 5 A diagram for explaining a method for manufacturing a semiconductor integrated circuit device according to a first embodiment;

[0027] Figure 6 A diagram for explaining a method for manufacturing a semiconductor integrated circuit device according to a first embodiment;

[0028] Figure 7 A diagram for explaining a method for manufacturing a semiconductor integrated circuit device according to a first embodiment;

[0029] Figure 8 is a plan view showing another example of the layout structure of the standard cell involved in the first embodiment;

[0030] Fig. 9 is a plan view showing an example of a layout structure of a semiconductor integrated circuit device according to the second embodiment;

[0031] Fig.10 is a diagram for explaining a method for manufacturing a semiconductor integrated circuit device according to a second embodiment;

[0032] Fig.11 is a diagram for explaining a method for manufacturing a semiconductor integrated circuit device according to a second embodiment;

[0033] Fig.12 is a diagram for explaining a method for manufacturing a semiconductor integrated circuit device according to a second embodiment;

[0034] Fig.13 It is a diagram for explaining the method for manufacturing the semiconductor integrated circuit device according to the second embodiment. DETAILED DESCRIPTION

[0035] In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (hereinafter referred to as cells as appropriate), at least some of which include nanosheet FETs (Field Effect Transistors).

[0036] In this specification, a semiconductor layer portion formed at both ends of a nanosheet and constituting a terminal to be a source or a drain of a transistor is referred to as a "pad".

[0037] In the top view and cross-sectional view of the following embodiments, the illustration of each insulating film, etc. may be omitted. In the top view and cross-sectional view of the following embodiments, the nanosheet and the pads on both sides thereof may be shown in simplified linear shapes. In this specification, expressions such as "same size" and the like, which mean the same size, etc., include the range of deviation in manufacturing.

[0038] In this specification, the source and drain of a transistor are referred to as "nodes" of the transistor as appropriate. That is, one node of a transistor refers to the source or drain of the transistor, and two nodes of a transistor refer to the source and drain of the transistor.

[0039] In the following embodiments, "VDD" or "VSS" is used to indicate a voltage or a power source itself.

[0040] In the following embodiments and their modifications, the same components and the like are denoted by the same reference numerals and their description may be omitted.

[0041] (First Embodiment)

[0042] Figure 1 and Figure 2 is a diagram showing an example of a layout structure of a semiconductor integrated circuit device according to the first embodiment, Figure 1 It is a top view. Figure 2 is a top view of a longitudinal section. Specifically, Figure 2 is along Figure 1 The cross section is shown along the CC' line.

[0043] It should be noted that in the following description, Figure 1 In the top view, the horizontal direction of the drawing is set as the X direction, the vertical direction of the drawing is set as the Y direction, and the direction perpendicular to the substrate surface is set as the Z direction. Figure 1 In the plan view, the solid line shown so as to surround the cell indicates the cell frame (the outer edge of the standard cell C1 and the filling cell CF).

[0044] exist Figure 1 In the figure, a plurality of standard cells are arranged along the X direction to form a cell column. Specifically, a filling cell CF is arranged between the standard cells C1. It should be noted that the standard cell C1 arranged on the left side of the figure is sometimes referred to as a standard cell C1a, and the standard cell C1 arranged on the right side of the figure is sometimes referred to as a standard cell C1b.

[0045] The standard cell C1 includes a nanosheet FET and has a logic function (a two-input NAND circuit). The filled cell CF does not include a nanosheet FET and has no logic function.

[0046] In the present disclosure, a cell having a logic function such as a NAND gate or a NOR gate in the cell, like the standard cell C1, is referred to as a "logic cell" as appropriate. A cell that does not contribute to the logic function of a circuit block because it does not have a logic function and is arranged between logic cells, like the filler cell CF, is referred to as a "filler cell" as appropriate.

[0047] In the present disclosure, the standard cell C1 and the like include nanosheets that function as a channel portion of a transistor and nanosheets that do not function as a channel portion of a transistor. In particular, a nanosheet that does not function as a channel portion of a transistor is referred to as a "dummy nanosheet."

[0048] In the present disclosure, the standard cell C1 and the like include gate wirings that form transistors and gate wirings that do not form transistors. In particular, gate wirings that do not form transistors are referred to as "dummy gate wirings."

[0049] like Figure 1 and Figure 2As shown, in the standard cell C1 and the filling cell CF, an N-well region 1 extending in the X-direction and the Y-direction is formed from the center in the Y-direction to the upper end of the figure. In the standard cell C1 and the filling cell CF, power wirings 11 and 12 extending in the X-direction are respectively provided at both ends in the Y-direction. Both the power wirings 11 and 12 are buried power wirings (BPR: Buried Power Rail) formed in the buried wiring layer. The power wiring 11 is formed in the N-well region 1 and supplies the power voltage VDD. The power wiring 12 supplies the power voltage VSS.

[0050] Figure 3 yes Figure 1 The circuit diagram of the standard cell C1 is shown in FIG. Figure 3 As shown, in the standard cell C1, transistors P1, P2, N1, and N2 are provided to form a two-input NAND circuit with inputs A and B and output Y.

[0051] (Configuration of Standard Cell C1)

[0052] The following takes the standard cell C1a as an example to illustrate the structure of the standard cell C1. Figure 1 In the figure, the nanosheets 25, 26, dummy nanosheets 35, 36, pads 47 to 50, gate wiring 53, dummy gate wiring 57 and transistors P3, N3 of the standard cell C1b are respectively equivalent to the nanosheets 21, 23, dummy nanosheets 31, 33, pads 41, 42, 44, 45, gate wiring 51, dummy gate wiring 55 and transistors P1, N1 of the standard cell C1 (C1a).

[0053] In the standard cell C1, sheet-like nanosheets 21 to 24 and sheet-like dummy nanosheets 31 to 34 extending in the X direction and the Y direction are formed on the upper layer of the power supply wirings 11 and 12. The nanosheets 21 and 22 and the dummy nanosheets 31 and 32 are arranged in the X direction. The nanosheets 23 and 24 and the dummy nanosheets 33 and 34 are arranged in the X direction.

[0054] Nanosheets 21 and 23 overlap with gate wiring 51 in plan view. Nanosheets 22 and 24 overlap with gate wiring 52 in plan view. Dummy nanosheets 31 and 33 overlap with dummy gate wiring 55 in plan view. Dummy nanosheets 32 and 34 overlap with dummy gate wiring 56 in plan view.

[0055] The dummy nanosheets 31 and 33 extend from the right end of the dummy gate wiring 55 in the figure to the center of the dummy gate wiring 55 in the figure (near the cell frame on the left side of the standard cell C1 in the figure). The dummy nanosheets 32 and 34 extend from the left end of the dummy gate wiring 56 in the figure to the center of the dummy gate wiring 56 in the figure (near the cell frame on the right side of the standard cell C1 in the figure).

[0056] Pads 41 to 43 doped with P-type semiconductor are formed between dummy nanosheet 31 and nanosheet 21, between nanosheets 21 and 22, and between nanosheet 22 and dummy nanosheet 32. Pads 44 to 46 doped with N-type semiconductor are formed between dummy nanosheet 33 and nanosheet 23, between nanosheets 23 and 24, and between nanosheet 24 and dummy nanosheet 34.

[0057] Nanosheets 21 to 24 constitute the channel portions of transistors P1, P2, N1, and N2, respectively. Pads 41 and 42 constitute the node of transistor P1. Pads 42 and 43 constitute the node of transistor P2. Pads 44 and 45 constitute the node of transistor N1. Pads 45 and 46 constitute the node of transistor N2.

[0058] In the standard cell C1, gate wirings 51, 52 and dummy gate wirings 55, 56 extending in the Y direction and the Z direction are formed. The dummy gate wirings 55, 56 are arranged at both ends of the standard cell C1 in the X direction. The dummy gate wiring 55, the gate wirings 51, 52, and the dummy gate wiring 56 are arranged at equal center spacings in the X direction. The gate wiring 51 forms the gates of the transistors P1, N1, and the gate wiring 52 forms the gates of the transistors P2, N2.

[0059] That is, the nanosheet 21, the pads 41, 42, and the gate wiring 51 constitute the transistor P1. The nanosheet 22, the pads 42, 43, and the gate wiring 52 constitute the transistor P2. The nanosheet 23, the pads 44, 45, and the gate wiring 51 constitute the transistor N1. The nanosheet 24, the pads 45, 46, and the gate wiring 52 constitute the transistor N2.

[0060] like Figure 2 As shown, nanosheets 22 and 24 are respectively composed of two sheet-like semiconductor layers (nanosheets). For each nanosheet 22 and 24, the two nanosheets are arranged to overlap when viewed from above and separated along the Z direction. Nanosheets 21, 23 and dummy nanosheets 31 to 34 have the same structure as nanosheets 22 and 24, and are omitted from the illustration. That is, transistors P1, P2, N1, and N2 each include two nanosheets.

[0061] like Figure 1 As shown, local wirings 61 to 65 extending in the Y direction are formed on the upper layer of the pads 41 to 46. The local wiring 61 is connected to the pad 41. The local wiring 62 is connected to the pad 42. The local wiring 63 is connected to the pads 43 and 46. The local wiring 64 is connected to the pad 44. The local wiring 65 is connected to the pad 45.

[0062] The local wiring 62 extends to overlap with the power wiring 11 in plan view and is connected to the power wiring 11 through the contact hole 71. The local wiring 64 extends to overlap with the power wiring 12 in plan view and is connected to the power wiring 12 through the contact hole 72.

[0063] In the first metal wiring layer above the local wirings 61 to 65, wirings 81 to 83 extending in the X direction are formed. Wiring 81 is connected to the local wiring 61 through a contact hole 91, and is connected to the local wiring 63 through a contact hole 92. Wiring 82 is connected to the gate wiring 52 through a contact hole 93. Wiring 83 is connected to the gate wiring 51 through a contact hole 94. It should be noted that wirings 81 to 83 are respectively equivalent to Figure 3 The output Y and input A and B in.

[0064] As described above, nanosheets 21 to 24 function as the channel portions of transistors P1, P2, N1, and N2, respectively. On the other hand, one end of dummy nanosheets 31 to 34 is connected to pads 41, 43, 44, and 46, respectively, and the other end is not connected to the pad. Therefore, dummy nanosheets 31 to 34 do not function as the channel portions of transistors.

[0065] Here, pad 42 is formed between nanosheets 21 and 22, and pad 45 is formed between nanosheets 23 and 24. On the other hand, pad 41 is formed between dummy nanosheet 31 and nanosheet 21, pad 43 is formed between nanosheet 22 and dummy nanosheet 32, pad 44 is formed between dummy nanosheet 33 and nanosheet 23, and pad 46 is formed between nanosheet 24 and dummy nanosheet 34. That is, pads 42 and 45 are formed between nanosheets that function as channel portions. On the other hand, pads 41, 43, 44, and 46 are formed between a nanosheet that functions as a channel portion and a dummy nanosheet that does not function as a channel portion. Therefore, in standard cell C1, pads formed between nanosheets that function as channel portions and pads formed between a nanosheet that functions as a channel portion and a dummy nanosheet that does not function as a channel portion are included.

[0066] It should be noted that, as described above, the standard cell C1b is also constructed in the same manner as the standard cell C1a. That is, the transistor P3 is composed of the nanosheet 25, the pads 47, 48, and the gate wiring 53. The transistor N3 is composed of the nanosheet 26, the pads 49, 50, and the gate wiring 53. The pad 47 is formed between the nanosheet 25 that functions as the channel portion of the transistor P3 and the dummy nanosheet 35 that does not function as the channel portion of the transistor. The pad 49 is formed between the nanosheet 26 that functions as the channel portion of the transistor N3 and the dummy nanosheet 36 that does not function as the channel portion of the transistor.

[0067] (Configuration of Filling Cell CF)

[0068] like Figure 1 As shown, the filling cell CF is arranged between the standard cells C1a and C1b.

[0069] At both ends of the filling cell CF in the X direction, dummy gate wirings 56 and 57 are formed. The filling cell CF shares the dummy gate wiring 56 with the standard cell C1a and shares the dummy gate wiring 57 with the standard cell C1b. It should be noted that the filling cell CF does not include the dummy nanosheets 32 and 34 of the standard cell C1a and the dummy nanosheets 35 and 36 of the standard cell C1b.

[0070] In the center portion of the filling cell CF in the X direction, local wirings 66 and 67 extending in the Y direction are formed. The local wirings 66 and 67 are formed in the same layer as the local wirings 61 to 65 .

[0071] (Regarding the Manufacturing Method of the Semiconductor Integrated Circuit Device According to the First Embodiment)

[0072] Refer to the following Figures 4 to 7 , a method for manufacturing a semiconductor integrated circuit device is described. Specifically, Figures 4 to 7 Shown along Figure 1 The cross section taken along the line X1-X1'.

[0073] First, if Figure 4 As shown in (a), a stacked semiconductor 200 is formed on a semiconductor substrate 100. The stacked semiconductor 200 is formed by alternately stacking semiconductor layers 210 and sacrificial semiconductor layers 220. The semiconductor layers 210 and the sacrificial semiconductor layers 220 are made of different semiconductor materials. For example, the semiconductor material is silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors.

[0074] Here, the material of the semiconductor layer 210 is silicon (Si), and the material of the sacrificial semiconductor layer 220 is silicon-germanium alloy (SiGe). Silicon (Si) and silicon-germanium alloy (SiGe) are alternately stacked by epitaxial growth on the semiconductor substrate 100, thereby realizing a stacked structure of the stacked semiconductor 200. The epitaxial growth is realized by methods such as rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE).

[0075] Then, if Figure 4 As shown in (b), the stacked semiconductor 200 is patterned. The patterning is performed by known photolithography and etching. In this way, a stacked semiconductor portion 201 is formed on the left side of the figure, and a stacked semiconductor portion 202 is formed on the right side of the figure.

[0076] Then, if Figure 5 As shown in (a), sacrificial gate structures 301 to 304 are formed on the semiconductor substrate 100 and on the upper portions of the stacked semiconductor portions 201 and 202. Specifically, the sacrificial gate structures 301 to 304 are formed on Figure 1 The gate wiring 52, dummy gate wirings 56, 57 and gate wiring 53 are formed at the positions. The sacrificial gate structures 302, 303 are formed to cover the side surface of the stacked semiconductor portion 201 on the right side of the drawing and the side surface of the stacked semiconductor portion 202 on the left side of the drawing, respectively.

[0077] The sacrificial gate structures 301-304 are made of, for example, polycrystalline silicon, amorphous silicon, metal (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), or alloys made of various metals. The sacrificial gate structures 301-304 may be structures formed by forming the above materials into layers. Spacers may be formed on the surfaces of the sacrificial gate structures 301-304 using insulating materials such as silicon oxide and silicon nitride.

[0078] The sacrificial gate structures 301 to 304 are formed by methods such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), etc. The sacrificial gate structures 301 to 304 are formed at predetermined positions by known photolithography and etching.

[0079] Then, if Figure 5 As shown in (b), the stacked semiconductor portions 201 and 202 other than the portions covered by the sacrificial gate structures 301 to 304 are removed. Specifically, the stacked semiconductor portions 201 and 202 other than the portions covered by the sacrificial gate structures 301 to 304 are removed by anisotropic etching such as reactive ion etching (RIE). In this way, stacked semiconductor portions 203 to 206 respectively covered by the sacrificial gate structures 301 to 304 are formed on the semiconductor substrate 100. It should be noted that in the following description, the semiconductor layers respectively included in the stacked semiconductor portions 203 to 206 are referred to as semiconductor layers 213 to 216, and the sacrificial semiconductor layers respectively included in the stacked semiconductor portions 203 to 206 are referred to as sacrificial semiconductor layers 223 to 226.

[0080] Here, the side surfaces of the stacked semiconductor portions 203 and 206 are exposed on both sides of the drawing. On the other hand, the side surface of the stacked semiconductor portion 204 on the left side of the drawing is exposed, and the side surface on the right side of the drawing is covered by the sacrificial gate structure 302. The side surface of the stacked semiconductor portion 205 on the left side of the drawing is covered by the sacrificial gate structure 303, and the side surface on the right side of the drawing is exposed.

[0081] Then, if Figure 6 As shown in (a), an insulating film 401 as a spacer is formed on the semiconductor substrate 100. Specifically, the insulating film 401 is formed to cover the upper surface of the semiconductor substrate 100 that is not covered by the sacrificial gate structures 301 to 304 and the stacked semiconductor parts 203 to 206. The material of the insulating film 401 is, for example, silicon oxide, silicon nitride, etc. The insulating film 401 can be formed by known film formation and etching.

[0082] Then, if Figure 6 As shown in (b), pads 501 to 504 are formed. Specifically, pads 501 to 504 are formed by epitaxially growing stacked semiconductor portions 203 to 206. It should be noted that pads 501 to 504 correspond to Figure 1 The pads 45, 46, 49, 50 in the figure.

[0083] More specifically, the pad 501 is formed on the left side of the stacked semiconductor portion 203 in the drawing with the exposed portion of the stacked semiconductor portion 203 (the side surface on the left side of the drawing) as the base point. The pad 502 is formed between the stacked semiconductor portions 203 and 204 with the exposed portion of the stacked semiconductor portion 203 (the side surface on the right side of the drawing) and the exposed portion of the stacked semiconductor portion 204 (the side surface on the left side of the drawing) as the base point. The pad 503 is formed between the stacked semiconductor portions 205 and 206 with the exposed portion of the stacked semiconductor portion 205 (the side surface on the right side of the drawing) and the exposed portion of the stacked semiconductor portion 206 (the side surface on the left side of the drawing) as the base point. The pad 504 is formed on the right side of the stacked semiconductor portion 206 in the drawing with the exposed portion of the stacked semiconductor portion 206 (the side surface on the right side of the drawing) as the base point.

[0084] Here, since the side surface of the stacked semiconductor portion 204 on the right side of the drawing and the side surface of the stacked semiconductor portion 205 on the left side of the drawing are respectively covered by the sacrificial gate structures 302 and 303 , no pad is formed between the sacrificial gate structures 302 and 303 .

[0085] The epitaxial growth for forming the pads 501 to 504 uses a semiconductor material with impurities added. The semiconductor material is, for example, silicon. The impurities (semiconductors) added to the semiconductor material are as follows: P-type semiconductors are, for example, boron, aluminum, gallium, and indium, and N-type semiconductors are, for example, antimony, arsenic, and phosphorus.

[0086] Insulating film 402 is formed on pads 501 to 504. Insulating film 403 is formed between sacrificial gate structures 302 and 303. Materials of insulating films 402 and 403 are, for example, silicon dioxide, silicate glass, etc. Insulating films 402 and 403 are formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, etc.

[0087] Then, if Figure 7 As shown in (a), the sacrificial gate structures 301 to 304 and the sacrificial semiconductor layers 223 to 226 are removed. Specifically, the sacrificial gate structures 301 to 304 are removed by known etching. Furthermore, the sacrificial semiconductor layers 223 to 226 are selectively removed (etched) from the stacked semiconductor portions 203 to 206, respectively, so that the semiconductor layers 213 to 216 remain on the semiconductor substrate 100. It should be noted that the semiconductor layers 213 to 216 are respectively equivalent to Figure 1 and Figure 2 The nanosheet 24, the dummy nanosheets 34, 36 and the nanosheet 26 in FIG.

[0088] Then, if Figure 7As shown in (b), gate oxide films 601 to 604 and gate wirings 701 to 704 are formed in the portions where the sacrificial gate structures 301 to 304 and the sacrificial semiconductor layers 223 to 226 are removed.

[0089] Specifically, the gate oxide film 601 is formed to cover the side of the insulating film 402, the side of the pad 501 on the right side of the drawing, the side of the pad 502 on the left side of the drawing, and the surface of the semiconductor layer 213 ( Figure 7 (b) shows the upper and lower surfaces of the semiconductor layer 213) and the upper surface of the semiconductor substrate 100. The gate oxide film 602 is formed to cover the side of the insulating film 402, the side of the pad 502 on the right side of the drawing, the side of the insulating film 403 on the left side of the drawing, the surface of the semiconductor layer 214 ( Figure 7 (b) shows the upper surface, lower surface and side surface on the right side of the drawing of the semiconductor layer 214) and the upper surface of the semiconductor substrate 100. The gate oxide film 603 is formed to cover the side surface of the insulating film 402, the side surface on the right side of the drawing of the pad 403, the side surface on the left side of the drawing of the pad 503, the surface of the semiconductor layer 215 ( Figure 7 (b) shows the upper surface, lower surface and side surface on the left side of the semiconductor layer 215) and the upper surface of the semiconductor substrate 100. The gate oxide film 604 is formed to cover the side surface of the insulating film 402, the side surface on the right side of the pad 503, the side surface on the left side of the pad 504, the surface of the semiconductor layer 216 ( Figure 7 (b) shows the upper and lower surfaces of the semiconductor layer 216 and the upper surface of the semiconductor substrate 100 .

[0090] Gate oxide films 601-604 are, for example, silicon oxide films, silicon nitride oxide films, or HighK films (films formed using materials with a higher dielectric constant than silicon oxide). Gate oxide films 601-604 are formed by, for example, chemical vapor deposition, plasma chemical vapor deposition, physical vapor deposition, sputtering, atomic layer deposition, or the like.

[0091] Furthermore, gate wirings 701 to 704 are formed on the semiconductor substrate 100. Specifically, the gate wiring 701 is formed between the pads 501 and 502. The gate wiring 702 is formed between the pad 502 and the insulating film 403. The gate wiring 703 is formed between the insulating film 403 and the pad 503. The gate wiring 704 is formed between the pads 503 and 504. It should be noted that the gate wirings 701 to 704 correspond to Figure 1 and Figure 2 The gate wiring 52, dummy gate wirings 56, 57 and gate wiring 53 are provided.

[0092] The gate wirings 701 to 704 are formed of polysilicon, metals such as tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, platinum, or alloys thereof, etc. The gate wirings 701 to 704 are formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, or the like.

[0093] Through the above manufacturing method, transistors N2 and N3 are formed near the boundary between the adjacent standard cells Cia and C1b and the filling cell CF. Figure 7 (b) Then, vias and local wiring are formed on the upper layer of the transistors by known techniques to achieve connections between the transistors.

[0094] According to the above configuration, the standard cells C1a and C1b are arranged along the X direction. The standard cell C1a includes a gate wiring 52, a dummy gate wiring 56, a pad 46, a nanosheet 24, and a dummy nanosheet 34. The dummy gate wiring 56 is formed to be adjacent to the gate wiring 52 on the right side of the drawing (the standard cell C1b side) in the X direction. The pad 46 is provided between the gate wiring 52 and the dummy gate wiring 56. The nanosheet 24 is formed to overlap with the gate wiring 52 in a plan view and is connected to the pad 46. The dummy nanosheet 34 is formed to overlap with the dummy gate wiring 56 in a plan view and is connected to the pad 46. The standard cell C1b includes a gate wiring 53, a dummy gate wiring 57, and a pad 49. The dummy gate wiring 57 is formed to be adjacent to the gate wiring 53 on the left side of the drawing (the standard cell C1a side) located in the X direction and is formed to be adjacent to the dummy gate wiring 56. The pad 49 is provided between the dummy gate wiring 57 and the gate wiring 53.

[0095] At the right end of the standard cell C1a in the attached figure, a pad 46 is formed between the nanosheet 24 that functions as a channel portion and the dummy nanosheet 34 that does not function as a channel portion. The pad 46 is formed by epitaxially growing the stacked semiconductor portion that forms the nanosheet 24 and the dummy nanosheet 34. On the other hand, the pads (for example, pads 45, etc.) formed between the nanosheets that function as the channel portion are formed by epitaxially growing from the stacked semiconductor portion formed on both sides of the X direction. That is, the pad formed at the end (right end) of the standard cell C1 in the X direction and the pad formed between the nanosheets that function as the channel portion are formed in the same manner. In this way, the shape deviation of the above-mentioned pad can be suppressed. Therefore, since the deviation in the manufacturing accuracy of the transistor and the performance deviation of the transistor can be suppressed, the reliability and yield of the semiconductor integrated circuit device can be improved.

[0096] The standard cell C1 b includes a nanosheet 26 and a dummy nanosheet 36 . The nanosheet 26 is formed to overlap with the gate wiring 53 in a plan view and is connected to the pad 49 . The dummy nanosheet 36 is formed to overlap with the dummy gate wiring 57 in a plan view and is connected to the pad 49 .

[0097] At the left end of the standard cell C1b in the attached figure, a pad 49 is formed between the nanosheet 26 that functions as a channel portion and the dummy nanosheet 36 that does not function as a channel portion. The pad 49 is formed by epitaxially growing the stacked semiconductor portion that forms the nanosheet 26 and the dummy nanosheet 36. On the other hand, the pads (for example, pads 50, etc.) formed between the nanosheets that function as the channel portion are formed by epitaxially growing from the stacked semiconductor portion formed on both sides of the X direction. That is, the pad formed at the end (left end) of the standard cell C1 in the X direction and the pad formed between the nanosheets that function as the channel portion are formed in the same manner. In this way, the shape deviation of the above-mentioned pad can be suppressed. Therefore, since the deviation in the manufacturing accuracy of the transistor and the performance deviation of the transistor can be suppressed, the reliability and yield of the semiconductor integrated circuit device can be improved.

[0098] It should be noted that part or all of the local wirings 66 and 67 may not be formed in the filler cell CF.

[0099] Figure 8 1 is a top view showing another example of the layout structure of the standard cell involved in the first embodiment. Specifically, in the standard cell C2, compared with the standard cell C1, local wirings 68a and 69a extending in the X direction are formed at the left end of the figure, and local wirings 68b and 69b extending in the X direction are formed at the right end of the figure. The local wirings 68a, 68b, 69a, and 69b are formed in the same layer as the local wirings 61 to 65.

[0100] By Figure 8 The standard cells C2 are arranged adjacent to each other along the X direction to form Figure 1 The same semiconductor integrated circuit device and the same layout structure. Specifically, the local wirings 68b and 69b of the standard cell C2 arranged on the left and the local wirings 68a and 69a of the standard cell C2 arranged on the right are shared. In this way, the same effect can be obtained.

[0101] (Second Embodiment)

[0102] Fig. 9 FIG. 2 is a plan view showing an example of the layout structure of the semiconductor integrated circuit device according to the second embodiment. Fig. 9In the figure, two standard cells C3 are arranged adjacent to each other along the X direction. Like the standard cell C1, a two-input "NAND" circuit is formed in the standard cell C3. Sometimes the standard cell C3 arranged on the left side of the figure is called the standard cell C3a, and the standard cell C3 arranged on the right side of the figure is called the standard cell C3b. The nanosheets 25, 26, dummy nanosheets 35a, 36a, pads 47 to 50, gate wiring 53, dummy gate wiring 56a and transistors P3 and N3 of the standard cell C3b are respectively equivalent to the nanosheets 21, 23, dummy nanosheets 31a, 33a, pads 41, 42, 44, 45, gate wiring 51, dummy gate wiring 55a and transistors P1 and N1 of the standard cell C3 (C3a).

[0103] Specifically, standard cell C3a and standard cell C3b share dummy gate wiring 56a formed on the right end of standard cell C3a in the figure. Standard cell C3a and standard cells arranged on the left side of standard cell C3a in the figure share dummy gate wiring 55a formed on the left end of standard cell C3a in the figure, which is omitted in the figure.

[0104] In the standard cell C3a, dummy nanosheets 32a and 34a are formed at the right end of the figure. The dummy nanosheets 32a and 34a are connected to the pads 43 and 46, respectively. The dummy nanosheets 32a and 34a extend from the left end of the figure of the dummy gate wiring 56a toward the right side of the figure. The dummy nanosheets 32a and 34a overlap with the dummy gate wiring 56a when viewed from above.

[0105] In the standard cell C3b, dummy nanosheets 35a and 36a are formed at the left end of the figure. The dummy nanosheets 35a and 36a are connected to the pads 47 and 49, respectively. The dummy nanosheets 35a and 36a extend from the right end of the dummy gate wiring 56a in the figure toward the left side of the figure. The dummy nanosheets 35a and 36a overlap with the dummy gate wiring 56a in a top view.

[0106] The dummy nanosheets 32a and 35a are separated along the X direction so as not to be electrically connected to each other. The dummy nanosheets 34a and 36a are separated along the X direction so as not to be electrically connected to each other.

[0107] In the standard cell C3a, dummy nanosheets 31a and 33a are formed at the left end of the figure. The dummy nanosheets 31a and 33a are connected to the pads 41 and 44, respectively. The dummy nanosheets 31a and 33a extend from the right end of the figure of the dummy gate wiring 55a toward the left side of the figure. The dummy nanosheets 31a and 33a overlap with the dummy gate wiring 55a when viewed from above. The dummy nanosheets 31a and 33a are respectively formed not to be electrically connected to the following dummy nanosheets, which are dummy nanosheets arranged to overlap with the dummy gate wiring 55a of the standard cell arranged on the left side of the figure of the standard cell C3a, and are omitted from the figure.

[0108] (Regarding the Manufacturing Method of the Semiconductor Integrated Circuit Device According to the Second Embodiment)

[0109] Refer to the following Figure 10 to Figure 13 , a method for manufacturing a semiconductor integrated circuit device is described. Specifically, Figure 10 to Figure 13 Show Fig. 9 A cross section taken along line X2-X2'.

[0110] First, if Fig.10 As shown in (a), a stacked semiconductor 230 is formed on a semiconductor substrate 100. The stacked semiconductor 230 is formed by alternately stacking semiconductor layers 240 and sacrificial semiconductor layers 250. The semiconductor layers 240 and sacrificial semiconductor layers 250 are made of different semiconductor materials. Specifically, the semiconductor layers 240 and sacrificial semiconductor layers 250 are made of the same materials as the semiconductor layers 210 and the sacrificial semiconductor layers 220. Figure 4 (a) Using the same method, a stacked semiconductor 230 is formed on the semiconductor substrate 100 .

[0111] It should be noted that in Fig.10 (a) After that, the stacked semiconductor 230 is patterned (not shown). The patterning is performed by known photolithography and etching.

[0112] Then, if Fig.10 As shown in (b), sacrificial gate structures 311 to 313 are formed on the stacked semiconductor 230. Specifically, the sacrificial gate structures 311 to 313 are formed on Fig. 9 The gate wiring 52, the dummy gate wiring 56a and the gate wiring 53 are formed at the positions of the gate wiring 52, the dummy gate wiring 56a and the gate wiring 53. The sacrificial gate structures 311 to 313 are made of the same material as the sacrificial gate structures 301 to 304. Figure 5 (a) In the same manner, sacrificial gate structures 311 to 313 are formed at predetermined positions of the stacked semiconductor 230 .

[0113] Then, as shown in FIG. J1(a), the stacked semiconductor 230 except for the portion covered by the sacrificial gate structures 311 to 313 is removed. Fig.11 (a) by Figure 5 (b) The stacked semiconductor 230 is removed in the same manner. In this way, stacked semiconductor portions 231 to 233 covered with sacrificial gate structures 311 to 313 are formed on the semiconductor substrate 100 .

[0114] Here, the left and right side surfaces of each of the stacked semiconductor portions 231 to 233 are exposed. The semiconductor layers included in the stacked semiconductor portions 231 to 233 are semiconductor layers 241 to 243. The sacrificial semiconductor layers included in the stacked semiconductor portions 231 to 233 are sacrificial semiconductor layers 251 to 253.

[0115] Then, if Fig.11 As shown in (b), an insulating film 411 is formed as a spacer on the semiconductor substrate 100. Specifically, the insulating film 411 is formed to cover the upper surface of the semiconductor substrate 100 that is not covered by the sacrificial gate structures 311 to 313 and the stacked semiconductor portions 231 to 233. The insulating film 411 is formed of the same material as the insulating film 401. Fig.11 (b) by Figure 6 (a) In the same manner, an insulating film 411 is formed.

[0116] Then, if Fig.12 As shown in (a), pads 511 to 514 are formed. Specifically, the pads 511 to 514 are formed by epitaxially growing the stacked semiconductor portions 231 to 233. Fig.12 (a), use Figure 6 (b) The same material is used for epitaxial growth. It should be noted that the pads 511 to 514 are respectively equivalent to Fig. 9 The pads 45, 46, 49, 50 in the figure.

[0117] More specifically, the pad 511 is formed on the left side of the stacked semiconductor portion 231 in the drawing with the exposed portion of the stacked semiconductor portion 231 (the side surface on the left side of the drawing) as the base point. The pad 512 is formed between the stacked semiconductor portions 231 and 232 with the exposed portion of the stacked semiconductor portion 231 (the side surface on the right side of the drawing) and the exposed portion of the stacked semiconductor portion 232 (the side surface on the left side of the drawing) as the base point. The pad 513 is formed between the stacked semiconductor portions 232 and 233 with the exposed portion of the stacked semiconductor portion 232 (the side surface on the right side of the drawing) and the exposed portion of the stacked semiconductor portion 233 (the side surface on the left side of the drawing) as the base point. The pad 514 is formed on the right side of the stacked semiconductor portion 233 in the drawing with the exposed portion of the stacked semiconductor portion 233 (the side surface on the right side of the drawing) as the base point.

[0118] Furthermore, an insulating film 412 is formed on the upper portions of the pads 511 to 514. The insulating film 412 is made of the same material as the insulating film 402. Figure 6 (b) formed by the same method.

[0119] Then, if Fig.12 As shown in (b), the sacrificial gate structures 311 to 313 and a portion of the stacked semiconductor portion 232 are removed. Specifically, the sacrificial gate structures 311 to 313 are removed by known etching. Then, a portion other than the center portion in the X direction of the stacked semiconductor portion 232 is masked, and the center portion in the X direction of the stacked semiconductor portion 232 is removed by anisotropic etching.

[0120] Here, the central portion of the stacked semiconductor portion 232 is removed so that the left and right ends are slightly left. It should be noted that in the following description, in the stacked semiconductor portion 232, the remaining portion on the left side of the drawing (the portion in contact with the pad 512) is referred to as the stacked semiconductor portion 234, and the remaining portion on the right side of the drawing (the portion in contact with the pad 513) is referred to as the stacked semiconductor portion 235. The semiconductor layers respectively included in the stacked semiconductor portions 234 and 235 are referred to as semiconductor layers 244 and 245, and the sacrificial semiconductor layers respectively included in the stacked semiconductor portions 234 and 235 are referred to as sacrificial semiconductor layers 254 and 255.

[0121] Then, if Fig.13 As shown in (a), the sacrificial semiconductor layers 251, 253 to 255 are removed. Specifically, the sacrificial semiconductor layers 251, 253 to 255 are selectively removed (etched) from the stacked semiconductor portions 231, 233 to 235, respectively, so that the semiconductor layers 241, 243 to 245 remain on the semiconductor substrate 100. It should be noted that the semiconductor layers 241, 243 to 245 are equivalent to Fig. 9 The nanosheets 24, 26 and the dummy nanosheets 34a, 36a in FIG.

[0122] Then, if Fig.13 As shown in (b), gate oxide films 611 to 613 and gate wirings 711 to 713 are formed on portions where a portion of the stacked semiconductor portion 232 , the sacrificial gate structures 311 to 313 , and the sacrificial semiconductor layers 251 , 253 to 255 are removed.

[0123] Specifically, the gate oxide film 611 is formed to cover the side of the insulating film 412, the side of the pad 511 on the right side of the drawing, the side of the pad 512 on the left side of the drawing, the surface of the semiconductor layer 241 ( Fig.13(b) shows the upper and lower surfaces of the semiconductor layer 241) and the upper surface of the semiconductor substrate 100. The gate oxide film 612 is formed to cover the side of the insulating film 412, the side of the pad 512 on the right side of the drawing, the side of the pad 513 on the left side of the drawing, the surface of the semiconductor layer 244 ( Fig.13 (b) shows the upper surface, lower surface and side surface on the right side of the drawing of the semiconductor layer 244), the upper surface, lower surface and side surface on the left side of the drawing of the semiconductor layer 245, and the upper surface of the semiconductor substrate 100. The gate oxide film 613 is formed to cover the side surface of the insulating film 412, the side surface on the right side of the drawing of the pad 513, the side surface on the left side of the drawing of the pad 514, the surface of the semiconductor layer 243 ( Fig.13 (b) shows the upper and lower surfaces of the semiconductor layer 243 and the upper surface of the semiconductor substrate 100.

[0124] The gate oxide films 611 to 613 are made of the same material as the gate oxide films 601 to 604. Fig.13 (b) by Figure 7 (b) In the same manner, gate oxide films 611 to 613 are formed.

[0125] Furthermore, gate wirings 711 to 713 are formed on semiconductor substrate 100. Specifically, gate wiring 711 is formed between pads 511 and 512. Gate wiring 712 is formed between pads 512 and 513. Gate wiring 713 is formed between pads 513 and 514. Gate wirings 711 to 713 are made of the same material as gate wirings 701 to 704. Fig.13 (b) by Figure 7 (b) The gate wirings 711 to 713 are formed in the same manner. It should be noted that the gate wirings 711 to 713 are respectively equivalent to Figure 1 and Figure 2 The gate wiring 52, the dummy gate wiring 56a and the gate wiring 53 are provided.

[0126] Through the above manufacturing method, transistors N2 and N3 are formed near the boundary between adjacent standard cells C3a and C3b. Fig.13 (b) Then, vias and local wiring are formed on the upper layer of the transistors by known techniques to achieve connections between the transistors.

[0127] According to the above configuration, the standard cells C3a and C3b are arranged adjacent to each other along the X direction. A dummy gate wiring 56a is formed at the cell boundary between the standard cells C3a and C3b. The standard cell C3a includes a gate wiring 52, a pad 46, a nanosheet 24, and a dummy nanosheet 34a. The gate wiring 52 is formed to be adjacent to the dummy gate wiring 56a along the X direction. The pad 46 is provided between the dummy gate wiring 56a and the gate wiring 52. The nanosheet 24 is formed to overlap with the gate wiring 52 when viewed from above and is connected to the pad 46. The dummy nanosheet 34a is formed to overlap with the dummy gate wiring 56a when viewed from above and is connected to the pad 46. The standard cell C3b includes a gate wiring 53, a pad 49, a nanosheet 26, and a dummy nanosheet 36a. The gate wiring 53 is formed to be adjacent to the dummy gate wiring 56a along the X direction. The pad 49 is provided between the dummy gate wiring 56a and the gate wiring 53. The nanosheet 26 is formed to overlap with the gate wiring 53 when viewed from above and is connected to the pad 49. The dummy nanosheet 36a is formed to overlap with the dummy gate wiring 56a when viewed from above and is connected to the pad 49 and is formed to be separated from the dummy nanosheet 34a.

[0128] At the right end of the standard cell C3a in the figure, a pad 46 is formed between the nanosheet 24 that functions as a channel portion and the dummy nanosheet 34a that does not function as a channel portion. At the left end of the standard cell C3b in the figure, a pad 49 is formed between the nanosheet 26 that functions as a channel portion and the dummy nanosheet 36a that does not function as a channel portion. The dummy nanosheets 34a and 36a are separated in the X direction to avoid electrical connection.

[0129] The pad 46 is formed by epitaxially growing the stacked semiconductors forming the nanosheet 24 and the dummy nanosheet 34a. The pad 49 is formed by epitaxially growing the stacked semiconductors forming the nanosheet 26 and the dummy nanosheet 36a. On the other hand, the pads (for example, pads 45, etc.) formed between the nanosheets that function as the channel portion are formed by epitaxially growing from the stacked semiconductor portions formed on both sides of the X direction. That is, the pads formed at the two ends of the standard cell C3 in the X direction and the pads formed between the nanosheets that function as the channel portion are formed in the same manner. In this way, the shape deviation of the above-mentioned pads can be suppressed. Therefore, since the deviation in the manufacturing accuracy of the transistor and the performance deviation of the transistor can be suppressed, the reliability and yield rate of the semiconductor integrated circuit device can be improved.

[0130] Since the standard cells C3 a and C3 b are arranged adjacent to each other in the X direction, the area of ​​the semiconductor integrated circuit device can be reduced.

[0131] It should be noted that in Fig.12In (b), the entire stacked semiconductor portion 232 may be removed, or one of the stacked semiconductor portions 234 and 235 may be removed.

[0132] In the above-mentioned embodiments, a two-input NAND circuit is formed in the standard cells C1 to C3 , but the invention is not limited thereto and other circuits may be formed therein.

[0133] In the above embodiments, the number of nanosheets included in a nanosheet FET is not limited to two, but may be one or more than three nanosheets.

[0134] In the above embodiments, the cross-sectional shape of the nanosheet is a rectangle, but is not limited thereto and may be, for example, a square, a circle, an ellipse, or the like.

[0135] In the above embodiments, each nanosheet is shown to be covered by the gate wiring all around, but each nanosheet may also be partially uncovered by the gate wiring. Figure 2 In the figure, the side surface of the nanosheet 22 on the left side of the drawing and the side surface of the nanosheet 24 on the right side of the drawing may not be covered.

[0136] In the above-mentioned embodiments, each stacked semiconductor is composed of two semiconductor layers and two sacrificial semiconductor layers, but is not limited thereto. For example, the stacked semiconductor may also be composed of two or more semiconductor layers and two or more sacrificial semiconductor layers. In addition, the film thickness of the semiconductor layer and the sacrificial semiconductor layer may be different or the same.

[0137] In the above-described embodiments, the insulating film 401 or the insulating film 411 is formed on the semiconductor substrate 100 in the manufacturing process of the semiconductor integrated circuit device, but the insulating film 401 or the insulating film 411 may not be formed. In this case, epitaxial growth is performed from the semiconductor substrate 100 .

[0138] -Industrial Applicability-

[0139] In the present disclosure, in the layout structure of a semiconductor integrated circuit device including a standard cell using a nanosheet FET, it is possible to suppress performance variations of transistors formed in the standard cell.

[0140] -Explanation of symbols-

[0141] C1(C1a, C1b), C2, C3(C3a, C3b) Standard cells

[0142] CF Filling Unit

[0143] 11.12 Power supply wiring

[0144] 21~25 Nemi slices

[0145] 31-36, 31a-36a Dummy nanosheets

[0146] 41~50 pads

[0147] 51~53 Gate wiring

[0148] 55 to 57, 55a, 56a Dummy gate wiring

[0149] 200, 230 Stacked semiconductors

[0150] 201-206, 231-235 Laminated semiconductor part

[0151] 210, 213-216, 241, 243-245 semiconductor layer

[0152] 220, 223-226, 251, 253-255 Sacrificial semiconductor layer

[0153] 301-304, 311-313 Sacrificial gate structure

[0154] 501~504、511~514 pads

[0155] 601~604、611~613 Gate oxide film

[0156] 701~704、711~713 Gate wiring

Claims

1. A semiconductor integrated circuit device, comprising a first standard cell and a second standard cell, characterized in that: The first standard cell and the second standard cell are arranged along a first direction, The first standard cell includes a first gate wiring, a first dummy gate wiring, a first pad, a first nanosheet, and a first dummy nanosheet. The first dummy gate wiring is formed adjacent to the first gate wiring on the second standard cell side of the first gate wiring in the first direction, The first pad is provided between the first gate wiring and the first dummy gate wiring, The first nanosheet is formed to overlap with the first gate wiring in a plan view and is connected to the first pad. The first dummy nanosheet is formed to overlap with the first dummy gate wiring in a plan view and is connected to the first pad. The second standard cell includes a second gate wiring, a second dummy gate wiring and a second pad, the second dummy gate wiring is formed adjacent to the second gate wiring and adjacent to the first dummy gate wiring on the first standard cell side of the second gate wiring in the first direction, The second pad is provided between the second gate wiring and the second dummy gate wiring.

2. The semiconductor integrated circuit device according to claim 1, wherein: The second standard cell further includes a second nanosheet and a second dummy nanosheet. The second nanosheet is formed to overlap with the second gate wiring in a plan view and is connected to the second pad. The second dummy nanosheet is formed to overlap with the second dummy gate wiring in a plan view and is connected to the second pad.

3. The semiconductor integrated circuit device according to claim 1 or 2, wherein: A filling cell is arranged between the first standard cell and the second standard cell.

4. The semiconductor integrated circuit device according to claim 1 or 2, wherein: In a plan view, a local wiring is formed between the first dummy gate wiring and the second dummy gate wiring. The local wiring extends along a second direction perpendicular to the first direction.

5. The semiconductor integrated circuit device according to claim 3, wherein: In a plan view, a local wiring is formed between the first dummy gate wiring and the second dummy gate wiring. The local wiring extends along a second direction perpendicular to the first direction.

6. A semiconductor integrated circuit device, comprising a first standard cell and a second standard cell, characterized in that: The first standard cell and the second standard cell are arranged adjacent to each other along a first direction, A first dummy gate wiring is formed at a cell boundary between the first standard cell and the second standard cell. The first standard cell includes a first gate wiring, a first pad, a first nanosheet, and a first dummy nanosheet. The first gate wiring is formed adjacent to the first dummy gate wiring along the first direction, The first pad is provided between the first dummy gate wiring and the first gate wiring. The first nanosheet is formed to overlap with the first gate wiring in a plan view and is connected to the first pad. The first dummy nanosheet is formed to overlap with the first dummy gate wiring in a plan view and is connected to the first pad. The second standard cell includes a second gate wiring, a second pad, a second nanosheet, and a second dummy nanosheet. the second gate wiring is formed adjacent to the first dummy gate wiring along the first direction, The second pad is provided between the first dummy gate wiring and the second gate wiring, The second nanosheet is formed to overlap with the second gate wiring in a plan view and is connected to the second pad. The second dummy nanosheet is formed to overlap with the first dummy gate wiring in a plan view and is connected to the second pad and is formed to be separated from the first dummy nanosheet.

7. A method for manufacturing a semiconductor integrated circuit device, the semiconductor integrated circuit device comprising a first standard cell and a second standard cell, characterized in that: The first standard cell and the second standard cell are arranged adjacent to each other along a first direction, The method for manufacturing a semiconductor integrated circuit device comprises the following steps: Two different semiconductors are alternately stacked on a semiconductor substrate to form a stacked semiconductor; In the upper part of the stacked semiconductor, a first sacrificial gate structure is formed at a position where the first standard cell and the second standard cell meet, a second sacrificial gate structure is formed at a position where the first standard cell is formed, and a third sacrificial gate structure is formed at a position where the second standard cell is formed; The stacked semiconductor formed between the first sacrificial gate structure and the second sacrificial gate structure and between the first sacrificial gate structure and the third sacrificial gate structure when viewed from above is removed, thereby forming a first stacked semiconductor portion, a second stacked semiconductor portion, and a third stacked semiconductor portion under the first sacrificial gate structure, the second sacrificial gate structure, and the third sacrificial gate structure, respectively; Forming a first pad between the first stacked semiconductor portion and the second stacked semiconductor portion by epitaxially growing the first stacked semiconductor portion and the second stacked semiconductor portion, and forming a second pad between the first stacked semiconductor portion and the third stacked semiconductor portion by epitaxially growing the first stacked semiconductor portion and the third stacked semiconductor portion; removing the first sacrificial gate structure, the second sacrificial gate structure, and the third sacrificial gate structure; A portion or all of the first stacked semiconductor portion is removed so that the first pad and the second pad are not electrically connected through the second stacked semiconductor portion.

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