Zero-crossing detection circuit and driving device

Abstract

A zero-crossing detection circuit and a driving device are disclosed. The zero-crossing detection circuit can be applied to a switching power supply and includes: a common-source amplifier circuit connected to the switching node, configured to detect and amplify the ringing voltage of the switching node and output it; and a turn-off detection circuit connected to the common-source amplifier circuit and the lower switching transistor, configured to acquire a control signal of the lower switching transistor, the control signal including a turn-off signal, and output a corresponding zero-crossing detection signal according to the interval between the occurrence time of the ringing voltage and the occurrence time of the turn-off signal, the zero-crossing detection signal being used to adjust the occurrence time of the turn-off signal. This application can dynamically control the turn-off time of the lower switching transistor according to actual conditions, making the turn-off time of the lower switching transistor more accurate.

Description

Technical Field

[0001] This application belongs to the field of switching power supply technology, and in particular relates to a zero-crossing detection circuit and a driving device. Background Technology

[0002] Currently, the traditional zero-crossing detection circuit is mainly used in switching power supplies that employ synchronous rectification technology. In such power supplies, the zero-crossing point of the current of the synchronous rectifier is a crucial moment. Precisely controlling the synchronous rectifier to turn off at the moment of current zero-crossing can not only allow the synchronous rectifier to fully utilize its freewheeling function but also prevent current backflow, thereby improving the efficiency of the power supply.

[0003] Existing technologies often achieve zero-crossing turn-off of the lower transistor by simply comparing the voltage of the switching node with a fixed voltage. However, the delay and misalignment of the comparator can lead to inaccurate turn-off point of the lower transistor, thus affecting efficiency. Summary of the Invention

[0004] The purpose of this application is to provide a zero-crossing detection circuit and driving device, which aims to solve the problem of low accuracy in traditional zero-crossing detection.

[0005] A first aspect of this application provides a zero-crossing detection circuit applied to a switching power supply. The switching power supply includes an upper switching transistor and a lower switching transistor connected in series between the input and ground, and an energy storage and release circuit connected to a switching node between the upper and lower switching transistors for outputting power. The zero-crossing detection circuit includes: a common-source amplifier circuit connected to the switching node, configured to detect and amplify the ringing voltage of the switching node and output it; and a shutdown detection circuit connected to the common-source amplifier circuit and the lower switching transistor, configured to acquire a control signal of the lower switching transistor, the control signal including a shutdown signal, and output a corresponding zero-crossing detection signal according to the interval between the occurrence time of the ringing voltage and the occurrence time of the shutdown signal, the zero-crossing detection signal being used to adjust the occurrence time of the shutdown signal.

[0006] In one embodiment, the shutdown detection circuit includes a comparison circuit, a reference voltage circuit, and a sampling detection circuit. The comparison circuit is configured to output a counting signal according to the order of the occurrence times of the ringing voltage and the shutdown signal. The reference voltage circuit is connected to the comparison circuit and is configured to generate a corresponding reference voltage based on the counting signal. The sampling detection circuit is connected to the reference voltage circuit and the switching node of the switching power supply. The sampling detection circuit is configured to generate a corresponding detection voltage based on the node voltage of the switching node, and when the detection voltage reaches the reference voltage, the sampling detection circuit outputs the zero-crossing detection signal to control the switching power supply to shut down the lower switching transistor.

[0007] In one embodiment, the common-source amplifier circuit includes a first switching transistor and an inverter. The first conducting terminal of the first switching transistor is connected to a first current source, the second conducting terminal of the first switching transistor is grounded, the controlled terminal of the first switching transistor is connected to the switching node, the input terminal of the inverter is connected to the first conducting terminal of the first switching transistor, and the output terminal of the inverter is connected to the comparison circuit.

[0008] In one embodiment, the comparison circuit includes a comparison module, a trigger, a first delay module, and a second delay module. The first input terminal of the trigger is connected to the common-source amplifier circuit, the second input terminal of the trigger is connected to the controlled terminal of the lower switching transistor, and the output terminal of the trigger is connected to the comparison module. The first terminal of the first delay module is connected to the controlled terminal of the lower switching transistor, the second terminal of the first delay module is connected to the comparison module, the first terminal of the second delay module is connected to the controlled terminal of the lower switching transistor, and the second terminal of the second delay module is connected to the comparison module. The turn-off signal requires a first delay time to pass through the first delay module, and a second delay time to pass through the second delay module, wherein the first delay time is less than the second delay time. The comparison module is configured to output a corresponding counting signal based on the order in which the feedback signal received from the trigger and the turn-off signals output by the first and second delay modules are received.

[0009] In one embodiment, the first delay module includes a first delay buffer, a first end of which is connected to the controlled terminal of the lower switching transistor, and a second end of the second delay buffer is connected to the comparison module; the second delay module includes a second delay buffer and a third delay buffer, a first end of which is connected to the controlled terminal of the lower switching transistor, a second end of which is connected to the first end of the third delay buffer, and a second end of the third delay buffer is connected to the comparison module.

[0010] In one embodiment, the reference voltage circuit includes a counter and a digital-to-analog converter module. The input terminal of the counter is connected to the comparison circuit, the output terminal of the counter is connected to the input terminal of the digital-to-analog converter module, and the output terminal of the digital-to-analog converter module is connected to the sampling detection circuit. The counter is configured to adjust the digital signal output by the counter according to the counting signal, and the digital-to-analog converter module is configured to convert the digital signal output by the counter into the reference voltage.

[0011] In one embodiment, the sampling detection circuit includes a zero-crossing detector and a sampling module. The non-inverting input of the zero-crossing detector is connected to the reference voltage circuit to receive the reference voltage. The inverting input of the zero-crossing detector is connected to the sampling module. The sampling module is connected to the switching node. The sampling module is configured to output a corresponding detection voltage to the zero-crossing detector based on the node voltage. The zero-crossing detector is configured to output the zero-crossing detection signal when the detection voltage reaches the reference voltage, so as to control the switching power supply to turn off the lower switching transistor.

[0012] In one embodiment, the sampling circuit includes a sampling resistor, a first end of which is connected to a second current source, a second end of which is connected to the switching node, and the first end of which is also connected to the inverting input of the zero-crossing detector.

[0013] In one embodiment, the energy storage and release circuit includes an output inductor and an output capacitor. The first end of the output inductor is connected to the switching node, the second end of the output inductor is used to output power, the first end of the output capacitor is connected to the second end of the output inductor, and the second end of the output capacitor is grounded.

[0014] A second aspect of this application provides a driving device, including a switching power supply and a zero-crossing detection circuit as described above.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: the common-source amplifier circuit and the turn-off detection circuit can determine whether the turn-off time of the corresponding lower switch is appropriate based on the interval between the occurrence time of the ringing voltage and the occurrence time of the turn-off signal, and output the corresponding zero-crossing detection signal, thereby changing the turn-off time of the corresponding lower switch. This application can dynamically control the turn-off time of the lower switch according to the actual situation, making the turn-off time of the lower switch more accurate. Attached Figure Description

[0016] Figure 1 A schematic block diagram of the driving device provided in the embodiments of this application;

[0017] Figure 2A circuit diagram of the zero-crossing detection circuit provided in an embodiment of this application;

[0018] Figure 3 The signal waveform diagram of the zero-crossing detection circuit provided in the embodiment of this application is shown.

[0019] The above figures illustrate the following: 100, switching power supply; 200, common-source amplifier circuit; 300, shutdown detection circuit; 310, comparison circuit; 320, reference voltage circuit; 330, sampling detection circuit. Detailed Implementation

[0020] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0021] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0022] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] Figure 1 A schematic block diagram of the driving device provided in the first embodiment of this application is shown, and the details are as follows:

[0025] A driving device includes a switching power supply 100 and a zero-crossing detection circuit.

[0026] like Figure 2As shown, in this embodiment, the switching power supply 100 includes a drive control module U7, an upper switching transistor Q1, a lower switching transistor Q2, and an energy storage and release circuit. The energy storage and release circuit is used to output power to the load. Specifically, the first conducting terminal of the upper switching transistor Q1 is connected to the input (drive power supply terminal VIN), the second conducting terminal of the upper switching transistor Q1 is connected to the first conducting terminal of the lower switching transistor Q2, the connection point of the upper switching transistor Q1 and the lower switching transistor Q2 is the switching node SW, the second conducting terminal of the lower switching transistor Q2 is grounded, and the controlled terminals of both the upper switching transistor Q1 and the lower switching transistor Q2 are connected to the drive control module U7. The drive control module U7 is used to control the conduction and turn-off of the upper switching transistor Q1 and the lower switching transistor Q2. The energy storage and release circuit is connected to the switching node SW and is configured to convert the node voltage of the switching node SW into an output voltage. The output voltage is used to drive the load RT connected to the energy storage and release circuit.

[0027] Specifically, both the upper switch Q1 and the lower switch Q2 are NMOS transistors. The first conducting terminal of the upper switch Q1 and the lower switch Q2 is the drain of the NMOS transistor, the second conducting terminal of the upper switch Q1 and the lower switch Q2 is the source of the NMOS transistor, and the controlled terminal of the upper switch Q1 and the lower switch Q2 is the gate of the NMOS transistor.

[0028] The energy storage and release circuit includes an output inductor L1 and an output capacitor C1. The first end of the output inductor L1 is connected to the switch node SW, the second end of the output inductor L1 is connected to the first end of the output capacitor C1, the second end of the output capacitor C1 is grounded, and the second end of the output inductor L1 is used to connect to the load RT.

[0029] It should be noted that the switching power supply 100 in this embodiment is a step-down power supply. By controlling the upper switching transistor Q1 and the lower switching transistor Q2, a lower DC voltage can be output on the energy storage and release circuit. Specifically, when the upper switching transistor Q1 is turned off and the lower switching transistor Q2 begins to conduct, the output inductor L1 will begin to generate an inductor current I1. Therefore, the lower switching transistor Q2 needs to be turned off when the inductor current I1 drops to 0. Otherwise, if the lower switching transistor Q2 is turned off too early, the inductor current I1 will flow through the parasitic diode of the lower switching transistor Q2; if the lower switching transistor Q2 is turned off too late, it will cause the inductor current I1 to flow backward. Both of these abnormal situations will lead to a decrease in the conversion efficiency of the switching power supply 100.

[0030] Meanwhile, when the current switch Q2 is turned off, the energy storage and release circuit will experience a ringing effect. This ringing effect will cause a fluctuating ringing voltage after a certain interval following the turn-off of the next switch Q2, and this interval will vary depending on the turn-off time of the next switch Q2. Specifically, if the next switch Q2 turns off before the inductor current I1 drops to 0 (i.e., the turn-off time is too early), the interval will be too long. If the next switch Q2 turns off after the inductor current I1 has already dropped to 0 (i.e., the turn-off time is too late), the interval will be too short. Therefore, the appropriateness of the turn-off time of the next switch Q2 can be detected by monitoring the interval.

[0031] The zero-crossing detection circuit can compare the generation time of the ringing voltage with the turn-off time of the delayed lower switch Q2, and output the corresponding zero-crossing detection signal, thereby achieving the purpose of adjusting the turn-off time of the lower switch Q2.

[0032] In this embodiment, the driving device further includes a voltage conversion module, which includes a working voltage terminal VCC, a driving power supply terminal VIN, a first current source IDC1, and a second current source IDC2. The input terminals of the first current source IDC1 and the second current source IDC2 are both connected to the working voltage terminal VCC. The voltage conversion module is used to supply power to the switching power supply 100 and the zero-crossing detection circuit.

[0033] The second embodiment of this application provides a zero-crossing detection circuit, which can be applied to the switching power supply 100 of the above embodiment, as detailed below:

[0034] like Figure 2 As shown, the zero-crossing detection circuit includes a common-source amplifier circuit 200 and a turn-off detection circuit 300. The common-source amplifier circuit 200 is connected to the switching node SW of the switching power supply 100. The common-source amplifier circuit 200 is configured to generate a corresponding feedback signal based on the node voltage of the switching node SW. The common-source amplifier circuit 200 can amplify the ringing voltage at the switching node SW and output it. The turn-off detection circuit 300 is connected to the common-source amplifier circuit 200 and the lower switching transistor Q2. The turn-off detection circuit 300 is configured to acquire the control signal of the lower switching transistor Q2, which includes a turn-off signal. Based on the interval between the occurrence time of the ringing voltage and the occurrence time of the turn-off signal, the circuit outputs a corresponding zero-crossing detection signal. The zero-crossing detection signal is used to adjust the occurrence time of the turn-off signal.

[0035] The turn-off detection circuit 300 includes a comparison circuit 310, a reference voltage circuit 320, and a sampling detection circuit 330. The comparison circuit 310 is connected to the common-source amplifier circuit 200 and the switching power supply 100. The comparison circuit 310 is configured to delay and acquire the turn-off signal of the lower switching transistor of the switching power supply 100, and output corresponding counting signals based on the sequence of triggering the comparison circuit 310 according to the feedback signal and the turn-off signal. The reference voltage circuit 320 is connected to the comparison circuit 310 and is configured to generate a corresponding reference voltage based on the counting signal. The sampling detection circuit 330 is connected to the reference voltage circuit 320 and the switching node SW of the switching power supply 100. The sampling detection circuit 330 is configured to generate a corresponding detection voltage based on the node voltage of the switching node SW, and when the detection voltage reaches the reference voltage, the sampling detection circuit 330 controls the switching power supply 100 to turn off the lower switching transistor.

[0036] In this embodiment, the common-source amplifier circuit 200 includes a first switch Q3 and an inverter U1. The first conducting terminal of the first switch Q3 is connected to the output terminal of the first current source IDC1, the second conducting terminal of the first switch Q3 is grounded, the controlled terminal of the first switch Q3 is connected to the switching node SW, the input terminal of the inverter U1 is connected to the first conducting terminal of the first switch Q3, and the output terminal of the inverter U1 is connected to the comparison circuit 310.

[0037] Specifically, the first switching transistor Q3 is an NMOS transistor. The first conducting terminal of Q3 is the drain of the NMOS transistor, the second conducting terminal is the source of the NMOS transistor, and the controlled terminal is the gate of the NMOS transistor. When the voltage at the switching node SW is high, turning on the first switching transistor Q3, the first conducting terminal of Q3 is connected to ground, resulting in a low level at the first conducting terminal. After passing through inverter U1, inverter U1 outputs a high level. When the voltage at the switching node SW is low, turning off the first switching transistor Q3, the first current source IDC1 makes the first conducting terminal of Q3 high, resulting in a low level output through inverter U1. The common-source amplifier circuit 200 can convert the linearly changing voltage of the switching node SW into a standard-level feedback signal, allowing the comparison circuit 310 to accurately read the transition edge of the feedback signal.

[0038] In this embodiment, the comparison circuit 310 includes a comparison module U3, a trigger U2, a first delay module, and a second delay module. The first input terminal of the trigger U2 is connected to the common-source amplifier circuit 200, the second input terminal of the trigger U2 is connected to the controlled terminal of the lower switch Q2, and the output terminal of the trigger U2 is connected to the comparison module U3. The first terminal of the first delay module is connected to the controlled terminal of the lower switch Q2, the second terminal of the first delay module is connected to the comparison module U3, the first terminal of the second delay module is connected to the controlled terminal of the lower switch Q2, and the second terminal of the second delay module is connected to the comparison module U3. The turn-off signal requires a first delay time to pass through the first delay module, and the turn-off signal requires a second delay time to pass through the second delay module. The first delay time is less than the second delay time. The comparison module U3 is configured to output a corresponding counting signal according to the order of the feedback signal received from the trigger U2, the turn-off signal transmitted by the first delay module, and the turn-off signal transmitted by the second delay module.

[0039] Specifically, flip-flop U2 is an RS flip-flop U2. Its first input is the R terminal of the RS flip-flop U2, its second output is the S terminal of the RS flip-flop U2, and its final output is the Q terminal of the RS flip-flop U2. The comparator module U3 can be a microcontroller or a single-chip microcomputer.

[0040] The first delay module includes a first delay buffer DL1, the first end of which is connected to the controlled terminal of the lower switching transistor Q2, and the second end of the second delay buffer DL2 is connected to the comparison module U3. The second delay module includes a second delay buffer DL2 and a third delay buffer DL3, the first end of which is connected to the controlled terminal of the lower switching transistor Q2, the second end of which is connected to the first end of the third delay buffer DL3, and the second end of the third delay buffer DL3 is connected to the comparison module U3.

[0041] like Figure 3 As shown, it should be noted that when the current switch Q2 is turned on, both the second input terminal of the flip-flop U2 and the controlled terminal of the current switch Q2 are at a high level, the node voltage of the switching node SW is at a low level, and the first input terminal of the flip-flop U2 is at a low level. Therefore, the output terminal of the flip-flop U2 is at a high level. At the same time, both the first delay module and the second delay module output a high level to the comparator module U3.

[0042] When the current switch Q2 is turned off, the second input of flip-flop U2 immediately goes low. After the ringing voltage rises to the turn-on threshold of the first switch Q3, the first input of flip-flop U2 goes high, and its output goes low. This causes the comparator module U3 to receive a falling edge of the feedback signal. There is a third delay time between the turn-off of the lower switch Q2 and the receipt of the first falling edge of the feedback signal by the comparator module U3. This third delay time represents the interval between the occurrence of the ringing voltage and the occurrence of the turn-off signal. Simultaneously, the falling edge of the turn-off signal from the controlled terminal of the lower switch Q2 is also transmitted to the comparator module U3 through the first and second delay modules.

[0043] The order of the feedback signal and the turn-off signal received by the comparison module U3 reflects the relationship between the third delay time and the first and second delay times, respectively. In other words, it reflects the length of the interval between the occurrence of the ringing voltage and the occurrence of the turn-off signal, and indicates whether the turn-off time of the lower switch Q2 is appropriate.

[0044] Specifically, if the third delay time is less than the first delay time, it indicates that the interval between the occurrence of the ringing voltage and the occurrence of the turn-off signal is too short, meaning the turn-off time of the lower switching transistor Q2 is too late. Similarly, if the third delay time is greater than the first delay time but less than the second delay time, it indicates that the interval between the occurrence of the ringing voltage and the occurrence of the turn-off signal is appropriate. Likewise, if the third delay time is greater than the second delay time, it indicates that the interval between the occurrence of the ringing voltage and the occurrence of the turn-off signal is too early. Figure 3 The falling edge output of the flip-flop U2 is exactly after the falling edge is received by the V2 pin of the comparator module U3 and before the falling edge is received by the V3 pin of the comparator module U3. Figure 3 The waveforms shown are the waveforms of each node / parameter when the turn-off time of the lower switch Q2 is appropriate.

[0045] In this embodiment, the reference voltage circuit 320 includes a counter U4 and a digital-to-analog converter module U5. The input terminal of the counter U4 is connected to the comparison circuit 310, the output terminal of the counter U4 is connected to the input terminal of the digital-to-analog converter module U5, and the output terminal of the digital-to-analog converter module U5 is connected to the sampling and detection circuit 330. The counter U4 is configured to adjust the digital signal output by the output terminal of the counter U4 according to the counting signal, and the digital-to-analog converter module U5 is configured to convert the digital signal output by the output terminal of the counter U4 into a reference voltage.

[0046] Specifically, if the turn-off time of switching transistor Q2 is too late, the counting signal output by the comparator circuit 310 to the reference voltage circuit 320 will decrement the digital signal output by counter U4 by 1, for example, changing the binary digital signal 1101 to the binary digital signal 1100. If the turn-off time of switching transistor Q2 is too early, the counting signal output by the comparator circuit 310 to the reference voltage circuit 320 will increment the digital signal output by counter U4 by 1, for example, changing the binary digital signal 1101 to the binary digital signal 1110. The digital-to-analog converter module U5 will output an analog voltage of corresponding magnitude according to the digital signal output by counter U4, and output this analog voltage as a reference voltage to the sampling and detection circuit 330. The larger the digital signal, the larger the output analog voltage.

[0047] In this embodiment, the sampling and detection circuit 330 includes a zero-crossing detector U6 and a sampling module. The non-inverting input terminal of the zero-crossing detector U6 is connected to the reference voltage circuit 320 to receive the reference voltage. The inverting input terminal of the zero-crossing detector U6 is connected to the sampling module, which is connected to the switching node SW. The sampling module is configured to output a corresponding detection voltage to the zero-crossing detector U6 according to the node voltage. The zero-crossing detector U6 is configured to output a zero-crossing detection signal when the detection voltage reaches the reference voltage. The zero-crossing detection signal is used to control the lower switch Q2 to turn off.

[0048] Specifically, the sampling circuit includes a sampling resistor R1. The first end of the sampling resistor R1 is connected to the output terminal of the second current source IDC2, the second end of the sampling resistor R1 is connected to the switching node SW, and the first end of the sampling resistor R1 is also connected to the inverting input terminal of the zero-crossing detector U6.

[0049] It should be noted that after the current switching transistor Q2 is turned on, the voltage of the switching node SW will gradually increase, causing the detection voltage to gradually increase. When the detection voltage reaches the reference voltage, the zero-crossing detector U6 outputs the corresponding zero-crossing detection signal, causing the lower switching transistor Q2 to turn off. The larger the reference voltage, the later the turn-off time of the lower switching transistor Q2. After adjusting the reference voltage through the common-source amplifier circuit 200, the comparison circuit 310 and the reference voltage circuit 320, when the detection voltage reaches the reference voltage, the lower switching transistor Q2 can be turned off when the inductor current I1 is 0 or infinitely close to 0.

[0050] In this embodiment, the output terminal of the zero-crossing detector U6 is connected to the input terminal IN of the drive control module U7 to transmit the zero-crossing detection signal to the drive control module U7. The zero-crossing detection signal is used to control the drive control module U7 to output the corresponding turn-off signal to turn off the lower switch Q2.

[0051] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A zero-crossing detection circuit applied to a switching power supply, the switching power supply comprising an upper switching transistor and a lower switching transistor connected in series between the input and ground, and an energy storage and release circuit connected to a switching node between the upper and lower switching transistors for outputting power, characterized in that, The zero-crossing detection circuit includes: A common-source amplifier circuit is connected to the switching node, and the common-source amplifier circuit is configured to detect the ringing voltage of the switching node and amplify it before outputting it. A shutdown detection circuit is connected to the common-source amplifier circuit and the lower switching transistor. The shutdown detection circuit is configured to acquire the control signal of the lower switching transistor, the control signal including a shutdown signal, and output a corresponding zero-crossing detection signal according to the interval between the occurrence time of the ringing voltage and the occurrence time of the shutdown signal. The zero-crossing detection signal is used to adjust the occurrence time of the shutdown signal. The shutdown detection circuit includes a comparison circuit, a reference voltage circuit, and a sampling detection circuit; The comparison circuit is configured to output a counting signal according to the order in which the ringing voltage occurs and the off signal occurs; A reference voltage circuit, connected to the comparison circuit, is configured to generate a corresponding reference voltage based on the counting signal; A sampling and detection circuit is connected to the reference voltage circuit and the switching node of the switching power supply. The sampling and detection circuit is configured to generate a corresponding detection voltage based on the node voltage of the switching node, and when the detection voltage reaches the reference voltage, the sampling and detection circuit outputs the zero-crossing detection signal to control the switching power supply to turn off the lower switching transistor.

2. The zero-crossing detection circuit as described in any one of claims 1, characterized in that, The common-source amplifier circuit includes a first switching transistor and an inverter. The first conducting terminal of the first switching transistor is connected to a first current source, the second conducting terminal of the first switching transistor is grounded, the controlled terminal of the first switching transistor is connected to the switching node, the input terminal of the inverter is connected to the first conducting terminal of the first switching transistor, and the output terminal of the inverter is connected to the comparison circuit.

3. The zero-crossing detection circuit as described in claim 1, characterized in that, The comparison circuit includes a comparison module, a trigger, a first delay module, and a second delay module. The first input terminal of the trigger is connected to the common-source amplifier circuit, the second input terminal of the trigger is connected to the controlled terminal of the lower switching transistor, and the output terminal of the trigger is connected to the comparison module. The first terminal of the first delay module is connected to the controlled terminal of the lower switching transistor, the second terminal of the first delay module is connected to the comparison module, the first terminal of the second delay module is connected to the controlled terminal of the lower switching transistor, and the second terminal of the second delay module is connected to the comparison module. The shutdown signal requires a first delay time to pass through the first delay module, and the shutdown signal requires a second delay time to pass through the second delay module. The first delay time is less than the second delay time. The comparison module is configured to output a corresponding counting signal according to the order in which the feedback signal received from the trigger and the shutdown signal output by the first delay module and the second delay module are received.

4. The zero-crossing detection circuit as described in claim 3, characterized in that, The first delay module includes a first delay buffer, a first end of which is connected to the controlled terminal of the lower switching transistor, and a second end of which is connected to the comparison module. The second delay module includes a second delay buffer and a third delay buffer. The first end of the second delay buffer is connected to the controlled end of the lower switching transistor, the second end of the second delay buffer is connected to the first end of the third delay buffer, and the second end of the third delay buffer is connected to the comparison module.

5. The zero-crossing detection circuit as described in claim 1, characterized in that, The reference voltage circuit includes a counter and a digital-to-analog converter module. The input terminal of the counter is connected to the comparison circuit, the output terminal of the counter is connected to the input terminal of the digital-to-analog converter module, and the output terminal of the digital-to-analog converter module is connected to the sampling and detection circuit. The counter is configured to adjust the digital signal output from the counter's output terminal according to the counting signal, and the digital-to-analog converter module is configured to convert the digital signal output from the counter's output terminal into the reference voltage.

6. The zero-crossing detection circuit as described in claim 1, characterized in that, The sampling and detection circuit includes a zero-crossing detector and a sampling module. The non-inverting input terminal of the zero-crossing detector is connected to the reference voltage circuit to receive the reference voltage. The inverting input terminal of the zero-crossing detector is connected to the sampling module. The sampling module is connected to the switching node. The sampling module is configured to output a corresponding detection voltage to the zero-crossing detector according to the node voltage. The zero-crossing detector is configured to output the zero-crossing detection signal when the detection voltage reaches the reference voltage, so as to control the switching power supply to turn off the lower switching transistor.

7. The zero-crossing detection circuit as described in claim 6, characterized in that, The sampling module includes a sampling resistor. The first end of the sampling resistor is connected to a second current source, and the second end of the sampling resistor is connected to the switching node. The first end of the sampling resistor is also connected to the inverting input terminal of the zero-crossing detector.

8. The zero-crossing detection circuit as described in any one of claims 1-7, characterized in that, The energy storage and release circuit includes an output inductor and an output capacitor. The first end of the output inductor is connected to the switching node, the second end of the output inductor is used to output power, the first end of the output capacitor is connected to the second end of the output inductor, and the second end of the output capacitor is grounded.

9. A driving device, characterized in that, It includes a switching power supply and a zero-crossing detection circuit as described in any one of claims 1-8.

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