Digital signal testing device and method based on FPGA

Abstract

A digital signal testing device and method based on FPGA, the device includes a power module, a communication module, an input simulation module, an output sampling module and an error detection module. The steps of the method include: loading user configuration; inputting a signal to the device under test; sampling the output signal of the device under test; detecting the sampling RAM; the error detection module fixes the RAM pointer that generates the edge, searches another RAM, and determines whether an edge with the same edge direction as the edge direction of the fixed RAM and the same value of the search edge counter as the fixed edge counter is found; handles the error according to the result; and reports the result to the user. The present invention realizes the test of the device under test by reading the RAM content and adopting the output, and realizes the function of judging the error type by detecting the edge.

Description

Technical Field

[0001] The present invention belongs to the field of signal detection technology, and further relates to a digital signal testing device and method based on a field programmable gate array (FPGA) in the field of logic signal detection technology. The present invention can be used to test whether the logic program of a digital circuit meets expectations, use FPGA to simulate the communication of peripherals, and sample the output of the device under test, and match it with the expected timing to detect whether the logic of the device under test meets the timing requirements. Background Art

[0002] With the development of integrated circuit technology, the communication protocols of various peripherals are becoming more and more diverse. In addition, large-scale integrated circuits have made the scale of chip logic continue to increase. There is a need for a device for automatically testing whether the communication protocol of digital circuits meets the requirements and whether the logic program works as expected. Generally speaking, communication testing of digital circuits requires simulating multi-channel inputs and collecting multi-channel outputs. In addition, it is necessary to generate timing and waveforms that meet the protocol requirements based on the simulated peripherals, and match the sampled results with the expected output to detect failed communications. At present, the detection methods for testing hardware communication are relatively mature, but there is a lack of better solutions in engineering applications. The method of using a logic analyzer requires engineers to invest a lot of energy in manual troubleshooting, and it is difficult to achieve full coverage automatic testing; the use of a dedicated analyzer lacks versatility and can only be used for a few protocols or needs to be customized according to the board. FPGA has parallel processing capabilities, flexible hardware IO and high-speed acquisition capabilities, which can realize a more general digital signal test device with the function of automated testing.

[0003] Shengda Semiconductor Technology (Shanghai) Co., Ltd. disclosed a method for implementing a customized module on a digital test channel based on FPGA in its patent application document "A method for implementing a customized module on a digital test channel based on FPGA" (application date: 2021.01.15, application number 202110053251.6, application publication number CN 112858892 A). The application scenario of the method in the patent application is similar to that of the present invention. It can use a customized module as a test unit on a digital test channel to output a periodic signal and sample the input signal, which is mainly used to generate the timing of the digital signal input to the device under test. However, the method of this patent application has the following shortcomings: firstly, when synthesizing the custom modules designed by the user, redundant modules will be generated as the filling of the logic units LEs (Logic Elements). The output signals and input signals of these redundant units will self-circulate, which inevitably increases the power consumption of the FPGA; secondly, the method lacks the function of saving the input signal, that is, the input signal cannot be reproduced, which is not conducive to reproducing the scene after the test fails; thirdly, the method only considers the testing of the device under test, lacks the analysis of the test results, and cannot provide feedback to the designers, which requires additional manpower and material resources for error analysis.

[0004] The Microsatellite Innovation Institute of the Chinese Academy of Sciences disclosed a device and method for hardware-to-hardware communication simulation in its patent application document "A configuration connection device and method for hardware-to-hardware communication simulation" (application date: 2020.01.10, application number 201910898349.4, application publication number: CN110674067 A). The device in this patent application includes two parts: a stand-alone machine and a peripheral interface. The stand-alone machine is used for initialization, parsing configuration files, assigning channel numbers, and registering callback functions; the peripheral interface is used to realize the connection between stand-alone machines and is responsible for transmitting the simulated channel data back to the stand-alone machine. The device needs to use a specific configuration format to simulate the stand-alone machine into a device pre-stored in the library. The shortcomings of the device in this patent application are: first, a pre-specified communication protocol must be used, and users cannot generate a customized communication protocol according to their needs; second, the patent is designed for hardware-to-hardware communication simulation, and the processor needs to use callback functions to simulate the communication protocol; third, the input and output channels must be set before they are enabled, and bidirectional channels cannot be realized. The method of the patent application includes the following steps: reading the configuration of the hardware connection part in the configuration file; parsing the configuration file and using the corresponding data structure to save the configuration string of the hardware connection; parsing the configuration string of the sending part and the receiving part to obtain the corresponding hardware sending and receiving channel number; according to the configuration string of the sending part and the receiving part, obtaining the corresponding hardware class object handle; using an algorithm to register the callback function of the receiving channel to the sending channel. The shortcomings of the method of the patent application are that, first, since the callback function needs to be used for testing, the method can only test the protocol type that the device can recognize, and the communication protocol needs to support the verification function; second, the receiving and sending channels can only use one-to-many or one-to-one modes, and cannot support the many-to-many mode of the sending and receiving channels; third, there is also a lack of analysis function for the test results, which is not conducive to the debugging of the device under test. Summary of the invention

[0005] The purpose of the present invention is to provide a digital signal testing device and method based on FPGA to solve the problem that the existing device can only test specific types of data and the existing method cannot analyze the test results.

[0006] The idea of ​​realizing the purpose of the present invention is as follows: the device of the present invention is realized by using FPGA, and the characteristic that the IO of FPGA can be freely reallocated is used to realize the input simulation and output sampling of the digital signal of the device under test; the method of the present invention is realized by comparing the edges bit by bit, and when the values ​​of the bit comparison are not equal, the edges are searched, and if it is a timing error, the number of edges of the sampling RAM can be made equal to the number of edges of the expected RAM at the edge of the timing matching. At this time, the time difference of the timing offset is reflected as the address difference between the address of the error edge in the sampling RAM and the address of the searched matching edge. If it is a pulse error, such as a glitch, etc., the number of edges of the sampling RAM cannot be made equal to the number of edges of the expected RAM at the edge of the first direction matching.

[0007] The digital signal testing device of the present invention comprises a power supply module, a communication module, an input simulation module, an output sampling module and an error detection module, wherein:

[0008] The power module is used to provide power to the FPGA and adjust the block voltage of the FPGA; input the selected power rail to the FPGA through the corresponding power channel;

[0009] The communication module is used to read the user's configuration file from the host computer and write it into the configuration register and RAM of the FPGA; and read the recorded content from the error detection module and send it to the host computer;

[0010] The input simulation module is used to read the data stored in the waveform RAM and output it to the device under test using its own sampling clock; it uses its own sampling clock or register flag to generate a trigger signal;

[0011] The output sampling module is used to select a sampling mode using a register flag: if a sampling mode synchronized with the output signal is selected, the strobe trigger signal is used as the timing circuit clock; if a sampling mode synchronized with the input is selected, the input of the strobe user-defined clock IO waveform signal is used as the timing circuit clock, and the IO waveform signal will not be recorded in the sampling RAM; if an asynchronous sampling mode is selected, the frequency division of the local phase-locked loop is used as the clock signal, and the edge of the user-defined sensitive clock IO waveform signal is used as the synchronization signal of the divider according to the configuration, and the IO waveform signal will be recorded in the sampling RAM as a channel; the output of the IO waveform signal of the device under test is sampled and saved in the sampling RAM, and the flag signal is set;

[0012] The error detection module is used to compare the value of the expected RAM with the value of the sampled RAM bit by bit; respectively count the number of edges in the expected RAM and the sampled RAM before different bit values ​​in each comparison result, and save them in the expected edge counter and the sampled edge counter respectively; fix the RAM pointer that generates the edge, search for another RAM, determine the error type according to the search result, and handle the error.

[0013] The steps of the digital signal testing method of the present invention include the following:

[0014] Step 1, load user configuration:

[0015] (1a) The power module provides power to the FPGA and adjusts the block voltage of the FPGA; it inputs the selected power rail to the FPGA through the corresponding power channel;

[0016] (1b) The communication module reads the user's configuration file from the host computer and writes it into the configuration register and RAM of the FPGA;

[0017] Step 2: Input the signal to the device under test:

[0018] (2a) The input analog module reads the data stored in the waveform RAM and outputs it to the device under test using its own sampling clock;

[0019] (2b) The input analog module generates a trigger signal using its own sampling clock or register flag bit;

[0020] Step 3: Sample the output signal of the device under test:

[0021] (3a) The output sampling module uses register flags to select the sampling mode:

[0022] If you choose to use the sampling mode synchronized with the output signal, the strobe trigger signal is used as the timing circuit clock;

[0023] If you choose to use the sampling mode synchronized with the input, the input of the user-defined clock IO waveform signal will be selected as the timing circuit clock, and the IO waveform signal will not be recorded in the sampling RAM;

[0024] If the asynchronous sampling mode is selected, the frequency division of the local phase-locked loop is used as the clock signal. According to the configuration, the edge of the user-defined sensitive clock IO waveform signal is used as the synchronization signal of the divider. The IO waveform signal will be recorded into the sampling RAM as a channel.

[0025] (3b) The output sampling module starts working, samples the output of the IO waveform signal of the device under test and saves it into the sampling RAM, and completes the setting of the flag signal;

[0026] Step 4: Check the sample RAM:

[0027] The error detection module compares the value of the expected RAM with the value of the sampled RAM bit by bit; the number of edges in the expected RAM and the sampled RAM before different bit values ​​in each comparison result are counted respectively, and saved in the expected edge counter and the sampled edge counter respectively;

[0028] Step 5, the error detection module fixes the RAM pointer that generates the edge, searches another RAM, and determines whether an edge is found whose edge direction is the same as the edge direction of the fixed RAM and makes the value of the search edge counter equal to the value of the fixed edge counter. If so, execute step 6, otherwise, execute step 7;

[0029] Step 6, handle timing errors:

[0030] (6a) If the value of the pointer of the expected RAM is greater than the value of the pointer of the sampled RAM, the error type of the bit is determined to be timing advance, and the difference between the pointer of the sampled RAM and the pointer of the expected RAM is taken as the offset;

[0031] (6b) If the value of the pointer of the expected RAM is less than the value of the pointer of the sampled RAM, the error type of the bit is determined to be timing delay, and the difference between the pointer of the expected RAM and the pointer of the sampled RAM is taken as the offset;

[0032] Step 7, handle pulse errors:

[0033] If searching forward and backward respectively cannot make the value of the search edge counter equal to the value of the fixed edge counter, the error type of the bit of the sampling RAM is an error pulse or glitch; the value of the sampling edge counter is assigned to the expected edge counter;

[0034] Step 8: Report the results to the user:

[0035] After the error detection module processes all bits of the sampling RAM, the communication module reads the recorded content from the error detection module and sends it to the host computer.

[0036] Compared with the prior art, the present invention has the following advantages:

[0037] First, the device of the present invention has an input analog module. Compared with the prior art, the module can generate multiple outputs at the same time and generate two trigger signals, including a periodic trigger signal and a single pulse trigger signal, which overcomes the shortcomings of the prior art that the receiving and sending channels can only use one-to-many or one-to-one modes, and cannot support the many-to-many mode of the sending and receiving channels. This makes the device of the present invention have the characteristic of being able to have multiple sending channels corresponding to multiple receiving channels.

[0038] Second, the device of the present invention has an output sampling module, which can use three methods to sample the output of the device under test, a sampling mode synchronized with the output signal, a sampling mode synchronized with the input, and an asynchronous sampling mode, which overcomes the shortcomings of the prior art of using existing communication protocols to test the device under test, so that the device of the present invention can flexibly sample the device under test and can accept user-defined communication protocols.

[0039] Third, the method of the present invention has an error analysis step, which can analyze the results output by the device under test. By processing the edge, the method of the present invention can analyze whether the error type of the error edge is a timing error or a pulse error. If it is a timing error, the offset can be further given through the address difference of the RAM, which overcomes the problem that the existing technical solution can only save sampling information and lacks the ability to analyze the sampling results. The method of the present invention has the advantages of analyzing the error type of the sampling result and further giving the offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a structural schematic diagram of the device of the present invention;

[0041] Figure 2 It is a functional block diagram of the input simulation module in the device of the present invention;

[0042] Figure 3 It is a functional block diagram of the input and output sampling module in the device of the present invention;

[0043] Figure 4 It is a flow chart of an embodiment of the method of the present invention. DETAILED DESCRIPTION

[0044] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0045] Reference Figure 1 The device of the present invention is further described in detail with reference to the accompanying drawings and embodiments.

[0046] The digital signal testing device of the present invention comprises a power supply module, a communication module, an input simulation module, an output sampling module and an error detection module.

[0047] The power module of the embodiment of the present invention is used to provide power to the FPGA and adjust the block voltage of the FPGA, and supports protocols of different voltage standards by selecting different power rails.

[0048] The communication module of the embodiment of the present invention is used to read the user's configuration file from the host computer, write it into the configuration register and RAM of the FPGA, and read the recorded content from the error detection module and send it to the host computer. The communication module is used to interact with the user and can transmit data by connecting to the host computer or other embedded master control.

[0049] The input simulation module of the embodiment of the present invention is used to read the data stored in the waveform RAM, output it to the device under test using its own sampling clock, and generate a trigger signal using its own sampling clock or register flag.

[0050] The output sampling module of the embodiment of the present invention is used to select the sampling mode using the register flag bit: if the sampling mode synchronized with the output signal is selected, the trigger signal is used as the timing circuit clock; if the sampling mode synchronized with the input is selected, the input of the user-defined clock IO waveform signal is selected as the timing circuit clock, and the IO waveform signal will not be recorded in the sampling RAM. If the asynchronous sampling mode is selected, the frequency division of the local phase-locked loop is used as the clock signal, and the edge of the user-defined sensitive clock IO waveform signal is used as the synchronization signal of the divider according to the configuration, and the IO waveform signal will be recorded in the sampling RAM as one channel. The output of the IO waveform signal of the device under test is sampled and saved in the sampling RAM, and the flag signal is set.

[0051] The error detection module of the embodiment of the present invention is used to compare the value of the expected RAM with the value of the sampled RAM bit by bit. The number of edges in the expected RAM and the sampled RAM before different bit values ​​in each comparison result is counted respectively, and saved in the expected edge counter and the sampled edge counter respectively. The RAM pointer that generates the edge is fixed, and another RAM is searched. The error type is determined according to the search result, and the error is processed.

[0052] Reference Figure 2 The input simulation module of the device of the present invention is further described in the following embodiments.

[0053] The user writes the setting information into the sampling clock register group, trigger setting register group, and pin enable register through the communication module, and writes the waveform information of the communication protocol to be simulated into the RAM table in chronological order in the direction of address growth. The sampling clock reconfigurator reads the contents of the sampling clock configuration register group, reconfigures the value of the sampling clock PLL, and sets it to the user-defined output sampling rate. After that, the sampling clock starts working and outputs the clock to the latch and combinational logic block. The combinational logic block reads the trigger setting register and chooses to use the sampling clock output or the flag bit output of the trigger setting register to obtain a variety of trigger signals. After the latch obtains the clock signal, it latches the contents of the RAM table and outputs it to the tri-state gate. The enable signal of the tri-state gate is given by the combinational logic block, which reads the pin enable register to determine the working status of each tri-state gate and ultimately determines the output status of the IO.

[0054] Reference Figure 3 The output sampling module of the device of the present invention is further described in the following embodiments.

[0055] The trigger signal setting register group configures the working mode of the edge detection block. If the sampling mode synchronized with the output signal is used, the trigger signal here is a periodic signal, and the edge detection block directly outputs it to the clock selection block. Otherwise, the trigger signal is a pulse signal, and the edge detection block uses the edge of the trigger signal as the enable flag of the divider. The splitter uses the value of the sampling IO configuration register group to determine the sensitive signal and outputs the sensitive signal to the divider. The sampling clock uses the sampling clock configuration register group to complete the configuration of its own sampling rate, and the divider divides the output of the sampling clock. If the asynchronous sampling mode is used, the divider uses the sensitive signal of the splitter as a synchronization flag and outputs the result to the clock selection block; if the sampling mode synchronized with the input is used, the divider outputs the sensitive signal of the splitter to the clock selection block. The clock selection block uses the result of the clock selector register to determine the clock signal of the latch. The latch latches the signal of the splitter except the sensitive signal and saves it in the sampling RAM. At the same time, the clock selection block outputs the clock to the register, which increments by 1 in each clock cycle and saves the result to the operation status register. The sampling RAM uses a dual-port RAM, which allows the read port to output the RAM contents while the write port is working.

[0056] Reference Figure 4 The method of the present invention is further described in detail with reference to the accompanying drawings and embodiments.

[0057] Step 1: Load user configuration.

[0058] The power module provides power to the FPGA and adjusts the block voltage of the FPGA; the selected power rail is input to the FPGA through the corresponding power channel.

[0059] The communication module reads the user's configuration file from the host computer and writes it into the configuration register and RAM of the FPGA.

[0060] Step 2: Input a signal to the device under test.

[0061] The input analog module reads the data stored in the waveform RAM and outputs it to the device under test using its own sampling clock.

[0062] The input analog module generates a trigger signal using its own sampling clock or register flag.

[0063] The trigger signal is a periodic signal using a clock source or a single pulse signal generated using a flag. The input analog module generates a periodic trigger signal by gating the clock source, generates a single pulse signal by using a register flag, and determines the final output signal through a multiplexer.

[0064] Step 3: Sample the output signal of the device under test.

[0065] In step 1, the output sampling module uses register flags to select the sampling mode.

[0066] If you choose to use the sampling mode synchronized with the output signal, the strobe trigger signal will be used as the timing circuit clock.

[0067] If you choose to use the sampling mode synchronized with the input, the input of the user-defined clock IO waveform signal will be selected as the timing circuit clock, and the IO waveform signal will not be recorded in the sampling RAM.

[0068] If you choose to use the asynchronous sampling mode, use the local phase-locked loop's frequency division as the clock signal. According to the configuration, use the edge of the user-defined sensitive clock IO waveform signal as the synchronization signal of the divider. The IO waveform signal will be recorded in the sampling RAM as a channel.

[0069] In step 2, the output sampling module starts working, samples the output of the IO waveform signal of the device under test and saves it into the sampling RAM, and completes the setting of the flag signal.

[0070] Step 4: Test the sampling RAM.

[0071] The error detection module compares the expected RAM value with the sampled RAM value bit by bit. If the comparison results are the same, the next bit is compared. If the comparison results are different, step 5 is executed.

[0072] Step 5: Count the edges.

[0073] The edges of the sampling RAM and the expected RAM are counted respectively from the starting position. Every time an edge is encountered, 1 is added to the corresponding edge counter until the current position is reached.

[0074] Step 6: The error detection module fixes the RAM pointer that generates the edge and searches another RAM.

[0075] The search refers to moving the search pointer forward, and each time encountering any edge, the value of the search edge counter is reduced by 1 until an edge with the same direction as the edge of the RAM with a fixed address is found or the starting position of the RAM is reached; moving the search pointer backward, and each time encountering any edge, the value of the search edge counter is increased by 1 until an edge with the same direction as the edge of the RAM with a fixed address is found or the end position of the RAM is reached.

[0076] When both the forward search and the backward search are completed, execute step 8.

[0077] Step 8, determine whether the value of the search pointer edge counter is equal to the value of the fixed pointer edge counter. If not, mark the bit error at the sampling RAM as a pulse error and execute step 9; if equal, mark the bit error at the sampling RAM as a timing error and execute step 10.

[0078] Step 9, handle pulse errors.

[0079] If searching forward and backward respectively cannot make the value of the search edge counter equal to the value of the fixed edge counter, the error type of the bit of the sampling RAM is an error pulse or a glitch.

[0080] The value of the sampled edge counter is assigned to the expected edge counter in order to ignore this error later and not interfere with other edges.

[0081] The pointer of the sampling RAM moves to the next edge. This is because the bit of the sampling RAM belongs to a pulse error, so the value before the next edge has no comparison value.

[0082] Step 10, handle timing errors.

[0083] If the value of the expected RAM pointer is greater than the value of the sampling RAM pointer, the error type of the bit is determined to be a timing advance, and the difference between the sampling RAM pointer and the expected RAM pointer is used as the offset. Then the sampling pointer value is moved to the same position as the expected RAM pointer. This is because the bit of the sampling RAM is a timing error, and the timing needs to be corrected before comparing the next bit.

[0084] If the value of the expected RAM pointer is less than the value of the sampling RAM pointer, the error type of this bit is determined to be timing lag, and the difference between the expected RAM pointer and the sampling RAM pointer is used as the offset. Then the expected pointer moves to the same position as the sampling RAM pointer. This is because the bit of the sampling RAM is a timing error, and the timing needs to be corrected before comparing the next bit.

[0085] Step 11, determine whether the sampling RAM end point has been reached.

[0086] If the sampling RAM end point has not been reached, the process moves to the next bit and then executes step 4; otherwise, the process executes step 12.

[0087] Step 12: Report the result to the user.

[0088] After the error detection module processes all bits of the sampling RAM, the communication module reads the recorded content from the error detection module and sends it to the host computer.

Claims

1. A digital signal test device based on FPGA, comprising a power module and a communication module, characterized in that It also includes an input simulation module, an output sampling module and an error detection module, and the three modules are built on the FPGA; wherein: The power module is used to provide power to the FPGA and adjust the block voltage of the FPGA; input the selected power rail to the FPGA through the corresponding power channel; The communication module is used to read the user's configuration file from the host computer and write it into the configuration register and RAM of the FPGA; and read the recorded content from the error detection module and send it to the host computer; The input simulation module is used to read the data stored in the waveform RAM and output it to the device under test using its own sampling clock; it uses its own sampling clock or register flag to generate a trigger signal; The output sampling module is used to select a sampling mode using a register flag: if a sampling mode synchronized with the output signal is selected, the strobe trigger signal is used as the timing circuit clock; if a sampling mode synchronized with the input is selected, the input of the strobe user-defined clock IO waveform signal is used as the timing circuit clock, and the IO waveform signal will not be recorded in the sampling RAM; if an asynchronous sampling mode is selected, the frequency division of the local phase-locked loop is used as the clock signal, and the edge of the user-defined sensitive clock IO waveform signal is used as the synchronization signal of the divider according to the configuration, and the IO waveform signal will be recorded in the sampling RAM as a channel; the output of the IO waveform signal of the device under test is sampled and saved in the sampling RAM, and the flag signal is set; The error detection module is used to compare the value of the expected RAM with the value of the sampled RAM bit by bit; respectively count the number of edges in the expected RAM and the sampled RAM before different bit values ​​in each comparison result, and save them in the expected edge counter and the sampled edge counter respectively; fix the RAM pointer that generates the edge, search for another RAM, determine the error type according to the search result, and handle the error.

2. A digital signal testing method based on FPGA according to the device of claim 1, characterized in that: The output sampling module supports three sampling modes, including: sampling mode synchronized with the output signal, sampling mode synchronized with the IO clock, and asynchronous sampling mode using the IO edge; the error detection module can detect the sampling results to determine whether they meet the user's expectations and automatically calculate the offset of their edges; the steps of this method include the following: Step 1, load user configuration: (1a) The power module provides power to the FPGA and adjusts the block voltage of the FPGA; it inputs the selected power rail to the FPGA through the corresponding power channel; (1b) The communication module reads the user's configuration file from the host computer and writes it into the configuration register and RAM of the FPGA; Step 2: Input signal to the device under test: (2a) The input analog module reads the data stored in the waveform RAM and outputs it to the device under test using its own sampling clock; (2b) The input analog module generates a trigger signal using its own sampling clock or register flag bit; Step 3: Sample the output signal of the device under test: (3a) The output sampling module uses register flags to select the sampling mode: If you choose to use the sampling mode synchronized with the output signal, the strobe trigger signal is used as the timing circuit clock; If you choose to use the sampling mode synchronized with the input, the input of the user-defined clock IO waveform signal will be selected as the timing circuit clock, and the IO waveform signal will not be recorded in the sampling RAM; If the asynchronous sampling mode is selected, the frequency division of the local phase-locked loop is used as the clock signal. According to the configuration, the edge of the user-defined sensitive clock IO waveform signal is used as the synchronization signal of the divider. The IO waveform signal will be recorded into the sampling RAM as a channel. (3b) The output sampling module starts working, samples the output of the IO waveform signal of the device under test and saves it into the sampling RAM, and completes the setting of the flag signal; Step 4: Check the sample RAM: The error detection module compares the value of the expected RAM with the value of the sampled RAM bit by bit; the number of edges in the expected RAM and the sampled RAM before different bit values ​​in each comparison result are counted respectively, and saved in the expected edge counter and the sampled edge counter respectively; Step 5, the error detection module fixes the RAM pointer that generates the edge, searches another RAM, and determines whether an edge is found whose edge direction is the same as the edge direction of the fixed RAM and makes the value of the search edge counter equal to the value of the fixed edge counter. If so, execute step 6, otherwise, execute step 7; Step 6, handle timing errors: (6a) If the value of the pointer of the expected RAM is greater than the value of the pointer of the sampled RAM, the error type of the bit is determined to be timing advance, and the difference between the pointer of the sampled RAM and the pointer of the expected RAM is taken as the offset; (6b) If the value of the pointer of the expected RAM is less than the value of the pointer of the sampled RAM, the error type of the bit is determined to be timing delay, and the difference between the pointer of the expected RAM and the pointer of the sampled RAM is taken as the offset; Step 7, handle pulse errors: If searching forward and backward respectively cannot make the value of the search edge counter equal to the value of the fixed edge counter, the error type of the bit of the sampling RAM is an error pulse or glitch; the value of the sampling edge counter is assigned to the expected edge counter; Step 8: Report the results to the user: After the error detection module processes all bits of the sampling RAM, the communication module reads the recorded content from the error detection module and sends it to the host computer.

3. A digital signal testing method based on FPGA according to claim 2, characterized in that: The trigger signal described in step (2b) is a periodic signal using a clock source or a single pulse signal generated using a flag bit; the input analog module generates a periodic trigger signal by selecting the clock source, generates a single pulse signal by using a register flag bit, and determines the final output signal through a multiplexer.

4. The FPGA-based digital signal testing method according to claim 2, characterized in that: The search described in step 5 means that the search pointer is moved forward, and each time an edge is encountered, the value of the search edge counter is decremented by 1 until an edge with the same direction as the edge of the RAM with a fixed address is found or the starting position of the RAM is reached; the search pointer is moved backward, and each time an edge is encountered, the value of the search edge counter is incremented by 1 until an edge with the same direction as the edge of the RAM with a fixed address is found or the end position of the RAM is reached.

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