A circuit simulation method and apparatus

Abstract

Embodiments of the present application provide a circuit simulation method and device, the first to be tested circuit includes the first digital circuit and the first analog circuit, after using the simulation EDA tool to carry out the simulation operation to the first to be tested circuit, obtain the first simulation configuration script, the first simulation configuration script includes the first configuration information of the simulation operation, after the first digital circuit is optimized to the second digital circuit, obtain the second to be tested circuit including the second digital circuit and the first analog circuit, obtain the second simulation configuration script, the second simulation configuration script is obtained by updating the first simulation configuration script, and the second simulation configuration script includes the second configuration information, then the second simulation configuration script can be run to use the second configuration information to call the simulation EDA tool to carry out the simulation operation to the second to be tested circuit, so that the simulation operation is carried out by the script of the configuration information to replace the storage position of the digital circuit related file, the efficiency and accuracy of the digital circuit unit update are realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a circuit simulation method and device. BACKGROUND

[0002] With the development of the complexity of integrated circuit design, many integrated circuit designs are not limited to pure digital circuit design or analog circuit design, but tend to be mixed design of digital circuit and analog circuit. The development trend of mixed digital and analog circuit design drives the continuous development of mixed digital and analog circuit simulation verification.

[0003] Currently, for simulation of mixed digital and analog circuit, a simulation electronic design automation (EDA) tool for analog circuit design is needed, which can directly call the data of the analog circuit, and for the digital circuit part, simulation staff needs to create corresponding libraries and digital circuit units in the simulation EDA tool and edit the RTL form to integrate and call the digital circuit units.

[0004] In the circuit design verification process, with the simulation verification, the update and modification of the circuit are inevitable. If it is only the simulation of the pure analog circuit, the modification of the internal circuit in the later stage can be realized by automatically calling the new data of the analog circuit in the simulation system to update, so as to not affect the accuracy and real-time performance of the data of the analog circuit in the simulation system.

[0005] However, for the mixed digital and analog circuit simulation system, when the digital circuit design engineer makes changes to the local digital circuit RTL, in order to synchronize the changes to the current simulation system, the simulation staff needs to create corresponding libraries and digital circuit unit pages in the simulation EDA tool, and make synchronous changes to the previously created digital circuit units, which is a complex and inefficient operation process and is prone to errors. SUMMARY

[0006] To solve the above technical problems, the embodiments of the present application provide a circuit simulation method and device, which realize the efficiency and accuracy of digital circuit unit update and improve the development progress.

[0007] The embodiments of the present application provide a circuit simulation method, which comprises:

[0008] After simulation operation is performed on the first to-be-tested circuit by using the simulation EDA tool, a first simulation configuration script is acquired; the first to-be-tested circuit comprises a first digital circuit and a first analog circuit; the first simulation configuration script comprises first configuration information of the simulation operation, and the first configuration information comprises a storage location of a verilog netlist of the first digital circuit, which is generated by the simulation operation;

[0009] After the first digital circuit is optimized into a second digital circuit, a second to-be-tested circuit comprising the second digital circuit and the first analog circuit is obtained, and a second simulation configuration script is acquired; the second simulation configuration script is obtained by updating the first simulation configuration script, wherein the second simulation configuration script comprises second configuration information, and the storage location of the verilog netlist of the first digital circuit in the first configuration information is updated into a storage location of a verilog code file of the second digital circuit to obtain the second configuration information;

[0010] The second simulation configuration script is run to perform simulation operation on the second to-be-tested circuit by using the simulation EDA tool according to the second configuration information.

[0011] Optionally, the first configuration information and the second configuration information further comprise a storage location of a netlist of the first analog circuit.

[0012] Optionally, the method further comprises:

[0013] After the first analog circuit is optimized into a second analog circuit, a third to-be-tested circuit comprising the second analog circuit and the second digital circuit is obtained, and a netlist of the first analog circuit is replaced with a netlist of the second analog circuit at the storage location of the first analog circuit; a third simulation configuration script is acquired, which is obtained by updating the second simulation configuration script, wherein the third simulation configuration script comprises third configuration information, and the storage location of the netlist of the first analog circuit in the second configuration information is replaced with a storage location of the netlist of the second analog circuit to obtain the third configuration information;

[0014] The third simulation configuration script is run to perform simulation operation on the third to-be-tested circuit by using the simulation EDA tool according to the third configuration information.

[0015] Optionally, the first configuration information further comprises a storage location of a simulation system top-level netlist, a storage location of a verilog code of an outsourcing test item layer of the first digital circuit, and a storage location of a netlist of an excitation circuit, wherein the excitation circuit is configured to provide an excitation signal.

[0016] Optionally, the first simulation configuration script further comprises simulation configuration information for simulating the third analog circuit.

[0017] Embodiments of the present application provide a circuit simulation device, comprising:

[0018] The first script obtaining unit is configured to obtain a first simulation configuration script after simulating the first digital circuit and the first analog circuit by using the simulation EDA tool.

[0019] The second script obtaining unit is configured to obtain a second simulation configuration script after the first digital circuit is optimized into a second digital circuit, wherein the second simulation configuration script is obtained by updating the first simulation configuration script.

[0020] The script running unit is configured to run the second simulation configuration script to simulate the second digital circuit and the first analog circuit by using the simulation EDA tool.

[0021] Optionally, the first configuration information and the second configuration information further comprise a storage location of a netlist of the first analog circuit.

[0022] Optionally, the device further comprises:

[0023] The third script obtaining unit is configured to obtain a third simulation configuration script after the first analog circuit is optimized into a second analog circuit, wherein the third simulation configuration script is obtained by updating the second simulation configuration script.

[0024] The script running unit is further configured to run the third simulation configuration script to invoke the simulation EDA tool to perform simulation operation on the third to-be-tested circuit by using the third configuration information.

[0025] Optionally, the first configuration information further includes a storage location of a simulation system top-level netlist, a storage location of a verilog code of an external test item layer of the first digital circuit, and a storage location of a netlist of a stimulus circuit, the stimulus circuit being configured to provide a stimulus signal.

[0026] Optionally, the first simulation configuration script further includes analog configuration information used for performing simulation operation on the third analog circuit.

[0027] Embodiments of the present application provide a circuit simulation method and device, which perform simulation operation on a first to-be-tested circuit by using a simulation EDA tool, the first to-be-tested circuit including a first digital circuit and a first analog circuit, the simulation operation generating a verilog netlist of the first digital circuit, after performing simulation operation on the first to-be-tested circuit, a first simulation configuration script can be obtained, the first simulation configuration script including first configuration information of the simulation operation, the first configuration information including a storage location of the verilog netlist of the first digital circuit, after the first digital circuit is optimized into a second digital circuit, a second to-be-tested circuit including the second digital circuit and the first analog circuit is obtained, a second simulation configuration script is obtained, the second simulation configuration script being obtained by updating the first simulation configuration script, wherein the second simulation configuration script includes second configuration information, the storage location of the verilog netlist of the first digital circuit in the first configuration information is updated into a storage location of a verilog code file of the second digital circuit to obtain the second configuration information, and then the second simulation configuration script can be run to invoke the simulation EDA tool to perform simulation operation on the second to-be-tested circuit by using the second configuration information, so that the storage location of the digital circuit related file is replaced by scripting of the configuration information, the simulation EDA tool called can obtain the verilog code file of the second digital circuit based on the storage location of the verilog code file of the second digital circuit in the second simulation configuration script and perform simulation operation, without the need for simulation staff to add a digital circuit unit according to the verilog code file of the second digital circuit to input information of the second digital circuit, thereby avoiding circuit modification errors caused by human modification of the circuit by the simulation staff, reducing error checking time caused by such errors, realizing efficiency and accuracy of digital circuit unit updating, and improving development progress. In addition, the fixed script template enhances the portability of different projects, saves the time for starting and debugging of the simulation tool graphical interface, helps to reduce the difficulty of simulation of the digital-analog mixed circuit system, and can shorten the development cycle of the digital-analog mixed circuit design to a certain extent. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to make the technical solutions in the embodiments of the present application clearer, the accompanying drawings needed in the embodiment description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments described in the present application, and other accompanying drawings can be obtained by those skilled in the art based on these accompanying drawings.

[0029] Figure 1 A flow chart of a circuit simulation method provided by the embodiments of the present application;

[0030] Figure 2 A simulation environment structure schematic diagram provided by the embodiments of the present application;

[0031] Figure 3 A structure block diagram of a circuit simulation device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0032] In order to make the technical solutions in the embodiments of the present application clearer, the accompanying drawings needed in the embodiment description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments described in the present application, and other accompanying drawings can be obtained by those skilled in the art based on these accompanying drawings.

[0033] At present, for the simulation of digital-analog hybrid circuit, a simulation EDA tool designed for analog circuit needs to be used, which can directly call the data of analog circuit, and for the digital circuit part, simulation staff needs to create corresponding library and digital circuit unit in the simulation EDA tool, and edit the form of RTL to integrate and call the digital circuit unit.

[0034] In the circuit design verification process, with the simulation verification, the update and modification of the circuit are inevitable. If it is only the simulation of analog circuit, the internal modification of the circuit in the later stage can be realized by automatically calling the new data of analog circuit in the simulation system to update, thus not affecting the accuracy and real-time performance of the data of analog circuit in the simulation system.

[0035] However, for the mixed analog-digital circuit simulation system, when the digital circuit design engineer makes changes to the local digital circuit RTL, in order to synchronize the changes to the current simulation system, the simulation staff needs to create the corresponding library and the page of the digital circuit unit in the simulation EDA tool, and make synchronous changes to the previously created digital circuit unit. Each update needs to open the user interface mode of the simulation EDA software, which is single in means and complex and inefficient in operation process. In addition, since the digital circuit unit in the simulation system is updated by the simulation staff according to the changes of the actual design engineer, the probability of error is high, and the situation that the digital circuit unit in the simulation system does not match the digital circuit unit designed by the actual design engineer is easy to occur, which increases the difficulty of error checking in the later simulation verification process, and to some extent, affects the progress of the entire development.

[0036] To solve the above technical problems, the circuit simulation method and device provided in the embodiments of the present application are used to simulate the first to-be-tested circuit by using a simulation EDA tool, the first to-be-tested circuit comprising a first digital circuit and a first analog circuit, the simulation operation generating a verilog netlist of the first digital circuit, and after one simulation operation is performed on the first to-be-tested circuit, a first simulation configuration script can be obtained, the first simulation configuration script comprising first configuration information of the simulation operation, the first configuration information comprising a storage location of the verilog netlist of the first digital circuit, after the first digital circuit is optimized into a second digital circuit, a second to-be-tested circuit comprising the second digital circuit and the first analog circuit is obtained, a second simulation configuration script is obtained, the second simulation configuration script being obtained by updating the first simulation configuration script, wherein the second simulation configuration script comprises second configuration information, the storage location of the verilog netlist of the first digital circuit in the first configuration information is updated into a storage location of a verilog code file of the second digital circuit to obtain the second configuration information, and then the second simulation configuration script can be run to call the simulation EDA tool to perform a simulation operation on the second to-be-tested circuit by using the second configuration information. In this way, the storage location of the digital circuit related file is replaced by scripting the configuration information, and the simulation EDA tool called can obtain the verilog code file of the second digital circuit based on the storage location of the verilog code file of the second digital circuit in the second simulation configuration script and perform a simulation operation, without the need for a simulation worker to add a digital circuit unit according to the verilog code file of the second digital circuit to input the information of the second digital circuit, thereby avoiding circuit modification errors caused by human modification of the circuit, reducing the error checking time caused by such errors, improving the efficiency and accuracy of the update of the digital circuit unit, and improving the development progress. In addition, the fixed script template enhances the portability of different projects, saves the time for starting and debugging the graphical interface of the simulation tool, helps to reduce the difficulty of simulation of the digital-analog hybrid circuit system, and can shorten the development cycle of the digital-analog hybrid circuit design to a certain extent.

[0037] The specific implementation of the circuit simulation method and device in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0038] Reference Figure 1 As shown in FIG. 1, the flowchart of the circuit simulation method provided in the embodiments of the present application can comprise the following steps:

[0039] S101, after the simulation EDA tool is used to simulate the first to-be-tested circuit, a first simulation configuration script is obtained.

[0040] In the embodiments of the present application, the first to-be-tested circuit can include a first digital circuit and a first analog circuit, and can be an initial circuit for completing design or an optimized circuit. In the embodiments of the present application, the simulation EDA tool can be used to perform simulation operation on the first to-be-tested circuit, so that the performance parameters of the first to-be-tested circuit can be obtained, and then the first to-be-tested circuit can be optimized according to the performance parameters of the first to-be-tested circuit, for example, the first digital circuit in the first to-be-tested circuit can be optimized, or the first analog circuit in the first to-be-tested circuit can be optimized.

[0041] Before the simulation EDA tool is used to perform simulation operation on the first to-be-tested circuit, the simulation system can be built.

[0042] Specifically, before the simulation EDA tool is used to perform simulation operation on the first to-be-tested circuit, the information of the first to-be-tested circuit can be imported into the simulation EDA tool, that is, the information of the first digital circuit and the information of the first analog circuit can be imported into the simulation EDA tool. The information of the first analog circuit can be obtained by the simulation EDA tool automatically reading, and the information of the first digital circuit needs a simulation staff to create a corresponding library and a digital circuit unit in the simulation EDA tool, and edit the form of RTL to integrate and call the digital circuit unit.

[0043] Specifically, before the simulation EDA tool is used to perform simulation operation on the first to-be-tested circuit, configuration information of the simulation operation can also be set, so that the simulation EDA tool can perform simulation operation on the first to-be-tested circuit according to the configuration information. The configuration information can be, for example, a model file required for simulation, a script used in a simulation process, a simulation running position and a simulation result generation position, a storage position of a user-defined configuration file and the like, so that the simulation EDA tool can call the required files to perform simulation operation on the first to-be-tested circuit according to the configuration information.

[0044] Reference Figure 2As shown, a simulation environment structure provided by the embodiment of the present application is shown, and the simulation environment structure includes a database (Database) which includes a model (Models) folder, a script (Script) folder, a simulation (Simulation) folder, a circuit information (Src) folder and a user-defined (User_define) folder, etc. The model folder is used to store all model files required by simulation, the script folder is used to store all scripts used in the simulation process, the simulation folder is the simulation running position and the simulation result generation position, the circuit information folder is used to store the information of the first digital circuit and the information of the first analog circuit used in the simulation, and the user-defined folder stores the configuration files required to be defined by the user in the simulation process. The information of the first digital circuit includes the RTL code file or the RTL netlist of the first digital circuit, and the information of the first analog circuit includes the RTL code file or the RTL netlist of the first analog circuit.

[0045] Specifically, before the simulation EDA tool is used to perform the simulation operation on the first to-be-tested circuit, the information of the excitation circuit can also be set. The excitation circuit is used to provide the excitation signal. When the simulation EDA tool is used to perform the simulation operation on the first to-be-tested circuit, the excitation circuit is used to provide the excitation signal for the first to-be-tested circuit. The simulation operation on the first to-be-tested circuit is to simulate the response signal generated by the first to-be-tested circuit under the action of the excitation signal. Through the analysis of the response signal, the simulation operation result of the first to-be-tested circuit can be obtained. The simulation operation result of the first to-be-tested circuit reflects the performance parameters of the first to-be-tested circuit.

[0046] After the simulation EDA tool performs the simulation operation on the first to-be-tested circuit, the simulation EDA tool can automatically generate the simulation data. The simulation data includes the simulation system top-level netlist, the outsourcing test top-level verilog code of the first digital circuit, the verilog netlist of the first digital circuit, the netlist of the analog circuit and the netlist of the excitation circuit, etc.

[0047] After the simulation operation on the first to-be-tested circuit by the simulation EDA tool, a first simulation configuration script can be obtained, the first simulation configuration script can include first configuration information of the simulation operation, the first configuration information of the simulation operation includes each configuration information of the simulation operation, or can only include part of the configuration information. In the embodiment of the application, the first configuration information can include a storage location of simulation data, for example, the first configuration information includes a storage location of a verilog netlist of the first digital circuit, and the verilog netlist of the first digital circuit is generated by the simulation operation. That is, after the simulation operation on the first to-be-tested circuit by the simulation EDA tool, the first simulation configuration script can be formed according to the configuration information of the simulation operation, and the first simulation configuration script includes the configuration information of the simulation operation, so that running the first simulation configuration script can perform the simulation operation on the first to-be-tested circuit according to the first configuration information.

[0048] In the embodiment of the application, the first configuration information can also include a storage location of other simulation data, for example, a storage location of a netlist of the first analog circuit, in some embodiments, the first configuration information can also include a storage location of a simulation system top-level netlist, a storage location of a test item layer verilog code of the first digital circuit, and a storage location of a netlist of a stimulus circuit, etc., and the stimulus circuit is used to provide a stimulus signal.

[0049] In the embodiment of the application, the first simulation configuration script can be generated by a worker according to the configuration information of the simulation operation on the first to-be-tested circuit by the simulation EDA tool. The first configuration information and the simulation option configuration when the simulation operation on the first to-be-tested circuit are consistent. The first simulation configuration script can be stored in a simulation folder.

[0050] S102, after the first digital circuit is optimized to the second digital circuit, a second to-be-tested circuit including the second digital circuit and the first analog circuit is obtained, and a second simulation configuration script is obtained.

[0051] In the embodiment of the application, the first digital circuit can be optimized to the second digital circuit, that is, the first to-be-tested circuit including the first digital circuit and the first analog circuit is optimized to the second to-be-tested circuit including the second digital circuit and the first analog circuit. Since the first digital circuit is updated, in the prior art, a simulation worker needs to create a corresponding library and a page of a digital circuit unit in the simulation EDA tool, and synchronously change the previously created digital circuit unit. Each time the update needs to open a user interface mode of the simulation EDA software, and the probability of error is relatively high.

[0052] In the embodiments of the present application, the second simulation configuration script can be obtained after the first digital circuit is optimized into the second digital circuit, and the second simulation configuration script is obtained by updating the first simulation configuration script, wherein the second simulation configuration script includes second configuration information, and the storage location of the verilog netlist of the first digital circuit in the first configuration information is updated to the storage location of the verilog code file of the second digital circuit to obtain the second configuration information. That is, after the simulation operation is performed on the first to-be-tested circuit, the first simulation configuration script is generated, and after the first to-be-tested circuit is optimized to obtain the second to-be-tested circuit, the first simulation configuration script can be updated to obtain the second simulation configuration script. Through the scripting of the configuration file, after the digital circuit is changed, the storage location of the verilog netlist of the first digital circuit in the first simulation configuration script corresponds to the first digital circuit in the first to-be-tested circuit, and the storage location of the verilog code file of the second digital circuit in the second simulation configuration script corresponds to the second digital circuit in the second to-be-tested circuit. By changing the storage location of the related file of the digital circuit in the script, the updating of the configuration information of the simulation operation can be realized, and the operation is simplified.

[0053] In S103, the second simulation configuration script is run to call the simulation EDA tool to perform a simulation operation on the second to-be-tested circuit by using the second configuration information.

[0054] In the embodiments of the present application, the second simulation configuration script includes the storage location of the verilog code file of the second digital circuit, so that when the second simulation configuration script is run, the simulation EDA tool can be called to perform a simulation operation on the second to-be-tested circuit by using the second configuration information. Specifically, the simulation EDA tool can obtain the verilog code file of the second digital circuit according to the storage location of the verilog code file of the second digital circuit in the second configuration information, and the digital circuit is replaced quickly by using the file replacement mode, so that the information of the second digital circuit is obtained without driving the graphical interface of the simulation EDA tool, manually creating the corresponding library and the page of the digital circuit unit in the simulation EDA tool, and synchronously modifying the previously created digital circuit unit, thereby simplifying the operation. In addition, the verilog code file is a file generated by an actual design engineer, and the file is directly called without modification, which reduces the possibility of errors.

[0055] In the embodiments of the present application, the analog circuit can also be optimized. Since the information of the analog circuit can be automatically read by the simulation EDA tool, the netlist of the old analog circuit can be replaced with the netlist of the new analog circuit at the storage location of the analog circuit, and the storage location of the netlist of the old analog circuit in the script can be replaced with the storage location of the netlist of the new analog circuit.

[0056] Specifically, after the first analog circuit is optimized to the second analog circuit, a third to-be-tested circuit including the second analog circuit and the second digital circuit can be obtained, the netlist of the first analog circuit is replaced by the netlist of the second analog circuit at the storage location of the first analog circuit, and a third simulation configuration script is obtained, the third simulation configuration script being obtained by updating the second simulation configuration script, wherein the third simulation configuration script includes third configuration information, and the third configuration information is obtained by replacing the storage location of the netlist of the first analog circuit in the second configuration information by the storage location of the netlist of the second analog circuit. Then, the third simulation configuration script can be run to call the simulation EDA tool to perform simulation operation on the third to-be-tested circuit by using the third configuration information.

[0057] Specifically, after the first analog circuit is optimized to the second analog circuit, a fourth to-be-tested circuit including the second analog circuit and the first digital circuit can be obtained, the netlist of the first analog circuit is replaced by the netlist of the second analog circuit at the storage location of the first analog circuit, and a fourth simulation configuration script is obtained, the fourth simulation configuration script being obtained by updating the first simulation configuration script, wherein the fourth simulation configuration script includes fourth configuration information, and the fourth configuration information is obtained by replacing the storage location of the netlist of the first analog circuit in the first configuration information by the storage location of the netlist of the second analog circuit. Then, the fourth simulation configuration script can be run to call the simulation EDA tool to perform simulation operation on the fourth to-be-tested circuit by using the fourth configuration information.

[0058] In the embodiments of the present application, the first simulation configuration script further includes analog configuration information for performing simulation operation on the third analog circuit, so that when the circuit to be simulated includes a digital circuit and an analog circuit, the first configuration information in the first simulation configuration script is used to perform simulation operation on the circuit to be simulated, and when the circuit to be simulated only includes an analog circuit, the analog configuration information in the first simulation configuration script is used to perform simulation operation on the circuit to be simulated. The second simulation configuration script, the third simulation configuration script, and the like are the same.

[0059] Therefore, running the first simulation configuration script can first determine whether the current simulation is a mixed analog-digital circuit or an analog circuit, if it is a mixed analog-digital circuit simulation, the first configuration information will be used for simulation operation, and if it is an analog simulation, the analog configuration information will be used for simulation operation. According to the setting of the simulation option in the first simulation configuration script, the first simulation configuration script can automatically generate another command line option set that can be implemented by the simulation EDA tool, and the option set includes the first configuration information or the analog configuration information set in the first simulation configuration script, so that the simulation command of the simulation tool is started according to the option set generated by the first simulation configuration script to call the simulation EDA tool to perform simulation operation on the circuit to be simulated. The second simulation configuration script, the third simulation configuration script, and the like are the same.

[0060] The embodiment of the present application provides a circuit simulation method, a simulation EDA tool is used to perform simulation operation on a first to-be-tested circuit, the first to-be-tested circuit comprises a first digital circuit and a first analog circuit, the simulation operation generates a verilog netlist of the first digital circuit, after performing one simulation operation on the first to-be-tested circuit, a first simulation configuration script can be acquired, the first simulation configuration script comprises first configuration information of the simulation operation, the first configuration information comprises a storage location of the verilog netlist of the first digital circuit, after the first digital circuit is optimized into a second digital circuit, a second to-be-tested circuit comprising the second digital circuit and the first analog circuit is obtained, a second simulation configuration script is acquired, the second simulation configuration script is obtained by updating the first simulation configuration script, wherein the second simulation configuration script comprises second configuration information, the storage location of the verilog netlist of the first digital circuit in the first configuration information is updated into a storage location of a verilog code file of the second digital circuit to obtain the second configuration information, and then the second simulation configuration script can be run to call the simulation EDA tool to perform simulation operation on the second to-be-tested circuit by using the second configuration information, so that the storage location of the digital circuit related file is replaced through the scripting of the configuration information, the simulation EDA tool called can acquire the verilog code file of the second digital circuit based on the storage location of the verilog code file of the second digital circuit in the second simulation configuration script and perform simulation operation, without the need for a simulation worker to add a digital circuit unit according to the verilog code file of the second digital circuit to input the information of the second digital circuit, thereby avoiding circuit modification errors caused by manual modification of the circuit by the simulation worker, reducing error checking time caused by such errors, realizing the efficiency and accuracy of the digital circuit unit update, and improving the development progress. In addition, the fixed script template enhances the portability of different projects, saves the time for starting and debugging the simulation tool graphical interface, helps to reduce the difficulty of mixed digital-analog circuit system simulation, and can shorten the development cycle of the mixed digital-analog circuit design to a certain extent.

[0061] Based on the above three-dimensional reconstruction method, the embodiment of the present application further provides a circuit simulation device, referring to Figure 3 The device can comprise:

[0062] The first script acquisition unit 110 is configured to acquire a first simulation configuration script after performing simulation operation on the first to-be-tested circuit by using the simulation EDA tool; the first to-be-tested circuit comprises a first digital circuit and a first analog circuit; the first simulation configuration script comprises first configuration information of the simulation operation, and the first configuration information comprises a storage location of a verilog netlist of the first digital circuit, wherein the verilog netlist of the first digital circuit is generated by the simulation operation.

[0063] The second script obtaining unit 120 is configured to obtain a second simulation configuration script after the first digital circuit is optimized into a second digital circuit, the second simulation configuration script being obtained by updating the first simulation configuration script, wherein the second simulation configuration script comprises second configuration information, and the first configuration information is updated by replacing a storage location of a verilog netlist of the first digital circuit with a storage location of a verilog code file of the second digital circuit to obtain the second configuration information.

[0064] The script running unit 130 is configured to run the second simulation configuration script to call the simulation EDA tool to perform simulation operation on the second digital circuit by using the second configuration information.

[0065] Optionally, the first configuration information and the second configuration information further comprise a storage location of a netlist of the first analog circuit.

[0066] Optionally, the apparatus further comprises:

[0067] The third script obtaining unit is configured to obtain a third simulation configuration script after the first analog circuit is optimized into a second analog circuit, the third simulation configuration script being obtained by updating the second simulation configuration script, wherein the third simulation configuration script comprises third configuration information, and the third configuration information is obtained by replacing the storage location of the netlist of the first analog circuit in the second configuration information with a storage location of a netlist of the second analog circuit.

[0068] The script running unit is further configured to run the third simulation configuration script to call the simulation EDA tool to perform simulation operation on the third digital circuit by using the third configuration information.

[0069] Optionally, the first configuration information further comprises a storage location of a simulation system top-level netlist, a storage location of a third-party test item layer verilog code of the first digital circuit, and a storage location of a netlist of an excitation circuit, the excitation circuit being configured to provide an excitation signal.

[0070] Optionally, the first simulation configuration script further comprises analog configuration information used for performing simulation operation on a third analog circuit.

[0071] The embodiment of the application provides a circuit simulation device, which utilizes a simulation EDA tool to perform simulation operation on a first to-be-tested circuit, the first to-be-tested circuit comprising a first digital circuit and a first analog circuit, the simulation operation generates a verilog netlist of the first digital circuit, after performing the simulation operation on the first to-be-tested circuit, a first simulation configuration script can be acquired, the first simulation configuration script comprises first configuration information of the simulation operation, the first configuration information comprises a storage location of the verilog netlist of the first digital circuit, after the first digital circuit is optimized into a second digital circuit, a second to-be-tested circuit comprising the second digital circuit and the first analog circuit is obtained, a second simulation configuration script is acquired, the second simulation configuration script is obtained by updating the first simulation configuration script, wherein the second simulation configuration script comprises second configuration information, the storage location of the verilog netlist of the first digital circuit in the first configuration information is updated into a storage location of a verilog code file of the second digital circuit to obtain the second configuration information, and then the second simulation configuration script can be run to utilize the second configuration information to call the simulation EDA tool to perform simulation operation on the second to-be-tested circuit, so that the storage location of the digital circuit related file is replaced through the scripting of the configuration information, the simulation EDA tool called can acquire the verilog code file of the second digital circuit based on the storage location of the verilog code file of the second digital circuit in the second simulation configuration script and perform simulation operation, without the need of a simulation staff to add a digital circuit unit according to the verilog code file of the second digital circuit to input the information of the second digital circuit, thereby avoiding circuit modification errors caused by manual modification of the circuit by the simulation staff, reducing error checking time caused by such errors, realizing the efficiency and accuracy of the update of the digital circuit unit, and improving the development progress. In addition, the fixed script template enhances the portability of different projects, saves the time for starting and debugging of the simulation tool graphical interface, helps to reduce the simulation difficulty of the digital-analog mixed circuit system, and can shorten the development cycle of the digital-analog mixed circuit design to a certain extent.

[0072] The "first" in the names such as "first digital circuit" and "first analog circuit" mentioned in the embodiment of the application is only used for name identification, and does not represent the first in sequence. The same rule applies to "second" and the like.

[0073] Those skilled in the art can clearly understand that all or part of the steps of the above-mentioned method in the embodiments can be implemented by means of software plus a general hardware platform, from the description of the above-mentioned embodiments. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product. The computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments.

[0074] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, they are described more simply, and the relevant parts can be referred to the part of the method embodiments. The above-described device and system embodiments are only schematic, and the modules shown as separate components can or can not be physically separated, and the components shown as modules can or can not be physical modules, i.e. they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiments according to the actual needs. Those skilled in the art can understand and implement it without creative labor.

[0075] The above is only the preferred embodiment of the present application, and is not used to limit the protection scope of the present application. It should be pointed out that, for those skilled in the art, without departing from the present application, a number of improvements and refinements can be made, and these improvements and refinements should be regarded as the protection scope of the present application.

Claims

1. A circuit simulation method, characterized by, Comprising: After simulation operation is performed on the first to-be-tested circuit by using the simulation EDA tool, a first simulation configuration script is acquired; wherein the first to-be-tested circuit comprises a first digital circuit and a first analog circuit; the first simulation configuration script comprises first configuration information of the simulation operation, and the first configuration information comprises a storage location of a verilog netlist of the first digital circuit and a storage location of a netlist of the first analog circuit, the verilog netlist of the first digital circuit being generated by the simulation operation; By optimizing the first digital circuit into a second digital circuit, a second to-be-tested circuit comprising the second digital circuit and the first analog circuit is acquired; According to the second to-be-tested circuit, a second simulation configuration script is acquired; wherein the second simulation configuration script is obtained by updating the first simulation configuration script, the second simulation configuration script comprises second configuration information, and the second configuration information comprises a storage location of a verilog netlist of the second digital circuit, the storage location of the verilog netlist of the second digital circuit being obtained by updating the storage location of the verilog netlist of the first digital circuit; The second simulation configuration script is run to call the simulation EDA tool to perform simulation operation on the second to-be-tested circuit by using the second configuration information; By optimizing the first analog circuit into a second analog circuit, a third to-be-tested circuit comprising the second digital circuit and the second analog circuit is acquired; According to the third to-be-tested circuit, a third simulation configuration script is acquired; wherein the third simulation configuration script is obtained by updating the second simulation configuration script, the third simulation configuration script comprises third configuration information, and the third configuration information comprises a storage location of a netlist of the second analog circuit, the storage location of the netlist of the second analog circuit being obtained by updating the storage location of the netlist of the first analog circuit; The third simulation configuration script is run to call the simulation EDA tool to perform simulation operation on the third to-be-tested circuit by using the third configuration information.

2. The method of claim 1, wherein, The first configuration information further comprises a storage location of a simulation system top-level netlist, a storage location of a third-party test item layer verilog code of the first digital circuit, and a storage location of a netlist of an excitation circuit, and the excitation circuit is configured to provide an excitation signal.

3. The method of claim 1, wherein, The first simulation configuration script further comprises analog configuration information used for performing simulation operation on a third analog circuit.

4. A circuit emulation device, comprising: Comprising: A first script acquisition unit is configured to acquire a first simulation configuration script after simulation operation is performed on a first to-be-tested circuit by using a simulation EDA tool; wherein the first to-be-tested circuit comprises a first digital circuit and a first analog circuit; the first simulation configuration script comprises first configuration information of the simulation operation, and the first configuration information comprises a storage location of a verilog netlist of the first digital circuit and a storage location of a netlist of the first analog circuit, the verilog netlist of the first digital circuit being generated by the simulation operation; The second script acquisition unit is configured to acquire a second to-be-tested circuit including the second digital circuit and the first analog circuit by optimizing the first digital circuit into the second digital circuit. The second script acquisition unit is further configured to acquire a second simulation configuration script according to the second to-be-tested circuit, wherein the second simulation configuration script is obtained by updating the first simulation configuration script, and the second simulation configuration script includes second configuration information, and the second configuration information includes a storage location of a verilog netlist of the second digital circuit, and the storage location of the verilog netlist of the second digital circuit is obtained by updating a storage location of a verilog netlist of the first digital circuit. The script running unit is configured to run the second simulation configuration script to call the simulation EDA tool to perform a simulation operation on the second to-be-tested circuit by using the second configuration information. The third script acquisition unit is configured to acquire a third to-be-tested circuit including the second digital circuit and a second analog circuit by optimizing the first analog circuit into the second analog circuit. The third script acquisition unit is further configured to acquire a third simulation configuration script according to the third to-be-tested circuit, wherein the third simulation configuration script is obtained by updating the second simulation configuration script, and the third simulation configuration script includes third configuration information, and the third configuration information includes a storage location of a netlist of the second analog circuit, and the storage location of the netlist of the second analog circuit is obtained by updating a storage location of a netlist of the first analog circuit. The script running unit is further configured to run the third simulation configuration script to call the simulation EDA tool to perform a simulation operation on the third to-be-tested circuit by using the third configuration information.

5. The apparatus of claim 4, wherein, The first configuration information further includes a storage location of a simulation system top-level netlist, a storage location of a third-party test item layer verilog code of the first digital circuit, and a storage location of a netlist of an excitation circuit, and the excitation circuit is configured to provide an excitation signal.

6. The apparatus of claim 4, wherein, The first simulation configuration script further includes analog configuration information used for performing a simulation operation on a third analog circuit.

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