Read threshold optimization system and method using model-free regression

Abstract

The present invention relates to a read threshold optimization system and method. A controller optimizes read thresholds of a memory device using model-free regression. The controller performs a read operation on a cell using a read threshold voltage value. The controller measures a probability value for a plurality of read threshold voltage values and estimates a threshold voltage distribution curve based on the plurality of read threshold voltage values and the measured probability values using a set regression formula. The controller determines a read threshold voltage value corresponding to a set point on the threshold voltage distribution curve and performs a read operation on the cell using the read threshold voltage value.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a scheme for optimizing read thresholds in a memory system. Background Technology

[0002] The computing environment paradigm has evolved into ubiquitous computing, enabling computer systems to be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices, or data storage devices. These data storage devices are used as either the main memory or secondary memory devices of the portable electronic devices.

[0003] Because memory systems using memory devices have no moving parts, they offer excellent stability, durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and Solid State Drives (SSDs). Memory systems can perform read operations using a variety of read thresholds. Summary of the Invention

[0004] Aspects of the present invention include a memory system and method for optimizing read thresholds using model-less regression.

[0005] On one hand, a memory system includes: a memory device comprising a plurality of cells; and a controller. The controller performs a plurality of read operations on the plurality of cells using a plurality of read threshold voltage values, measures probability values ​​of the plurality of read threshold voltage values, estimates a threshold voltage distribution curve based on the plurality of read threshold voltage values ​​and the measured probability values ​​using a set regression formula, determines a read threshold voltage value corresponding to a set point on the threshold voltage distribution curve, and performs read operations on the plurality of cells using the read threshold voltage values.

[0006] On the other hand, a method for operating a memory system includes: performing multiple read operations on multiple cells using multiple read threshold voltage values; measuring probability values ​​of the multiple read threshold voltage values; estimating a threshold voltage distribution curve based on the multiple read threshold voltage values ​​and the measured probability values ​​using a set regression formula; determining a read threshold voltage value corresponding to a set point on the threshold voltage distribution curve; and performing read operations on the multiple cells using the read threshold voltage values.

[0007] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0008] Figure 1This is a block diagram illustrating a data processing system according to an embodiment of the present invention.

[0009] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention.

[0011] Figure 4 It is a diagram showing the state distribution of different types of cells in a memory device.

[0012] Figure 5 This is a diagram illustrating a memory system according to an embodiment of the present invention.

[0013] Figure 6 This is a diagram illustrating an example of Gray code for a three-layer cell (TLC).

[0014] Figure 7 This is a diagram showing the state distribution of pages in a three-layer cell (TLC).

[0015] Figure 8 An example of the distribution of the overall read threshold (Vt) is shown.

[0016] Figures 9A to 10 The operation of a read threshold optimizer according to an embodiment of the present invention is shown.

[0017] Figure 11A A comparison between the estimated read threshold (Vt) distribution and the actual read threshold (Vt) distribution according to an embodiment of the present invention is shown.

[0018] Figure 11B A comparison between the estimated read threshold (Vt) distribution and the actual read threshold (Vt) distribution according to an embodiment of the present invention is shown.

[0019] Figure 12 An example of the distribution of the overall read threshold (Vt) is shown.

[0020] Figure 13 A comparison between the estimated read threshold (Vt) distribution and the actual read threshold (Vt) distribution according to an embodiment of the present invention is shown.

[0021] Figure 14 This is a flowchart illustrating the read threshold optimization operation according to an embodiment of the present invention. Detailed Implementation

[0022] Various embodiments will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals refer to the same parts in the accompanying drawings and embodiments of the invention.

[0023] This invention can be embodied in a variety of ways, including processes; devices; systems; computer program products embodied on computer-readable storage media; and / or processors, such as processors adapted to execute instructions stored on and / or provided by memory linked to and / or to the processor. In this specification, these embodiments or any other form in which the invention may take may be referred to as technology. Generally, within the scope of this invention, the order of steps of the disclosed process may be varied. Unless otherwise stated, components such as processors or memory described as suitable for performing tasks may be implemented as general components temporarily configured to perform tasks at a given time or manufactured as specific components for performing tasks. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0024] The following provides a detailed description of embodiments of the invention, along with accompanying drawings illustrating various aspects of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is defined only by the claims. The invention includes many substitutions, modifications, and equivalents within the scope of the claims. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided by way of example only; the invention may be practiced without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail, so as not to unnecessarily obscure the invention.

[0025] Figure 1 This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0026] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0027] The host device 5 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 5 may include electronic devices such as desktop computers, workstations, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, and / or digital video recorders and digital video players. In various embodiments, the host device 5 may include portable electronic devices such as mobile phones, smartphones, e-book readers, MP3 players, portable multimedia players (PMPs), and / or portable game consoles.

[0028] The memory system 10 can be implemented using any of a variety of memory devices such as solid-state drives (SSDs) and memory cards. In various embodiments, the memory system 10 can be configured as one of a variety of components among electronic devices such as: computers, ultra-mobile personal computers (PCs) (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablet PCs, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, memory devices for data centers, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and one of a variety of electronic devices for home networks, one of a variety of electronic devices for computer networks, one of a variety of electronic devices for telematics networks, or one of a variety of components for computing systems.

[0029] The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control the overall operation of the semiconductor memory device 200.

[0030] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. The control signals (CTRL) may include command latch enable signals, address latch enable signals, chip enable signals, write enable signals, read enable signals, and other operating signals according to the design and configuration of the memory system 10.

[0031] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a solid-state drive (SSD). The SSD may include a memory device for storing data. When the semiconductor memory system 10 is used in an SSD, the performance of host devices coupled to the memory system 10 (e.g., Figure 1 The operating speed of the main unit 5).

[0032] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated to configure: PC cards of the Personal Computer Memory Card International Association (PCMCIA), Compact Flash (CF) cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC), Reduced Size Multimedia Cards (RS-MMC), Miniature Version of MMC (Micro MMC), Secure Digital (SD) cards, Mini Secure Digital (Mini SD) cards, Micro Secure Digital (Micro SD) cards, High Capacity Secure Digital (SDHC) cards, and / or Universal Flash Memory (UFS).

[0033] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0034] Reference Figure 2 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can respond to input from a host device (e.g., Figure 1 The host device 5) operates upon request, and in particular, stores data that will be accessed by the host device.

[0035] The semiconductor memory device 200 can store data that will be accessed by the host device.

[0036] The semiconductor memory device 200 may be implemented using volatile memory devices such as dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0037] The memory controller 100 can control the storage of data in the semiconductor memory device 200. For example, the memory controller 100 can control the semiconductor memory device 200 in response to a request from a host device. The memory controller 100 can provide data read from the semiconductor memory device 200 to the host device, and can store data provided by the host device into the semiconductor memory device 200.

[0038] The memory controller 100 may include a storage device 110 connected via a bus 160, a control component 120 which may be implemented as a processor such as a central processing unit (CPU), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0039] Storage device 110 can be used as working memory for memory system 10 and memory controller 100, and stores data for driving memory system 10 and memory controller 100. When memory controller 100 controls the operation of semiconductor memory device 200, storage device 110 can store data used by memory controller 100 and semiconductor memory device 200 for operations such as read operations, write operations, programming operations and erase operations.

[0040] Storage device 110 may be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by a host device in semiconductor memory device 200 for read and write operations. To store data, storage device 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0041] The control component 120 can control the general operation of the memory system 10 in response to corresponding requests from the host device, and in particular, control the write and read operations of the semiconductor memory device 200. The control component 120 can drive firmware called a flash translation layer (FTL) to control the general operation of the memory system 10. For example, the FTL can perform operations such as logic-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. L2P mapping is called logical block addressing (LBA).

[0042] ECC component 130 can detect and correct errors in data read from semiconductor memory device 200 during a read operation. When the number of error bits is greater than or equal to the threshold number of correctable error bits, ECC component 130 may not correct the error bits, but may instead output an error correction failure signal indicating that the correction of the error bits has failed.

[0043] In various embodiments, ECC component 130 may perform error correction operations based on coded modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Therefore, ECC component 130 may include any and all circuitry, systems, or means for suitable error correction operations.

[0044] The host interface 140 can communicate with the host device through one or more of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and / or Electronic Integrated Drive (IDE).

[0045] Memory interface 150 provides an interface between memory controller 100 and semiconductor memory device 200, allowing memory controller 100 to control semiconductor memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for semiconductor memory device 200 and process data under the control of control component 120. When semiconductor memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate control signals for flash memory and process data under the control of control component 120.

[0046] Semiconductor memory device 200 may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250 (which may be in the form of a page buffer array), column decoder 260, and input / output (input / output) circuitry 270. The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and input / output circuitry 270 may form peripheral circuitry for the memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0047] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0048] The line decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. In response to a line address generated by the control circuit 220, the line decoder 240 can select at least one memory block from the plurality of memory blocks 211 and transmit the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0049] Page buffer 250 can be connected to memory cell array 210 via bit line BL. Figure 3 (As shown in the diagram). Page buffer 250 can precharge bit line BL with a positive voltage in response to a page buffer control signal generated by control circuit 220, transfer data to and receive data from the selected memory block during programming and read operations, or temporarily store the transferred data.

[0050] The column decoder 260 can transmit data to and receive data from the page buffer 250, or transmit data to and receive data from the input / output circuit 270.

[0051] Input / output circuit 270 can input from external devices (e.g., Figure 1 The memory controller 100 receives commands and addresses and transmits them to the control circuit 220, which transmits data from the external device to the column decoder 260, or outputs data from the column decoder 260 to the external device through the input / output circuit 270.

[0052] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0053] Figure 3 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 210 shown.

[0054] Reference Figure 3 The exemplary storage block 211 may include multiple word lines WL0 to WLn-1, a drain select line DSL, and a source select line SSL connected to the line decoder 240. These lines may be arranged in parallel with the multiple word lines between DSL and SSL.

[0055] The exemplary memory block 211 may further include a plurality of cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, a plurality of memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each of the memory cells may be configured as a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a three-level cell (TLC) storing 3 bits of data, or a four-level cell (QLC) storing 4 bits of data.

[0056] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gates of memory cells across cell strings can be connected to the corresponding word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. This group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0057] Page buffer array 250 may include multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during read or verification operations.

[0058] In some embodiments, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a 1-NAND flash memory with the controller embedded inside the memory chip.

[0059] Figure 4 It is a diagram showing the distribution of the state or programming voltage (PV) levels of different types of cells in a memory device.

[0060] As mentioned above, each memory cell can be implemented using a specific type of cell, such as a single-level cell (SLC) that stores 1 bit of data, a multi-level cell (MLC) that stores 2 bits of data, a three-level cell (TLC) that stores 3 bits of data, or a four-level cell (QLC) that stores 4 bits of data. Typically, all memory cells in a particular memory device are of the same type, but this is not required. Figure 4 Show the state of each of those types of cells.

[0061] An SLC can include two states, P0 and P1. P0 can indicate an erase state, while P1 can indicate a programmable state. Because an SLC can be set to one of two different states, each SLC can be programmed or store one bit according to the set encoding method. An MLC can include four states, P0, P1, P2, and P3. In these states, P0 can indicate an erase state, and P1 through P3 can indicate a programmable state. Because an MLC can be set to one of four different states, each MLC can be programmed or store two bits according to the set encoding method. A TLC can include eight states, P0 through P7. In these states, P0 can indicate an erase state, and P1 through P7 can indicate a programmable state. Because a TLC can be set to one of eight different states, each TLC can be programmed or store three bits according to the set encoding method. A QLC can include 16 states, P0 through P15. In these states, P0 can indicate an erase state, and P1 through P15 can indicate a programmable state. Because a QLC can be set to one of sixteen different states, each QLC can be programmed or store four bits according to the set encoding method.

[0062] Figure 5 This is a diagram illustrating a memory system 10 according to an embodiment of the present invention.

[0063] Reference Figure 5 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200 coupled to the memory controller 100. The semiconductor memory device 200 may include multiple memory cells (e.g., NAND flash memory cells). Figure 3As shown, memory cells are arranged in an array of rows and columns. Cells in each row are connected to word lines (e.g., WL0), while cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, data to be written ("1" or "0") is provided at the bit line while the word line is asserted. During a read operation, the word line is asserted again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. An encoding scheme (e.g., Gray code) can be used to program memory cells in order to increase the capacity of a memory system 10, such as an SSD.

[0064] Figure 6 This is a diagram illustrating an example of Gray code used for three-level cell (TLC).

[0065] Reference Figure 6 Gray code can be used to program a TLC. A TLC can have eight programming states, including an erase state E (or PV0) and first programming states PV1 through seventh programming states PV7. Eraser state E (or PV0) can correspond to "110". First programming state PV1 can correspond to "011". Second programming state PV2 can correspond to "001". Third programming state PV3 can correspond to "000". Fourth programming state PV4 can correspond to "010". Fifth programming state PV5 can correspond to "110". Sixth programming state PV6 can correspond to "100". Seventh programming state PV7 can correspond to "101".

[0066] In TLC, such as Figure 7As shown, there are three types of pages: LSB pages, CSB pages, and MSB pages. Two or three thresholds can be applied to retrieve data from the TLC. For MSB pages, the two thresholds include threshold VT0, which distinguishes between erase state E and first programming state PV1, and threshold VT4, which distinguishes between fourth programming state PV4 and fifth programming state PV5. For CSB pages, the three thresholds include VT1, VT3, and VT5. VT1 distinguishes between first programming state PV1 and second programming state PV2. VT3 distinguishes between third programming state PV3 and fourth programming state PV4. VT5 distinguishes between fourth programming state PV5 and sixth programming state PV6. For LSB pages, the two thresholds include VT2 and VT6. VT2 distinguishes between second programming state PV2 and third programming state PV3. VT6 distinguishes between sixth programming state PV6 and seventh programming state PV7.

[0067] Re-reference Figure 5 The memory controller 100 may include a read processor 510, a decoder 520, and a read threshold optimizer 530. These components can be used... Figure 2 The control component 120 is implemented using its internal components (i.e., firmware (FW)). Although Figure 5 The read processor 510 and the read threshold optimizer 530 are shown as different components, but they can be implemented as a single component. Although Figure 5 Not shown, but the memory controller 100 and the semiconductor memory device 200 may include, for example, Figure 2 The various other components shown.

[0068] Typically, model-based schemes, such as Gaussian mixture (GM) algorithms and various curve fitting algorithms, are used for read threshold optimization. Various embodiments provide read threshold optimization schemes using model-free regression, meaning that no specific model is assumed after the observable data. The read threshold optimization scheme of this invention does not assume any underlying NAND Vt distribution, while many model-based schemes do. The read threshold optimization scheme is relatively easy to implement and can improve read threshold prediction accuracy, and thus improve the durability and quality of service (QoS) of memory systems (or storage devices) (e.g., SSDs). In some embodiments, the read threshold optimization scheme estimates the read threshold voltage value or read threshold (Vt) distribution and finds a minimum point on the estimated Vt distribution.

[0069] The read processor 510 can control read operations on multiple cells of the semiconductor memory device 200. In some embodiments, the read processor 510 can perform multiple read operations (or multiple test read operations) on multiple cells using multiple read threshold voltage values.

[0070] In an embodiment, the read processor 510 may perform a first read operation on multiple units using a first read threshold voltage value and a second read operation on multiple units using a second read threshold voltage value. As an example, the first read threshold voltage value may be a successful, previously used read threshold voltage value (i.e., a historical read threshold voltage value). This value may be a recently used or most recently previously used read threshold. Previously successful read threshold voltage values ​​may be stored and managed as historical read threshold voltage values ​​in a read history table. As an example, the second read threshold may be used for read retry operations. Multiple read retry threshold voltage values ​​may be stored in a read retry table (e.g., a high-priority read retry (HRR) table). The second read threshold may be the first entry in the read retry table, indicating that the second read threshold has the highest priority among all entries in the HRR table. The multiple read retry threshold voltage values ​​in the HRR table may be arranged in order from highest to lowest priority.

[0071] In another embodiment, the read processor 510 may perform three read operations on multiple units. In addition to using the first and second read thresholds described above, a third read threshold may also be used. The third read threshold may be a second entry in the read retry table. That is, in the HRR table, the third read threshold has a lower priority than the second read threshold.

[0072] More generally, the read processor 510 can perform more than three test reads, and its threshold search accuracy increases with the number of test reads.

[0073] The read threshold optimizer 530 can estimate a threshold voltage distribution curve based on multiple read threshold voltage values ​​using a set regression formula. Furthermore, the read threshold optimizer 530 can determine the read threshold voltage value corresponding to a set point on the threshold voltage distribution curve. The operation for determining the read threshold voltage value corresponding to the set point on the threshold voltage distribution curve is described below.

[0074] The read processor 510 can perform read operations on multiple units using a determined read threshold voltage value. The decoder 520 can decode the data associated with the read operation and determine whether the data was successfully decoded, i.e., whether the read operation was successful. When the read operation is determined to be successful, the read processor 510 can terminate the read operation. When the read operation is determined to be unsuccessful, the read threshold optimizer 530 can perform an operation to determine another read threshold voltage value along the curve.

[0075] Reference Figures 8 to 12 Describe the read threshold optimization scheme for memory controller 100. Figure 8 Figure 11 shows two examples of the total read threshold (Vt) distribution.

[0076] exist Figure 8 In the diagram, the horizontal axis (i.e., the x-axis) represents the reading threshold Vt, and the vertical axis (i.e., the y-axis) represents the probability (or distribution on a logarithmic scale). The population Vt distribution curve is the probability density function (PDF) of the reading threshold. Figure 8 In the example shown, the population Vt distribution curve is a mixture of a Gaussian distribution (i.e., the portion of the curve to the right of Vtmin) and a Student's T distribution (i.e., the portion of the curve to the left of Vtmin). In this example, it is assumed that the minimum point on the Vt distribution curve (Vtmin) is at Vt = 0.677, and the corresponding probability (i.e., the distribution value) is 0.0121.

[0077] Re-reference Figure 5 The read threshold optimizer 530 can obtain multiple read threshold voltage values ​​from the read processor 510. Furthermore, the read threshold optimizer 530 can estimate a threshold voltage distribution curve based on the multiple read threshold voltage values.

[0078] The read threshold optimizer 530 can measure probability values ​​y = [y1, y2, y3] for multiple read threshold voltage values ​​x = [x1, x2, x3]. In this example, assume three read operations are performed. For example, x1 is the first read threshold voltage value for the first read operation, x2 is the second read threshold voltage value for the second read operation, and x3 is the third read threshold voltage value for the third read operation. The Vt distribution curve of the discrete read threshold voltage values ​​can be a probability mass function (PMF) rather than a PDF. Therefore, as... Figure 9A As shown, for multiple read threshold voltage values ​​x = [x1, x2, x3], a probability value y = [y1, y2, y3] can be measured using a PMF. In some embodiments, such as Figure 9B As shown, PMF can be measured by the difference between two cumulative quality function (CMF) values, i.e., PMF[i] = CMF[i] - CMF[i-1]. In some embodiments, for each read threshold voltage value, the CMF value can be determined based on the number of cells (cell count) associated with the read operation using each read threshold voltage value and the number of specific binary values ​​(1 or 0) among the cells. For example, each CMF value can be determined as {the number of 1s or 0s (e.g., the number of 1s) / cell count}.

[0079] The read threshold optimizer 530 can determine the CMF value CMF(i) of the current read threshold voltage value x(i) and the CMF value CMF(i-1) of the previous read threshold voltage value x(i-1). For example... Figure 9B As shown, the read threshold optimizer 530 can determine the difference between the CMF values ​​of the current read threshold voltage value x(i) and the previous read threshold voltage value x(i-1) (i.e., CMF(i) - CMF(i-1)) as the PMF probability value PMF(i) of the current read threshold voltage value x(i). For example, as Figure 9C As shown, the read threshold optimizer 530 can determine the difference between the CMF values ​​of the current read threshold voltage value x(2) and the previous read threshold voltage value x(1) (i.e., CMF(x2)-CMF(x1)) as the PMF probability value PMF (i.e., y2) for the current read threshold voltage value x(2). Similarly, the read threshold optimizer 530 can determine the difference between the CMF values ​​of the current read threshold voltage value x(3) and the previous read threshold voltage value x(2) (i.e., CMF(x3)-CMF(x2)) as the PMF probability value PMF (i.e., y3) for the current read threshold voltage value x(3). For the current read threshold voltage value x(1), the read threshold optimizer 530 can determine the difference between the CMF value of the current read threshold voltage value x(1) and the previous read threshold voltage value 0 (i.e., CMF(x1)-0) as the PMF probability value PMF (i.e., y1). In this way, the probability value of the Vt distribution can be measured. As an example, the probability value of the Vt distribution is measured at x = [0.5, 0.6, 0.7], and the result is y = [0.0202961, 0.0135188, 0.0122511].

[0080] The read threshold optimizer 530 estimates the Vt distribution curve by applying multiple read threshold voltage values ​​and measured probability values ​​to a set regression formula. In other words, as... Figure 10 As shown, the read threshold optimizer 530 can apply a set regression formula to multiple read threshold voltage values ​​x = [x1, x2, x3] and the measured probability values ​​y = [y1, y2, y3]. In some embodiments, the set regression formula can be represented by equation (1) shown below.

[0081]

[0082] The regression formula in equation (1) can be a function of multiple reading threshold voltage values ​​x[i] and probability values ​​y[i]. The variables in the regression formula are defined in List 1 below.

[0083] List 1:

[0084]

[0085] When the set regression formula is applied to multiple reading threshold voltage values ​​x = [0.5, 0.6, 0.7] and the measured probability values ​​y = [0.0202961, 0.0135188, 0.0122511], the set regression formula can be obtained as follows:

[0086]

[0087] The above equation applies to any number of test reads and is independent of any predetermined probability model of Vt. It is simply a function of the measured data points x[i] and y[i]. As more data points are collected, the estimated read threshold distribution Vt'(v) becomes closer to the true read threshold distribution Vt(v).

[0088] exist Figure 11A In the figure, relative to the population Vt distribution curve 1110, the estimated Vt distribution curve 1120 is shown, which corresponds to Figure 8 The Vt distribution curve is shown in Figure 1120. The Vt distribution curve 1120 is estimated using three reading threshold voltage values ​​x = [0.5, 0.6, 0.7].

[0089] Re-reference Figure 5 The read threshold optimizer 530 can determine the read threshold voltage value corresponding to a set point on the threshold voltage distribution curve. For example, the read threshold optimizer 530 can determine the read threshold voltage value corresponding to a set point on the threshold voltage distribution curve (e.g., ...). Figure 11A The minimum point on the threshold voltage distribution curve 1120 corresponds to the readout threshold voltage value. In some embodiments, the readout threshold optimizer 530 may evaluate the regression formula above Vt'(v) step by step and determine the lowest value among all points evaluated as the minimum point on the threshold voltage distribution curve 1120. This step size can be any suitable value. It can be observed that the minimum point of Vt'(v) is at v = 0.7, and the corresponding minimum value is 0.0121. As per [reference to...] Figure 8 The minimum point on the Vt distribution curve is described as being at Vt = 0.677, and the corresponding probability (i.e., distribution value) is 0.0121.

[0090] The read threshold optimizer 530 can estimate the Vt distribution curve with four read threshold voltage values ​​x = [0.5, 0.6, 0.7, 0.8]. As an example, the probability value of the Vt distribution is measured at x = [0.5, 0.6, 0.7, 0.8], and the measurement result is y = [0.0202961, 0.0135188, 0.0122511, 0.0159058]. When the regression formula set above is applied to multiple read threshold voltage values ​​x = [0.5, 0.6, 0.7, 0.8] and the measured probability value y = [0.0202961, 0.0135188, 0.0122511, 0.0159058], the Vt distribution curve 1130 is estimated as follows: Figure 11B As shown. Relative to Figure 8 The overall Vt distribution curve in 1110, Figure 11B The estimated distribution curve of Vt is shown at 1130. The minimum point of Vt'(v) is observed at v = 0.66, and the corresponding minimum value is 0.01225. (See also: Regarding...) Figure 8 The minimum point on the Vt distribution curve is described as being at Vt = 0.677, and the corresponding probability (i.e., distribution value) is 0.0121. From... Figure 11A and Figure 11B It can be seen that when more test reads are performed, the estimated Vt'(v) is close to Figure 8 The actual Vt(v) in the equation.

[0091] The example can be applied to a noisy overall read threshold (Vt) distribution, such as... Figure 12The Vt distribution with noise is shown. In this example, the gradient descent-based algorithm can be easily captured at one of the local minima. The read threshold optimizer 530 can estimate the Vt distribution curve with nine read threshold voltage values ​​x = [0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6]. As an example, the probability value of the Vt distribution is measured at x = [0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6], and the measurement result is y = [0.0138716, 0.0127417, 0.0423129, 0.0161038, 0.00714726, 0.0437911, 0.0428013, 0.0903059, 0.305872]. When the regression formula set above is applied to multiple reading threshold voltage values ​​x = [0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6] and the measured probability values ​​y = [0.0138716, 0.0127417, 0.0423129, 0.0161038, 0.00714726, 0.0437911, 0.0428013, 0.0903059, 0.305872], the Vt distribution curve 1320 is estimated as follows: Figure 13 As shown. In Figure 13 In the figure, the estimated Vt distribution curve 1320 is shown relative to the population Vt distribution curve 1310, which corresponds to Figure 12 The Vt distribution curves in the population are shown. It is observed that the minimum point of the estimated Vt distribution curve 1320 is at v = 1.175, while the true minimum of the population Vt distribution curve 1310 is at 1.163.

[0092] Figure 14 This is a flowchart illustrating a read threshold optimization operation 1400 according to an embodiment of the present invention. The read threshold optimization operation 1400 can be performed by... Figure 5 The read processor 510, decoder 520, and read threshold optimizer 530 of the memory controller 100 are executed.

[0093] Reference Figure 14 In operation 1410, the read processor 510 can perform multiple read operations on multiple units using multiple read threshold voltage values.

[0094] In some embodiments, the read processor 510 may perform a first read operation on a plurality of units using a first read threshold voltage value, and may perform a second read operation on a plurality of units using a second read threshold voltage value. In some embodiments, the first read threshold voltage value may be a successful, previously used read threshold voltage value (i.e., a historical read threshold voltage value), and the second read threshold may be used for read retry operations. Among a plurality of read retry threshold voltage values ​​stored in a read retry table for read retry operations, the second read threshold may have a higher (or highest) priority.

[0095] In operation 1420, the read threshold optimizer 530 can use a set regression formula to estimate the threshold voltage distribution curve based on multiple read threshold voltage values.

[0096] In some embodiments, the read threshold optimizer 530 may use a probability mass function (PMF) to measure the probability values ​​of multiple read threshold voltage values. Further, the read threshold optimizer 530 may estimate the threshold voltage distribution curve by applying a set regression formula to the multiple read threshold voltage values ​​and the measured probability values.

[0097] In some embodiments, the read threshold optimizer 530 may determine the cumulative quality function (CMF) value of the current read threshold voltage value and the previous read threshold voltage value. Further, the read threshold optimizer 530 may determine the difference between the CMF value of the current read threshold voltage value and the CMF value of the previous read threshold voltage value as the PMF probability value of the current read threshold voltage value. For example, for each read threshold voltage value, each CMF value may be determined based on the number of cells associated with the read operation using each read threshold voltage value and the number of specific binary values ​​(0 or 1) among those cells.

[0098] In some embodiments, the set regression formula may include a function of multiple read threshold voltage values ​​and probability values. The read threshold optimizer 530 can estimate the threshold voltage distribution curve by applying the set regression formula to multiple read threshold voltage values ​​and measured probability values.

[0099] In some embodiments, the read threshold optimizer 530 can evaluate the set regression formula step by step, the step size of which can be any suitable value, and can determine the lowest value among all points evaluated as set points on the threshold voltage distribution curve.

[0100] In operation 1430, the read threshold optimizer 530 can determine the read threshold voltage value corresponding to the set point on the threshold voltage distribution curve.

[0101] In operation 1440, the read processor 510 can perform read operations on multiple cells using a determined read threshold voltage value.

[0102] In operation 1450, the read processor 510 can determine the number of read operations performed, i.e., whether the number of read attempts has reached the set maximum number. If the number of read attempts performed so far is less than the set maximum number, the process can proceed to the next stage (e.g., other read threshold searches). When it is determined that the number of read attempts performed has reached the set maximum number, in operation 1460, the read processor 510 can determine whether the read operation using the determined read threshold voltage value was successful or failed based on the decoding result of the decoder 520.

[0103] If a read operation using the determined read threshold voltage value fails, the process can return to operation 1430, where another read threshold voltage value is determined using the distribution curve. If a read operation using the determined read threshold voltage value succeeds, read threshold optimization operation 1400 terminates.

[0104] As described above, the embodiments provide a scheme for optimizing the read threshold of a memory system using model-free regression. This scheme uses model-free regression instead of model-based schemes such as GM or curve fitting algorithms. Therefore, the embodiments can be easily implemented and can improve read threshold prediction accuracy, and thus improve the durability and QoS of the memory system (e.g., SSD).

[0105] Although the embodiments described above have been shown and described in considerable detail for clarity and understanding, the invention is not limited to the details provided. As will be understood by those skilled in the art based on the above disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention is intended to include all modifications and substitutions falling within the scope of the claims.

Claims

1. A memory system, comprising: A memory device comprising multiple units; as well as A controller is connected to the memory device, and: Multiple read operations are performed on the multiple units using multiple read threshold voltage values; Measure the probability values ​​of the plurality of read threshold voltage values; The threshold voltage distribution curve is estimated using the set regression formula based on the multiple read threshold voltage values ​​and the measured probability values; Determine the reading threshold voltage value corresponding to the set point on the threshold voltage distribution curve; and The read threshold voltage value is used to perform a read operation on the plurality of units.

2. The memory system according to claim 1, wherein the controller: The first read operation of the plurality of read operations is performed on the plurality of units using a first read threshold voltage value; and The second read operation is performed on the plurality of units using the second read threshold voltage value.

3. The memory system of claim 2, wherein the first read threshold voltage value includes a successful, previously used read threshold voltage value.

4. The memory system according to claim 2, wherein the second read threshold is used for read retry operations.

5. The memory system of claim 4, wherein among the plurality of read retry voltage values ​​for the read retry operation stored in the read retry table, the second read threshold has a higher priority.

6. The memory system of claim 1, wherein the controller: The probability mass function (PMF) is used to measure the probability values ​​of the multiple read threshold voltage values; and The threshold voltage distribution curve is estimated by applying the set regression formula to the plurality of read threshold voltage values ​​and the measured probability values.

7. The memory system of claim 6, wherein the controller: Determine the cumulative quality function (CMF) value between the current read threshold voltage value and the previous read threshold voltage value; and The difference between the CMF value of the current reading threshold voltage value and the CMF value of the previous reading threshold voltage value is determined as the PMF probability value of the current reading threshold voltage value.

8. The memory system of claim 7, wherein each CMF value is determined based on the number of cells associated with a read operation using each read threshold voltage value and the number of preset binary values ​​in the cells.

9. The memory system of claim 6, wherein the regression formula for the setting comprises a function of multiple read threshold voltage values ​​and probability values, and The controller estimates the threshold voltage distribution curve by applying the set regression formula to the plurality of read threshold voltage values ​​and the measured probability values.

10. The memory system of claim 9, wherein the controller evaluates the set regression formula step by step and determines the lowest value among all points evaluated as the set point on the threshold voltage distribution curve, wherein each of the steps has a set uniform size.

11. A method for operating a memory system, comprising: Perform multiple read operations on multiple cells using multiple read threshold voltage values; Measure the probability values ​​of the plurality of read threshold voltage values; The threshold voltage distribution curve is estimated using the set regression formula based on the multiple read threshold voltage values ​​and the measured probability values; Determine the reading threshold voltage value corresponding to the set point on the threshold voltage distribution curve; and The read threshold voltage value is used to perform a read operation on the plurality of units.

12. The method of claim 11, wherein performing the plurality of read operations comprises: The first read operation of the plurality of read operations is performed on the plurality of units using a first read threshold voltage value; and The second read operation is performed on the plurality of units using the second read threshold voltage value.

13. The method of claim 12, wherein the first read threshold voltage value is a successful, previously used read threshold voltage value.

14. The method of claim 12, wherein the second read threshold is used for read retry operations.

15. The method of claim 14, wherein among a plurality of read retry voltage values ​​for the read retry operation stored in the read retry table, the second read threshold has a higher priority.

16. The method of claim 11, wherein the measurement of the probability value comprises measuring the probability value of the plurality of read threshold voltage values ​​using a probability mass function, i.e., a probability factor function (PMF), and The estimation of the threshold voltage distribution curve includes estimating the threshold voltage distribution curve by applying the set regression formula to the plurality of read threshold voltage values ​​and the measured probability values.

17. The method of claim 16, wherein the measurement of the probability value comprises: Determine the cumulative quality function (CMF) value between the current read threshold voltage value and the previous read threshold voltage value; and The difference between the CMF value of the current reading threshold voltage value and the CMF value of the previous reading threshold voltage value is determined as the PMF probability value of the current reading threshold voltage value.

18. The method of claim 17, wherein each CMF value is determined based on the number of units associated with a read operation using each read threshold voltage value and the number of preset binary values ​​among the units.

19. The method of claim 16, wherein the set regression formula comprises a function of multiple read threshold voltage values ​​and probability values, and The estimation of the threshold voltage distribution curve involves applying the set regression formula to the plurality of read threshold voltage values ​​and the measured probability values.

20. The method of claim 19, wherein determining the read threshold voltage value comprises: The regression formula is evaluated step by step, each step having a set uniform size; and The lowest value among all points evaluated as the set point on the threshold voltage distribution curve is determined.

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