A surface treatment method for heteroepitaxial thin film epitaxial layer

Abstract

The present invention discloses a surface treatment method for a heteroepitaxial thin film epitaxial layer, comprising providing an epitaxial substrate, preparing an epitaxial layer on the upper surface of the epitaxial substrate, providing a layer to be bonded; bonding the epitaxial layer and the layer to be bonded; mechanically thinning and polishing the lower surface of the epitaxial substrate, stopping polishing when the thickness of the epitaxial substrate is reduced to 20-40 μm, and spin-coating a photoresist three-layer structure mask containing a Si anti-reflective coating / organic carbon layer on the thinned lower surface of the epitaxial substrate; heating the surface of the three-layer photoresist structure mask and then performing chemical mechanical thinning and polishing to obtain an epitaxial substrate with a planarized three-layer structure mask; and dry etching the surface of the epitaxial substrate after CMP polishing until the epitaxial layer is exposed to obtain a heteroepitaxial thin film epitaxial layer. This method can ensure that the thickness uniformity of the epitaxial layer exposed by transfer peeling is improved.

Description

Technical Field

[0001] The invention belongs to a manufacturing process of semiconductor devices, and in particular relates to a surface treatment method of a heteroepitaxial thin film epitaxial layer. Background Art

[0002] Group III-V compounds are considered third-generation semiconductor materials. Nitrides, due to their wide bandgap, high electron mobility, high luminous efficiency, and high frequency, are widely used in blue and violet light-emitting diodes and semiconductor lasers. As light-emitting material technology matures, LEDs, with their long lifespan, high efficiency, and high brightness, are widely used in lighting and display applications such as traffic lights, street lamps, and large-area display screens.

[0003] Gallium nitride (GaN), indium nitride (GaIn), aluminum nitride (AlN), and their ternary compounds are currently the most widely used semiconductor materials, primarily in lighting and display applications, such as lasers, detectors, and high-power amplifiers. The band gap of (Al, Ga, In)N materials covers a wide range, ranging from 0.7eV for InN to 3.4eV for GaN and 6.2eV for AlN.

[0004] In particular, the rapid development of gallium nitride (GaN) and aluminum nitride (AlN)-based light-emitting diodes (LEDs), along with white light illumination and full-color displays based on blue LEDs, has become a hot topic in global lighting research and development. LEDs are already gradually replacing incandescent lamps, heralding the advent of the semiconductor lighting era. High-efficiency, high-power gallium nitride (GaN) and aluminum nitride (AlN)-based light-emitting diodes (LEDs) are currently a research focus in the fields of solid-state lighting and electronic displays. Homoepitaxial growth of GaN-based LEDs is extremely difficult, so heteroepitaxial growth is often used to grow GaN thin films.

[0005] Although the heteroepitaxial growth process for GaN and AlN-based LEDs using sapphire (Al2O3) as a substrate material has matured and industrialized, the large lattice mismatch (~13.4%) and thermal expansion difference (~25.5%) between sapphire and GaN and AlN lead to high defect density in epitaxial GaN and AlN films, seriously affecting LED performance. Silicon (Si) substrate materials have excellent thermal and electrical conductivity, mature wafer processing, and low cost, making them ideal substrate materials for high-efficiency, high-power LEDs. However, the lattice mismatch (~16.9%) and thermal mismatch (~54%) between Si and GaN and AlN are even greater, leading to film cracking. Therefore, growing high-quality GaN epitaxial films on Si substrates is more difficult.

[0006] With the increasing requirements for LED display performance, the epitaxial substrate layer after bonding sometimes requires the complete removal of leaked GaN and AlN layers for subsequent processing. In many other fields, such as high-frequency communications, similar heteroepitaxial technologies based on sapphire and SIC are also needed to grow high-quality single-crystal GaN and AlN films and complete the transfer of silicon substrates. Due to the difficulty of completely removing the excess epitaxial substrate after the transfer of GaN and AlN, the direct use of mechanical thinning and polishing methods cannot guarantee the same removal rate between the middle and edge of the wafer due to the characteristics of the polishing and CMP processes, resulting in poor thickness uniformity (TTV) of the final thinning, which can reach more than 15um in severe cases. It is difficult to ensure good thickness uniformity of the final GaN and AlN. The thickness of GaN and AlN in BAW directly affects the filtering frequency, so it is difficult to ensure the frequency consistency of devices cut from the same wafer.

[0007] Therefore, it is urgent to develop a heteroepitaxial thin film substrate peeling transfer process to prevent the poor TTV of the film surface after transfer. Summary of the Invention

[0008] The present invention provides a surface treatment method for a heteroepitaxial thin film epitaxial layer, which can ensure that the thickness uniformity of the epitaxial layer exposed by transfer peeling is better.

[0009] A surface treatment method for a heteroepitaxial thin film epitaxial layer, comprising:

[0010] (1) providing an epitaxial substrate, preparing an epitaxial layer on the upper surface of the epitaxial substrate, and providing a layer to be bonded; bonding the epitaxial layer and the layer to be bonded;

[0011] (2) mechanically thinning and polishing the lower surface of the epitaxial substrate, stopping the polishing when the thickness of the epitaxial substrate is thinned to 20-40 μm, and spin-coating a photoresist trilayer mask containing a Si anti-reflective coating (SIARC) / organic carbon layer (SOC) on the lower surface of the thinned epitaxial substrate;

[0012] (3) heating the surface of the three-layer structure mask of the photoresist and performing chemical mechanical polishing (CMP) to obtain an epitaxial substrate with a planarized three-layer structure mask;

[0013] (4) Dry etching the surface of the epitaxial substrate planarized by the three-layer structure mask until the epitaxial layer leaks out to obtain a heteroepitaxial thin film epitaxial layer.

[0014] Since butterfly pits are formed on the epitaxial substrate after thinning in step (2), if polishing is continued to the epitaxial layer, the epitaxial layer finally obtained will also have butterfly pits (Dishing), resulting in poor TTV on the surface of the epitaxial layer. The present invention spin-coats a relatively soft photoresist three-layer structure mask on the lower surface of the epitaxial substrate after thinning in step (2) to fill the butterfly pits, and then thins the epitaxial substrate coated with the photoresist three-layer structure mask to a smaller thickness, and uses CMP to flatten the surface to the greatest extent to save time for subsequent dry etching of the epitaxial layer. Then, the remaining epitaxial substrate is removed by dry etching to ensure better thickness uniformity of the epitaxial layer. Due to the presence of the three-layer photoresist structure, the dry etching selectivity is adjusted by adjusting the ratio of the reflective coating (SIARC) / organic carbon layer (SOC) content, thereby improving the thickness uniformity of the surface after the substrate is removed.

[0015] In step (1):

[0016] The step of bonding the epitaxial layer and the layer to be bonded comprises:

[0017] A first bonding layer is deposited to cover the upper surface of the epitaxial layer; a second bonding layer is formed on the upper surface of the layer to be bonded, and the epitaxial layer and the layer to be bonded are bonded with the first bonding layer and the second bonding layer as bonding surfaces.

[0018] The bonding layer material is single crystal Si, amorphous silicon, SiO2, gold, tin or silver.

[0019] The bonding method is fusion bonding, metal bonding or plasma activation bonding, and the bonding temperature is 200°C-1400°C.

[0020] The present invention performs amorphous silicon bonding on the epitaxial layer and the layer to be bonded, and avoids the problem of film cracking due to interface matching between the epitaxial layer and the bonding layer through appropriate bonding method and bonding temperature control.

[0021] The epitaxial substrate material is one or more of glass, silicon, silicon carbide, silicon nitride, sapphire or ceramic.

[0022] The thickness of the epitaxial substrate is 300 μm-1 mm.

[0023] The material of the layer to be bonded is one or more of glass, silicon, silicon carbide, silicon nitride, sapphire or ceramic.

[0024] The epitaxial layer material is one or more of aluminum nitride, scandium aluminum nitride, and gallium nitride.

[0025] The thickness of the three-layer photoresist structure mask is 10 μm-20 μm.

[0026] In step (2):

[0027] The mass ratio of Si to C in the three-layer photoresist mask is 10%-90%.

[0028] By adjusting the Si and C in the three-layer structure mask of the photoresist to match the composition of the epitaxial substrate, the purpose of polishing consistency with the epitaxial layer can be achieved during the CMP process, the flatness of the epitaxial layer surface can be maintained, and the purpose of removing the remaining epitaxial coating simultaneously by dry etching can be achieved, making the surface thickness of the epitaxial layer uniform.

[0029] In step (3):

[0030] The heating temperature is 100°C-150°C.

[0031] The three-layer photoresist mask is cured by heating to ensure the flatness of the CMP polished epitaxial substrate.

[0032] The thickness uniformity of the planarized three-layer structure mask is less than 1 μm.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] (1) The present invention uses a photoresist three-layer structure mask containing Si anti-reflective coating (SIARC) / organic carbon layer (SOC) to fill the butterfly resist of the polished epitaxial substrate layer, then CMP thinning and polishing, and dry etching to remove the epitaxial coating of the spin-coated photoresist three-layer structure mask, so that the surface of the epitaxial layer has good thickness uniformity. From the best embodiment, it is found that the thickness uniformity of the AlN film obtained by using the method provided by the present invention is controlled to be 600nm±5nm.

[0035] (2) Compared with the prior art method of introducing a sacrificial layer and then removing the substrate by laser stripping, the present invention obtains the epitaxial layer by polishing and dry etching, avoiding the problem of contamination of the epitaxial layer by the introduction of the sacrificial layer, which leads to a decrease in the quality of the transferred film. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of the epitaxial substrate and epitaxial layer provided in a specific embodiment, and the structure of the layer to be bonded, wherein 101 is the epitaxial substrate layer, 102 is the epitaxial layer, and 103 is the layer to be bonded;

[0037] Figure 2 Schematic diagram of depositing bonding layers on the surface of the layer to be bonded and the epitaxial layer respectively prepared in a specific embodiment, wherein 104 is the bonding layer;

[0038] Figure 3 The structure diagram of the heteroepitaxial thin film obtained after bonding is obtained in a specific embodiment;

[0039] Figure 4 This is a structural diagram of a heteroepitaxial thin film obtained after thinning the epitaxial substrate layer according to a specific embodiment;

[0040] Figure 5 105 is a three-layer mask layer of a photoresist including a Si anti-reflective coating layer and an organic carbon layer;

[0041] Figure 6 The structure diagram of the heteroepitaxial film after CMP chemical mechanical polishing SIARC / SOC prepared in a specific embodiment;

[0042] Figure 7 This is a structural diagram of a heteroepitaxial thin film with a leaked epitaxial layer obtained after dry etching an epitaxial substrate according to a specific embodiment;

[0043] Figure 8 The XRD pattern of the epitaxial layer of the heteroepitaxial film prepared in a specific embodiment;

[0044] Figure 9 The epitaxial layer thickness mapping diagram and SEM diagram of the heteroepitaxial film prepared in a specific embodiment are shown in FIG. Figure 9 a is the epitaxial layer thickness mapping diagram of the heteroepitaxial film, Figure 9 b is the SEM image of the epitaxial layer of the heteroepitaxial film in a;

[0045] Figure 10 The figure is a structural diagram of a single crystal acoustic wave resonator made according to a specific implementation method. DETAILED DESCRIPTION

[0046] The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become more apparent. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0047] like Figure 1 As shown, in this embodiment, the epitaxial layer 102 is made of AlN, the epitaxial substrate 101 is made of SiC, and the layer to be bonded 103 is made of Si.

[0048] A surface treatment method for a heteroepitaxial thin film epitaxial layer, comprising the following steps:

[0049] (1) Figure 2As shown, a bonding layer is grown on the upper surface of the epitaxial layer 102 and the upper surface of the layer to be bonded 103 by plasma enhanced chemical vapor deposition (PECVD). The bonding layer 104 has a thickness of 1 μm and is amorphous silicon. The deposited bonding layers are then planarized using CMP technology to achieve a surface roughness of 0.5 nm. Silicon fusion bonding is used and the bonding is completed after annealing at 1410° C., as shown in FIG. Figure 3 The structure shown;

[0050] (2) Mechanical thinning, polishing and grinding are performed on the lower surface of the epitaxial substrate 101 to reduce the thickness of the epitaxial substrate to 20 μm. The parameters of mechanical thinning and polishing are: wafer speed / grinding speed are 200 / 800 rpm, feed rate is 0.5 μm / s; grinding parameters are: load: 20 kg, time: 10 min, wafer speed is 6 rpm, and the following is obtained: Figure 4 The structure shown;

[0051] (3) Spin-coat a layer of SIARC / SOC on the lower surface of the epitaxial substrate after mechanical thinning, polishing and grinding in step (2). SIARC / SOC is a trilayer mask 105 commonly used in 55nm photolithography process; parameters: 1000r / min, baking at 250℃, 60s, thickness 12um±0.2um, SIARC / SOC mass ratio 40 / 60%, and obtain the following: Figure 5 The structure shown;

[0052] (4) Chemical mechanical thinning and polishing (CMP) makes the TTV of SIARC / SOC surface less than 1 μm, such as Figure 6 As shown, the parameters of chemical mechanical polishing (CMP) are: the polishing liquid is Z40, the pH is adjusted to 10.3, the polishing rate is 7200 A / min, the Dishing value is 100nm-200nm, and the surface roughness is 0.6nm.

[0053] (5) Dry etching the SIARC / SOC and epitaxial substrate 101 surface to expose the epitaxial layer 102. The transfer and exposure of the epitaxial layer 102 film are completed, as shown in FIG. Figure 7 shown.

[0054] like Figure 8 As shown, the XRD measurement of the epitaxial layer 102 shows a half-height width of 288 sec, indicating that the surface of the epitaxial layer has relatively pure AlN single crystals, and the epitaxial substrate material and SIARC / SOC are removed by dry etching;

[0055] like Figure 9 As shown in a, the maximum thickness difference of the epitaxial layer measured by the automatic optical film thickness measurement test method is 6nm, and the thickness uniformity is good, as shown in Figure 9 As shown in Figure b, the thickness of the epitaxial AlN layer was measured by SEM sectioning. The number of measurement sampling points was 9, and the thickness uniformity was good.

[0056] Application examples:

[0057] A single crystal acoustic wave resonator is prepared based on this method. The specific process is as follows:

[0058] 1) A double-polished sapphire substrate was cleaned and a single-crystal AlN film with a thickness of 800 nm was grown at 1200°C using MOCVD epitaxial method.

[0059] 2) Photolithography islanding patterning: ICP dry etching of AlN using RF / BF = 600W / 100W, Cl2 / O2 = 60 / 10sccm, and a pressure of 10mT. After etching for 190s, wet stripping (acetone / IPA / DI for 30 minutes) was performed to obtain island-shaped AlN. This helps to reduce global warpage and facilitate the bonding process. The lateral dimensions of the AlN after islanding are 300μm x 300μm.

[0060] 3) The surface formed in 2) was coated with 180 nm of Mo 103' by magnetron sputtering with a sputtering power of 6000 kW, an Ar gas split flow of 28 sccm, a sputtering time of 25 s, and four 90-degree rotations to ensure uniform film thickness within the surface.

[0061] 4) Mo was patterned using photolithography. Etching process: RF / BF = 700W / 150W, SF6 / O2 = 40 / 25sccm, 10mT: 120s; wet stripping (acetone / IPA / DI for 30 minutes).

[0062] 5) Patterning of the sacrificial layer: PECVD was used at 350°C, SP: 2000W to grow a SiO2 / Si sacrificial layer 104', of which the Si layer was 105'. Etching was performed using a P5000RIE etching device. The etching process was as follows: pressure: 250mT, RF: 300W, SF6 / CHF3 / Ar = 80 / 40 / 100. After etching for 180s, another process was switched: SF6 / CHF3 / Ar = 8 / 20 / 100sccm, power: 150W, pressure 200mT, mainly used for over-etching and reducing the rate to optimize the in-plane etching uniformity.

[0063] 6) Bonding: Bonding is done with reverse mold UV resin glue. Use a glue spreader to spin-coat 5um reverse mold UV resin 106'. Apply 200N pressure on the bonder and hold for 1.5 hours. Transfer to a 36V UV lamp and irradiate for half an hour for curing.

[0064] 7) Mechanical Thinning and Grinding: Use an ENGIS thinning machine to thin the backside of the wafer, removing approximately 400 μm. Process: Thinning: Wafer speed / Grinding speed: 200 / 800 rpm; Feed rate: 0.5 μm / s. Grinding: Load: 20 kg, Time: 10 min, Wafer speed: 60 rpm.

[0065] 8) Using the method of the present invention, a layer of SIARC / SOC is spin-coated on the lower surface of the epitaxial substrate after mechanical thinning, polishing and grinding in step (7). SIARC / SOC is a trilayer mask commonly used in 55nm photolithography process; parameters: 1000r / min, baking at 250℃, 60s, thickness 12um±0.2um, SIARC / SOC mass ratio 40 / 60%, chemical mechanical thinning and polishing (CMP) to make the TTV of the SIARC / SOC surface less than 1um: the grinding liquid is Z40, the pH is adjusted to 10.3, the polishing rate is 7200A / min, so that the Dishing value is 100nm-200nm and the surface roughness is 0.6nm; the SIARC / SOC and the epitaxial substrate surface are dry-etched to expose the epitaxial layer 102'.

[0066] 9) The surface formed in 8) was magnetron sputtered to deposit 150 nm of Mo 107′ at a sputtering power of 6000 kW, an Ar gas split flow of 28 sccm, a sputtering time of 21 s, and four 90-degree rotations to ensure uniform film thickness within the surface.

[0067] 10) Mo was patterned using photolithography. Etching process: RF / BF = 700W / 150W, SF6 / O2 = 40 / 25sccm, 10mT: 110s; wet stripping (acetone / IPA / DI for 30 minutes).

[0068] 11) The first and second electrode pins 108' were fabricated using a lift-off process. Note: Since the remaining thickness of the first substrate after thinning and grinding is relatively thick, spraying is preferred. After photolithography, low-temperature magnetron sputtering of Ti / Au (20 / 400 nm) was performed. The photoresist was stripped using NMP ultrasonication at 90°C for 1 hour.

[0069] 12) Wet release process: BOE / H2O = 7 / 1, ultrasonically immerse the sample at room temperature for 3 hours. After immersion, remove the sample and rinse with DI water for 10 minutes.

[0070] 13) Fabrication of the Third Substrate Cover Plate 301': A through-hole (TSV) pattern was photoetched on the silicon wafer with a hole diameter of 10 μm. Thick resist 4620 (10 μm thick) was used. A Bosch process was used to etch the through-holes to a depth of 120 μm. The process was as follows: Maintain etching power = 3200 W, cycle number = 250, etching gas (SF6) flow rate = 700 sccm, shielding gas (O2) flow rate = 320 sccm, and shielding gas exposure time = 1.7 s.

[0071] 14) Use copper electroplating to fill the TSV vias with copper conductors. Specific process parameters: Cu ion concentration: 80-110 g / L; Cl ion concentration: 40-60 mg / ml; accelerator concentration: 2-8 ml / L; inhibitor concentration: 5-15 ml / L; leveler concentration: 2-10 ml / L; plating type: rack plating; current density: 1.3 ASD; temperature: 24 ± 0.5°C; plating time: 60 minutes; plating bath circulation rate: 8 L / min; coating thickness: 10 μm.

[0072] 15) Thinning the cover plate, mechanical thinning: Use an ENGIS thinning machine to thin the backside of the wafer, removing 380µm. Process: Thinning: Wafer speed / grind speed: 200 / 800rpm; Feed rate: 0.5µm / s.

[0073] 16) Bonding. Use EVG lithography machine for back overlay, with precision controlled at 1um. After alignment, use gold-gold bonding, process: 450℃, pressure 5000N, vacuum degree 0.00008pa. Figure 10 The structure shown.

[0074] Those skilled in the art will understand that the foregoing descriptions are merely preferred embodiments of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, those skilled in the art will still be able to modify the technical solutions described in the foregoing examples or substitute equivalents for some of the technical features therein. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the invention shall be included within the scope of protection of the invention.

Claims

1. A surface treatment method for a heteroepitaxial thin film epitaxial layer, characterized in that: include: (1) providing an epitaxial substrate, preparing an epitaxial layer on the upper surface of the epitaxial substrate, and providing a layer to be bonded; bonding the epitaxial layer and the layer to be bonded; (2) mechanically thinning and polishing the lower surface of the epitaxial substrate, stopping the polishing when the thickness of the epitaxial substrate is thinned to 20-40 μm, and spin-coating a photoresist three-layer structure mask containing a Si anti-reflective coating / organic carbon layer on the thinned lower surface of the epitaxial substrate; (3) heating the surface of the three-layer structure mask of the photoresist and then performing chemical mechanical thinning and polishing to obtain an epitaxial substrate with a planarized three-layer structure mask; (4) Dry etching the surface of the epitaxial substrate planarized by the three-layer structure mask until the epitaxial layer leaks out to obtain a heteroepitaxial thin film epitaxial layer.

2. The surface treatment method of the heteroepitaxial thin film epitaxial layer according to claim 1, characterized in that: In step (1), bonding the epitaxial layer and the layer to be bonded comprises: A first bonding layer is deposited to cover the upper surface of the epitaxial layer; a second bonding layer is formed on the upper surface of the layer to be bonded, and the epitaxial layer and the layer to be bonded are bonded with the first bonding layer and the second bonding layer as bonding surfaces.

3. The surface treatment method of the heteroepitaxial thin film epitaxial layer according to claim 2, characterized in that: In step (1), the bonding layer material is single crystal Si, amorphous silicon, SiO2, gold, tin or silver.

4. The surface treatment method of the heteroepitaxial thin film epitaxial layer according to claim 1 or 2, characterized in that: In step (1), the bonding method is fusion bonding, metal bonding or plasma activation bonding, and the bonding temperature is 200°C-1400°C.

5. The surface treatment method of the heteroepitaxial thin film epitaxial layer according to claim 1, characterized in that: In step (1), the epitaxial substrate material is one or more of glass, silicon, silicon carbide, silicon nitride, sapphire or ceramic.

6. The surface treatment method of the heteroepitaxial thin film epitaxial layer according to claim 1, characterized in that: In step (1), the epitaxial layer material is one or more of aluminum nitride, scandium aluminum nitride, and gallium nitride.

7. The surface treatment method of the heteroepitaxial thin film epitaxial layer according to claim 1, characterized in that: In step (1), the thickness of the three-layer photoresist structure mask is 10 μm-20 μm.

8. The surface treatment method of the heteroepitaxial thin film epitaxial layer according to claim 1, characterized in that: In step (2), the mass ratio of Si to C in the three-layer photoresist mask is 10%-90%.

9. The surface treatment method of the heteroepitaxial thin film epitaxial layer according to claim 1, characterized in that: In step (3), the heating temperature is 100°C-150°C.

10. The surface treatment method of the heteroepitaxial thin film epitaxial layer according to claim 1, characterized in that: The thickness uniformity of the planarized three-layer structure mask is less than 1 μm.

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