Method for manufacturing semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device, providing a substrate, on which a cell region and first to third device regions are formed in sequence and adjacent to each other; forming a second gate oxide layer on the substrate, the second gate oxide layer comprising a bottom oxide layer, a nitride layer and a top oxide layer stacked from bottom to top; etching and removing the second gate oxide layer in the cell region, depositing a fourth gate oxide layer covering the cell region and the second gate oxide layer on the substrate; etching and removing the second gate oxide layer and the fourth gate oxide layer in the first device region, and then forming a first gate oxide layer covering the first device region; etching and removing the top oxide layer and the nitride layer in the second device region and the third device region; etching and removing the bottom oxide layer on the third device region, and then forming a third gate oxide layer on the third device region. In the semiconductor device of the present invention, different gate oxide layers are formed on the surface of each device region, respectively, so that the coexistence of gate oxide layers of different devices is achieved, and the speed and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] Embedded flash (E-Flash) is to embed flash memory into CMOS (Complementary Metal-Oxide-Semiconductor Transistor) to form SOC (System on a Chip). Embedded SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) flash memory is to embed SONOS flash into the logic platform based on the existing logic platform. The semiconductor device contains a selection tube (SG) and a storage tube (CG), namely the SG area and the Cell area.

[0003] In existing CMOS, the threshold voltage of the core device is 1.1V, while the threshold voltage of the IO (input and output) device is 2.5V and 3.3V, and they cannot coexist. In existing semiconductor devices, 2.5V is used as the operating voltage of the selector (SG) and IO devices. However, in actual applications, in order to increase the computing speed, a lower operating voltage, such as 1.8V, is used, and in order to improve reliability, a higher operating voltage, such as 3.3V, is used. Therefore, a non-2.5V operating voltage is used on the 2.5V SG, which leads to a decrease in the life of the device. The inability of gate oxide layers of different devices to coexist actually restricts the coexistence of device speed and reliability. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing a semiconductor device, which is used to solve the problem in the prior art that gate oxide layers of different devices cannot coexist, thereby restricting the speed and reliability of the device.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] Step 1, providing a substrate, on which a cell region, a first device region, a second device region and a third device region are sequentially formed and adjacent to each other;

[0007] Step 2: forming a second gate oxide layer on the substrate covering the cell region and the first to third device regions, wherein the second gate oxide layer comprises a bottom oxide layer, a nitride layer and a top oxide layer stacked from bottom to top;

[0008] Step 3, etching and removing the second gate oxide layer above the cell region, and then depositing a fourth gate oxide layer covering the cell region and the second gate oxide layer on the substrate;

[0009] Step 4: etching and removing the second gate oxide layer and the fourth gate oxide layer above the first device region, and then forming a first gate oxide layer covering the first device region;

[0010] Step 5: etching and removing the top oxide layer and the top nitride layer of the second device region and the third device region;

[0011] Step six: etching and removing the bottom oxide layer on the third device region, and then forming a third gate oxide layer on the third device region.

[0012] Preferably, the threshold voltage of the device in the first device region in step 1 is 3.3V.

[0013] Preferably, the threshold voltage of the device in the second device region in step one is 2.5V.

[0014] Preferably, the threshold voltage of the device in the third device region in step 1 is 1.1V.

[0015] Preferably, in step 1, the first to third device areas include flash memory devices or logic devices.

[0016] Preferably, the etching in step three to step six is ​​dry etching.

[0017] Preferably, the etching in step three to step six is ​​wet etching.

[0018] Preferably, in step five, the method for removing the top oxide layer and the nitride layer is: removing the top oxide layer by a first etching, and then removing the nitride layer by a second etching, so that the bottom oxide layer remains.

[0019] Preferably, the first to fourth gate oxide layers in step 2 to step 6 are formed by a furnace tube.

[0020] Preferably, the first to fourth gate oxide layers in step 2 to step 6 are formed by an in-situ water vapor generation process.

[0021] A semiconductor device can be formed by the method of any of the above steps, including:

[0022] A substrate is provided on which a cell region and a plurality of device regions are sequentially adjacent to each other; different gate oxide layers are respectively formed on the surfaces of the cell region and each of the device regions.

[0023] Preferably, the device region includes devices with a threshold voltage of 3.3V.

[0024] Preferably, the device region includes devices with a threshold voltage of 2.5V.

[0025] Preferably, the device region includes devices with a threshold voltage of 1.1V.

[0026] Preferably, the device is a flash memory device or a logic device.

[0027] As described above, the method for manufacturing a semiconductor device of the present invention has the following beneficial effects:

[0028] In the semiconductor device of the present invention, different gate oxide layers are formed on the surface of each device region, thereby achieving the coexistence of gate oxide layers of different devices and improving the speed and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is a schematic diagram of the process flow of the present invention;

[0030] Figure 2 Shown is a schematic diagram of the structure of the substrate portion of the present invention;

[0031] Figure 3 It is a schematic diagram showing the formation of a second gate oxide layer according to the present invention;

[0032] Figure 4 Shown is an enlarged schematic diagram of the structure at A of the present invention;

[0033] Figure 5 It is a schematic diagram showing the formation of a fourth gate oxide layer according to the present invention;

[0034] Figure 6 It is a schematic diagram showing the formation of a first gate oxide layer according to the present invention;

[0035] Figure 7 It is a schematic diagram showing etching of the fourth gate oxide layer, the top oxide layer and the nitride layer according to the present invention;

[0036] Figure 8 It is a schematic diagram showing etching the bottom oxide layer on the third device region according to the present invention;

[0037] Fig. 9 It is a schematic diagram showing the formation of the third gate oxide layer according to the present invention. DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] See also Figure 1 The present invention provides a method for manufacturing a semiconductor device, comprising:

[0040] Step 1, see Figure 2 , providing a substrate 1, on which a cell region 11, a first device region 12, a second device region 13 and a third device region 14 are formed in sequence and adjacent to each other;

[0041] It should be understood that more device regions may be formed on the substrate 1 , and only the first to third device regions ( 12 , 13 , 14 ) are described in this embodiment.

[0042] In an optional implementation, the threshold voltage of the first device region 12 in step 1 is 3.3V.

[0043] In an optional implementation, the threshold voltage of the second device region 13 in step 1 is 2.5V.

[0044] In an optional implementation, the threshold voltage of the third device region 14 in step 1 is 1.1V.

[0045] It should be understood that the threshold voltages of the first to third device regions ( 12 , 13 , 14 ) in step 1 may also be changed according to actual product requirements, and more device regions with different threshold voltages may also be formed on the substrate 1 .

[0046] In an optional implementation, the first to third devices in step one are flash memory devices or logic devices.

[0047] Step 2, see Figure 3 A second gate oxide layer 131 is formed on the substrate 1, covering the cell region 11 and the first to third device regions (12, 13, 14). The second gate oxide layer 131 includes stacked layers from bottom to top, such as Figure 4 The bottom oxide layer 1313, the nitride layer 1312 and the top oxide layer 1311 are shown;

[0048] Specifically, the second gate oxide layer 131 may be formed by, for example, placing the substrate 1 in a furnace tube or using an in-situ water vapor generation process.

[0049] Step 3, see Figure 5, etching and removing the second gate oxide layer 131 above the cell region 11, and then depositing a fourth gate oxide layer 111 covering the cell region 11 and the second gate oxide layer 131 on the substrate 1;

[0050] Specifically, a photoresist may be formed by photolithography on top of the first to third gate oxide layers (12, 13, 14) to expose the second gate oxide layer 131 on the cell region 11. The second gate oxide layer 131 on the cell region 11 may then be removed by dry etching or wet etching the exposed second gate oxide layer 131. A fourth gate oxide layer 111 may then be formed on the cell region 11 by, for example, placing the substrate 1 in a furnace tube or by an in-situ water vapor generation process, and then removing the photoresist.

[0051] Step 4, see Figure 6 , etching and removing the second gate oxide layer 131 and the fourth gate oxide layer 111 above the first device region 12, and then forming a first gate oxide layer 121 covering the first device region 12;

[0052] Specifically, a photoresist may be formed by photolithography above the cell region 11, the second device region 13, and the third device region 14, so that the first gate oxide layer 121 and the third gate oxide layer 141 on the first device region 12 are exposed, and then the second gate oxide layer 131 on the first device region 12 may be removed by dry etching or wet etching of the exposed first gate oxide layer 121 and the third gate oxide layer 141, and then the second gate oxide layer 131 may be formed on the cell region 11 by, for example, placing the substrate 1 in a furnace tube or by an in-situ water vapor generation process, and then removing the photoresist.

[0053] Step 5, see Figure 7 , removing the top oxide layer 1311 and the top nitride layer 1312 of the second device region 13 and the third device region 14 by dry etching or wet etching;

[0054] In an optional embodiment, the method for removing the top oxide layer 1311 and the nitride layer 1312 in step five is: after forming a mask protection such as a photoresist on the first gate oxide layer and the second gate oxide layer, remove the top oxide layer 1311 by a first etching, and then remove the nitride layer 1312 by a second etching, so that the bottom oxide layer 1313 is retained.

[0055] Step 6, see Figure 8 The bottom oxide layer 1313 on the third device region 14 is removed by dry etching or wet etching, and then, for example, the substrate 1 can be placed in a furnace tube or an in-situ water vapor generation process to form a substrate 1313 on the third device region 14. Fig. 9 A third gate oxide layer 141 is shown.

[0056] A semiconductor device can be formed by the method of any of the above steps, including:

[0057] A substrate 1 is provided on which a cell region 11 and first to third device regions are formed in sequence; different gate oxide layers are respectively formed on the surfaces of the cell region 11 and the first to third device regions (12, 13, 14).

[0058] In an optional implementation, the first device region 12 includes devices with a threshold voltage of 3.3V.

[0059] In an optional implementation, the second device region 13 includes devices with a threshold voltage of 2.5V.

[0060] In an optional implementation, the third device region 14 includes devices with a threshold voltage of 1.1V.

[0061] In an optional implementation, the devices in the first to third device areas (12, 13, 14) are flash memory devices or logic devices.

[0062] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0063] In summary, in the semiconductor device of the present invention, different gate oxide layers are formed on the surface of each device region, achieving the coexistence of gate oxide layers of different devices, and improving the speed and reliability of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: At least: Step 1, providing a substrate, on which a cell region and first to third device regions are sequentially adjacent to each other are formed; Step 2: forming a second gate oxide layer on the substrate covering the cell region and the first to third device regions, wherein the second gate oxide layer comprises a bottom oxide layer, a nitride layer and a top oxide layer stacked from bottom to top; Step 3, etching and removing the second gate oxide layer above the cell region, and then depositing a fourth gate oxide layer covering the cell region and the second gate oxide layer on the substrate; Step 4: etching and removing the second gate oxide layer and the fourth gate oxide layer above the first device region, and then forming a first gate oxide layer covering the first device region; Step 5: etching and removing the top oxide layer and the top nitride layer of the second device region and the third device region; Step six: etching and removing the bottom oxide layer on the third device region, and then forming a third gate oxide layer on the third device region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The threshold voltage of the device in the first device region in step 1 is 3.3V.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The threshold voltage of the device in the second device region in step 1 is 2.5V.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The threshold voltage of the device in the third device region in step 1 is 1.1V.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: In step 1, the first to third device areas include flash memory devices or logic devices.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching in step 3 to step 6 is dry etching.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching in step 3 to step 6 is wet etching.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for removing the top oxide layer and the nitride layer in step five is: removing the top oxide layer by a first etching, and then removing the nitride layer by a second etching, so that the bottom oxide layer remains.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The first to fourth gate oxide layers in step 2 to step 6 are formed by using a furnace tube.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The first to fourth gate oxide layers in step 2 to step 6 are formed by an in-situ water vapor generation process.

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