Semiconductor structure

Abstract

A semiconductor structure includes a first substrate including a wiring structure, a first semiconductor die and a second semiconductor die disposed on the first substrate, and a multi-terminal multi-capacitor structure disposed on the first substrate, the multi-terminal multi-capacitor structure including a second substrate, an insulating layer disposed above the second substrate, a first multi-terminal capacitor disposed above the insulating layer and electrically coupled to the first semiconductor die through the wiring structure, and a second multi-terminal capacitor disposed above the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate. The present invention can reduce the space occupied by the capacitor and can increase the conductive structure reserved on the substrate. Therefore, the present invention can increase the design flexibility and can be designed more easily.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor structure, and in particular, to a semiconductor structure. BACKGROUND

[0002] As high performance integrated circuits require larger currents at lower supply voltages at higher frequencies, the design of power supply systems is increasingly a challenge. Decoupling capacitors can be employed as temporary charge reservoirs to prevent momentary fluctuations in the supply voltage. Decoupling capacitors are increasingly important to reduce power supply noise in digital circuits, such as microprocessors, which include many transistors that alternate between on and off states.

[0003] While existing semiconductor structures are generally adequate, they are not satisfactory in every respect. For example, it is challenging to integrate decoupling capacitors because multiple capacitors must be used for different power domains. For example, a central processing unit (CPU) can require one decoupling capacitor, while a high performance system-on-chip (SOC) die can require 5 to 10 decoupling capacitors. Therefore, there is a need for further improvements in semiconductor structures to provide design flexibility. SUMMARY

[0004] Accordingly, the present application provides a semiconductor structure to solve the above problems.

[0005] According to a first aspect of the present application, there is disclosed a semiconductor structure comprising:

[0006] a first substrate comprising a wiring structure;

[0007] a first semiconductor die and a second semiconductor die disposed on the first substrate; and a multi-terminal multi-capacitance structure disposed on the first substrate, the multi-terminal multi-capacitance structure comprising:

[0008] a second substrate; an insulating layer disposed above the second substrate; a first multi-terminal capacitor disposed above the insulating layer and electrically coupled to the first semiconductor die through the wiring structure; and a second multi-terminal capacitor disposed above the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first and second multi-terminal capacitors are electrically isolated from the second substrate.

[0009] According to a second aspect of the present application, there is disclosed a semiconductor structure comprising:

[0010] A multi-terminal multi-capacitor structure includes: an insulating layer; a first multi-terminal capacitor disposed on the insulating layer and including a first positive terminal and a first ground terminal; and a second multi-terminal capacitor disposed on the insulating layer and including a second positive terminal and a second ground terminal, wherein the second multi-terminal capacitor is electrically isolated from the first multi-terminal capacitor; and

[0011] A package structure disposed on the multi-terminal multi-capacitor structure includes: a first semiconductor die electrically coupled to the first multi-terminal capacitor; and a second semiconductor die electrically coupled to the second multi-terminal capacitor.

[0012] The semiconductor structure of the present invention includes: a first substrate including a wiring structure; a first semiconductor die and a second semiconductor die disposed on the first substrate; and a multi-terminal multi-capacitor structure disposed on the first substrate, the multi-terminal multi-capacitor structure including: a second substrate; an insulating layer disposed above the second substrate; a first multi-terminal capacitor disposed above the insulating layer and electrically coupled to the first semiconductor die through the wiring structure; and a second multi-terminal capacitor disposed above the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate. Compared to using separate capacitors for different voltage domains for different semiconductors, the present invention employs a multi-terminal multi-capacitor structure including multiple capacitors and multiple terminals. The terminals include positive terminals and ground terminals. Therefore, the present invention can reduce the space occupied by the capacitors and can increase the conductive structures remaining on the substrate. Therefore, the present invention can increase design flexibility and can be designed more easily. The present invention can also provide an improvement in semiconductor package performance. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a top view of an exemplary semiconductor structure according to some embodiments;

[0014] Figure 2 is a top view of an exemplary semiconductor structure according to some embodiments;

[0015] Figure 3 is a cross-sectional view of an exemplary semiconductor structure according to some embodiments;

[0016] Figure 4A and 4B is a top view of a multi-terminal multi-capacitor structure of an exemplary semiconductor structure according to some embodiments;

[0017] Figure 5A 、 5B and 5C are conceptual diagrams of a multi-terminal multi-capacitor structure of an exemplary semiconductor structure according to some embodiments;

[0018] Figure 6 is a cross-sectional view of a multi-terminal multi-capacitance structure of an exemplary semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features are formed between the first and second features such that the first and second features do not directly contact. In addition, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0020] In addition, in some embodiments of the present disclosure, terms concerning attachments, coupling and the like, such as "connected" and "interconnected," refer to a relationship wherein structures are secured or attached to one another either directly or indirectly. Unless explicitly described as being "directly connected," otherwise, intervening structures, as well as attachable or detachable objects or relationships, can be included in the attachment or connection. In addition, the term "coupled" includes any method of direct and indirect electrical connection.

[0021] Furthermore, to facilitate description, spatially relative terms such as "beneath", "below", "lower", "above", "upper" are used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] The terms "about", "substantially" and "approximately" generally mean within ±20% of a stated value, or within ±10% of a stated value, or within ±5% of a stated value, or within ±3% of a stated value, or within ±2% of a stated value, or within ±1% of a stated value, or within ±0.5% of a stated value. The stated values of the present disclosure are approximations. The stated values include the meaning of "about", "substantially" and "approximately" when not specifically described. The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting of the present disclosure. As used herein, the singular terms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0023] Some embodiments of the application are described below. Additional operations can be provided before, after, and / or between stages described in these embodiments. Certain stages described can be replaced or eliminated, for different embodiments. Additional features can be added to the semiconductor device structure. For different embodiments, some features described below can be replaced or eliminated. Although some embodiments are discussed with operations performed in a particular order, these operations can be performed in another logical order.

[0024] A semiconductor structure is described according to some embodiments of the application. The semiconductor structure includes a multi-terminal multi-capacitor structure with more than one terminal and more than one capacitor to reduce footprint and improve design flexibility.

[0025] Figure 1 is a top view of a semiconductor structure 100 according to some embodiments of the application. Additional features can be added to the semiconductor structure 100. For different embodiments, some features described below can be replaced or eliminated. Only a portion of the semiconductor structure 100 is shown in this figure for simplicity.

[0026] As shown in Figure 1 , according to some embodiments, the semiconductor structure 100 includes a substrate 102. There can be wiring structures inside the substrate 102. In some embodiments, the wiring structures in the substrate 102 include conductive layers, conductive vias, conductive pillars, etc., or a combination thereof. The wiring structures in the substrate 102 can be formed of metal, such as copper, aluminum, or a combination thereof.

[0027] The wiring structures in the substrate 102 can be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer is formed of organic material, such as polymer base material, non-organic material, such as silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. The substrate 102 can have a first surface and a second surface opposite to the first surface. It is noted that the configuration of the substrate 102 shown in the figures is only exemplary and is not intended to limit the application. Any desired semiconductor elements can be formed in and on the substrate 102. However, only a flat substrate 102 is shown for simplicity.

[0028] As shown in Figure 1As shown, according to some embodiments, the semiconductor structure 100 includes a plurality of conductive structures 104. The conductive structures 104 can be disposed on the first surface of the substrate 102 and can be electrically coupled to the wiring structures of the substrate 102. In some embodiments, the conductive structures 104 include a conductive material, such as a metal. The conductive structures 104 can be micro bumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, or the like, or combinations thereof.

[0029] According to some embodiments, the semiconductor structure 100 includes a first semiconductor die 106 and a second semiconductor die 108. The first semiconductor die 106 and the second semiconductor die 108 can be disposed on the second surface of the substrate 102 and are shown for illustrative purposes only. For example, the conductive structures 104 are disposed on the first surface of the substrate 102, where the first semiconductor die 106, the second semiconductor die 108, and the multi-terminal multi-capacitance structure 110 are disposed above the second surface of the substrate 102.

[0030] The first semiconductor die 106 and the second semiconductor die 108 can be electrically coupled to the wiring structures of the substrate 102.

[0031] According to some embodiments, the first semiconductor die 106 and the second semiconductor die 108 each independently include a system on chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, or the like, or combinations thereof. For example, the first semiconductor die 106 and the second semiconductor die 108 can each independently include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a global positioning system (GPS) device, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input-output (IO) chip, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high bandwidth memory (HBM), or combinations thereof.

[0032] According to some embodiments, the semiconductor structure 100 includes a first capacitor 106C and a second capacitor 108C disposed on the second surface of the substrate 102. The first capacitor 106C can be electrically coupled to the first semiconductor die 106 through the wiring structure of the substrate 102, and the second capacitor 108C can be electrically coupled to the second semiconductor die 108 through the wiring structure of the substrate 102. The first capacitor 106C and the second capacitor 108C can be provided to reduce current-resistance (IR) drop.

[0033] The first capacitor 106C and the second capacitor 108C each occupy space. As shown, the first capacitor 106C and the second capacitor 108C each occupy, for example, the area of six (6) conductive structures 104, respectively. As the demand for more functionality and smaller devices continues to increase, it is challenging to integrate different capacitors for different semiconductor components. Accordingly, the present disclosure provides another embodiment to address the above issues. Figure 1

[0034] Figure 2 is a top view of a semiconductor structure 200 according to some other embodiments of the present disclosure. It is noted that the semiconductor structure 200 can include the same or similar components as the semiconductor structure 100 shown in Figure 1 , and these components will not be discussed in detail for the sake of simplicity. In contrast to the embodiment of the semiconductor structure 100 including multiple capacitors, the following embodiments replace these capacitors with a multi-terminal multi-capacitor structure to reduce the footprint. Figure 1 As shown, according to some embodiments, the semiconductor structure 200 includes a multi-terminal multi-capacitor structure (or multi-port multi-capacitor structure) 110. The multi-terminal multi-capacitor structure 110 can occupy, for example, the area of six (6) conductive structures 104. That is, different power domains can share one multi-terminal multi-capacitor structure 110. Thus, there is no need to design a separate capacitor for each different voltage. Accordingly, the footprint can be reduced, more conductive structures 104 can be preserved, and design flexibility can be provided.

[0035] Figure 2 As shown, according to some embodiments, the semiconductor structure 200 includes a multi-terminal multi-capacitor structure (or multi-port multi-capacitor structure) 110. The multi-terminal multi-capacitor structure 110 can occupy, for example, the area of six (6) conductive structures 104. That is, different power domains can share one multi-terminal multi-capacitor structure 110. Thus, there is no need to design a separate capacitor for each different voltage. Accordingly, the footprint can be reduced, more conductive structures 104 can be preserved, and design flexibility can be provided.

[0036] The multi-terminal multi-capacitor structure 110 can include capacitors for the first semiconductor die 106 and capacitors for the second semiconductor die 108 arranged side-by-side. The first semiconductor die 106 and the second semiconductor die 108 can also be arranged side-by-side. The sidewalls of the first semiconductor die 106 can be aligned with the sidewalls of the second semiconductor die 108. However, the present disclosure is not limited thereto. For example, the first semiconductor die 106 and the second semiconductor die 108 can be vertically stacked. ​​

[0037] In some embodiments, as shown in Figure 2 The multi-terminal multi-capacitance structure 110 partially overlaps the first semiconductor die 106 and the second semiconductor die 108 in a direction substantially perpendicular to the first surface of the substrate 102. Alternatively, the multi-terminal multi-capacitance structure 110 can partially overlap the first semiconductor die 106 or the second semiconductor die 108 in a direction substantially perpendicular to the first surface of the substrate 102.

[0038] As shown in Figure 2 The multi-terminal multi-capacitance structure 110 can be surrounded by the conductive structures 104. The number of conductive structures 104 adjacent to the multi-terminal multi-capacitance structure 110 can be the same or different on each side of the multi-terminal multi-capacitance structure 110. The number and configuration of the multi-terminal multi-capacitance structure 110 and the conductive structures 104 are shown for illustrative purposes only.

[0039] As shown in Figure 2 Two semiconductor dies, the first semiconductor die 106 and the second semiconductor die 108, share one multi-terminal multi-capacitance structure 110, but the present disclosure is not limited thereto. For example, more than two semiconductor dies can share a multi-terminal multi-capacitance structure 110 in a direction substantially perpendicular to the first surface of the substrate 102 and partially overlap the multi-terminal multi-capacitance structure 110 in the direction. Alternatively, more than one multi-terminal multi-capacitance structure can be used for multiple semiconductor dies. According to some embodiments, the semiconductor structure 200 further includes one or more passive elements (not shown), such as resistors, capacitors, inductors, or combinations thereof.

[0040] Figure 3 is a cross-sectional view of a semiconductor structure 300 according to some embodiments of the present disclosure. It is noted that the semiconductor structure 300 can include the same or similar elements as the semiconductor structure 200 shown in Figure 2 for simplicity and brevity. In the following embodiments, three semiconductor dies share a multi-terminal multi-capacitance structure.

[0041] As shown in Figure 3 According to some embodiments, the semiconductor structure 300 includes a first semiconductor die 122, a second semiconductor die 124, and a third semiconductor die 126 having a first voltage domain VI, a second voltage domain V2, and a third voltage domain V3, respectively. In some embodiments, the first semiconductor die 122, the second semiconductor die 124, and the third semiconductor die 126 can be included in a package structure (or referred to as a semiconductor package, a semiconductor package structure) 120. In some other embodiments, the first semiconductor die 122, the second semiconductor die 124, and the third semiconductor die 126 can be included in the package structure 120. The third semiconductor die 126 can be separate, e.g., not in the package structure 120.

[0042] The first semiconductor die 122, the second semiconductor die 124, and the third semiconductor die 126 may include similar or different components. The first semiconductor die 122, the second semiconductor die 124, and the third semiconductor die 126 may be similar to... Figure 2 The first semiconductor die 106 and / or the second semiconductor die 108 shown are not described in detail here. According to some embodiments, the package structure 120 also includes one or more passive components (not shown), such as resistors, capacitors, inductors, or combinations thereof.

[0043] like Figure 3 As shown, according to some embodiments, the semiconductor structure 300 includes a plurality of conductive structures 114 between the package structure 120 and the substrate 102. A first semiconductor die 122, a second semiconductor die 124, and a third semiconductor die 126 can be electrically coupled to the wiring structure of the substrate 102 via the conductive structures 114. In some embodiments, the conductive structures 114 include a conductive material, such as a metal. The conductive structures 114 may be microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, or combinations thereof. The conductive structures 114 may be similar to or different from the conductive structure 104. Figure 3 The arrangement shown has the semiconductor die and the multi-terminal multi-capacitor structure on two opposite surfaces of the substrate 102, and the conductive structure 104 is on the periphery of the multi-terminal multi-capacitor structure, which can save area and is beneficial to the miniaturization of semiconductor packaging.

[0044] like Figure 3 As shown, according to some embodiments, the semiconductor structure 300 includes a multi-terminal multi-capacitor structure 110. The multi-terminal multi-capacitor structure 110 may include a plurality of multi-terminal capacitors (not shown) for a first semiconductor die 122, a second semiconductor die 124, and a third semiconductor die 126, which may be referred to as the first multi-terminal capacitor, the second multi-terminal capacitor, and the third multi-terminal capacitor, respectively.

[0045] In some embodiments, the first multi-terminal capacitor, the second multi-terminal capacitor, and the third multi-terminal capacitor each include a first terminal 112a, a second terminal 112b, and a third terminal 112c. Each of the first terminal 112a, the second terminal 112b, and the third terminal 112c includes a positive terminal and a ground terminal (ground terminal), thereby reducing the equivalent series resistor (SR) and the equivalent series inductance (SL) to reduce the system IR voltage drop.

[0046] The first semiconductor die 122 can be electrically coupled to the first multi-terminal capacitor through the first terminal 112a, the wiring structure of the substrate 102 and the conductive structure 114. The second semiconductor die 124 can be electrically coupled to the second multi-terminal capacitor through the second terminal 112b, the wiring structure of the substrate 102 and the conductive structure 114. The third semiconductor die 126 can be electrically coupled to the third multi-terminal capacitor through the third terminal 112c, the wiring structure of the substrate 102 and the conductive structure 114. For example, the first terminal 112a has two terminals, which are the terminals of the two poles of the capacitor; the second terminal 112b and the third terminal 112c are also the same. Specifically, for example, the first semiconductor die 122 can be electrically coupled to the first multi-terminal capacitor through two first terminals 112a, a first set of wiring structures of the substrate 102 and a first set of conductive structures 114. The second semiconductor die 124 can be electrically coupled to the second multi-terminal capacitor through two second terminals 112n, a second set of wiring structures of the substrate 102 and a second set of conductive structures 114. The third semiconductor die 126 can be electrically coupled to the third multi-terminal capacitor through two third terminals 112c, a third set of wiring structures of the substrate 102 and a third set of conductive structures 114. Wherein the first set of wiring structures, the second set of wiring structures and the third set of wiring structures are independent of each other and are not electrically connected (for example, electrically isolated) with each other; the first set of conductive structures, the second set of conductive structures and the third set of conductive structures are independent of each other and are not electrically connected (for example, electrically isolated) with each other. In this way, each semiconductor die is independently connected to a mutually independent multi-terminal capacitor (for example, the first multi-terminal capacitor, the second multi-terminal capacitor, etc.), and works independently of each other. Of course, if necessary, the multi-terminal capacitors can also have electrical connection (for example, two multi-terminal capacitors are connected to a common voltage terminal, etc., which can be achieved by mutual connection between the wiring structures, or mutual connection between the conductive structures 114, or mutual connection between the terminals), depending on the specific needs, which is not limited by the present application. Figure 3In this embodiment, the multi-terminal multi-capacitor structure 110 has three capacitors, which are electrically connected to the first semiconductor die 122, the second semiconductor die 124, and the third semiconductor die 126, respectively, providing different voltage domains. The three capacitors in the multi-terminal multi-capacitor structure 110 may not be electrically connected to each other, or each may have a terminal connected to a common ground or a terminal connected to the same voltage. The three capacitors operate independently and are integrated into the multi-terminal multi-capacitor structure 110. Of course, the multi-terminal multi-capacitor structure 110 can have more capacitors, all of which can operate independently to meet different capacitance requirements. Furthermore, in this embodiment, the number of semiconductor dies can be four, five, or more, and the number of multi-terminal capacitors in the multi-terminal multi-capacitor structure can be four, five, or more; the number of semiconductor dies and the number of multi-terminal capacitors need not be the same, for example, there can be more semiconductor dies or more multi-terminal capacitors.

[0047] like Figure 3 As shown, according to some embodiments, the multi-terminal multi-capacitor structure 110 is a connected land-side capacitor (LSC). Specifically, the multi-terminal multi-capacitor structure 110 and semiconductor dies 122, 124, 126 (or package structure 120) can be disposed on opposite sides of the substrate 102. The multi-terminal multi-capacitor structure 110 and conductive structure 104 can be disposed on the same side of the substrate 102. The semiconductor dies 122, 124, 126 (or package structure 120) can partially overlap with the multi-terminal multi-capacitor structure 110 and conductive structure 104.

[0048] Alternatively, according to some other embodiments, the multi-terminal multi-capacitor structure 110 may be a die-side capacitor (DSC) (not shown). Specifically, the multi-terminal multi-capacitor structure 110 and the semiconductor dies 122, 124, 126 (or package structure 120) may be disposed on the same side of the substrate 102. The multi-terminal multi-capacitor structure 110 and the conductive structure 104 may be disposed on opposite sides of the substrate 102. The multi-terminal multi-capacitor structure 110 may be adjacent to one or more of the semiconductor dies 122, 124, 126 (or package structure 120). The semiconductor dies 122, 124, 126 (or package structure 120) and the multi-terminal multi-capacitor structure 110 may partially overlap with the conductive structure 104.

[0049] like Figure 3As shown, the first semiconductor die 122, the second semiconductor die 124, and the third semiconductor die 126 are arranged in a row, shown for illustrative purposes only. For example, the first semiconductor die 122, the second semiconductor die 124, and the third semiconductor die 126 may be stacked vertically. Similarly, the first terminal 112a, the second terminal 112b, and the third terminal 112c arranged in a row are for illustrative purposes only. Some exemplary configurations are described below.

[0050] Figure 4A This is a top view of a multi-terminal multi-capacitor structure 400a according to some embodiments. It is worth noting that the multi-terminal multi-capacitor structure 400a may include... Figure 3 The components of the multi-terminal multi-capacitor structure 110 of the semiconductor structure 300 shown are the same or similar, and for simplicity, these components will not be discussed in detail.

[0051] In some embodiments, the first terminal 112a includes a first positive terminal V1 and a first ground terminal GND1, the second terminal 112b includes a second positive terminal V2 and a second ground terminal GND2, and the third terminal 112c includes a third positive terminal V3 and a third ground terminal GND3. The multi-terminal multi-capacitor structure 110 also includes some other terminals shown for illustrative purposes only. Two adjacent terminals 112a, 112b, and 112c can be arranged side-by-side. Two adjacent terminals in a multi-terminal capacitor including terminals 112a, 112b, and 112c can also be arranged side-by-side.

[0052] like Figure 4A As shown, the first positive terminal V1, the second ground terminal GND2, and the third positive terminal V3 can be arranged along the first line, and the first ground terminal GND1, the second positive terminal V2, and the third ground terminal GND3 can be arranged along the second line. The first line can be substantially parallel to the second line. Figure 4A In this embodiment, the two electrodes of each multi-terminal capacitor are connected to different locations to accommodate different needs. Alternatively, at least two of the multi-terminal capacitors may have their two electrodes connected to the same voltage terminal, depending on design requirements.

[0053] According to some embodiments, Figure 5A A conceptual diagram of a multi-terminal, multi-capacitor structure 400a is shown. The first multi-terminal capacitor (including a first positive terminal V1 and a first ground terminal GND1), the second multi-terminal capacitor (including a second positive terminal V2 and a second ground terminal GND2), and the third multi-terminal capacitor (including a third positive terminal V3 and a third ground terminal GND3) can be separate. Specifically, the first, second, and third multi-terminal capacitors can be electrically isolated from each other.

[0054] Figure 4B is a top view of a multi-terminal multi-capacitance structure 400b according to some embodiments. Note that the multi-terminal multi-capacitance structure 400b can include the same or similar components as the multi-terminal multi-capacitance structure 400a shown in Figure 4B for simplicity, these components are not discussed in detail again.

[0055] In some embodiments, the first positive terminal, the second positive terminal, the third positive terminal, and the fourth positive terminal are equal, which can be referred to as V4. In some embodiments, the first ground terminal, the second ground terminal, the third ground terminal, and the fourth ground terminal are equal, which can be referred to as GND4. Two adjacent terminals can be arranged side by side. Two adjacent ones in a multi-terminal capacitor including these terminals can also be arranged side by side.

[0056] As shown in Figure 4B , the first positive terminal, the second positive terminal, the third positive terminal, and the fourth positive terminal V4 can be arranged along a first line, and the first ground terminal, the second ground terminal, the third ground terminal, and the fourth ground terminal GND4 can be arranged along a second line. The first line can be substantially parallel to the second line. Figure 4B In some embodiments, one of the two electrodes of each of the plurality of multi-terminal capacitors is connected to the same reference voltage, and the other electrode is connected to another same reference voltage. For example, one of the two electrodes is connected to the voltage V4, and the other electrode is connected to the voltage GND4. Of course, at least one of the two electrodes of at least one of the multi-terminal capacitors can be connected differently from the two electrodes of the other multi-terminal capacitors (for example, the Figure 4A embodiments can be used in combination with, or partially in combination with, the embodiments of Figure 4B , depending on design requirements. Figure 4A-4B Figures 1A and 1B show different connection examples of the two electrodes (or terminals) of each capacitor in the multi-terminal multi-capacitance structure 100, where the two electrodes (or terminals) of each capacitor can also have other connection manners, and are not limited to the manners shown in Figure 4A-4B Figures 1A and 1B. The two electrodes (or terminals) of each capacitor in the multi-terminal multi-capacitance structure 100 can be electrically connected freely according to different needs.

[0057] According to some embodiments, a conceptual diagram of six terminals of a multi-terminal multi-capacitance structure 400b is shown in Figure 5B . The first positive terminal, the second positive terminal, and the third positive terminal V4 can be electrically coupled to each other. The first ground terminal, the second ground terminal, and the third ground terminal GND4 can be electrically coupled to each other. That is, the first multi-terminal capacitor, the second multi-terminal capacitor, and the third multi-terminal capacitor can be electrically coupled to each other.

[0058] Figure 5Cis a conceptual diagram of a multi-terminal multi-capacitance structure according to some embodiments. In some embodiments, a first terminal includes a first positive terminal VI and a first ground terminal, a second terminal includes a second positive terminal V2 and a second ground terminal, and a third terminal includes a third positive terminal V3 and a third ground terminal. The first ground terminal, the second ground terminal, and the third ground terminal can be electrically coupled to a common ground terminal GND5. Figure 5A-5C The connection of the two electrodes (or terminals) of each capacitor in the multi-terminal multi-capacitance structure 100 is shown as an example, and each capacitor can have other connection manners, and is not limited to Figure 5A-5C the shown manner. The two electrodes (or terminals) of each capacitor in the multi-terminal multi-capacitance structure 100 can be freely electrically connected according to different needs. Figure 5A-5C The two electrodes of each capacitor in the shown three capacitors are not electrically connected, so each capacitor works independently.

[0059] Figure 6 is a cross-sectional view of a multi-terminal multi-capacitance structure 600 of a semiconductor structure according to some embodiments. It should be noted that the multi-terminal multi-capacitance structure 600 can include the same or similar components as the multi-terminal multi-capacitance structure 110 shown Figure 3 , and these components will not be discussed in detail for the sake of simplicity.

[0060] As shown in Figure 6 , according to some embodiments, the multi-terminal multi-capacitance structure 600 includes a semiconductor substrate (substrate) 602. The semiconductor substrate 602 can be formed of silicon, silicon germanium, germanium, other suitable semiconductor, or a combination thereof. It should be noted that the configuration of the semiconductor substrate 602 shown in the figure is only exemplary and is not intended to limit the present application. Any desired semiconductor element can be formed in and on the semiconductor substrate 602. However, only a flat semiconductor substrate 602 is shown for the sake of simplicity of illustration.

[0061] As shown in Figure 6 , according to some embodiments, the multi-terminal multi-capacitance structure 600 includes an insulating layer 604 disposed above the semiconductor substrate 602. The insulating layer 604 can cover the top surface of the semiconductor substrate 602. The insulating layer 604 can be formed of silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material, or a combination thereof.

[0062] As shown in Figure 6As shown, the multi-terminal multi-capacitor structure 600 includes a first multi-terminal capacitor 610a and a second multi-terminal capacitor 610b disposed above an insulating layer 604. The insulating layer 604 electrically isolates the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b. The multi-terminal capacitors 610a and 610b are separated from the substrate 102. Therefore, multiple multi-terminal capacitors can be grouped to form a single capacitor (i.e., the multi-terminal multi-capacitor structure 600), which provides decoupling capacitance for different voltage domains, thereby reducing the space occupied by the capacitors. Furthermore, design flexibility can be improved, and performance enhancements can also be provided.

[0063] like Figure 6 As shown, according to some embodiments, each of the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b includes conductive layers 606, 608, and 616. The conductive layers 606, 608, and 616 may be formed of a metal, such as tungsten. According to some embodiments, each of the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b includes a capacitor unit 612 between conductive layers 606 and 608, and includes a plurality of through-holes 614 between conductive layers 606 and 616 and between conductive layers 608 and 616. The through-holes 614 may be formed of a metal, such as copper. Specifically, the capacitor unit 612 in this invention is configured such that conductive layers 606 and 608 can be two electrodes of the capacitor unit, and an insulating layer 630 (e.g., a high-k material) is present between conductive layers 606 and 608. Conductive layers 606 and 608 may include tungsten or other metals, and conductive materials 631 (e.g., polycrystalline silicon) and 632 (e.g., polycrystalline silicon) are further present between conductive layers 606 and 608. Conductive layer 608 is electrically connected to conductive material 631, and conductive layer 606 is electrically connected to conductive material 632. Insulating layer 630 surrounds conductive materials 631 and 632, and spacees conductive material 631 from conductive layer 606 and conductive material 632 from conductive layer 608, thereby forming a capacitor unit. In this invention, each of the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b may have multiple capacitors or capacitor units. Figure 6 The examples shown are merely illustrative and not intended to limit the invention (e.g., limitations on quantity). Furthermore, the multi-terminal multi-capacitor structure 600 of the present invention may include more multi-terminal capacitors in addition to the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b. Figure 6 The examples shown are merely illustrative and are not intended to limit the invention (e.g., limitations on quantity, etc.).

[0064] like Figure 6As shown, according to some embodiments, the multi-terminal multi-capacitance structure 600 includes a dielectric layer 618 disposed above the insulating layer 604 and surrounding the first multi-terminal capacitor 610a and the second multi-terminal capacitor 610b. The dielectric layer 618 can be formed of an organic material (e.g., a polymer base material), a non-organic material (e.g., silicon nitride, silicon oxide, silicon oxynitride), or a combination thereof.

[0065] As shown, according to some embodiments, the multi-terminal multi-capacitance structure 600 includes a plurality of terminals 620 disposed above the conductive layer 616. The terminals 620 can be exposed by the dielectric layer 618. The terminals 620 can be formed of a conductive material such as metal. Figure 6

[0066] The terminals 620 of the first multi-terminal capacitor 610a can include a positive terminal and a ground terminal and can be electrically coupled to a semiconductor die (e.g., the first semiconductor die 122 shown in FIG. 1). The terminals 620 of the second multi-terminal capacitor 610b can include a positive terminal and a ground terminal and can be electrically coupled to another semiconductor die (e.g., the second semiconductor die 124 shown in FIG. 1). The two terminals 620 of each multi-terminal capacitor (e.g., the first multi-terminal capacitor 610a) can be two electrodes of a capacitor, respectively. The multi-terminal capacitors (e.g., the first multi-terminal capacitor 610a, the first multi-terminal capacitor 610b, etc.) in the multi-terminal multi-capacitance structure 600 can be disposed side-by-side or in an array, etc., to achieve integration of multiple capacitors in the multi-terminal multi-capacitance structure to meet different application requirements. Figure 3 Figure 3

[0067] In summary, the present disclosure employs a multi-terminal multi-capacitance structure including multiple capacitors and multiple terminals. The terminals include a positive terminal and a ground terminal. Thus, the present disclosure can reduce the space occupied by the capacitors and can increase the conductive structures (e.g., the conductive structures 104) reserved on the substrate. Thus, the present disclosure can increase design flexibility and can be designed more easily. The present disclosure can also provide an improvement in semiconductor package performance. In addition, the present disclosure can reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), thereby reducing system IR drop.

[0068] Those skilled in the art will readily observe that numerous modifications and changes in the described devices and methods can be made without departing from the teachings of the present disclosure. Accordingly, the above disclosure should be interpreted as illustrative only and is not intended to be in any way limiting.​​​

Claims

1. A semiconductor structure, characterized in that, include: The first substrate includes a wiring structure; A first semiconductor die and a second semiconductor die are disposed on the first substrate; as well as A multi-terminal, multi-capacitor structure is disposed on the first substrate, and the multi-terminal, multi-capacitor structure includes: A second substrate; an insulating layer disposed above the second substrate; a first multi-terminal capacitor disposed above the insulating layer and electrically coupled to the first semiconductor die through the wiring structure; and a second multi-terminal capacitor disposed above the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate. The first semiconductor die and the second semiconductor die are disposed on the first surface of the first substrate, and the multi-terminal multi-capacitor structure is disposed on the second surface of the first substrate opposite to the first surface of the first substrate, and the second substrate is a semiconductor substrate.

2. The semiconductor structure as described in claim 1, characterized in that, It also includes multiple conductive structures disposed on the second surface of the first substrate and adjacent to the multi-terminal multi-capacitor structure.

3. The semiconductor structure as described in claim 1, characterized in that, It also includes multiple conductive structures disposed on the first surface of the first substrate, wherein the first semiconductor die, the second semiconductor die, and the multi-terminal multi-capacitor structure are disposed on a second surface opposite to the first surface of the first substrate.

4. The semiconductor structure as described in claim 1, characterized in that, The first multi-terminal capacitor includes a first positive terminal and a first ground terminal, and the second multi-terminal capacitor includes a second positive terminal and a second ground terminal; The first positive terminal, the first ground terminal, the second positive terminal, and the second ground terminal are disposed between the first substrate and the second substrate.

5. The semiconductor structure as described in claim 4, characterized in that, The first positive terminal and the second positive terminal are arranged along a first line, and the first ground terminal and the second ground terminal are arranged along a second line, wherein the first line is parallel to the second line; or, wherein the first positive terminal and the second ground terminal are arranged along a first line, and the first ground terminal and the second positive terminal are arranged along a second line, wherein the first line is parallel to the second line.

6. The semiconductor structure as described in claim 4, characterized in that, The first grounding terminal and the second grounding terminal are electrically coupled to a common grounding terminal.

7. The semiconductor structure as described in claim 4, characterized in that, The first grounding terminal is electrically coupled to the second grounding terminal.

8. The semiconductor structure as described in claim 7, characterized in that, The first positive terminal is electrically coupled to the second positive terminal.

9. A semiconductor structure, characterized in that, include: A multi-terminal, multi-capacitor structure includes: an insulating layer; a first multi-terminal capacitor disposed on the insulating layer and including a first positive terminal and a first ground terminal; and a second multi-terminal capacitor disposed on the insulating layer and including a second positive terminal and a second ground terminal, wherein the second multi-terminal capacitor is electrically isolated from the first multi-terminal capacitor; and A package structure, disposed on the multi-terminal multi-capacitor structure, includes: a first semiconductor die electrically coupled to the first multi-terminal capacitor; and a second semiconductor die electrically coupled to a second multi-terminal capacitor. The semiconductor structure includes a first substrate, the packaging structure is disposed on a first surface of the first substrate, the multi-terminal multi-capacitor structure includes a second substrate, the insulating layer is disposed on the second substrate, the multi-terminal multi-capacitor structure is disposed on a second surface of the first substrate opposite to the first surface of the first substrate, and the second substrate is a semiconductor substrate.

10. The semiconductor structure as described in claim 9, characterized in that, It also includes a plurality of conductive structures adjacent to the multi-terminal multi-capacitor structure, wherein the encapsulation structure at least partially overlaps with the multi-terminal multi-capacitor structure and the plurality of conductive structures.

11. The semiconductor structure as described in claim 9, characterized in that, The multi-terminal multi-capacitor structure also includes a third multi-terminal capacitor disposed above the insulating layer. The third multi-terminal capacitor includes a third positive terminal and a third ground terminal, and the first multi-terminal capacitor, the second multi-terminal capacitor and the third multi-terminal capacitor are electrically isolated from each other.

12. The semiconductor structure as claimed in claim 11, characterized in that, The first positive terminal, the second positive terminal, and the third positive terminal are arranged along a first line, and the first ground terminal, the second ground terminal, and the third ground terminal are arranged along a second line; or, the first positive terminal, the second ground terminal, and the third positive terminal are arranged along a first line, and the first ground terminal, the second positive terminal, and the third ground terminal are arranged along a second line.

13. The semiconductor structure as described in claim 11, characterized in that, The package structure also includes a third semiconductor die electrically coupled to the third multi-terminal capacitor.

14. The semiconductor structure as claimed in claim 11, characterized in that, Two of the first multi-terminal capacitor, the second multi-terminal capacitor, and the third multi-terminal capacitor are arranged side by side.

15. The semiconductor structure as claimed in claim 11, characterized in that, The first positive terminal, the first ground terminal, the second positive terminal, the second ground terminal, the third positive terminal, and the third ground terminal are disposed between the encapsulation structure and the insulating layer.

16. The semiconductor structure as claimed in claim 9, characterized in that, The first substrate is disposed between the package structure and the multi-terminal multi-capacitor structure and has a wiring structure, wherein the wiring structure is electrically coupled to the package structure and the multi-terminal multi-capacitor structure.

17. The semiconductor structure as claimed in claim 16, characterized in that, It also includes multiple conductive structures disposed between the packaging structure and the substrate, and electrically couples the packaging structure to the wiring structure.

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