Superconducting integrated circuit of a double-layer josephson junction and a method for manufacturing the same

Abstract

The application provides a superconducting integrated circuit with double-layer Josephson junctions and a preparation method thereof. The superconducting integrated circuit comprises a substrate, a logic layer and a signal transmission layer. The logic layer is located above the substrate and comprises at least one lower Josephson junction for storage and / or operation. The signal transmission layer is located above the logic layer and is electrically connected with the logic layer to transmit input and output signals of the logic layer. The signal transmission layer comprises at least one upper Josephson junction for a Josephson transmission line. The application adopts the double-layer Josephson junctions. The upper Josephson junctions can be configured without bias resistors and parallel resistors. The application is beneficial to improving the integration of the superconducting integrated circuit and the frequency of the superconducting integrated circuit. Smaller integration area of the Josephson transmission line makes the wiring of the upper signal transmission layer to the lower logic more flexible and free. In addition, the signal transmission layer can be used to manufacture passive transmission lines, further improving the integration of the superconducting integrated circuit.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of superconducting electronics, and relates to a superconducting integrated circuit of a double-layer Josephson junction and a preparation method thereof. BACKGROUND

[0002] Rapid Single Flux Quantum (RSFQ) is a new superconducting digital logic technology taking the presence or absence of a single magnetic flux quantum (SFQ) as a digital signal carrier. A logic circuit is composed of two parts: 1, a Josephson junction (JJ) with a parallel resistor; and 2, a superconducting inductor connected to the Josephson junction. These two basic components can provide a structure for transmitting or storing a single magnetic flux quantum. From the basic elements of the superconducting RSFQ circuit, it can be seen that the simplest process structure that can be implemented is as follows: in addition to the superconductor-insulator-superconductor (SIS) three-layer film and the resistor layer that constitute the Josephson junction, an insulating layer is also needed to isolate the resistor and the Josephson junction, and additional wiring layers and ground layers are also needed, and an insulating layer is also needed to isolate the metal layers from each other. The SIMIT-Nb03 process developed by the Superconducting Excellence Center of the Shanghai Microsystem and Information Technologies Institute of the Chinese Academy of Sciences is a typical representative of the simplest process structure. The circuit scale that can be carried by the SIMIT-Nb03 process is limited to the order of 10 5 JJ / cm 5 JJ / cm 2). On this basis, the integration of the process, the basic idea is as follows: 1, increase the number of wiring layer; 2, reduce the process of preparing the feature size, for example: the line width limit of the metal line, the size limit of the insulating layer hole, this item is related to the thickness of the film, the thinner the film, the smaller the feature size, generally, the metal film in superconducting integrated process is niobium (Nb), the penetration depth of Nb is 90 nm, the thickness of Nb film needs to exceed the penetration depth, in order to ensure the coverage of the step, each layer of film needs to be at least 50 nm thicker than the thickness of the previous layer of film, if not using chemical mechanical polishing (CMP) planarization technology, the upper film is very thick, the feature size is large, using CMP technology can reduce the thickness of the film, and the corresponding feature size is reduced, in addition, the feature size is also related to the physical limit that can be reached by the lithography equipment; 3, reduce the size of Josephson junction, SIS Josephson junction without parallel external resistance has hysteresis, JJ without hysteresis can ensure the normal operation of SFQ circuit, the hysteresis of JJ can be characterized by damping coefficient β C = 2π(I C R N ) 2 C S / Φ0J C , β C ≤1 represents that JJ is in the over-damped state without hysteresis, β C >1 represents that JJ is in the under-damped state with hysteresis. From the formula of damping coefficient, in order to make JJ reach the over-damped state without hysteresis, a small resistance can be connected in parallel to suppress the damping coefficient, or the current density J C in the process can be increased to suppress it; 4, use materials with large square inductance to reduce the occupied area of inductance.

[0003] Since the digital signal carrier of the superconducting SFQ circuit is a single magnetic flux quantum, which is quantized to a voltage pulse on the waveform of the relationship between time and voltage, the transmission of the voltage pulse cannot be directly connected and transmitted by metal wires as in semiconductor circuits, but can only be transmitted losslessly through a specific transmission unit. This way of transmitting signals is one of the main reasons why the integration level of superconducting circuits is much lower than that of semiconductor circuits. The specific transmission unit mainly has two types: Josephson Transmission Line (JTL) and Passive Transmission Line (PTL). The current domestic and foreign superconducting SFQ circuit integration process structure is based on a single-layer JJ multi-wiring layer process structure. Under the process structure of a single-layer JJ, the cross-circuit unit interlayer wiring can be connected by a PTL. However, a driver and a receiver need to be placed before and after the signal transmitting and receiving units when the PTL is used. PTL is more suitable for long-distance transmission. Using PTL in the case of short-distance cross-unit transmission will cause additional area loss. The JTL wiring method of a single-layer JJ can only be used for wiring in the two-dimensional plane where the logic unit is located, which occupies a large area. However, the unique advantage of JTL wiring is that it can adjust the timing.

[0004] Therefore, how to provide a new superconducting integrated circuit and a preparation method thereof to improve the integration level of the superconducting integrated circuit has become an important technical problem to be solved by those skilled in the art. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a superconducting integrated circuit with a double-layer Josephson junction and a preparation method thereof, which is used to solve the problem of low integration level of the existing superconducting integrated circuit.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a superconducting integrated circuit with a double-layer Josephson junction, comprising:

[0007] a substrate;

[0008] a logic layer located above the substrate, the logic layer comprising at least one lower-layer Josephson junction for storage and / or operation;

[0009] a signal transmission layer located above the logic layer and electrically connected to the logic layer to transmit the input and output signals of the logic layer, the signal transmission layer comprising at least one upper-layer Josephson junction for Josephson Transmission Line.

[0010] Optionally, the signal transmission layer comprises a plurality of upper-layer Josephson junctions, and the junction area sizes of the plurality of upper-layer Josephson junctions are consistent.

[0011] Optionally, the upper Josephson junction is not shunted by a parallel resistor.

[0012] Optionally, the signal transmission layer further comprises a passive transmission line.

[0013] Optionally, the superconducting integrated circuit further comprises a common ground layer between the logic layer and the signal transmission layer, a top electrode of at least one of the lower Josephson junctions is electrically connected to the common ground layer, and a bottom electrode of at least one of the upper Josephson junctions is electrically connected to the common ground layer.

[0014] Optionally, the superconducting integrated circuit further comprises a resistive layer between the substrate and the logic layer, the resistive layer comprising at least one shunt resistor in parallel with the lower Josephson junction.

[0015] Optionally, the logic layer comprises a plurality of the lower Josephson junctions, and the resistive layer further comprises a bias resistor for distributing current to the plurality of the lower Josephson junctions.

[0016] Optionally, the superconducting integrated circuit further comprises a first wiring layer above the logic layer and a second wiring layer above the signal transmission layer, a top electrode of the lower Josephson junction is electrically connected to the first wiring layer, and a top electrode of the upper Josephson junction is electrically connected to the second wiring layer.

[0017] The present application also provides a method for manufacturing a superconducting integrated circuit with a double-layer Josephson junction, comprising the following steps:

[0018] providing a substrate, forming a logic layer above the substrate, the logic layer comprising at least one lower Josephson junction for storage and / or operation;

[0019] forming a signal transmission layer above the logic layer, the signal transmission layer being electrically connected to the logic layer to transmit input and output signals of the logic layer, the signal transmission layer comprising at least one upper Josephson junction for a Josephson transmission line.

[0020] Optionally, before forming the logic layer, the method further comprises:

[0021] forming a resistive layer on the substrate, and patterning the resistive layer to obtain at least one shunt resistor in parallel with the lower Josephson junction;

[0022] forming a first insulating layer on the substrate to cover the resistive layer, and patterning the first insulating layer to obtain a first via hole exposing the resistive layer.

[0023] Optionally, the logic layer comprises a plurality of the lower Josephson junctions, and the resistive layer further comprises a bias resistor for distributing current to the plurality of the lower Josephson junctions.

[0024] Optionally, forming the logic layer comprises the steps of:

[0025] forming a first superconducting layer, a first barrier layer, and a second superconducting layer in sequence;

[0026] patterning the second superconducting layer to obtain a top electrode of the lower Josephson junction;

[0027] patterning the first barrier layer to obtain a barrier layer of the lower Josephson junction;

[0028] patterning the first superconducting layer to obtain a bottom electrode of the lower Josephson junction.

[0029] Optionally, the method further comprises the steps of:

[0030] forming a second insulating layer to cover the logic layer and planarizing the second insulating layer;

[0031] patterning the second insulating layer to obtain a second via hole exposing the top electrode of the lower Josephson junction;

[0032] forming a third superconducting layer on the second insulating layer and patterning the third superconducting layer to obtain a first wiring layer;

[0033] forming a third insulating layer on the third superconducting layer and planarizing;

[0034] patterning the third insulating layer to obtain a third via hole exposing the first wiring layer;

[0035] forming a fourth superconducting layer on the third insulating layer and patterning to obtain a common ground layer;

[0036] forming a fourth insulating layer on the fourth superconducting layer and planarizing;

[0037] patterning the fourth insulating layer to obtain a fourth via hole exposing the common ground layer.

[0038] Optionally, forming the signal transmission layer comprises the steps of:

[0039] forming a fifth superconducting layer, a second barrier layer, and a sixth superconducting layer in sequence;

[0040] patterning the sixth superconducting layer to obtain a top electrode of the upper Josephson junction;

[0041] patterning the second barrier layer to obtain a barrier layer of the upper Josephson junction;

[0042] patterning the fifth superconducting layer to obtain a bottom electrode of the upper layer Josephson junction.

[0043] Optionally, further comprising the following steps:

[0044] forming a fifth insulating layer on the signal transmission layer;

[0045] patterning the fifth insulating layer to obtain a fifth via hole exposing a top electrode of the upper layer Josephson junction;

[0046] forming a seventh superconducting layer on the fifth insulating layer;

[0047] patterning the seventh superconducting layer to obtain a second wiring layer.

[0048] Optionally, the signal transmission layer comprises a plurality of the upper layer Josephson junctions, and the plurality of the upper layer Josephson junctions have the same junction size.

[0049] Optionally, the upper layer Josephson junction is not shunted by a resistance.

[0050] Optionally, the signal transmission layer further comprises a passive transmission line.

[0051] As described above, the superconducting integrated circuit of the double layer Josephson junction and the preparation method thereof of the present application separately place the Josephson junctions for logic circuits and the Josephson junctions for Josephson transmission lines in different layers (logic layer and signal transmission layer), wherein the different layer arrangement makes the size design of the upper layer Josephson junctions for making the Josephson transmission lines not be restricted by the size of the lower layer Josephson junctions for logic circuits, so that the sizes of the plurality of upper layer Josephson junctions can be designed to be the same, and the critical currents flowing through the plurality of upper layer Josephson junctions are the same, without facing the current distribution problem of the Josephson junctions with different critical currents, so that the bias resistance for distributing the current to the upper layer Josephson junctions can be removed, which is beneficial to improving the integration of the superconducting integrated circuit. Meanwhile, the upper layer Josephson junctions can be without shunt resistance, because the area of the shunt resistance is removed, the integrated area of a single Josephson transmission line is small, and because the high damping coefficient of the large hysteresis of the upper layer Josephson junction without shunt resistance, the transmission delay of a single Josephson transmission line is small, so that not only the integration of the superconducting integrated circuit is improved, but also the frequency of the superconducting integrated circuit is improved, and the smaller integrated area of the Josephson transmission line makes the wiring of the upper layer signal transmission layer to the lower layer logic more flexible and free. In addition, the signal transmission layer can also be used to make a passive transmission line, further improving the integration of the superconducting integrated circuit. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 shows a cross-sectional structure schematic diagram of the superconducting integrated circuit of the present application.

[0053] Element number explanation

[0054] 1 substrate

[0055] 2, 2a lower Josephson junction

[0056] 201 first superconducting layer

[0057] 202 first barrier layer

[0058] 203 second superconducting layer

[0059] 3 upper Josephson junction

[0060] 301 fifth superconducting layer

[0061] 302 second barrier layer

[0062] 303 sixth superconducting layer

[0063] 4 common ground layer

[0064] 5a shunt resistor

[0065] 5b bias resistor

[0066] 6 first wiring layer

[0067] 7 second wiring layer

[0068] 8 first insulating layer

[0069] 9 first via

[0070] 10 second insulating layer

[0071] 11 second via

[0072] 12 third insulating layer

[0073] 13 third via

[0074] 14 fourth insulating layer

[0075] 15 fourth via

[0076] 16 fifth insulating layer

[0077] 17 fifth via DETAILED DESCRIPTION

[0078] Following, the embodiments of the present application will be described in detail by specific examples. Those skilled in the art can easily understand other advantages and functions of the present application from the disclosure of the specification. The present application can also be implemented or applied by other different embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0079] Please refer to Figure 1 It is to be noted that the drawings provided in the embodiments only schematically illustrate the basic concepts of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complicated.

[0080] Embodiment One

[0081] In the embodiments, a superconducting integrated circuit with double-layer Josephson junctions is provided. Please refer to Figure 1 , which is a schematic diagram showing the cross-sectional structure of the superconducting integrated circuit, including a substrate 1, a logic layer and a signal transmission layer. The logic layer is located above the substrate 1, and includes at least one lower Josephson junction 2 for storage and / or operation. The signal transmission layer is located above the logic layer and electrically connected to the logic layer to transmit the input and output signals of the logic layer. The signal transmission layer includes at least one upper Josephson junction 3 for Josephson transmission line.

[0082] As an example, the signal transmission layer includes a plurality of upper Josephson junctions 3, and the junction area sizes of the plurality of upper Josephson junctions 3 are consistent, so that the critical currents flowing through the plurality of upper Josephson junctions 3 are the same, and there is no need to face the current distribution problem of Josephson junctions with different critical currents. Therefore, the bias resistor for distributing current to the upper Josephson junctions 3 can be removed, which is beneficial to improve the integration of the superconducting integrated circuit.

[0083] As an example, the upper Josephson junctions 3 are not connected in parallel with shunt resistors. Since the area of the parallel resistors is eliminated, the integration area of a single Josephson transmission line is smaller. At the same time, since the upper Josephson junctions without parallel resistors have a large hysteresis and a high damping coefficient, the transmission delay of a single Josephson transmission line is small. Therefore, it is not only beneficial to improve the integration of the superconducting integrated circuit, but also beneficial to improve the frequency of the superconducting integrated circuit. Moreover, the smaller integration area of the Josephson transmission line makes the wiring of the upper signal transmission layer to the lower logic more flexible and free.

[0084] As an example, the signal transmission layer further comprises a passive transmission line. Generally, the length of the passive transmission line is long and requires a large area. In the present application, the superconducting layer used to fabricate the bottom electrode of the upper Josephson junction in the signal transmission layer can also be used to fabricate the passive transmission line, which can further save the area and greatly improve the integration of the superconducting integrated circuit.

[0085] As an example, the superconducting integrated circuit further comprises a common ground layer 4 between the logic layer and the signal transmission layer, the top electrode of at least one of the lower Josephson junctions 2 is electrically connected to the common ground layer 4 to be upwardly grounded, and the bottom electrode of at least one of the upper Josephson junctions 3 is electrically connected to the common ground layer 4 to be downwardly grounded. Wherein, Figure 1 Another ungrounded floating lower Josephson junction 2a is also shown in the middle.

[0086] As an example, the superconducting integrated circuit further comprises a resistance layer between the substrate 1 and the logic layer, the resistance layer comprises at least one shunt resistance 5a in parallel with the lower Josephson junction 2. In the present embodiment, the logic layer comprises a plurality of lower Josephson junctions 2, and the resistance layer further comprises a bias resistance 5b for distributing current to the plurality of lower Josephson junctions 2.

[0087] As an example, the superconducting integrated circuit further comprises a first wiring layer 6 above the logic layer and a second wiring layer 7 above the signal transmission layer, the top electrode of the lower Josephson junction 2 is electrically connected to the first wiring layer 6, and the top electrode of the upper Josephson junction 3 is electrically connected to the second wiring layer 7.

[0088] The superconducting integrated circuit of the double-layer Josephson junction of the present application places the Josephson junctions for logic circuits and the Josephson junctions for Josephson transmission lines in different layers (logic layer and signal transmission layer) respectively, wherein the different-layer arrangement makes the size design of the upper-layer Josephson junctions for making Josephson transmission lines not subject to the size of the lower-layer Josephson junctions for logic circuits, so that the sizes of the multiple upper-layer Josephson junctions can be designed to be consistent, so that the critical currents flowing through the multiple upper-layer Josephson junctions are the same, without facing the problem of current distribution of Josephson junctions with different critical currents, so that the bias resistors for distributing current to the upper-layer Josephson junctions can be removed, which is beneficial to improving the integration of the superconducting integrated circuit. At the same time, the upper-layer Josephson junctions can be free of parallel resistors, because the area of the parallel resistors is saved, so that the integrated area of a single Josephson transmission line is small, and because the upper-layer Josephson junctions without parallel resistors have a large hysteresis and a high damping coefficient, the transmission delay of a single Josephson transmission line is small, so that not only is the integration of the superconducting integrated circuit improved, but also the frequency of the superconducting integrated circuit is improved, and the smaller integrated area of the Josephson transmission line makes the wiring of the upper-layer signal transmission layer to the lower-layer logic more flexible and free.

[0089] Embodiment Two

[0090] The present embodiment provides a preparation method of a superconducting integrated circuit of a double-layer Josephson junction, which can be used to prepare the superconducting integrated circuit of a double-layer Josephson junction as shown in Figure 1 The method comprises the following steps:

[0091] S1: providing a substrate 1, forming a logic layer above the substrate 1, the logic layer comprising at least one lower-layer Josephson junction 2 for storage and / or operation;

[0092] S2: forming a signal transmission layer above the logic layer, the signal transmission layer being electrically connected to the logic layer to transmit the input and output signals of the logic layer, the signal transmission layer comprising at least one upper-layer Josephson junction 3 for Josephson transmission lines.

[0093] As an example, before forming the logic layer, the following steps are performed first:

[0094] (1) Forming a resistance layer on the substrate 1 by sputtering, electroplating or other suitable methods, and patterning the resistance layer by photolithography, etching or other semiconductor processes to obtain at least one shunt resistance 5a in parallel with the lower Josephson junction 2, wherein the material of the substrate 1 includes magnesium oxide or other suitable materials, and the material of the resistance layer can include one or more of Mo, Pd and Ti. In this embodiment, the logic layer includes a plurality of lower Josephson junctions 2, and the resistance layer further includes a bias resistance 5b for distributing current to the plurality of lower Josephson junctions 2.

[0095] (2) Forming a first insulating layer 8 on the substrate 1 by chemical vapor deposition, physical vapor deposition or other suitable methods to cover the resistance layer, and patterning the first insulating layer 8 by photolithography, etching or other semiconductor processes to obtain a first via 9 exposing the resistance layer. The material of the first insulating layer 8 can include one or more of silicon dioxide and silicon nitride.

[0096] As an example, forming the logic layer includes the following steps:

[0097] (3) Forming a first superconducting layer 201, a first barrier layer 202 and a second superconducting layer 203 on the first insulating layer 8 in sequence by physical vapor deposition or other suitable methods, wherein the first superconducting layer 201 also fills into the first via 9, the first superconducting layer 201 can include a niobium layer, the first barrier layer 202 can include an aluminum oxide layer, and the second superconducting layer 203 can include a niobium layer. The critical current density of the lower Josephson junction 2 or the lower Josephson junction 2a can be adjusted by adjusting the oxidation time of the first barrier layer 202.

[0098] It should be noted that in this embodiment, the area where the lower Josephson junction is located avoids the resistance area and is located in the flat area of the first insulating layer 8, so the first insulating layer 8 can not need to be planarized.

[0099] (4) Patterning the second superconducting layer 203 by photolithography, etching or other semiconductor processes to obtain the top electrode of the lower Josephson junction 2, wherein the top electrode of the lower Josephson junction 2 determines the junction area.

[0100] (5) Patterning the first barrier layer 202 by photolithography, etching or other semiconductor processes to obtain the barrier layer of the lower Josephson junction 2.

[0101] (6) Patterning the first superconducting layer 201 by photolithography, etching or other semiconductor processes to obtain the bottom electrode of the lower Josephson junction 2, wherein the first superconducting layer 201 can also be used to make inductors required in superconducting integrated circuits.

[0102] As an example, after the logic layer is formed, the following steps are performed:

[0103] (7) A second insulating layer 10 is formed over the logic layer using chemical vapor deposition, physical vapor deposition, or other suitable method, and the second insulating layer 10 is planarized using chemical mechanical polishing (CMP) or other suitable process.

[0104] (8) The second insulating layer 10 is patterned using photolithography, etching, or other semiconductor process to obtain a second via 11 that exposes the top electrode of the underlying Josephson junction 2.

[0105] (9) A third superconducting layer is formed over the second insulating layer 10 using physical vapor deposition or other suitable method, and the third superconducting layer is patterned to obtain a first wiring layer 6, wherein the third superconducting layer also fills into the second via 11.

[0106] (10) A third insulating layer 12 is formed over the third superconducting layer using chemical vapor deposition, physical vapor deposition, or other suitable method, and the third insulating layer 12 is planarized using chemical mechanical polishing (CMP) or other suitable process.

[0107] (11) The third insulating layer 12 is patterned using photolithography, etching, or other semiconductor process to obtain a third via 13 that exposes the first wiring layer 6.

[0108] (12) A fourth superconducting layer is formed over the third insulating layer 12 using physical vapor deposition or other suitable method and is patterned to obtain a common ground layer 4, wherein the fourth superconducting layer also fills into the third via 13.

[0109] (13) A fourth insulating layer 14 is formed over the fourth superconducting layer using chemical vapor deposition, physical vapor deposition, or other suitable method, and the fourth insulating layer 14 is planarized using chemical mechanical polishing (CMP) or other suitable process.

[0110] (14) The fourth insulating layer 14 is patterned using photolithography, etching, or other semiconductor process to obtain a fourth via 15 that exposes the common ground layer 4.

[0111] As an example, forming the signal transmission layer includes the following steps:

[0112] (15) forming a fifth superconducting layer 301, a second barrier layer 302 and a sixth superconducting layer 303 on the fourth insulating layer 14 in sequence by physical vapor deposition or other suitable methods, the fifth superconducting layer 301 also fills into the fourth via hole 15, wherein the fifth superconducting layer 301 can include a niobium layer, the second barrier layer 302 can include an aluminum oxide layer, and the sixth superconducting layer 303 can include a niobium layer. The critical current density of the upper Josephson junction 3 can be adjusted by adjusting the oxidation time of the second barrier layer 302.

[0113] (16) patterning the sixth superconducting layer 303 by photolithography, etching and other semiconductor processes to obtain the top electrode of the upper Josephson junction 3, wherein the top electrode of the upper Josephson junction 3 determines the junction area thereof.

[0114] (17) patterning the second barrier layer 302 by photolithography, etching and other semiconductor processes to obtain the barrier layer of the upper Josephson junction 3.

[0115] (18) patterning the fifth superconducting layer 301 by photolithography, etching and other semiconductor processes to obtain the bottom electrode of the upper Josephson junction 3, wherein the fifth superconducting layer 301 can also be used to make inductors required in superconducting integrated circuits.

[0116] As an example, the signal transmission layer includes a plurality of the upper Josephson junctions 3, the junction areas of the plurality of the upper Josephson junctions 3 are consistent, so that the critical currents flowing through the plurality of the upper Josephson junctions 3 are the same, without facing the problem of current distribution of Josephson junctions with different critical currents, so that the biasing resistor for distributing current to the upper Josephson junctions 3 can be removed, which is conducive to improving the integration of superconducting integrated circuits.

[0117] As an example, the upper Josephson junctions 3 are not connected in parallel with shunt resistors, because the area of the shunt resistors is saved, the integration area of a single Josephson transmission line is smaller, and because the upper Josephson junctions without shunt resistors have a large hysteresis and a high damping coefficient, the transmission delay of a single Josephson transmission line is small, so that not only the integration of superconducting integrated circuits is improved, but also the frequency of superconducting integrated circuits is improved, and the smaller integration area of Josephson transmission lines makes the upper signal transmission layer more flexible and free in wiring the lower logic.

[0118] As an example, the signal transmission layer also includes passive transmission lines. Generally, passive transmission lines have a relatively long length and need to occupy a relatively large area. In the present application, the superconducting layer for making the bottom electrode of the upper Josephson junction in the signal transmission layer can also be used to make passive transmission lines, which can further save area and greatly improve the integration of superconducting integrated circuits.

[0119] As an example, after the signal transmission layer is formed, the following steps are continued to be performed:

[0120] (19) A fifth insulating layer 16 is formed on the signal transmission layer by chemical vapor deposition, physical vapor deposition or other suitable methods.

[0121] (20) The fifth insulating layer 16 is patterned by photolithography, etching or other semiconductor process to obtain a fifth via hole 17 which exposes the top electrode of the upper layer Josephson junction 3.

[0122] (21) A seventh superconducting layer is formed on the fifth insulating layer 16 by physical vapor deposition or other suitable methods, wherein the seventh superconducting layer also fills into the fifth via hole 17.

[0123] (22) The seventh superconducting layer is patterned by photolithography, etching or other semiconductor process to obtain a second wiring layer 7.

[0124] At this point, a superconducting integrated circuit with double-layer Josephson junction is prepared, wherein the connection between the upper and lower layer Josephson junctions is achieved by the interlaced punching of the first superconducting layer (i.e. the superconducting layer where the bottom electrode of the lower layer Josephson junction is located) to the seventh superconducting layer (i.e. the wiring layer of the upper layer Josephson junction).

[0125] In summary, the superconducting integrated circuit with double-layer Josephson junction and the preparation method thereof of the present application separately place the Josephson junctions for logic circuits and the Josephson junctions for Josephson transmission lines in different layers (logic layer and signal transmission layer), wherein the separate layer arrangement makes the size design of the upper layer Josephson junctions for making Josephson transmission lines not subject to the size of the lower layer Josephson junctions for logic circuits, so that the sizes of multiple upper layer Josephson junctions can be designed to be consistent, making the critical current flowing through multiple upper layer Josephson junctions the same, without facing the problem of current distribution of Josephson junctions with different critical currents, so that the bias resistance for distributing current to the upper layer Josephson junctions can be removed, which is beneficial to improve the integration of the superconducting integrated circuit. At the same time, the upper layer Josephson junctions can be without parallel resistance, since the area of the parallel resistance is saved, the integrated area of a single Josephson transmission line is small, and since the upper layer Josephson junctions without parallel resistance have a large hysteresis high damping coefficient, the transmission delay of a single Josephson transmission line is small, so that not only is it beneficial to improve the integration of the superconducting integrated circuit, but also is beneficial to improve the frequency of the superconducting integrated circuit, and the smaller integrated area of the Josephson transmission line makes the wiring of the lower layer logic by the upper layer signal transmission layer more flexible and free. In addition, the signal transmission layer can also be used to make passive transmission lines, further improving the integration of the superconducting integrated circuit. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0126] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A superconducting integrated circuit of a double-layer Josephson junction, characterized by, The superconducting integrated circuit comprises: a substrate; a logic layer above the substrate, the logic layer comprising at least one lower Josephson junction for storage and / or operation; a signal transmission layer above the logic layer and electrically connected to the logic layer to transmit input and output signals of the logic layer, the signal transmission layer comprising a plurality of upper Josephson junctions for Josephson transmission lines, the plurality of upper Josephson junctions having the same junction area, and the upper Josephson junctions not being in parallel with shunt resistors. The superconducting integrated circuit further comprises a resistance layer between the substrate and the logic layer, the resistance layer comprising at least one shunt resistor in parallel with the lower Josephson junction, the logic layer comprising a plurality of the lower Josephson junctions, and the resistance layer further comprising bias resistors for distributing currents to the plurality of lower Josephson junctions.

2. The superconducting integrated circuit of a double-layer Josephson junction according to claim 1, characterized in that: The signal transmission layer further comprises passive transmission lines.

3. The superconducting integrated circuit of a double-layer Josephson junction according to claim 1, characterized in that: The superconducting integrated circuit further comprises a common ground layer between the logic layer and the signal transmission layer, a top electrode of at least one of the lower Josephson junctions being electrically connected to the common ground layer, and a bottom electrode of at least one of the upper Josephson junctions being electrically connected to the common ground layer.

4. The superconducting integrated circuit of a double-layer Josephson junction according to claim 1, characterized in that: The superconducting integrated circuit further comprises a first wiring layer above the logic layer and a second wiring layer above the signal transmission layer, a top electrode of the lower Josephson junction being electrically connected to the first wiring layer, and a top electrode of the upper Josephson junction being electrically connected to the second wiring layer.

5. A method of fabricating a superconducting integrated circuit of a double-layer Josephson junction, characterized by, The superconducting integrated circuit comprises: a substrate; a logic layer above the substrate, the logic layer comprising at least one lower Josephson junction for storage and / or operation; a signal transmission layer above the logic layer and electrically connected to the logic layer to transmit input and output signals of the logic layer, the signal transmission layer comprising a plurality of upper Josephson junctions for Josephson transmission lines, the plurality of upper Josephson junctions having the same junction area, and the upper Josephson junctions not being in parallel with shunt resistors. The superconducting integrated circuit further comprises a resistance layer between the substrate and the logic layer, the resistance layer comprising at least one shunt resistor in parallel with the lower Josephson junction, the logic layer comprising a plurality of the lower Josephson junctions, and the resistance layer further comprising bias resistors for distributing currents to the plurality of lower Josephson junctions. The superconducting integrated circuit further comprises a common ground layer between the logic layer and the signal transmission layer, a top electrode of at least one of the lower Josephson junctions being electrically connected to the common ground layer, and a bottom electrode of at least one of the upper Josephson junctions being electrically connected to the common ground layer.

6. The method of claim 5, wherein the method further comprises: The superconducting integrated circuit further comprises a first wiring layer above the logic layer and a second wiring layer above the signal transmission layer, a top electrode of the lower Josephson junction being electrically connected to the first wiring layer, and a top electrode of the upper Josephson junction being electrically connected to the second wiring layer. The superconducting integrated circuit comprises: a substrate; a logic layer above the substrate, the logic layer comprising at least one lower Josephson junction for storage and / or operation; a signal transmission layer above the logic layer and electrically connected to the logic layer to transmit input and output signals of the logic layer, the signal transmission layer comprising a plurality of upper Josephson junctions for Josephson transmission lines, the plurality of upper Josephson junctions having the same junction area, and the upper Josephson junctions not being in parallel with shunt resistors.

7. The method of claim 5, wherein the method further comprises: The superconducting integrated circuit further comprises a resistance layer between the substrate and the logic layer, the resistance layer comprising at least one shunt resistor in parallel with the lower Josephson junction, the logic layer comprising a plurality of the lower Josephson junctions, and the resistance layer further comprising bias resistors for distributing currents to the plurality of lower Josephson junctions. The superconducting integrated circuit further comprises a common ground layer between the logic layer and the signal transmission layer, a top electrode of at least one of the lower Josephson junctions being electrically connected to the common ground layer, and a bottom electrode of at least one of the upper Josephson junctions being electrically connected to the common ground layer. The superconducting integrated circuit further comprises a first wiring layer above the logic layer and a second wiring layer above the signal transmission layer, a top electrode of the lower Josephson junction being electrically connected to the first wiring layer, and a top electrode of the upper Josephson junction being electrically connected to the second wiring layer. The superconducting integrated circuit comprises: a substrate; a logic layer above the substrate, the logic layer comprising at least one lower Josephson junction for storage and / or operation; a signal transmission layer above the logic layer and electrically connected to the logic layer to transmit input and output signals of the logic layer, the signal transmission layer comprising a plurality of upper Josephson junctions for Josephson transmission lines, the plurality of upper Josephson junctions having the same junction area, and the upper Josephson junctions not being in parallel with shunt resistors. The superconducting integrated circuit further comprises a resistance layer between the substrate and the logic layer, the resistance layer comprising at least one shunt resistor in parallel with the lower Josephson junction, the logic layer comprising a plurality of the lower Josephson junctions, and the resistance layer further comprising bias resistors for distributing currents to the plurality of lower Josephson junctions. The superconducting integrated circuit further comprises a common ground layer between the logic layer and the signal transmission layer, a top electrode of at least one of the lower Josephson junctions being electrically connected to the common ground layer, and a bottom electrode of at least one of the upper Josephson junctions being electrically connected to the common ground layer. The superconducting integrated circuit further comprises a first wiring layer above the logic layer and a second wiring layer above the signal transmission layer, a top electrode of the lower Josephson junction being electrically connected to the first wiring layer, and a top electrode of the upper Josephson junction being electrically connected to the second wiring layer. The superconducting integrated circuit comprises: a substrate; a logic layer above the substrate, the logic layer comprising at least one lower Josephson junction for storage and / or operation; a signal transmission layer above the logic layer and electrically connected to the logic layer to transmit input and output signals of the logic layer, the signal transmission layer comprising a plurality of upper Josephson junctions for Josephson transmission lines, the plurality of upper Josephson junctions having the same junction area, and the upper Josephson junctions not being in parallel with shunt resistors. The superconducting integrated circuit further comprises a resistance layer between the substrate and the logic layer, the resistance layer comprising at least one shunt resistor in parallel with the lower Josephson junction, the logic layer comprising a plurality of the lower Josephsson forming a third superconducting layer on the second insulating layer and patterning the third superconducting layer to obtain a first wiring layer; forming a third insulating layer on the third superconducting layer and planarizing; patterning the third insulating layer to obtain a third via hole exposing the first wiring layer; forming a fourth superconducting layer on the third insulating layer and patterning to obtain a common ground layer; forming a fourth insulating layer on the fourth superconducting layer and planarizing; patterning the fourth insulating layer to obtain a fourth via hole exposing the common ground layer.

8. The method of claim 5, wherein the method further comprises: forming the signal transmission layer comprises the following steps: forming a fifth superconducting layer, a second barrier layer and a sixth superconducting layer in sequence; patterning the sixth superconducting layer to obtain a top electrode of the upper Josephson junction; patterning the second barrier layer to obtain a barrier layer of the upper Josephson junction; patterning the fifth superconducting layer to obtain a bottom electrode of the upper Josephson junction.

9. The method of claim 5, wherein the method further comprises: further comprising the following steps: forming a fifth insulating layer on the signal transmission layer; patterning the fifth insulating layer to obtain a fifth via hole exposing the top electrode of the upper Josephson junction; forming a seventh superconducting layer on the fifth insulating layer; patterning the seventh superconducting layer to obtain a second wiring layer.

10. The method of claim 5, wherein: the signal transmission layer further comprises a passive transmission line.

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