Transistor layout for reduced flicker noise

Abstract

A transistor includes: a diffusion region including a drain, a source, and a channel between the drain and the source; an isolation region surrounding the diffusion region for electrically isolating the transistor; and a gate polysilicon overlapping at least a portion of the channel, wherein the diffusion region extends laterally beyond the gate polysilicon along the channel width direction.

Description

Technical Field

[0001] The present invention relates to transistors, and more particularly to a transistor layout for reducing flicker noise. Background Art

[0002] Transistors are ubiquitous in modern society, and there is a constant need to improve their performance.

[0003] Figures 1 to 3 An n-channel MOSFET (nmos) transistor 2 is shown formed in a substrate 3 and having a diffusion region 4 (also referred to in the art as an "active region" and refers to a region not covered by an isolation material such as shallow trench isolation STI or local oxidation of silicon (LOCOS)). The diffusion region 4 includes a drain 6, a source 8, and a channel 10 between the drain 6 and the source 8. The channel 10 (which is indicated as Figure 1 The region between the dashed lines (the middle dashed line) is the n-doped well 11, where current flows between source 8 and drain 6. Gate polysilicon (poly) 12, located above channel 10, is used to turn the transistor on or off by applying a bias to gate poly 12, thereby opening channel 10 and allowing current to flow through it from drain 6 to source 8. Gate poly 12 is separated from the underlying substrate 3 by gate oxide 13. Drain 6 and source 8 comprise n-doped regions within p-doped well 11. Transistor 2 is isolated by shallow trench isolation (STI) 14 surrounding diffusion region 4. Drain 6, source 8, and gate poly 12 each have metal contacts 16, 18, and 20 for electrical connection. The N+ symbol indicates that a large N+ implant covers the entire area of ​​transistor 2 but is blocked by STI 14 and gate poly 12, resulting in n-type doping of only the drain and source regions (bounded by STI 14 and gate poly 12). The gate polysilicon 12 also becomes n-doped, which is important to set the correct work function for the gate. Summary of the Invention

[0004] On the one hand, the present invention provides a transistor, comprising: a diffusion region, including a drain, a source, and a channel between the drain and the source, wherein the diffusion region has a cross shape, the cross shape including a first pair of opposite arms and a second pair of opposite arms, and the source and the drain are located in respective arms of the first pair of opposite arms; an isolation region surrounding the diffusion region, for electrically isolating the transistor; and a gate polysilicon, the gate polysilicon is H-shaped, having a pair of parallel rectangular portions, the rectangular portions being connected by a cross-beam portion and the gate polysilicon overlapping with at least a portion of the channel, wherein the second pair of opposite arms of the diffusion region extend beyond the pair of parallel rectangular portions of the gate polysilicon in the channel width direction.

[0005] Another aspect of the present invention provides a source follower circuit including the above transistor.

[0006] The present invention also provides a complementary metal oxide semiconductor (CMOS) image sensor comprising a plurality of the above transistors.

[0007] Specific embodiments of the present invention will now be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 shows a schematic top view of a conventional n-channel MOSFET;

[0009] Figure 2 shows a schematic cross section of an n-channel MOSFET;

[0010] Figure 3 shows a schematic diagram of another cross section of an n-channel MOSFET;

[0011] Figure 4 shows a schematic top view of an n-channel MOSFET according to an embodiment;

[0012] Figure 5 shows a schematic top view of an n-channel MOSFET according to another embodiment;

[0013] Figure 6 Shown according to Figure 4 or Figure 5 A schematic cross-sectional view of an n-channel MOSFET of an embodiment of the present invention;

[0014] Figure 7 shows a graph plotting spectrum ID (noise) versus frequency for a transistor according to an embodiment and a conventional transistor at a drain current of 0.01 μA;

[0015] Figure 8 shows a similar graph plotting spectral ID (noise) versus frequency for a transistor according to an embodiment and a conventional transistor at a drain current of 10 μA;

[0016] Figure 9 shows a schematic top view of another n-channel MOSFET according to an embodiment;

[0017] Figure 10 shows a graph plotting spectrum ID (noise) versus frequency for a transistor according to another embodiment and a conventional transistor at a drain current of 0.01 μA; and

[0018] Figure 11A similar graph is shown plotting Spectral ID (noise) versus frequency for a transistor according to an embodiment and a conventional transistor at a drain current of 10 μA. DETAILED DESCRIPTION

[0019] Many analog applications require low-noise complementary metal-oxide semiconductor (CMOS) transistors. For example, source followers in CMOS image sensors (CIS) may require low flicker noise performance at currents ranging from a few µA to tens of µA. Therefore, embodiments described herein can provide transistors that can reduce flicker noise in such source-follower circuits.

[0020] Figure 4 、 Figure 5 and Figure 6 An n-channel MOSFET transistor 2 according to various embodiments is shown. Similar or equivalent features in the different figures have been given the same reference numerals to aid understanding and are not intended to limit the embodiments shown.

[0021] Figure 4 A schematic top view of a transistor 2 is shown having a diffusion region 4 comprising a drain 6, a source 8 and a channel 10 therebetween. The diffusion region 4 is defined as a doped surface layer of the substrate 3, which is created during the manufacturing process using a so-called diffusion mask (DIFF mask). Figures 1 to 3 Unlike the transistor shown in , the diffusion regions 4 extend laterally on both sides of the channel 10 in the width direction (i.e., perpendicular to the direction of current flow in the channel 10, between the source 8 and the drain 6 when the transistor 2 is used). Therefore, the channel 10 is edged with P+ doped regions along its length, rather than being edged with the surrounding STI 14 as in conventional CMOS designs. The dotted areas indicate the locations of the P+ implants. These areas are typically shielded from the main N+ implants by the N+ mask. Gate polysilicon 12 and gate oxide 13 are located above the channel 10 and are used to turn the transistor on or off by applying a bias to the gate polysilicon 12, thereby opening the channel 10 and allowing current to flow through the channel 10 from the drain 6 to the source 8. The channel 10 passes through the diffusion regions 4 and extends all the way to the edge of the gate polysilicon 12 (so that although the channel 10 is in Figure 1 Indicated by dotted lines, but in Figure 4This is not possible because the dashed line indicating channel 10 would be obscured by the line of gate polysilicon 12 above diffusion region 4. Gate polysilicon 12 has an H-shape, with two sides 12a and 12b bridged by a crossbar 12c above channel 10. Along the width of channel 10, gate polysilicon 12 terminates above P+ region 22 in diffusion region 4, rather than above STI 14. This reduces the transistor's 1 / f noise, especially for low currents (typically less than 10µA). Metal contacts 16, 18, and 20 connect to drain 6, source 8, and gate polysilicon 12, respectively.

[0022] Figure 5 shows a similar Figure 4 Schematic top view of transistor 2 of the transistor. Figure 4 and Figure 5 The difference between the embodiments is the position of the diffusion region 4 relative to the gate polysilicon 12. Figure 5 As shown, the gate polysilicon 12 overlaps the diffusion region 4 at the drain 6 and source 8. This can further reduce flicker noise.

[0023] For example, Figure 6 Shown along Figure 4 or Figure 5 Schematic cross-sectional side view of transistor 2 along line CC' of an embodiment of the present invention. Channel 10 in p-doped well 11 below gate 12 is edged on both sides by heavily doped P+ regions 22 in diffusion region 4, rather than being in direct contact with STI 14. Heavily doped (also referred to as high doping) can refer to a doping concentration of the order of 1 dopant per 10,000 (ten thousand) atoms or higher.

[0024] Table 1 shows a MOSFET with an H-shaped gate according to an embodiment - e.g. Figure 4 and Figure 5 Figure 3 shows the output-referred noise (spectrum ID) of an n-channel MOSFET compared to the noise of a conventional transistor.

[0025] Table 1 – Noise comparison

[0026] Bias conditions at 100Hz Relative noise of the example Id = 0.01µA 1.9 decade lower Id = 0.1µA Reduced by 1.4 times Id = 1µA Reduced by 0.9 tenfold Id = 10µA Reduce 1.0 tenfold Id = 100µA Reduced by 0.3 tenfold

[0027] Figure 7 and Figure 8 FIG. 1 shows a graph plotting the spectrum ID versus frequency for two 3.3V n-channel MOSFETs at 0.01 μA and 10 μA, respectively, where both transistors have the same size, but one transistor has a current consumption according to an embodiment (e.g., as Figure 4 ), while the other transistor has an H-shaped gate as shown in Figure 1As can be seen from the graph, the transistor according to the embodiment has consistently lower noise over the entire frequency spectrum from 100 Hz to 10 kHz.

[0028] Figure 9 A schematic diagram illustrates another layout of an n-channel MOSFET transistor 2 that can reduce flicker noise according to an embodiment. Transistor 2 includes a diffusion region 4 having a drain 6 and a source 8, each with contacts 16 and 18. Gate polysilicon 12 is located above diffusion region 4 and has a contact 20. STI 14 surrounds the diffusion region to isolate transistor 2. Diffusion region 4 extends horizontally, so that gate polysilicon 12 terminates above a P+ region 22 in diffusion region 4, rather than above STI 14.

[0029] Table 2 shows an n-channel MOSFET according to an embodiment - for example, Figure 9 The noise of an n-channel MOSFET (spectrum ID) is shown in Figure 1 compared to the noise of a conventional n-channel transistor.

[0030] Table 2 - Noise comparison, n-channel MOSFET

[0031] Bias conditions at 100Hz Relative noise of the example Id = 0.01µA Reduced by 1.6 times Id = 0.1µA Reduced by 0.7 tenfold Id = 1µA Reduce 1.0 tenfold Id = 10µA Reduced by 0.4 tenfold Id = 100µA Reduced by 0.4 tenfold

[0032] Figure 10 and Figure 11 FIG. 4 shows a graph plotting the spectrum ID versus frequency for two 3.3V n-channel MOSFETs at 0.01 μA and 10 μA, respectively, where both transistors have the same size, but one transistor is in accordance with an embodiment. Figure 9 The transistor shown in FIG, and the other transistor has a Figure 1 As can be seen from the graph, the transistor according to the embodiment has consistently lower noise over the entire frequency spectrum from 100 Hz to 10 kHz.

[0033] Generally, embodiments described herein provide a transistor comprising a diffusion region and an isolation region surrounding the diffusion region for electrically isolating the transistor (e.g., STI or LOCOS), the diffusion region including a drain, a source, and a channel between the drain and source. The transistor also includes a gate overlapping at least a portion of the channel, wherein the diffusion region extends beyond the gate in a width direction—i.e., substantially perpendicular to the direction of current flow through the channel when the transistor is in use (i.e., when the transistor is turned on so that current flows through the channel). By terminating the gate above the diffusion region (e.g., above a P+ doped region of the diffusion region) rather than above the isolation region, noise can be significantly improved, particularly when drawing low currents. For example, the transistor is particularly suitable for use as a source follower in CMOS image sensors, which typically have a drain current of less than 10µA.

[0034] The drain and source can include respective n-doped regions, and the channel can extend between the n-doped regions in a p-doped well (e.g., an n-channel MOSFET), wherein opposing first and second sides of the channel are edged by heavily doped P+ regions, such that the heavily doped P+ regions separate the channel from the isolation region. By separating the channel from the isolation region with the heavily doped regions, noise can be further reduced. The gate can terminate before the heavily doped P+ regions (i.e., the gate does not extend widthwise above the heavily doped P+ regions).

[0035] Alternatively, the drain and source may comprise respective p-doped regions, and the channel may extend between the p-doped regions in an n-doped well (e.g., a p-channel MOSFET), wherein opposing first and second sides of the channel are edged by heavily doped N+ regions such that the heavily doped N+ regions separate the channel from the isolation region.

[0036] The gate may be H-shaped (see e.g. Figure 4 ), or may be square (see e.g. Figure 9 ), which has a cross-shaped diffusion (active) region to further reduce noise and provide some radiation protection by shielding the interface between the isolation region and the diffusion region. The gate typically comprises a polysilicon layer.

[0037] The transistor can be configured to operate at 1.8V, 3.3V, or 5V, etc. The transistor can be particularly advantageous in reducing noise in low-voltage transistors. Similarly, the transistor can be configured to draw a small current (e.g., less than 10 μA), for which the noise reduction can be even greater.

[0038] Other embodiments provide a source follower circuit including a transistor according to embodiments described herein and a CMOS image sensor (CIS) including a plurality of such transistors.

[0039] Although specific embodiments of the present invention have been described above, it will be appreciated that the present invention may be practiced in a manner other than as described. The foregoing description is intended to be illustrative and not restrictive. It will be apparent to those skilled in the art that modifications may be made to the described invention without departing from the scope of the claims set forth below.

[0040] Every feature disclosed or shown in this specification may be included in the invention either alone or in any appropriate combination with any other features disclosed or shown herein.

Claims

1. A transistor comprising: a diffusion region comprising a drain, a source, and a channel between the drain and the source, wherein the diffusion region has a cross shape including a first pair of opposing arms and a second pair of opposing arms, and the source and the drain are located in respective arms of the first pair of opposing arms; an isolation region surrounding the diffusion region for electrically isolating the transistor; and a gate polysilicon having an H-shape and having a pair of parallel rectangular portions connected by a beam portion and overlapping at least a portion of the channel, wherein the second pair of opposing arms of the diffusion region extend beyond the pair of parallel rectangular portions of the gate polysilicon in a channel width direction.

2. The transistor according to claim 1, wherein The drain and the source include respective n-doped regions, and the channel extends between the n-doped regions in a p-doped well, and wherein opposing first and second sides of the channel are edged by heavily doped P+ regions such that the heavily doped P+ regions separate the channel from the isolation region.

3. The transistor according to claim 2, wherein The gate polysilicon does not extend over the heavily doped P+ region.

4. The transistor according to claim 1, wherein The drain and the source include respective p-doped regions, and the channel extends between the p-doped regions in an n-doped well, and wherein opposing first and second sides of the channel are edged by heavily doped N+ regions such that the heavily doped N+ regions separate the channel from the isolation region.

5. The transistor according to claim 1, wherein The gate polysilicon includes a polysilicon layer. The transistor according to claim 1 , wherein: The transistor is configured to operate at one of 1.2 V, 1.5 V, 1.8 V, 3.3 V, and 5 V.

7. The transistor according to claim 1, wherein The transistor is configured to draw a current of less than 10 μA.

8. A source follower circuit comprising the transistor according to claim 1. 9 . A CMOS image sensor (CIS), comprising a plurality of transistors according to claim 1 .

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